Ian Romanick [Thu, 11 Mar 2021 04:46:50 +0000 (20:46 -0800)]
egl/dri2: Rely on drm-uapi for DRM_FORMAT defines
All of these formats, and ones that will be added later in this series,
are in the copy of drm_fourcc.h in drm-uapi.
Suggested-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9610>
Ian Romanick [Tue, 2 Mar 2021 00:21:10 +0000 (16:21 -0800)]
dri: Fix typo before __DRI_IMAGE_COMPONENTS defines
s/are may be/might be/
Also add a missing comma.
v2: Also s/its/it's/. Suggested by Nanley.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9610>
Ian Romanick [Mon, 1 Mar 2021 23:39:00 +0000 (15:39 -0800)]
util/format: Delete trailing whitespace
The angry red marks in Emacs were annoying me.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9610>
Kenneth Graunke [Thu, 20 May 2021 20:04:15 +0000 (13:04 -0700)]
iris: Don't advertise Y-tiled modifiers for scanout buffers on Gfx8
According to isl_gfx7.c:264, the display engine does not support Y
tiled buffers prior to Skylake. But we exposed I915_FORMAT_MOD_Y_TILED
even when querying for a list of modifiers with PIPE_BIND_SCANOUT set,
which we can't support. That led to crashes later when we tried to
create such an image, and isl rightly denied it.
Fixes crashes in wflinfo since
c03e79d7831f, but the bug exists before
that and it's probably worth a stable backport even without that patch.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4815
Fixes:
c03e79d7831 ("loader/dri: hook up createImageWithModifiers2")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10907>
Kenneth Graunke [Thu, 20 May 2021 20:04:15 +0000 (13:04 -0700)]
i965: Don't advertise Y-tiled modifiers for scanout buffers on Gfx8-
According to isl_gfx7.c:264, the display engine does not support Y
tiled buffers prior to Skylake. But we exposed I915_FORMAT_MOD_Y_TILED
even when querying for a list of modifiers with __DRI_IMAGE_USE_SCANOUT
set, which we can't support. That led to crashes later when we tried
to create such an image, and isl rightly denied it.
This duplicates a bit of code from ISL, but the isl_gfx6_filter_tiling
function that we ought to use to filter things relies on surf_info,
which we don't have at this stage. This is probably good enough.
Fixes crashes in wflinfo since
c03e79d7831f, but the bug exists before
that and it's probably worth a stable backport even without that patch.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4815
Fixes:
c03e79d7831 ("loader/dri: hook up createImageWithModifiers2")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10907>
Andres Gomez [Thu, 20 May 2021 07:47:17 +0000 (10:47 +0300)]
ci: Add test which occasionally times out to lavapipe-vk skips
E.g:
- https://gitlab.freedesktop.org/mesa/mesa/-/jobs/9881541
- https://gitlab.freedesktop.org/mesa/mesa/-/jobs/9916369
Signed-off-by: Andres Gomez <agomez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10893>
Kenneth Graunke [Thu, 20 May 2021 09:03:07 +0000 (02:03 -0700)]
isl: Work around NVIDIA and AMD display pitch requirements
In the case where we're rendering on the Intel GPU, but displaying
on an AMD and NVIDIA GPU, we need to follow their pitch requirements
for our linear scanout buffers.
Based on a patch by Lionel Landwerlin.
Closes: #4706
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10895>
Emma Anholt [Tue, 18 May 2021 19:27:34 +0000 (12:27 -0700)]
i915g: Fix undefined results for TGSI_OPCODE_KILL
The swizzle() requires a proper ureg with the 0/1 swizzle fields filled
in, or our ONE swizzles end up reading .x instead. This meant that we
were killing based on the incoming value of R0.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10874>
Emma Anholt [Tue, 18 May 2021 19:19:45 +0000 (12:19 -0700)]
i915g: Fix writing of undefined depth value if not writing any outputs.
This was showing up as flakes in CI on tests that didn't write any outputs
but did check the depth result.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10874>
Eric Anholt [Wed, 12 Aug 2020 17:51:15 +0000 (10:51 -0700)]
i915g: Stop advertising support for indirect addressing in the FS.
This hardware can't do any form of indirect addressing. The couple of new
Crashes are the backend falling over when faced with loops/ifs.
Fixes:
8a22064d316e ("i915g: Implement vertex textures.")
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10874>
Emma Anholt [Tue, 18 May 2021 17:07:11 +0000 (10:07 -0700)]
i915g: Add support for the .Absolute flag on TGSI srcs.
We don't have a way to ask TGSI to not have .Absolute, so lower it in the
backend.
Cc: mesa-stable
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10874>
Emma Anholt [Tue, 18 May 2021 20:56:50 +0000 (13:56 -0700)]
i915g: Make the FS for compile failures write red instead of DIFFUSE.
The DIFFUSE thing would write an undefined result if the shader that
failed to compile didn't read VARYING_SLOT_COL0, causing flakes in CI.
This does make 2 piglit tests that were expecting red spuriously pass.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10874>
Emma Anholt [Mon, 17 May 2021 22:06:34 +0000 (15:06 -0700)]
ci/i915g: Introduce manual testing of i915g using anholt's runner.
Now you can mash the button to see how badly i915g's broken these days.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10874>
Emma Anholt [Mon, 17 May 2021 20:54:10 +0000 (13:54 -0700)]
i915g: Fix dumping of the FS in batchbuffers.
We have to increment off of the packet header before disassembling (same
as i915c's copy of this code).
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10874>
Emma Anholt [Mon, 17 May 2021 20:24:16 +0000 (13:24 -0700)]
i915g: Switch batchbuffer dumping to mesa_logi().
This makes I915_DUMP_CMD=1 actually do something on non-DDEBUG builds.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10874>
Emma Anholt [Mon, 17 May 2021 18:33:26 +0000 (11:33 -0700)]
i915g: Disable 3D-pipeline clears.
The 3D-pipeline fast clears try to emit FS constants before an FS is
necessarily bound, causing segfaults in dEQP. Plus it flushes the whole
batchbuffer so it'll probably be slower anyway.
Fixes:
6358e6371b31 ("i915g: implement hw clear")
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10874>
Emma Anholt [Mon, 17 May 2021 19:08:35 +0000 (12:08 -0700)]
mesa/st: Only use 16-bit ints or floats in the NIR path.
For i915g or other drivers using the draw path, llvmpipe (reasonably)
reports int16 support. However, if we try to link and translate an int16
shader using st_glsl_to_tgsi, it will throw assertion failures.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10874>
Emma Anholt [Mon, 10 May 2021 19:03:48 +0000 (12:03 -0700)]
vulkan: Avoid stomping array padding in the MemoryProperties wrapper.
The deqp test for it expects that the unused array elements are untouched,
so make sure they don't get replaced with random stack data.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10737>
Yiwei Zhang [Mon, 17 May 2021 04:34:06 +0000 (04:34 +0000)]
venus: vn_GetAndroidHardwareBufferPropertiesANDROID (part 2/2)
Support VkAndroidHardwareBufferFormatPropertiesANDROID query.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10847>
Yiwei Zhang [Sun, 16 May 2021 23:59:02 +0000 (23:59 +0000)]
venus: vn_GetAndroidHardwareBufferPropertiesANDROID (part 1/2)
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10847>
Yiwei Zhang [Thu, 20 May 2021 06:05:09 +0000 (06:05 +0000)]
venus: add ahb image and buffer properties query support
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10847>
Yiwei Zhang [Tue, 4 May 2021 23:18:22 +0000 (23:18 +0000)]
venus: add vn_android_get_ahb_usage helper function
See "AHardwareBuffer Usage Equivalence" in the spec.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10847>
Yiwei Zhang [Wed, 5 May 2021 22:11:23 +0000 (22:11 +0000)]
venus: add AHB format and VkFormat conversion helper functions
See "AHardwareBuffer Format Equivalence" in the spec.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10847>
Yiwei Zhang [Fri, 14 May 2021 22:58:34 +0000 (22:58 +0000)]
venus: clean up vn_android api names
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10847>
Erik Faye-Lund [Thu, 20 May 2021 16:32:20 +0000 (18:32 +0200)]
zink: fix provoking-vertex cap for quads
The way we've doing this currently preserves provoking vertex for quads,
so let's report that to the state-tracker.
This fixes a couple of piglits.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10905>
Connor Abbott [Wed, 19 May 2021 16:18:52 +0000 (18:18 +0200)]
ir3: Use round-to-nearest-even for fquantize2f16
We're supposed to map a floating-point value too large to be represented
as fp16 to infinity, however round-to-zero naturally rounds it down to
the largest representable fp16 number instead. The blob emits a bunch of
fixup code to work around this, but instead we can just do what all the
other drivers seem to do and use round-to-nearest-even instead.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10897>
Tomeu Vizoso [Thu, 20 May 2021 14:36:10 +0000 (16:36 +0200)]
panfrost/ci: Add one more flake test for G72
dEQP-GLES31.functional.texture.gather.offset_dynamic.implementation_offset.2d_array.rgba8.size_pot.repeat_mirrored_repeat
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10901>
Daniel Schürmann [Wed, 19 May 2021 13:42:10 +0000 (15:42 +0200)]
aco: remove condition operand from branch in invert block
As value numbering only handles logical blocks, this
could lead to invalid IR until insert_exec_mask().
No fossil-db changes.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10894>
Timur Kristóf [Thu, 20 May 2021 10:43:00 +0000 (12:43 +0200)]
radv/cmd_buffer: Fix warning by initializing instance count.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10806>
Timur Kristóf [Fri, 14 May 2021 15:04:04 +0000 (17:04 +0200)]
nine: Fix uninitialized warning in texture9.c
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Axel Davy <davyaxel0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10806>
Timur Kristóf [Fri, 14 May 2021 15:03:36 +0000 (17:03 +0200)]
gallivm: Fix a few uninitialized variable warnings.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10806>
Timur Kristóf [Fri, 14 May 2021 14:35:29 +0000 (16:35 +0200)]
anv: Fix unused function warnings for memory range checks.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10806>
Timur Kristóf [Fri, 14 May 2021 14:31:13 +0000 (16:31 +0200)]
gallium/tessellator: Fix uninitialized variable warnings.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10806>
Timur Kristóf [Fri, 14 May 2021 13:57:47 +0000 (15:57 +0200)]
aco/util: Initialize IDSet::bits_set to zero.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10806>
Timur Kristóf [Fri, 14 May 2021 13:49:47 +0000 (15:49 +0200)]
aco/insert_exec_mask: Fixed unused variable warning in release build.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10806>
Matti Hamalainen [Thu, 13 May 2021 15:53:41 +0000 (18:53 +0300)]
aux/trace: add missing return value to trace output
trace_screen_resource_bind_backing() was missing printing of
the boolean return value. Add it.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10900>
Georg Lehmann [Wed, 19 May 2021 21:12:28 +0000 (23:12 +0200)]
radv: Fix compatible image handle type for dmabufs.
Reviewed-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Fixes:
6c83e3ea98b7 ("radv: Add format modifier format queries.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10891>
Samuel Pitoiset [Tue, 18 May 2021 07:14:57 +0000 (07:14 +0000)]
radv: fix heap indices when computing the budget
RADV_HEAP_* is the heap type, not the index.
Fixes dEQP-VK.info.device_memory_budget.
Fixes:
08d162f0b57 ("radv: expose 2/3rd of total memory as VRAM and 1/3rd as GTT on APUs")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10852>
Samuel Pitoiset [Mon, 17 May 2021 12:49:24 +0000 (14:49 +0200)]
Revert "radv: Do not access set layout during vkCmdBindDescriptorSets."
This was a temporary workaround for a Baldur's Gate 3 bug which
should now be fixed.
This reverts commit
eb104e949ee4b7e0813d14f11a4a952bae48fe80.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3701
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10839>
Samuel Pitoiset [Mon, 17 May 2021 13:21:13 +0000 (15:21 +0200)]
aco: fix derivatives/intrinsics with SGPR sources
ds_swizzle_b32 requires a VGPR and DPP can't encode SGPR sources.
Fixes
dEQP-VK.graphicsfuzz.cov-derivative-uniform-vector-global-loop-count.
Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10840>
Mike Blumenkrantz [Wed, 14 Apr 2021 14:43:46 +0000 (10:43 -0400)]
aux/trace: trace pipe_screen::resource_create_with_modifiers
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10361>
Alyssa Rosenzweig [Fri, 7 May 2021 17:24:48 +0000 (13:24 -0400)]
panfrost: Streamline varying linking code
Refactor all the linking code with the following objectives:
* Remove linking magic (especially around XFB)
* Cleaner code (obviously)
* Less stage coupling (in case someone ever implements geom/tess)
* Decouple ATTRIBUTE from ATTRIBUTE_BUFFER to enable optimizations
The main hack remaining is doing precision linking here to workaround
linking previously used.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10778>
Alyssa Rosenzweig [Fri, 7 May 2021 23:01:06 +0000 (19:01 -0400)]
glsl: Fix packing of matrices for XFB
The CAP for packed transform feedback concerns packing of unrelated
variables into the same varying slot. (On Mali, transform feedback is
implemented on a per-slot basis, so different variables need different
slots to be written to different buffers.) However, this requirement is
tangential to the packing of arrays, matrices, and structures inherent
to GLSL. These array-like values need to be packed /within/ their slot,
even though drivers using the CAP (just Panfrost) cannot pack
independent values in the slot. Transform feedback of individual
elements is not independent, after all.
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10778>
Alyssa Rosenzweig [Thu, 27 Aug 2020 12:21:40 +0000 (08:21 -0400)]
glsl: Fix subscripted arrays with no XFB packing
We need to duplicate the subscripted members even if they happen to be
aligned, since the other elements may be passed into the consumer
shader. Fixes on Panfrost:
dEQP-GLES3.functional.transform_feedback.array_element.interleaved.lines.highp_float
Note: the test did pass on main previously due to an elaborate set of
driver hacks. I don't believe the old behaviour was correct regardless.
Only Panfrost is affected by this change and the next, as every other
driver sets PIPE_CAP_PACKED_STREAM_OUTPUT.
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10778>
Alyssa Rosenzweig [Tue, 18 May 2021 17:53:52 +0000 (13:53 -0400)]
asahi: Set PACKED_STREAM_OUTPUT
Lazy copypaste from Panfrost. We don't support XFB yet at all, but when
we do, it will almost certainly be the way every other driver in Mesa
does.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10778>
Mike Blumenkrantz [Wed, 21 Apr 2021 18:08:02 +0000 (14:08 -0400)]
aux/trace: pipe_screen::get_dmabuf_modifier_planes
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10387>
Mike Blumenkrantz [Wed, 21 Apr 2021 18:05:39 +0000 (14:05 -0400)]
aux/trace: propagate pipe_screen::transfer_helper pointer
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10387>
Mike Blumenkrantz [Wed, 21 Apr 2021 17:58:35 +0000 (13:58 -0400)]
aux/trace: pipe_context::is_dmabuf_modifier_supported
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10387>
Mike Blumenkrantz [Wed, 21 Apr 2021 17:45:53 +0000 (13:45 -0400)]
aux/trace: pipe_screen::query_dmabuf_modifiers
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10387>
Mike Blumenkrantz [Wed, 21 Apr 2021 17:36:26 +0000 (13:36 -0400)]
aux/trace: support pipe_screen::query_memory_info
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10387>
Iago Toral Quiroga [Tue, 18 May 2021 07:50:17 +0000 (09:50 +0200)]
v3d: take TLB blit framebuffer dimensions from smallest surface dimensions
Typically, we program the framebuffer dimensions using the destination
surface, however, if we blit a rect from a surface that is smaller than
the destination, the simulator will complain that the TLB load stride
is not large enough to match the destination framebuffer. We can work
around this by programming the smallest size of both surfaces, which
should be okay because the tlb blit path requires that the blit
coordinates are the same for both src and dst.
Fixes assert crashes with the simulator for MSAA tests in:
./bin/gl-1.0-logicop
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10863>
Eric Anholt [Mon, 1 Mar 2021 21:03:48 +0000 (13:03 -0800)]
ci/intel: Add test jobs for dEQP.
This covers dEQP-EGL, GL, and GLES on GLK, APL (BXT), and AML-Y
Chromebooks. The GLES tests are fractional runs on some boards to keep
the pipeline time down. Flakes are reported to #intel-ci on freenode.
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10438>
Eric Anholt [Mon, 3 May 2021 17:51:44 +0000 (10:51 -0700)]
ci/deqp: Make DEQP_EXPECTED_RENDERER a required regex for VK like for GLES.
All devices want it, and regexes are nicer for handling more complicated
device names.
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10438>
Ian Romanick [Mon, 10 Aug 2020 22:34:42 +0000 (15:34 -0700)]
nir/algebraic: Add algebraic opt for float comparisons with identical operands.
The flt version could have been added in
56e21647e20d, but our
collective understanding of NaN and comparisons was poor in 2015. The
new "is_a_number" predicate makes the others possible.
All of the helped shaders in shader-db are either from Mad Max or Skia.
Some of the Skia shaders just get decimated by this change:
instructions helped: shaders/skia/580-4.shader_test FS SIMD8: 81 -> 29 (-64.20%) (scheduled: top-down)
I looked at a couple of those shaders, and they had sequences like:
vec1 32 ssa_44 = flt32 ssa_32, ssa_32
vec1 32 ssa_45 = b32csel ssa_44, ssa_43, ssa_0
vec1 32 ssa_46 = fge32 ssa_32, ssa_32
vec1 32 ssa_47 = b32csel ssa_46, ssa_0, ssa_45
vec1 32 ssa_48 = iand ssa_46, ssa_44
vec1 32 ssa_49 = b32csel ssa_48, ssa_43, ssa_0
ssa_44 is replaced with False. Then ssa_47 selects between ssa_0 and
ssa_0, so ssa_47 and ssa_46 are eliminated. ssa_48 is (False && don't
care), so ssa_48 and ssa_49 are eliminated. After that, many
calculations now involve constants of zero, so they are optimized down
too. So it continues until there's not much left!
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
All Intel platforms had similar results. (Tiger Lake shown)
total instructions in shared programs:
21072238 ->
21071386 (<.01%)
instructions in affected programs: 33722 -> 32870 (-2.53%)
helped: 146
HURT: 1
helped stats (abs) min: 1 max: 62 x̄: 5.84 x̃: 2
helped stats (rel) min: 0.19% max: 62.35% x̄: 4.09% x̃: 1.07%
HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel) min: 0.20% max: 0.20% x̄: 0.20% x̃: 0.20%
95% mean confidence interval for instructions value: -7.94 -3.65
95% mean confidence interval for instructions %-change: -5.87% -2.25%
Instructions are helped.
total cycles in shared programs:
856203326 ->
856192238 (<.01%)
cycles in affected programs: 749966 -> 738878 (-1.48%)
helped: 148
HURT: 0
helped stats (abs) min: 1 max: 1226 x̄: 74.92 x̃: 18
helped stats (rel) min: 0.07% max: 49.70% x̄: 2.69% x̃: 0.46%
95% mean confidence interval for cycles value: -104.82 -45.02
95% mean confidence interval for cycles %-change: -4.01% -1.37%
Cycles are helped.
LOST: 4
GAINED: 0
Fossil-db results:
Tiger Lake
Instructions in all programs:
160915223 ->
160898354 (-0.0%)
SENDs in all programs: 6812780 -> 6812780 (+0.0%)
Loops in all programs: 38340 -> 38340 (+0.0%)
Cycles in all programs:
7434144207 ->
7433978462 (-0.0%)
Spills in all programs: 192582 -> 192582 (+0.0%)
Fills in all programs: 304537 -> 304537 (+0.0%)
Ice Lake
Instructions in all programs:
145296298 ->
145279531 (-0.0%)
SENDs in all programs: 6863692 -> 6863692 (+0.0%)
Loops in all programs: 38334 -> 38334 (+0.0%)
Cycles in all programs:
8800257014 ->
8800088384 (-0.0%)
Spills in all programs: 216880 -> 216880 (+0.0%)
Fills in all programs: 334248 -> 334248 (+0.0%)
Skylake
Instructions in all programs:
135891664 ->
135874910 (-0.0%)
SENDs in all programs: 6802946 -> 6802946 (+0.0%)
Loops in all programs: 38331 -> 38331 (+0.0%)
Cycles in all programs:
8444273433 ->
8444130932 (-0.0%)
Spills in all programs: 194839 -> 194839 (+0.0%)
Fills in all programs: 301114 -> 301114 (+0.0%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10012>
Ian Romanick [Mon, 17 Aug 2020 22:26:07 +0000 (15:26 -0700)]
nir/algebraic: Rearrange some logic-joined comparisons and reduce
On Skylake and Broadwell, a single big compute shader in Dirt Rally has
spills and fills *REALLY* helped. That same shader is hurt very
slightly for spills and fills on Ice Lake.
v2: Move the patterns earlier to be nearer other patterns that are
similar. Mark the replacement fmin and fmax exact. Both suggested by
Rhys.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Tiger Lake
total instructions in shared programs:
21073812 ->
21073041 (<.01%)
instructions in affected programs: 77608 -> 76837 (-0.99%)
helped: 522
HURT: 33
helped stats (abs) min: 1 max: 26 x̄: 1.58 x̃: 1
helped stats (rel) min: 0.22% max: 14.29% x̄: 1.29% x̃: 1.02%
HURT stats (abs) min: 1 max: 8 x̄: 1.67 x̃: 1
HURT stats (rel) min: 0.25% max: 3.42% x̄: 1.06% x̃: 0.86%
95% mean confidence interval for instructions value: -1.57 -1.20
95% mean confidence interval for instructions %-change: -1.25% -1.05%
Instructions are helped.
total cycles in shared programs:
856224346 ->
856211096 (<.01%)
cycles in affected programs: 2394231 -> 2380981 (-0.55%)
helped: 603
HURT: 25
helped stats (abs) min: 1 max: 5218 x̄: 59.37 x̃: 28
helped stats (rel) min: 0.06% max: 5.61% x̄: 1.52% x̃: 1.37%
HURT stats (abs) min: 2 max: 21394 x̄: 901.92 x̃: 10
HURT stats (rel) min: 0.02% max: 5.90% x̄: 0.95% x̃: 0.59%
95% mean confidence interval for cycles value: -93.61 51.41
95% mean confidence interval for cycles %-change: -1.50% -1.34%
Inconclusive result (value mean confidence interval includes 0).
LOST: 1
GAINED: 1
Ice Lake
total instructions in shared programs:
20025692 ->
20024554 (<.01%)
instructions in affected programs: 104981 -> 103843 (-1.08%)
helped: 738
HURT: 0
helped stats (abs) min: 1 max: 30 x̄: 1.54 x̃: 1
helped stats (rel) min: 0.31% max: 10.53% x̄: 1.20% x̃: 1.06%
95% mean confidence interval for instructions value: -1.66 -1.43
95% mean confidence interval for instructions %-change: -1.26% -1.14%
Instructions are helped.
total cycles in shared programs:
979474407 ->
979422333 (<.01%)
cycles in affected programs: 4136364 -> 4084290 (-1.26%)
helped: 759
HURT: 59
helped stats (abs) min: 2 max: 11010 x̄: 72.78 x̃: 28
helped stats (rel) min: 0.03% max: 6.43% x̄: 1.23% x̃: 1.02%
HURT stats (abs) min: 1 max: 698 x̄: 53.66 x̃: 8
HURT stats (rel) min: 0.02% max: 24.05% x̄: 1.64% x̃: 0.33%
95% mean confidence interval for cycles value: -97.08 -30.24
95% mean confidence interval for cycles %-change: -1.14% -0.91%
Cycles are helped.
total spills in shared programs: 10568 -> 10569 (<.01%)
spills in affected programs: 102 -> 103 (0.98%)
helped: 0
HURT: 1
total fills in shared programs: 11347 -> 11349 (0.02%)
fills in affected programs: 277 -> 279 (0.72%)
helped: 0
HURT: 1
LOST: 2
GAINED: 2
Skylake
total instructions in shared programs:
18190419 ->
18188523 (-0.01%)
instructions in affected programs: 102502 -> 100606 (-1.85%)
helped: 791
HURT: 0
helped stats (abs) min: 1 max: 676 x̄: 2.40 x̃: 1
helped stats (rel) min: 0.34% max: 20.23% x̄: 1.41% x̃: 1.23%
95% mean confidence interval for instructions value: -4.07 -0.72
95% mean confidence interval for instructions %-change: -1.47% -1.34%
Instructions are helped.
total cycles in shared programs:
960737969 ->
960498951 (-0.02%)
cycles in affected programs: 4435351 -> 4196333 (-5.39%)
helped: 804
HURT: 67
helped stats (abs) min: 1 max: 198540 x̄: 300.54 x̃: 24
helped stats (rel) min: 0.03% max: 25.41% x̄: 1.21% x̃: 0.92%
HURT stats (abs) min: 2 max: 680 x̄: 39.06 x̃: 6
HURT stats (rel) min: 0.05% max: 23.98% x̄: 1.12% x̃: 0.19%
95% mean confidence interval for cycles value: -722.03 173.20
95% mean confidence interval for cycles %-change: -1.15% -0.91%
Inconclusive result (value mean confidence interval includes 0).
total spills in shared programs: 9757 -> 9722 (-0.36%)
spills in affected programs: 138 -> 103 (-25.36%)
helped: 1
HURT: 0
total fills in shared programs: 9861 -> 9576 (-2.89%)
fills in affected programs: 564 -> 279 (-50.53%)
helped: 1
HURT: 0
LOST: 5
GAINED: 2
Broadwell
total instructions in shared programs:
17853870 ->
17852414 (<.01%)
instructions in affected programs: 101276 -> 99820 (-1.44%)
helped: 777
HURT: 0
helped stats (abs) min: 1 max: 264 x̄: 1.87 x̃: 1
helped stats (rel) min: 0.34% max: 8.44% x̄: 1.37% x̃: 1.23%
95% mean confidence interval for instructions value: -2.54 -1.21
95% mean confidence interval for instructions %-change: -1.42% -1.32%
Instructions are helped.
total cycles in shared programs:
1029846029 ->
1029725458 (-0.01%)
cycles in affected programs: 4435791 -> 4315220 (-2.72%)
helped: 813
HURT: 43
helped stats (abs) min: 2 max: 68560 x̄: 149.95 x̃: 24
helped stats (rel) min: 0.02% max: 73.73% x̄: 1.43% x̃: 0.92%
HURT stats (abs) min: 2 max: 726 x̄: 31.12 x̃: 13
HURT stats (rel) min: 0.01% max: 8.43% x̄: 0.62% x̃: 0.31%
95% mean confidence interval for cycles value: -299.58 17.87
95% mean confidence interval for cycles %-change: -1.63% -1.02%
Inconclusive result (value mean confidence interval includes 0).
total spills in shared programs: 20333 -> 20307 (-0.13%)
spills in affected programs: 151 -> 125 (-17.22%)
helped: 1
HURT: 0
total fills in shared programs: 25899 -> 25775 (-0.48%)
fills in affected programs: 573 -> 449 (-21.64%)
helped: 1
HURT: 0
LOST: 5
GAINED: 0
Sandy Bridge, Ivy Bridge, and Haswell had similar results. (Haswell shown)
total instructions in shared programs:
16417658 ->
16416320 (<.01%)
instructions in affected programs: 96495 -> 95157 (-1.39%)
helped: 774
HURT: 0
helped stats (abs) min: 1 max: 18 x̄: 1.73 x̃: 1
helped stats (rel) min: 0.33% max: 9.80% x̄: 1.52% x̃: 1.20%
95% mean confidence interval for instructions value: -1.83 -1.63
95% mean confidence interval for instructions %-change: -1.59% -1.46%
Instructions are helped.
total cycles in shared programs:
1037104346 ->
1037080579 (<.01%)
cycles in affected programs: 3787747 -> 3763980 (-0.63%)
helped: 791
HURT: 53
helped stats (abs) min: 1 max: 5411 x̄: 65.87 x̃: 32
helped stats (rel) min: 0.02% max: 21.17% x̄: 1.44% x̃: 1.18%
HURT stats (abs) min: 2 max: 14160 x̄: 534.72 x̃: 18
HURT stats (rel) min: 0.02% max: 15.37% x̄: 5.70% x̃: 0.54%
95% mean confidence interval for cycles value: -69.39 13.07
95% mean confidence interval for cycles %-change: -1.19% -0.80%
Inconclusive result (value mean confidence interval includes 0).
LOST: 12
GAINED: 2
GM45 and Iron Lake had similar results. (Iron Lake shown)
total instructions in shared programs: 8132855 -> 8132703 (<.01%)
instructions in affected programs: 8782 -> 8630 (-1.73%)
helped: 38
HURT: 0
helped stats (abs) min: 4 max: 4 x̄: 4.00 x̃: 4
helped stats (rel) min: 1.66% max: 3.23% x̄: 1.77% x̃: 1.72%
95% mean confidence interval for instructions value: -4.00 -4.00
95% mean confidence interval for instructions %-change: -1.88% -1.65%
Instructions are helped.
total cycles in shared programs:
238300850 ->
238298568 (<.01%)
cycles in affected programs: 257202 -> 254920 (-0.89%)
helped: 62
HURT: 2
helped stats (abs) min: 4 max: 58 x̄: 36.90 x̃: 50
helped stats (rel) min: 0.15% max: 1.55% x̄: 0.87% x̃: 1.12%
HURT stats (abs) min: 2 max: 4 x̄: 3.00 x̃: 3
HURT stats (rel) min: 0.12% max: 0.22% x̄: 0.17% x̃: 0.17%
95% mean confidence interval for cycles value: -41.34 -29.98
95% mean confidence interval for cycles %-change: -0.95% -0.73%
Cycles are helped.
Fossil-db results:
All Intel platforms had similar results. (Ice Lake shown)
Instructions in all programs:
145296888 ->
145296346 (-0.0%)
SENDs in all programs: 6863696 -> 6863696 (+0.0%)
Loops in all programs: 38334 -> 38334 (+0.0%)
Cycles in all programs:
8800262303 ->
8800258950 (-0.0%)
Spills in all programs: 216880 -> 216880 (+0.0%)
Fills in all programs: 334248 -> 334248 (+0.0%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10012>
Ian Romanick [Fri, 29 Jan 2021 02:15:26 +0000 (18:15 -0800)]
nir/algebraic: Mark some more logic-joined comparison reductions as exact
If the values are known to be numbers, the the replacements are exact.
This is only applied to the patterns with constants. Constants should
always be numbers, and shaders with NaN constants should be handled in a
different way.
No shader-db or fossil-db changes on any Intel platform. The intention
is to make these patterns more future proof.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10012>
Ian Romanick [Wed, 19 Aug 2020 20:35:14 +0000 (13:35 -0700)]
nir/algebraic: Mark some more comparison reductions exact
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
All Haswell and later Intel platforms had similar results. (Tiger Lake shown)
total instructions in shared programs:
21049056 ->
21048939 (<.01%)
instructions in affected programs: 4716 -> 4599 (-2.48%)
helped: 39
HURT: 0
helped stats (abs) min: 1 max: 6 x̄: 3.00 x̃: 3
helped stats (rel) min: 0.99% max: 5.43% x̄: 2.80% x̃: 2.51%
95% mean confidence interval for instructions value: -3.46 -2.54
95% mean confidence interval for instructions %-change: -3.22% -2.38%
Instructions are helped.
total cycles in shared programs:
855141411 ->
855141159 (<.01%)
cycles in affected programs: 54491 -> 54239 (-0.46%)
helped: 28
HURT: 5
helped stats (abs) min: 2 max: 34 x̄: 12.82 x̃: 12
helped stats (rel) min: 0.06% max: 2.73% x̄: 0.94% x̃: 0.75%
HURT stats (abs) min: 2 max: 52 x̄: 21.40 x̃: 6
HURT stats (rel) min: 0.11% max: 2.46% x̄: 0.90% x̃: 0.56%
95% mean confidence interval for cycles value: -13.72 -1.55
95% mean confidence interval for cycles %-change: -1.01% -0.31%
Cycles are helped.
Tiger Lake
Instructions in all programs:
160902191 ->
160899554 (-0.0%)
SENDs in all programs: 6812435 -> 6812435 (+0.0%)
Loops in all programs: 38225 -> 38225 (+0.0%)
Cycles in all programs:
7428581420 ->
7428555881 (-0.0%)
Spills in all programs: 192582 -> 192582 (+0.0%)
Fills in all programs: 304539 -> 304539 (+0.0%)
A lot of fragment shaders in Shadow of the Tomb Raider were helped, and
a bunch of vertex shaders in Octopath Traveler were hurt.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10012>
Ian Romanick [Tue, 25 Feb 2020 23:24:10 +0000 (15:24 -0800)]
nir/algebraic: Equality comparison inversions require sources be numbers
v2: Update A630 expected image checksum for minetest.trace.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Tiger Lake
total instructions in shared programs:
21036690 ->
21049485 (0.06%)
instructions in affected programs: 852085 -> 864880 (1.50%)
helped: 240
HURT: 2514
helped stats (abs) min: 1 max: 46 x̄: 2.45 x̃: 2
helped stats (rel) min: 0.15% max: 4.30% x̄: 0.79% x̃: 0.55%
HURT stats (abs) min: 1 max: 198 x̄: 5.32 x̃: 2
HURT stats (rel) min: 0.06% max: 10.71% x̄: 1.48% x̃: 1.04%
95% mean confidence interval for instructions value: 4.14 5.15
95% mean confidence interval for instructions %-change: 1.23% 1.34%
Instructions are HURT.
total cycles in shared programs:
856045255 ->
855816220 (-0.03%)
cycles in affected programs:
16743786 ->
16514751 (-1.37%)
helped: 790
HURT: 1973
helped stats (abs) min: 1 max: 10766 x̄: 627.97 x̃: 18
helped stats (rel) min: <.01% max: 32.59% x̄: 3.01% x̃: 0.64%
HURT stats (abs) min: 1 max: 4078 x̄: 135.36 x̃: 18
HURT stats (rel) min: <.01% max: 54.56% x̄: 2.80% x̃: 0.82%
95% mean confidence interval for cycles value: -131.36 -34.42
95% mean confidence interval for cycles %-change: 0.88% 1.40%
Inconclusive result (value mean confidence interval and %-change mean confidence interval disagree).
total spills in shared programs: 9771 -> 9766 (-0.05%)
spills in affected programs: 47 -> 42 (-10.64%)
helped: 1
HURT: 0
total fills in shared programs: 9451 -> 9430 (-0.22%)
fills in affected programs: 91 -> 70 (-23.08%)
helped: 1
HURT: 0
LOST: 16
GAINED: 51
All Intel GPUs from Sandybridge through Ice Lake had similar results. (Ice Lake shown)
total instructions in shared programs:
20024781 ->
20025568 (<.01%)
instructions in affected programs: 103309 -> 104096 (0.76%)
helped: 12
HURT: 389
helped stats (abs) min: 1 max: 2 x̄: 1.17 x̃: 1
helped stats (rel) min: 0.20% max: 2.70% x̄: 1.36% x̃: 1.37%
HURT stats (abs) min: 1 max: 8 x̄: 2.06 x̃: 1
HURT stats (rel) min: 0.05% max: 7.14% x̄: 1.25% x̃: 0.95%
95% mean confidence interval for instructions value: 1.78 2.15
95% mean confidence interval for instructions %-change: 1.06% 1.28%
Instructions are HURT.
total cycles in shared programs:
979419070 ->
979439180 (<.01%)
cycles in affected programs: 4968711 -> 4988821 (0.40%)
helped: 60
HURT: 381
helped stats (abs) min: 1 max: 1296 x̄: 96.92 x̃: 26
helped stats (rel) min: <.01% max: 27.10% x̄: 1.64% x̃: 0.65%
HURT stats (abs) min: 1 max: 7320 x̄: 68.04 x̃: 30
HURT stats (rel) min: <.01% max: 19.77% x̄: 1.32% x̃: 0.87%
95% mean confidence interval for cycles value: 10.25 80.95
95% mean confidence interval for cycles %-change: 0.69% 1.15%
Cycles are HURT.
LOST: 1
GAINED: 2
GM45 and Iron Lake had similar results. (Iron Lake shown)
total instructions in shared programs: 8128474 -> 8132527 (0.05%)
instructions in affected programs: 642323 -> 646376 (0.63%)
helped: 12
HURT: 1972
helped stats (abs) min: 1 max: 4 x̄: 3.00 x̃: 4
helped stats (rel) min: 0.72% max: 1.72% x̄: 1.09% x̃: 0.83%
HURT stats (abs) min: 1 max: 16 x̄: 2.07 x̃: 3
HURT stats (rel) min: 0.12% max: 7.14% x̄: 0.77% x̃: 0.70%
95% mean confidence interval for instructions value: 1.99 2.10
95% mean confidence interval for instructions %-change: 0.74% 0.79%
Instructions are HURT.
total cycles in shared programs:
238280994 ->
238294376 (<.01%)
cycles in affected programs: 8841250 -> 8854632 (0.15%)
helped: 84
HURT: 1192
helped stats (abs) min: 4 max: 64 x̄: 12.50 x̃: 8
helped stats (rel) min: 0.02% max: 1.61% x̄: 0.28% x̃: 0.17%
HURT stats (abs) min: 2 max: 198 x̄: 12.11 x̃: 12
HURT stats (rel) min: 0.02% max: 8.03% x̄: 0.28% x̃: 0.14%
95% mean confidence interval for cycles value: 9.65 11.32
95% mean confidence interval for cycles %-change: 0.22% 0.27%
Cycles are HURT.
No fossil-db changes on any Intel platform.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10012>
Ian Romanick [Tue, 25 Feb 2020 18:36:23 +0000 (10:36 -0800)]
nir/algebraic: Invert comparisons less often
This fixes the piglit test range_analysis_fsat_of_nan.shader_test. That
test contains some code like
o = saturate(X) > 0 ? vec4(1.0, 0.0, 0.0, 1.0)
: vec4(0.0, 1.0, 0.0, 1.0);
A clever optimizer will convert this to
o = vec4(float(saturate(X) > 0),
float(!(saturate(X) > 0)),
0, 1);
Due to the ordering of optimizations in the compiler, the `saturate`
operations are removed. This is safe even in the presense of NaN.
o = vec4(float(X > 0), float(!(X > 0)), 0, 1);
Since the calculations are not marked precise, an overzealous
optimizer may reduce this to
o = vec4(float(X > 0), float(X <= 0), 0, 1);
This will result in black being output. The GLSL spec gives quite a bit
of leeway with respect to NaN, but that seems too far. The shader
author asked for a result of red or green. A result of black is still
"undefined behavior," but it's also a little mean.
This also enables CSE to do its job better.
v2: Update A530 expected image checksum for minetest.trace.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4531
Fixes:
0dbda153aae ("nir/algebraic: Flag inexact optimizations")
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Tiger Lake
total instructions in shared programs:
21041563 ->
21041789 (<.01%)
instructions in affected programs: 992066 -> 992292 (0.02%)
helped: 526
HURT: 548
helped stats (abs) min: 1 max: 16 x̄: 2.48 x̃: 2
helped stats (rel) min: 0.04% max: 5.56% x̄: 0.74% x̃: 0.49%
HURT stats (abs) min: 1 max: 27 x̄: 2.80 x̃: 2
HURT stats (rel) min: 0.04% max: 4.55% x̄: 0.59% x̃: 0.38%
95% mean confidence interval for instructions value: -0.00 0.42
95% mean confidence interval for instructions %-change: -0.12% <.01%
Inconclusive result (value mean confidence interval includes 0).
total cycles in shared programs:
855885569 ->
856118189 (0.03%)
cycles in affected programs:
343637248 ->
343869868 (0.07%)
helped: 907
HURT: 541
helped stats (abs) min: 1 max: 7724 x̄: 206.45 x̃: 36
helped stats (rel) min: <.01% max: 29.97% x̄: 1.01% x̃: 0.37%
HURT stats (abs) min: 1 max: 14177 x̄: 776.09 x̃: 31
HURT stats (rel) min: <.01% max: 29.94% x̄: 1.24% x̃: 0.35%
95% mean confidence interval for cycles value: 84.30 237.00
95% mean confidence interval for cycles %-change: -0.32% -0.01%
Inconclusive result (value mean confidence interval and %-change mean confidence interval disagree).
LOST: 3
GAINED: 5
Ice Lake
total instructions in shared programs:
20027107 ->
20025352 (<.01%)
instructions in affected programs: 1068856 -> 1067101 (-0.16%)
helped: 1153
HURT: 273
helped stats (abs) min: 1 max: 14 x̄: 1.83 x̃: 1
helped stats (rel) min: 0.03% max: 5.66% x̄: 0.61% x̃: 0.35%
HURT stats (abs) min: 1 max: 15 x̄: 1.29 x̃: 1
HURT stats (rel) min: 0.16% max: 1.30% x̄: 0.58% x̃: 0.60%
95% mean confidence interval for instructions value: -1.33 -1.13
95% mean confidence interval for instructions %-change: -0.43% -0.34%
Instructions are helped.
total cycles in shared programs:
979499227 ->
979448725 (<.01%)
cycles in affected programs:
344261539 ->
344211037 (-0.01%)
helped: 1079
HURT: 441
helped stats (abs) min: 1 max: 9384 x̄: 147.78 x̃: 48
helped stats (rel) min: <.01% max: 31.83% x̄: 0.90% x̃: 0.33%
HURT stats (abs) min: 1 max: 7220 x̄: 247.07 x̃: 32
HURT stats (rel) min: <.01% max: 31.30% x̄: 1.52% x̃: 0.53%
95% mean confidence interval for cycles value: -70.01 3.56
95% mean confidence interval for cycles %-change: -0.35% -0.05%
Inconclusive result (value mean confidence interval includes 0).
total spills in shared programs: 10564 -> 10568 (0.04%)
spills in affected programs: 143 -> 147 (2.80%)
helped: 0
HURT: 1
total fills in shared programs: 11343 -> 11347 (0.04%)
fills in affected programs: 287 -> 291 (1.39%)
helped: 0
HURT: 1
LOST: 3
GAINED: 2
Skylake
total instructions in shared programs:
18192274 ->
18190128 (-0.01%)
instructions in affected programs: 1000188 -> 998042 (-0.21%)
helped: 1149
HURT: 55
helped stats (abs) min: 1 max: 14 x̄: 1.92 x̃: 1
helped stats (rel) min: 0.04% max: 6.67% x̄: 0.67% x̃: 0.42%
HURT stats (abs) min: 1 max: 2 x̄: 1.05 x̃: 1
HURT stats (rel) min: 0.16% max: 0.55% x̄: 0.27% x̃: 0.26%
95% mean confidence interval for instructions value: -1.87 -1.69
95% mean confidence interval for instructions %-change: -0.67% -0.58%
Instructions are helped.
total cycles in shared programs:
960856054 ->
960728040 (-0.01%)
cycles in affected programs:
340840968 ->
340712954 (-0.04%)
helped: 1079
HURT: 233
helped stats (abs) min: 1 max: 7640 x̄: 170.95 x̃: 46
helped stats (rel) min: <.01% max: 30.20% x̄: 0.96% x̃: 0.28%
HURT stats (abs) min: 1 max: 6864 x̄: 242.23 x̃: 26
HURT stats (rel) min: <.01% max: 34.64% x̄: 2.10% x̃: 0.22%
95% mean confidence interval for cycles value: -135.62 -59.53
95% mean confidence interval for cycles %-change: -0.59% -0.25%
Cycles are helped.
LOST: 15
GAINED: 1
Broadwell
total instructions in shared programs:
17855624 ->
17853580 (-0.01%)
instructions in affected programs: 1012209 -> 1010165 (-0.20%)
helped: 1105
HURT: 52
helped stats (abs) min: 1 max: 13 x̄: 1.90 x̃: 1
helped stats (rel) min: 0.03% max: 6.67% x̄: 0.67% x̃: 0.36%
HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel) min: 0.13% max: 0.52% x̄: 0.26% x̃: 0.25%
95% mean confidence interval for instructions value: -1.86 -1.67
95% mean confidence interval for instructions %-change: -0.68% -0.58%
Instructions are helped.
total cycles in shared programs:
1029905447 ->
1029840699 (<.01%)
cycles in affected programs:
347102680 ->
347037932 (-0.02%)
helped: 1007
HURT: 211
helped stats (abs) min: 1 max: 1360 x̄: 89.76 x̃: 48
helped stats (rel) min: <.01% max: 16.26% x̄: 0.69% x̃: 0.25%
HURT stats (abs) min: 1 max: 1297 x̄: 121.51 x̃: 20
HURT stats (rel) min: <.01% max: 31.31% x̄: 1.21% x̃: 0.20%
95% mean confidence interval for cycles value: -62.39 -43.92
95% mean confidence interval for cycles %-change: -0.47% -0.25%
Cycles are helped.
total spills in shared programs: 20335 -> 20333 (<.01%)
spills in affected programs: 19 -> 17 (-10.53%)
helped: 2
HURT: 0
total fills in shared programs: 25905 -> 25899 (-0.02%)
fills in affected programs: 23 -> 17 (-26.09%)
helped: 2
HURT: 0
LOST: 9
GAINED: 0
Haswell
total instructions in shared programs:
16418516 ->
16417293 (<.01%)
instructions in affected programs: 223785 -> 222562 (-0.55%)
helped: 590
HURT: 67
helped stats (abs) min: 1 max: 15 x̄: 2.19 x̃: 1
helped stats (rel) min: 0.03% max: 6.52% x̄: 0.87% x̃: 0.60%
HURT stats (abs) min: 1 max: 2 x̄: 1.04 x̃: 1
HURT stats (rel) min: 0.04% max: 1.85% x̄: 0.44% x̃: 0.25%
95% mean confidence interval for instructions value: -2.01 -1.71
95% mean confidence interval for instructions %-change: -0.80% -0.67%
Instructions are helped.
total cycles in shared programs:
1037179754 ->
1037084874 (<.01%)
cycles in affected programs:
352541071 ->
352446191 (-0.03%)
helped: 1093
HURT: 182
helped stats (abs) min: 1 max: 888 x̄: 111.03 x̃: 64
helped stats (rel) min: <.01% max: 27.30% x̄: 0.84% x̃: 0.20%
HURT stats (abs) min: 1 max: 6777 x̄: 145.49 x̃: 21
HURT stats (rel) min: <.01% max: 24.10% x̄: 1.99% x̃: 0.29%
95% mean confidence interval for cycles value: -88.10 -60.73
95% mean confidence interval for cycles %-change: -0.58% -0.29%
Cycles are helped.
total spills in shared programs: 17457 -> 17456 (<.01%)
spills in affected programs: 12 -> 11 (-8.33%)
helped: 1
HURT: 0
total fills in shared programs: 20387 -> 20385 (<.01%)
fills in affected programs: 15 -> 13 (-13.33%)
helped: 1
HURT: 0
LOST: 6
GAINED: 1
Ivy Bridge and earlier platforms had similar results. (Ivy Bridge shown)
total instructions in shared programs:
15515482 ->
15513998 (<.01%)
instructions in affected programs: 239739 -> 238255 (-0.62%)
helped: 573
HURT: 57
helped stats (abs) min: 1 max: 20 x̄: 2.73 x̃: 2
helped stats (rel) min: 0.03% max: 9.84% x̄: 0.94% x̃: 0.55%
HURT stats (abs) min: 1 max: 2 x̄: 1.39 x̃: 1
HURT stats (rel) min: 0.09% max: 1.85% x̄: 0.52% x̃: 0.35%
95% mean confidence interval for instructions value: -2.57 -2.14
95% mean confidence interval for instructions %-change: -0.89% -0.73%
Instructions are helped.
total cycles in shared programs:
584509880 ->
584463152 (<.01%)
cycles in affected programs:
11765280 ->
11718552 (-0.40%)
helped: 661
HURT: 152
helped stats (abs) min: 1 max: 3073 x̄: 101.99 x̃: 32
helped stats (rel) min: <.01% max: 34.38% x̄: 1.46% x̃: 0.50%
HURT stats (abs) min: 1 max: 6637 x̄: 136.10 x̃: 15
HURT stats (rel) min: <.01% max: 24.19% x̄: 1.75% x̃: 0.25%
95% mean confidence interval for cycles value: -82.79 -32.16
95% mean confidence interval for cycles %-change: -1.11% -0.61%
Cycles are helped.
LOST: 9
GAINED: 0
Tiger Lake
Instructions in all programs:
160905127 ->
160900949 (-0.0%)
SENDs in all programs: 6812418 -> 6812085 (-0.0%)
Loops in all programs: 38225 -> 38225 (+0.0%)
Cycles in all programs:
7431911114 ->
7433914697 (+0.0%)
Spills in all programs: 192582 -> 192582 (+0.0%)
Fills in all programs: 304539 -> 304537 (-0.0%)
Ice Lake
Instructions in all programs:
145296733 ->
145292370 (-0.0%)
SENDs in all programs: 6863818 -> 6863485 (-0.0%)
Loops in all programs: 38219 -> 38219 (+0.0%)
Cycles in all programs:
8798257570 ->
8800204360 (+0.0%)
Spills in all programs: 216880 -> 216880 (+0.0%)
Fills in all programs: 334250 -> 334248 (-0.0%)
Skylake
Instructions in all programs:
135891485 ->
135887357 (-0.0%)
SENDs in all programs: 6803031 -> 6802698 (-0.0%)
Loops in all programs: 38216 -> 38216 (+0.0%)
Cycles in all programs:
8442221881 ->
8444201959 (+0.0%)
Spills in all programs: 194839 -> 194839 (+0.0%)
Fills in all programs: 301116 -> 301114 (-0.0%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10012>
Ian Romanick [Fri, 26 Feb 2021 15:12:42 +0000 (07:12 -0800)]
nir/algebraic: Tautology replacements require sources be numbers
It seems worth the small amount of damage to give an extra cushion of
not having to debug problems later.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
All Intel platforms had similar results. (Tiger Lake shown)
total instructions in shared programs:
21043197 ->
21043359 (<.01%)
instructions in affected programs: 4409 -> 4571 (3.67%)
helped: 0
HURT: 25
HURT stats (abs) min: 1 max: 16 x̄: 6.48 x̃: 5
HURT stats (rel) min: 0.39% max: 15.38% x̄: 4.59% x̃: 4.40%
95% mean confidence interval for instructions value: 4.37 8.59
95% mean confidence interval for instructions %-change: 2.93% 6.26%
Instructions are HURT.
total cycles in shared programs:
856175986 ->
856176921 (<.01%)
cycles in affected programs: 58908 -> 59843 (1.59%)
helped: 0
HURT: 25
HURT stats (abs) min: 7 max: 70 x̄: 37.40 x̃: 38
HURT stats (rel) min: 0.27% max: 5.63% x̄: 1.87% x̃: 1.39%
95% mean confidence interval for cycles value: 31.11 43.69
95% mean confidence interval for cycles %-change: 1.35% 2.39%
Cycles are HURT.
No fossil-db changes on any Intel platform.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10012>
Ian Romanick [Wed, 5 Aug 2020 17:38:52 +0000 (10:38 -0700)]
nir/algebraic: Remove some optimizations of comparisons with fsat
When most of these patterns were created, we believed, incorrectly, that
fsat(NaN) was NaN. We have since realized that fsat(NaN) is zero.
Originally, this changed the patterns to use is_a_number. This didn't
help any shaders, so it's easier to just drop the optimizations.
This commit crossed paths with
4c3ad4d0658 ("nir/algebraic: mark more
optimization with fsat(NaN) as inexact") and
bc123c396a9
("nir/algebraic: mark some optimizations with fsat(NaN) as inexact").
Given that these don't impact very many shaders, it seems safer to just
remove them.
As discussed in
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8716, I tried
modifying these patterns to use !(b cmp a). Unfortunately, on Intel
GPUs, the results were much worse than just removing the patterns
altogether.
Some other related patterns will be addressed in later commits.
There are still a number of patterns that use the identity fsat(1-X) ==
1 - fsat(X). If X is NaN, the former is zero while the latter is 1.0.
I haven't evaluted these patterns yet. If changes are needed in these
patterns, it should be a separate commit anyway.
v2: Replace arrow `=>` with `->` in comments because the `=>` looks a
lot like `<=` comparison. Suggested by Rhys.
Fixes:
92b75c126bb ("nir/algebraic: Replace checks that a value is between (or not) [0, 1]")
Fixes:
a7f0c57673d ("nir/algebraic: Eliminate useless fsat() on operand of comparison w/value in (0, 1)")
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
All Intel hardware had similar results. (Ice Lake shown)
total instructions in shared programs:
20029060 ->
20029670 (<.01%)
instructions in affected programs: 69236 -> 69846 (0.88%)
helped: 0
HURT: 263
HURT stats (abs) min: 1 max: 20 x̄: 2.32 x̃: 1
HURT stats (rel) min: 0.30% max: 11.11% x̄: 1.35% x̃: 0.98%
95% mean confidence interval for instructions value: 1.86 2.78
95% mean confidence interval for instructions %-change: 1.18% 1.52%
Instructions are HURT.
total cycles in shared programs:
979821278 ->
979834425 (<.01%)
cycles in affected programs: 1476848 -> 1489995 (0.89%)
helped: 49
HURT: 204
helped stats (abs) min: 1 max: 812 x̄: 102.31 x̃: 20
helped stats (rel) min: 0.01% max: 21.43% x̄: 2.23% x̃: 0.52%
HURT stats (abs) min: 2 max: 2600 x̄: 89.02 x̃: 16
HURT stats (rel) min: 0.04% max: 27.27% x̄: 1.49% x̃: 0.72%
95% mean confidence interval for cycles value: 13.18 90.75
95% mean confidence interval for cycles %-change: 0.29% 1.25%
Cycles are HURT.
No fossil-db changes.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10012>
Andres Gomez [Tue, 18 May 2021 09:31:01 +0000 (12:31 +0300)]
ci: Uprev piglit to
9d87cc3d79e ("framework/replay: send backend's subprocess stderr to sys.stderr")
This pulls in a fix for replayer to make the backends send their
stderr to sys.stderr always.
v2:
- Updated piglit results for llvmpipe, softpipe, zink and
radeonsi-stoney.
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> [v1]
Reviewed-by: Martin Peres <martin.peres@mupuf.org> [v1]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10854>
BillKristiansen [Tue, 18 May 2021 17:58:35 +0000 (10:58 -0700)]
d3d12: Sets all SRV descriptors as data-static
As Mesa d3d12 is currently implemented, all resource data is static
at the time a SRV or CBV is created. Therefore, it makes sense for all
descriptors to use the DESCRIPTORS_STATIC_KEEPING_BUFFER_BOUNDS_CHECKS
flag. Use of this flag broadens debug validation and allows some
optimizations in the underlying driver.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10871>
BillKristiansen [Tue, 18 May 2021 17:56:31 +0000 (10:56 -0700)]
d3d12: Fixes stale context bindings after copy, resolve, and clear
Some GL applications, including Blender, are producing rendering
artifacts due to missing resource state barriers.
The d3d12_context keeps track of all resources bound as shader resource
or constant buffers. If any of these resources are used for Copy,
Resolve, or Clear source/target, the context tracking must be updated
so the correct state can be restored before the next draw call.
This change is something of a big hammer. Essentially, if a resource
currently bound as an SRV or CBV gets used for a non-shader access, a
flag is set in the context that invalidates all bindings of the same
type on the same shader stage. Thus the next Draw execution refreshes
the shader views and state transitions state before invoking Draw on the
command list.
A more elegant (and complex) fix would limit the invalidation to
resource state only, rather than also forcing a recreation of resource
views. It is unclear right now whether it is worth the time to
implement a more elegant fix.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10871>
Emma Anholt [Wed, 19 May 2021 15:51:05 +0000 (08:51 -0700)]
ci/freedreno: Mark two more recent intermittent a530 flakes.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10886>
Nanley Chery [Fri, 14 May 2021 14:47:31 +0000 (07:47 -0700)]
iris: Prefer more GPU-based uploads for compression
Where possible, start compressing depth and stencil resources on upload.
This makes a couple of benchmarks (CS:GO, GFXBench5's gl_alu2_off) start
sampling HiZ buffers in a compressed state instead of the pass-through
state.
Improves the FPS of GFXBench5's gl_alu2_off by 3.14% ±0.52% on TGL.
Testing was done with the performance CI.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2617
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10872>
Nanley Chery [Fri, 14 May 2021 14:47:17 +0000 (07:47 -0700)]
isl: Add isl_aux_usage_has_compression
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10872>
Eric Engestrom [Wed, 19 May 2021 20:34:56 +0000 (22:34 +0200)]
docs/release-calendar: add the schedule for the 21.1 branch
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10890>
Eric Engestrom [Wed, 19 May 2021 20:30:04 +0000 (22:30 +0200)]
docs: update calendar and link releases notes for 21.1.1
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10890>
Eric Engestrom [Wed, 19 May 2021 20:30:00 +0000 (22:30 +0200)]
docs: update calendar and link releases notes for 21.1.0
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10890>
Eric Engestrom [Wed, 19 May 2021 18:16:06 +0000 (20:16 +0200)]
docs: add release notes for 21.1.1
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10890>
Eric Engestrom [Wed, 5 May 2021 17:04:04 +0000 (19:04 +0200)]
docs: add release notes for 21.1.0
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10890>
Connor Abbott [Mon, 17 May 2021 16:57:58 +0000 (18:57 +0200)]
ir3/cf: Rewrite pass
The old pass had a few bugs:
- It tried to avoid folding f2f32 into f2f16, but didn't consider
conversions that were already folded in.
- It didn't prevent folding an f2f16 or f2f32 into a non-floating-point
op.
In addition it wasn't written in a manner which made handling integer
conversions practical. This rewrites the pass to instead calculate the
"type" of the conversion source and then check whether folding the
conversion is allowed. This allows us to cleanly separate the
declarative part where we describe how the HW works from the policy part
where we decide whether the transform is allowed, and makes it simple to
add support for folding integer conversions.
Closes: #3208
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10859>
Pierre-Eric Pelloux-Prayer [Mon, 17 May 2021 13:52:49 +0000 (15:52 +0200)]
radeonsi: enable glsl_correct_derivatives_after_discard by default
Enabling this option by default allows the nir_opt_move_discards_to_top
to be used more often.
This is only done for LLVM13+ since doing this on LLVM11 hurts a lot of
shaders.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10522>
Pierre-Eric Pelloux-Prayer [Thu, 29 Apr 2021 09:26:49 +0000 (11:26 +0200)]
radeonsi/nir: enable nir_opt_move_discards_to_top pass
Since it affects discards and demotes, this commit also moves the
usage of nir_lower_discard_or_demote ealier.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10522>
Jason Ekstrand [Wed, 4 Jul 2018 00:39:15 +0000 (17:39 -0700)]
nir: Add a discard optimization pass
Many fragment shaders do a discard using relatively little information
but still put the discard fairly far down in the shader for no good
reason. If the discard is moved higher up, we can possibly avoid doing
some or almost all of the work in the shader. When this lets us skip
texturing operations, it's an especially high win.
One of the biggest offenders here is DXVK. The D3D APIs have different
rules for discards than OpenGL and Vulkan. One effective way (which is
what DXVK uses) to implement DX behavior on top of GL or Vulkan is to
wait until the very end of the shader to discard. This ends up in the
pessimal case where we always do all of the work before discarding.
This pass helps some DXVK shaders significantly.
v2 (Jason Ekstrand):
- Fix a couple of typos (Grazvydas, Ian)
- Use the new nir_instr_move helper
- Find all movable discards before moving anything so we don't
accidentally re-order anything and break dependencies
v3 (Pierre-Eric): remove the call to nir_opt_conditional_discard based
on Daniel Schürmann comment.
v4 (Pierre-Eric):
- handle demote intrinsics and drop derivatives_safe_after_discard
- add early return if discards/demotes aren't used
v5 (Pierre-Eric):
- use pass_flags instead of instr set (Daniel Schürmann)
v6 (Daniel Schürmann):
- cleanup and fix pass_flags handling
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10522>
Jason Ekstrand [Fri, 13 Nov 2020 06:14:04 +0000 (00:14 -0600)]
nir/gather_info: Expose a nir_intrinsic_writes_external_memory helper
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10522>
Jason Ekstrand [Wed, 4 Jul 2018 16:10:28 +0000 (09:10 -0700)]
nir: Add a nir_instr_move helper
Removes an instruction from one place and inserts it at another while
working around a weird cursor corner-case.
v2: change return value to bool (Daniel Schürmann)
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> (v1)
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10522>
Lucas Stach [Fri, 13 Nov 2020 13:26:23 +0000 (14:26 +0100)]
gallium/dri: copy image use in dup_image
Don't lose the use flags when dup'ing an image.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8106>
Lucas Stach [Tue, 15 Dec 2020 13:59:21 +0000 (14:59 +0100)]
loader/dri: hook up createImageWithModifiers2
Call into the new modifiers with usage createImage variant when available
to provide the DRI implementation with more context about the allocation.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8106>
Simon Ser [Sun, 22 Dec 2019 20:49:10 +0000 (21:49 +0100)]
i965: implement createImageWithModifiers2
This implements __DRIimageExtension version 19.
Signed-off-by: Simon Ser <contact@emersion.fr>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8106>
Simon Ser [Sun, 22 Dec 2019 20:47:42 +0000 (21:47 +0100)]
gallium/dri: implement createImageWithModifiers2
This implements __DRIimageExtension version 19.
Signed-off-by: Simon Ser <contact@emersion.fr>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8106>
Simon Ser [Mon, 14 Dec 2020 17:32:47 +0000 (18:32 +0100)]
dri: add createImageWithModifiers2 interface
With the addition of createImageWithModifiers usage flags were
dropped, as it was believed at the time that modifers will be a
full replacement for the usage flags. This has turned out to be
untrue, as modifiers are not able to describe buffer placement.
Add a new version of the interface, that allows to specifiy
use flags in addition to the modifier.
Signed-off-by: Simon Ser <contact@emersion.fr>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8106>
Lucas Stach [Tue, 15 Dec 2020 13:52:28 +0000 (14:52 +0100)]
loader/dri3: convert to loader_dri_create_image
Get rid of the code duplication and makes it easier to hook in a
new createImageWithModifiers2, but obscures the code flow a bit.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8106>
Lucas Stach [Tue, 15 Dec 2020 13:39:32 +0000 (14:39 +0100)]
dri: add loader_dri_create_image helper
The DRI image extension already has two different ways to allocate an
image (with and without a modifier) and will soon grow a third one.
Add a helper, which handles calling the appropriate implementation to
get rid of code duplication in the winsys.
This convert the two obvious call sites (GBM dri and EGL wayland)
that profit from the code dedup.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8106>
Erico Nunes [Thu, 13 May 2021 19:02:44 +0000 (21:02 +0200)]
lima: add reload command to the command dump
This was not being included in the command stream and may be
useful to debug further issues.
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10791>
Erico Nunes [Wed, 12 May 2021 23:40:46 +0000 (01:40 +0200)]
lima: enable z16 format
Other than listing the format as supported, an extra detail is to unset
one bit in the render state depth_test when a z16 texture needs to be
reloaded before rendering, following the mali blob behavior.
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10791>
Jason Ekstrand [Sun, 2 May 2021 22:19:02 +0000 (17:19 -0500)]
intel/vec4: Add support for UBO pushing
Shader-db results on Haswell (vec4 only):
total instructions in shared programs: 2853928 -> 2726576 (-4.46%)
instructions in affected programs: 855840 -> 728488 (-14.88%)
helped: 9500
HURT: 18
helped stats (abs) min: 1 max: 359 x̄: 13.54 x̃: 11
helped stats (rel) min: 0.44% max: 53.33% x̄: 19.13% x̃: 17.44%
HURT stats (abs) min: 4 max: 124 x̄: 71.00 x̃: 92
HURT stats (rel) min: 3.64% max: 77.86% x̄: 46.43% x̃: 52.12%
95% mean confidence interval for instructions value: -13.78 -12.98
95% mean confidence interval for instructions %-change: -19.21% -18.81%
Instructions are helped.
total cycles in shared programs:
101822616 ->
60245580 (-40.83%)
cycles in affected programs:
93312382 ->
51735346 (-44.56%)
helped: 13292
HURT: 4506
helped stats (abs) min: 2 max: 1229260 x̄: 3370.82 x̃: 776
helped stats (rel) min: 0.04% max: 96.70% x̄: 47.56% x̃: 43.76%
HURT stats (abs) min: 2 max: 17644 x̄: 716.37 x̃: 82
HURT stats (rel) min: 0.02% max: 491.80% x̄: 41.00% x̃: 11.11%
95% mean confidence interval for cycles value: -3037.07 -1635.03
95% mean confidence interval for cycles %-change: -26.03% -24.25%
Cycles are helped.
total spills in shared programs: 1080 -> 1314 (21.67%)
spills in affected programs: 74 -> 308 (316.22%)
helped: 0
HURT: 47
total fills in shared programs: 310 -> 497 (60.32%)
fills in affected programs: 71 -> 258 (263.38%)
helped: 0
HURT: 47
total sends in shared programs: 239884 -> 151799 (-36.72%)
sends in affected programs: 129302 -> 41217 (-68.12%)
helped: 9547
HURT: 0
helped stats (abs) min: 1 max: 226 x̄: 9.23 x̃: 8
helped stats (rel) min: 3.12% max: 98.15% x̄: 72.38% x̃: 80.00%
95% mean confidence interval for sends value: -9.48 -8.98
95% mean confidence interval for sends %-change: -72.80% -71.97%
Sends are helped.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10571>
Jason Ekstrand [Sun, 2 May 2021 18:54:01 +0000 (13:54 -0500)]
intel/vec4: Add support for masking pushed data
This is the vec4 equivalent of
d0d039a4d3f4, required for proper UBO
pushing in vertex stages for Vulkan on HSW. Sadly, the implementation
requires us to do everything in ALIGN1 mode and the vec4 instruction
scheduler doesn't understand HW_GRF <-> UNIFORM interference so it's
easier to do the whole thing in the generator. We add an instruction
to the top of the program which just means "emit the blob" and all the
magic happens in codegen.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10571>
Jason Ekstrand [Tue, 4 May 2021 15:40:17 +0000 (10:40 -0500)]
intel/vec4: Set up push ranges before we emit any code
In order to avoid switching pull constants to push constants and then
having to back to pull, compute the push ranges up-front. This way we
know by the time we emit code exactly what ranges are pushable. This is
a bit inefficient in the case where the "normal" push constants get
compacted. However, most apps don't use giant piles of dead uniforms
combined with substantial UBO use so this should be ok.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10571>
Jason Ekstrand [Tue, 4 May 2021 14:38:55 +0000 (09:38 -0500)]
intel/vec4: Update nr_params in pack_uniform_registers
This is where we re-arrange and re-pack the params.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10571>
Jason Ekstrand [Mon, 3 May 2021 20:34:41 +0000 (15:34 -0500)]
intel/vec4: Add some asserts to move_push_to_pull
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10571>
Jason Ekstrand [Tue, 4 May 2021 20:30:27 +0000 (15:30 -0500)]
intel/vec4: Don't spill fp64 registers more than once
The way we handle spilling for fp64 in vec4 is to emit a series of MOVs
which swizzles the data around and then a pair of 32-bit spills. This
works great except that the next time we go to pick a spill reg, the
compiler isn't smart enough to figure out that the register has already
been spilled. Normally we do this by looking at the sources of spill
instructions (or destinations of fills) but, because it's separated from
the actual value by a MOV, we can't see it. This commit adds a new
opcode VEC4_OPCODE_MOV_FOR_SCRATCH which is identical to MOV in
semantics except that it lets RA know not to spill again.
Fixes:
82c69426a5a3 "i965/vec4: support basic spilling of 64-bit registers"
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10571>
Jason Ekstrand [Tue, 4 May 2021 04:08:42 +0000 (23:08 -0500)]
anv: Push at most 32 regs for vec4 shaders
The vec4 back-end can't push UBOs just yet but it soon will be able.
When it starts pushing UBOs, it will have a lower limit than scalar due
to a crummy register allocator. Mirror that limit in ANV so we don't
run into asserts due to ANV and the back-end making different choices.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10571>
Jason Ekstrand [Sun, 2 May 2021 22:55:15 +0000 (17:55 -0500)]
anv: Support pushing shader constants
Usually, nir_opt_constant_folding will get rid of any load_constant
intrinsics which might possibly be pushed but there are rare cases where
we can still end up with them. Better to handle them.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10571>
Jason Ekstrand [Sun, 2 May 2021 22:54:57 +0000 (17:54 -0500)]
anv: Plumb the shader into push constant helpers
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10571>
Rhys Perry [Mon, 17 May 2021 13:37:54 +0000 (14:37 +0100)]
aco: disallow SGPRs on DPP instructions
They can't be encoded.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10841>
Jose Fonseca [Thu, 13 May 2021 11:48:30 +0000 (12:48 +0100)]
d3d10umd: Avoid duplication in CreateDevice.
As suggested by Jesse Natalie.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10687>
Jose Fonseca [Wed, 5 May 2021 13:51:34 +0000 (14:51 +0100)]
d3d10sw: Add a sanity test.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10687>
Jose Fonseca [Wed, 5 May 2021 10:57:43 +0000 (11:57 +0100)]
d3d10umd,d3d10sw: Initial import.
This change adds a gallium D3D10 state tracker that works as a WDDM UMD
software driver, similar to Microsoft WARP, but using llvmpipe/softpipe.
The final deliverable is a d3d10sw.dll, which is similar to WARP's
d3d10warp.dll.
This has been used to run Microsoft Windows HCK wgf11* tests with
llvmpipe, and they were at one point passing 100%.
Known limitations:
- TGSI (no NIR)
- D3D10 only (no D3D11 support yet)
- no WINE integration (WINE doesn't implement WDDM DDI.)
For further details see:
- src/gallium/frontends/d3d10umd/README.md
- src/gallium/targets/d3d10sw/README.md
v2: Drop the DXBC-based disassembly. Add missing break statements.
v3: Incorporate Jesse's feedback.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10687>