Reid Kleckner [Mon, 23 Oct 2017 22:44:51 +0000 (22:44 +0000)]
[PDB] Fix logging of bad type indices
llvm-svn: 316386
Reid Kleckner [Mon, 23 Oct 2017 22:44:24 +0000 (22:44 +0000)]
[codeview] Recognize two records with no type index fields
Thunk records do not have types and frame cookies do not have types.
These were found while linking libconcrt.lib from MSVC.
llvm-svn: 316385
Rong Xu [Mon, 23 Oct 2017 22:21:29 +0000 (22:21 +0000)]
[PM] Add pgo-memop-opt pass to the new pass manager
This pass adds pgo-memop-opt pass to the new pass manager.
It is in the old pass manager but somehow left out in the new pass manager.
Differential Revision: http://reviews.llvm.org/D39145
llvm-svn: 316384
Simon Pilgrim [Mon, 23 Oct 2017 22:05:02 +0000 (22:05 +0000)]
[X86][SSE] combineBitcastvxi1 - use PACKSSWB directly to pack v8i16 to v16i8
Avoid difficulties determining the number of sign bits later on in shuffle lowering to lower to PACKSS
llvm-svn: 316383
Alex Shlyapnikov [Mon, 23 Oct 2017 22:04:30 +0000 (22:04 +0000)]
[libFuzzer] Periodically purge allocator's quarantine to prolong fuzzing sessions.
Summary:
Fuzzing targets that allocate/deallocate a lot of memory tend to consume
a lot of RSS when ASan quarantine is enabled. Purging quarantine between
iterations and returning memory to OS keeps RSS down and should not
reduce the quarantine effectiveness provided the fuzz target does not
preserve state between iterations (in this case this feature can be turned off).
Based on D39153.
Reviewers: vitalybuka
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D39155
llvm-svn: 316382
Volodymyr Sapsai [Mon, 23 Oct 2017 22:01:41 +0000 (22:01 +0000)]
[Sema] Add support for flexible array members in Obj-C.
Allow Obj-C ivars with incomplete array type but only as the last ivar.
Also add a requirement for ivars that contain a flexible array member to
be at the end of class too. It is possible to add in a subclass another
ivar at the end but we'll emit a warning in this case. Also we'll emit a
warning if a variable sized ivar is declared in class extension or in
implementation because subclasses won't know they should avoid adding
new ivars.
In ARC incomplete array objects are treated as __unsafe_unretained so
require them to be marked as such.
Prohibit synthesizing ivars with flexible array members because order of
synthesized ivars is not obvious and tricky to control. Spelling out
ivar explicitly gives control to developers and helps to avoid surprises
with unexpected ivar ordering.
For C and C++ changed diagnostic to tell explicitly a field is not the
last one and point to the next field. It is not as useful as in Obj-C
but it is an improvement and it is consistent with Obj-C. For C for
unions emit more specific err_flexible_array_union instead of generic
err_field_incomplete.
rdar://problem/
21054495
Reviewers: rjmccall, theraven
Reviewed By: rjmccall
Subscribers: cfe-commits
Differential Revision: https://reviews.llvm.org/D38773
llvm-svn: 316381
Bob Wilson [Mon, 23 Oct 2017 21:51:50 +0000 (21:51 +0000)]
Add a new Simulator entry for the target triple environment.
Apple's iOS, tvOS and watchOS simulator platforms have never been clearly
distinguished in the target triples. Even though they are intended to
behave similarly to the corresponding device platforms, they have separate
SDKs and are really separate platforms from the compiler's perspective.
Clang now defines a macro when building for one of these simulator platforms
(r297866) but that relies on the very indirect mechanism of checking to see
which option was used to specify the minimum deployment target. That is not
so great. Swift would also like to distinguish these simulator platforms in
a similar way, but unlike Clang, Swift does not use a separate option to
specify the minimum deployment target -- it uses a -target option to
specify the target triple directly, including the OS version number.
Using a different target triple for the simulator platforms is a much
more direct and obvious way to specify this. Putting the "simulator" in
the environment component of the triple means the OS values can stay the
same and existing code the looks at the OS field will not be affected.
https://reviews.llvm.org/D39143
rdar://problem/
34729432
llvm-svn: 316380
Petr Hosek [Mon, 23 Oct 2017 21:31:05 +0000 (21:31 +0000)]
[Driver] Use ld.lld directly for Fuchsia rather than passing flavor
Passing a flavor to LLD requires command line argument, but if these
are being passed through a response file, this will fail because LLD
needs to know which driver to use before processing the response file.
Use ld.lld directly instead to avoid this issue.
Differential Revision: https://reviews.llvm.org/D39176
llvm-svn: 316379
Rafael Espindola [Mon, 23 Oct 2017 21:12:19 +0000 (21:12 +0000)]
Make Ctx a plain pointer again.
If a struct has a std::unique_ptr member, the logical interpretation
is that that member will be destroyed with the struct.
That is not the case for Ctx. It is has to be deleted earlier and its
lifetime is defined by the functions where the AddressState is
created.
llvm-svn: 316378
George Burgess IV [Mon, 23 Oct 2017 21:08:02 +0000 (21:08 +0000)]
Fix buildbot breakage
SP is only used in an assert. Caused by r316374.
llvm-svn: 316377
Rafael Espindola [Mon, 23 Oct 2017 21:00:15 +0000 (21:00 +0000)]
Document a change of behavior in r315552.
We used to reject this, but we now accept. The output seems
reasonable, so this is probably an OK extension over bfd/gold.
llvm-svn: 316376
Mitch Phillips [Mon, 23 Oct 2017 20:54:01 +0000 (20:54 +0000)]
Made llvm-cfi-verify not execute unit tests on non-x86 builds.
Patched out from D38427.
Reviewers: vlad.tsyrklevich
Reviewed By: vlad.tsyrklevich
Subscribers: llvm-commits, kcc, pcc, mgorny
Differential Revision: https://reviews.llvm.org/D39197
llvm-svn: 316375
George Burgess IV [Mon, 23 Oct 2017 20:46:36 +0000 (20:46 +0000)]
Don't crash when we see unallocatable registers in clobbers
This fixes a bug where we'd crash given code like the test-case from
https://bugs.llvm.org/show_bug.cgi?id=30792 . Instead, we let the
offending clobber silently slide through.
This doesn't fully fix said bug, since the assembler will still complain
the moment it sees a crypto/fp/vector op, and we still don't diagnose
calls that require vector regs.
Differential Revision: https://reviews.llvm.org/D39030
llvm-svn: 316374
Mitch Phillips [Mon, 23 Oct 2017 20:25:19 +0000 (20:25 +0000)]
Graph builder implementation.
Implement a localised graph builder for indirect control flow
instructions. Main interface is through GraphBuilder::buildFlowGraph,
which will build a flow graph around an indirect CF instruction. Various
modifications to FileVerifier are also made to const-expose some members
needed for machine code analysis done by the graph builder.
Reviewers: vlad.tsyrklevich
Reviewed By: vlad.tsyrklevich
Subscribers: llvm-commits, kcc, pcc
Differential Revision: https://reviews.llvm.org/D38427
llvm-svn: 316372
Stefan Pintilie [Mon, 23 Oct 2017 20:22:23 +0000 (20:22 +0000)]
Revert "[PowerPC] Try to simplify a Swap if it feeds a Splat"
Revert commit r316366.
Previous commit causes p8-scalar_vector_conversions.ll to fail.
This reverts commit
990e764ad8a2eec206ce5dda6aefab059ccd4e92.
llvm-svn: 316371
Rui Ueyama [Mon, 23 Oct 2017 20:03:32 +0000 (20:03 +0000)]
lld::COFF: better behavior when using as a library
Previously, the COFF driver would call exit(0) when called
as a library. Now it takes `ExitEarly` option, and if it
is false, it doesn't exit. So it is now more library-friendly.
Furthermore, link() calls freeArena() before returning, to
clean up resources.
Based on an Andrew Kelley's patch.
Differential Revision: https://reviews.llvm.org/D39202
llvm-svn: 316370
Mandeep Singh Grang [Mon, 23 Oct 2017 19:56:52 +0000 (19:56 +0000)]
[GVNSink] Fix failing GVNSink tests in the reverse iteration bot
Summary:
The elts of ActivePreds which is defined as a SmallPtrSet are copied
into Blocks using std::copy. This makes the resultant order of Blocks
non-deterministic. We cannot simply sort Blocks as they need to match
the corresponding Values. So a better approach is to define ActivePreds
as SmallSetVector.
This fixes the following failures in
http://lab.llvm.org:8011/builders/reverse-iteration:
LLVM :: Transforms/GVNSink/indirect-call.ll
LLVM :: Transforms/GVNSink/sink-common-code.ll
LLVM :: Transforms/GVNSink/struct.ll
Reviewers: dberlin, jmolloy, bkramer, efriedma
Reviewed By: dberlin
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D39025
llvm-svn: 316369
Pavel Labath [Mon, 23 Oct 2017 19:41:17 +0000 (19:41 +0000)]
Logging: Disable logging after fork()
Summary:
We had a bug where if we had forked (in the ProcessLauncherPosixFork)
while another thread was writing a log message, we would deadlock. This
happened because the fork child inherited the locked log rwmutex, which
would never get unlocked. This meant the child got stuck trying to
disable all log channels.
The bug existed for a while but only started being apparent after
D37930, which started using ThreadLauncher (which uses logging) instead
of std::thread (which does not) for launching TaskPool threads.
The fix is to use pthread_atfork to disable logging in the forked child.
Reviewers: zturner, eugene, clayborg
Subscribers: lldb-commits
Differential Revision: https://reviews.llvm.org/D38938
llvm-svn: 316368
Krzysztof Parzyszek [Mon, 23 Oct 2017 19:35:25 +0000 (19:35 +0000)]
[Hexagon] Return the correct chain edge for i1 function calls
In HexagonISelLowering, there is code to handle the case when
a function returns an i1 type. In this case, we need to generate
extra nodes to copy the result from R0 to a predicate register.
The code was returning the wrong value for the chain edge which
caused an assert "Wrong topological sorting" when converting the
instructions to MIs.
This patch fixes the problem by returning the chain for the final
copy.
Patch by Brendon Cahoon.
llvm-svn: 316367
Stefan Pintilie [Mon, 23 Oct 2017 19:33:31 +0000 (19:33 +0000)]
[PowerPC] Try to simplify a Swap if it feeds a Splat
If we have the situation where a Swap feeds a Splat we can sometimes change the
index on the Splat and then remove the Swap instruction.
Differential Revision: https://reviews.llvm.org/D39009
llvm-svn: 316366
Konstantin Zhuravlyov [Mon, 23 Oct 2017 19:31:31 +0000 (19:31 +0000)]
LLD: Fix large integer implicitly truncated to unsigned type gcc warning
This fixes gcc warning.
Change by Brian Sumner
llvm-svn: 316365
Martin Storsjo [Mon, 23 Oct 2017 19:29:36 +0000 (19:29 +0000)]
Abstract rwlocks into a class, provide a SRW lock implementation for windows
This requires _WIN32_WINNT >= 0x0600.
If someone wants to spend effort on supporting earlier versions,
one can easily add another fallback implementation based on
critical sections, or try to load SRW lock functions dynamically.
This makes sure that the FDE cache is thread safe on windows.
Differential Revision: https://reviews.llvm.org/D38704
llvm-svn: 316364
Krzysztof Parzyszek [Mon, 23 Oct 2017 19:07:50 +0000 (19:07 +0000)]
[Hexagon] Add extra pattern for S4_addaddi
One combination was missing: add(add(x,y),c).
llvm-svn: 316363
Jonas Hahnfeld [Mon, 23 Oct 2017 19:01:35 +0000 (19:01 +0000)]
[OpenMP] Avoid VLAs for some reductions on array sections
In some cases the compiler can deduce the length of an array section
as constants. With this information, VLAs can be avoided in place of
a constant sized array or even a scalar value if the length is 1.
Example:
int a[4], b[2];
pragma omp parallel reduction(+: a[1:2], b[1:1])
{ }
For chained array sections, this optimization is restricted to cases
where all array sections except the last have a constant length 1.
This trivially guarantees that there are no holes in the memory region
that needs to be privatized.
Example:
int c[3][4];
pragma omp parallel reduction(+: c[1:1][1:2])
{ }
This relands commit r316229 that I reverted in r316235 because it
failed on some bots. During investigation I found that this was because
Clang and GCC evaluate the two arguments to emplace_back() in
ReductionCodeGen::emitSharedLValue() in a different order, hence
leading to a different order of generated instructions in the final
LLVM IR. Fix this by passing in the arguments from temporary variables
that are evaluated in a defined order.
Differential Revision: https://reviews.llvm.org/D39136
llvm-svn: 316362
Jonas Hahnfeld [Mon, 23 Oct 2017 18:41:22 +0000 (18:41 +0000)]
Fix FormatVariadicTest with GCC
Looks like GCC didn't like the original specialization, try within namespace.
llvm-svn: 316361
Daniel Sanders [Mon, 23 Oct 2017 18:19:24 +0000 (18:19 +0000)]
[globalisel][tablegen] Import stores and allow GISel to automatically substitute zero regs like WZR/XZR/$zero.
This patch enables the import of stores. Unfortunately, doing so by itself,
loses an optimization where storing 0 to memory makes use of WZR/XZR.
To mitigate this, this patch also introduces a new feature that allows register
operands to nominate a zero register. When this is done, GlobalISel will
substitute (G_CONSTANT 0) with the nominated register automatically. This
is currently configured to only apply to the stores.
Applying it to GPR32/GPR64 register classes in general will be done after
review see (https://reviews.llvm.org/D39150).
llvm-svn: 316360
Mitch Phillips [Mon, 23 Oct 2017 18:17:56 +0000 (18:17 +0000)]
Accidently merged an incomplete upstream patch in
10e6ee563a6b5ca498f27972ca6dbe6c308f1ac2 - reverting the changes.
llvm-svn: 316359
Mitch Phillips [Mon, 23 Oct 2017 18:11:31 +0000 (18:11 +0000)]
Patch in
llvm-svn: 316358
Vedant Kumar [Mon, 23 Oct 2017 18:04:34 +0000 (18:04 +0000)]
[wasm] readSection: Avoid reading past eof (fixes oss-fuzz #3219)
A wasm file crafted with a bogus section size can trigger an ASan issue
in the DWARFObjInMemory constructor. Nip the problem in the bud when we
read the wasm section.
Found by OSS-Fuzz:
https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=3219
Differential Revision: https://reviews.llvm.org/D38777
llvm-svn: 316357
Alex Shlyapnikov [Mon, 23 Oct 2017 17:58:16 +0000 (17:58 +0000)]
[Sanitizers] Add total primary allocator RSS to allocator report.
Summary: .
Reviewers: cryptoad
Subscribers: llvm-commits, kubamracek
Differential Revision: https://reviews.llvm.org/D39131
llvm-svn: 316356
Davide Italiano [Mon, 23 Oct 2017 17:51:22 +0000 (17:51 +0000)]
[lldbtest] Simplify removing an unneeded else. NFCI.
llvm-svn: 316355
Simon Pilgrim [Mon, 23 Oct 2017 17:50:40 +0000 (17:50 +0000)]
[X86][SSE] Regenerate PACKSS tests on 32 + 64-bit targets
llvm-svn: 316354
Yaxun Liu [Mon, 23 Oct 2017 17:49:26 +0000 (17:49 +0000)]
CodeGen: Fix invalid bitcast in partial initialization of automatic arrary variable
Differential Revision: https://reviews.llvm.org/D39184
llvm-svn: 316353
Mitch Phillips [Mon, 23 Oct 2017 17:37:41 +0000 (17:37 +0000)]
Updated 'Getting Started' to use valid git links (added trailing slashes)
Reviewers: pcc, asl, tonic
Reviewed By: pcc
Subscribers: llvm-commits, kcc
Differential Revision: https://reviews.llvm.org/D38516
llvm-svn: 316352
Sanjay Patel [Mon, 23 Oct 2017 17:30:17 +0000 (17:30 +0000)]
[PassManager] add test to show the new PM uses -latesimplifycfg early; NFC
llvm-svn: 316351
Daniel Sanders [Mon, 23 Oct 2017 17:18:44 +0000 (17:18 +0000)]
[globalisel] Add very brief docs summarizing the ISel part of the LLVMDev tutorial.
Also added links to the talks available.
llvm-svn: 316350
Matt Arsenault [Mon, 23 Oct 2017 17:16:43 +0000 (17:16 +0000)]
AMDGPU: Cleanup local atomic node names
llvm-svn: 316349
Evgeniy Stepanov [Mon, 23 Oct 2017 17:13:24 +0000 (17:13 +0000)]
Revert "[Compiler-rt][MIPS] Fix cross build for XRAY."
Breaks build:
http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux/builds/4677/steps/build%20with%20ninja/logs/stdio
In file included from compiler-rt/lib/xray/xray_fdr_logging.cc:34:
In file included from compiler-rt/lib/xray/xray_fdr_logging_impl.h:36:
In file included from compiler-rt/lib/xray/xray_flags.h:18:
compiler-rt/lib/xray/../sanitizer_common/sanitizer_flag_parser.h:23:7: error: '__sanitizer::FlagHandlerBase' has virtual functions but non-virtual destructor [-Werror,-Wnon-virtual-dtor]
class FlagHandlerBase {
llvm-svn: 316348
Alex Shlyapnikov [Mon, 23 Oct 2017 17:12:07 +0000 (17:12 +0000)]
[Sanitizers] New sanitizer API to purge allocator quarantine.
Summary:
Purging allocator quarantine and returning memory to OS might be desired
between fuzzer iterations since, most likely, the quarantine is not
going to catch bugs in the code under fuzz, but reducing RSS might
significantly prolong the fuzzing session.
Reviewers: cryptoad
Subscribers: kubamracek, llvm-commits
Differential Revision: https://reviews.llvm.org/D39153
llvm-svn: 316347
Matt Arsenault [Mon, 23 Oct 2017 17:09:35 +0000 (17:09 +0000)]
AMDGPU: Fix default range in non-kernel functions
The range should be assumed to be the hardware maximum
if a workitem intrinsic is used in a callable function
which does not know the restricted limit of the calling
kernel.
llvm-svn: 316346
Craig Topper [Mon, 23 Oct 2017 16:49:26 +0000 (16:49 +0000)]
[X86] Fix disassembler table generation to prevent instructions tagged with 'PS' being inherited into PD/XS/XD attribute entries.
llvm-svn: 316345
Benjamin Kramer [Mon, 23 Oct 2017 16:48:46 +0000 (16:48 +0000)]
[ASTMatchers] Expose forEachOverriden in dynamic AST matchers.
llvm-svn: 316344
Marshall Clow [Mon, 23 Oct 2017 16:46:44 +0000 (16:46 +0000)]
Fix misguided error message in debug mode. No functional change. Fixes PR#34966
llvm-svn: 316343
Kostya Kortchinsky [Mon, 23 Oct 2017 16:27:47 +0000 (16:27 +0000)]
[scudo] Add a shared runtime
Summary:
Up to now, the Scudo cmake target only provided a static library that had to be
linked to an executable to benefit from the hardened allocator.
This introduces a shared library as well, that can be LD_PRELOAD'ed.
Reviewers: alekseyshl
Reviewed By: alekseyshl
Subscribers: srhines, mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D38980
llvm-svn: 316342
Jessica Paquette [Mon, 23 Oct 2017 16:25:53 +0000 (16:25 +0000)]
[MachineOutliner] NFC: Rename getters/setters to fit coding style
Rename endIdx, startIdx, and length to getEndIdx, getStartIdx, and getLength
in Candidate.
llvm-svn: 316341
Craig Topper [Mon, 23 Oct 2017 16:22:40 +0000 (16:22 +0000)]
[X86] Change VMPTRST to use PS instead of TB to match VMPTRLD.
llvm-svn: 316340
Craig Topper [Mon, 23 Oct 2017 16:22:38 +0000 (16:22 +0000)]
[X86] Change RDRAND to use PS instead of TB.
Should be no functional change for now. A future disassembler change will prevent disassembling with 0xf2/0xf3.
llvm-svn: 316339
Erich Keane [Mon, 23 Oct 2017 16:20:15 +0000 (16:20 +0000)]
Pull X86 "CPUKind" checking into .cpp file. [NFC]
Preparing to do a refactor of CPU/feature checking, this
patch pulls the one CPU implementation from the .h file
to the .cpp file.
llvm-svn: 316338
Craig Topper [Mon, 23 Oct 2017 16:11:33 +0000 (16:11 +0000)]
[X86] Change XRSTOR to use PS instead of TB to match XSAVE.
I don't think this changes anything functionally yet, but I plan to fix the disassembler to use this to disable matching certain instructions with 0xf3/0xf2/0x66 prefixes.
llvm-svn: 316337
Simon Pilgrim [Mon, 23 Oct 2017 16:00:57 +0000 (16:00 +0000)]
[X86][SSE] Remove AssertZext stage from PEXTRW/PEXTRB lowering. NFCI.
Remove AssertZext and instead add PEXTRW/PEXTRB support to computeKnownBitsForTargetNode to simplify instruction selection.
Differential Revision: https://reviews.llvm.org/D39169
llvm-svn: 316336
Nico Weber [Mon, 23 Oct 2017 15:54:44 +0000 (15:54 +0000)]
clang-cl: Expose --version.
This is for consistency with lld-link, see https://reviews.llvm.org/D38972
Also give --version a help text so it shows up in --help / /? output (for
both clang-cl and regular clang).
llvm-svn: 316335
Andrew V. Tischenko [Mon, 23 Oct 2017 15:53:30 +0000 (15:53 +0000)]
Update DPPD/DPPS instruction scheduling on btver2.
Differential Revision: https://reviews.llvm.org/D39046
llvm-svn: 316334
Craig Topper [Mon, 23 Oct 2017 15:53:21 +0000 (15:53 +0000)]
[X86] Add PTWRITE instruction for assembler and disassembler.
llvm-svn: 316333
Craig Topper [Mon, 23 Oct 2017 15:53:16 +0000 (15:53 +0000)]
[X86] Add RDPID instruction for assembler and disassembler.
llvm-svn: 316332
Simon Pilgrim [Mon, 23 Oct 2017 15:48:08 +0000 (15:48 +0000)]
[DAGCombine] Permit combining of shuffles of equivalent splat BUILD_VECTORs
combineShuffleOfScalars is very conservative about shuffled BUILD_VECTORs that can be combined together.
This patch adds one additional case - if both BUILD_VECTORs represent splats of the same scalar value but with different UNDEF elements, then we should create a single splat BUILD_VECTOR, sharing only the UNDEF elements defined by the shuffle mask.
Differential Revision: https://reviews.llvm.org/D38696
llvm-svn: 316331
Sam McCall [Mon, 23 Oct 2017 15:40:44 +0000 (15:40 +0000)]
Support formatting formatv_objects.
Summary:
Support formatting formatv_objects.
While here, fix documentation about member-formatters, and attempted
perfect-forwarding (I think).
Reviewers: zturner
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D38997
llvm-svn: 316330
Rui Ueyama [Mon, 23 Oct 2017 14:57:53 +0000 (14:57 +0000)]
Add the --version option.
Differential Revision: https://reviews.llvm.org/D38972
llvm-svn: 316329
Simon Pilgrim [Mon, 23 Oct 2017 14:47:49 +0000 (14:47 +0000)]
[X86][SSE] Regenerate bitcast-and-setcc tests
Avoid the retl/retq changes in an upcoming patch
llvm-svn: 316328
Ilya Biryukov [Mon, 23 Oct 2017 14:46:48 +0000 (14:46 +0000)]
[clangd] Allow to pass code completion opts to ClangdServer.
Reviewers: bkramer, krasimir, sammccall
Reviewed By: krasimir
Subscribers: klimek, cfe-commits
Differential Revision: https://reviews.llvm.org/D38731
llvm-svn: 316327
Simon Pilgrim [Mon, 23 Oct 2017 14:19:46 +0000 (14:19 +0000)]
[X86][AVX2] Regenerate AVX2 intrinsics tests on 32 + 64-bit targets
llvm-svn: 316326
Simon Pilgrim [Mon, 23 Oct 2017 14:17:59 +0000 (14:17 +0000)]
[X86][AVX] Regenerate AVX intrinsics tests on 32 + 64-bit targets
llvm-svn: 316325
Simon Pilgrim [Mon, 23 Oct 2017 14:15:24 +0000 (14:15 +0000)]
[X86][F16C] Regenerate F16C schedule tests
llvm-svn: 316324
Ilya Biryukov [Mon, 23 Oct 2017 14:08:52 +0000 (14:08 +0000)]
[clangd] Updated outdated test comment. NFC.
llvm-svn: 316323
Artur Gainullin [Mon, 23 Oct 2017 13:25:49 +0000 (13:25 +0000)]
Test commit.
llvm-svn: 316322
George Rimar [Mon, 23 Oct 2017 11:24:14 +0000 (11:24 +0000)]
[llvm-dwarfdump] - Teach tool about few GNU call_sites constants.
This teaches tool about following consants:
DW_TAG_GNU_call_site,
DW_TAG_GNU_call_site_parameter,
DW_AT_GNU_call_site_value,
DW_AT_GNU_all_call_sites.
Constants documented here: https://sourceware.org/elfutils/DwarfExtensions
Differential revision: https://reviews.llvm.org/D39119
llvm-svn: 316321
Ayman Musa [Mon, 23 Oct 2017 10:24:19 +0000 (10:24 +0000)]
[X86] Add test for opportunity to use bzhi X86 instruction instead of load+and instructions.
Transformation uploaded for CR in https://reviews.llvm.org/D34141.
llvm-svn: 316320
Andrew V. Tischenko [Mon, 23 Oct 2017 09:36:33 +0000 (09:36 +0000)]
Fix for Bug 30718 - Failure to disassemble certain MOV with rex.R. The issue was in illegal segment register index.
Differential Revision: https://reviews.llvm.org/D38786
llvm-svn: 316319
Martin Storsjo [Mon, 23 Oct 2017 09:08:28 +0000 (09:08 +0000)]
[MinGW] Omit libc++/libc++abi/libunwind from autoexporting
Differential Revision: https://reviews.llvm.org/D39167
llvm-svn: 316318
Martin Storsjo [Mon, 23 Oct 2017 09:08:24 +0000 (09:08 +0000)]
[COFF] Fix exporting of functions starting with underscores, etc
This fixes exporting functions in the following cases:
- functions starting with an underscore in def files
- functions starting with an underscore, via dllexport attributes, for mingw
- fastcall and vectorcall functions when declared undecorated in def files
- vectorcall functions when declared decorated in def files
- stdcall functions when declared decorated in def files for mingw
This still exports the stdcall functions with the wrong name
in the normal msvc/link.exe mode, if declared with decoration in
the def file though (this is not a regression though). Exporting
functions via def files including decoration is not something I
believe is routinely done though, but is tested to try to match
link.exe's behaviour as far as easily possible.
Differential Revision: https://reviews.llvm.org/D39170
llvm-svn: 316317
Martin Storsjo [Mon, 23 Oct 2017 09:08:13 +0000 (09:08 +0000)]
[COFF] Improve the check for functions that should get an extra underscore
This fixes exporting functions starting with an underscore, and
fully decorated fastcall/vectorcall functions.
Tests will be added in the lld repo.
Differential Revision: https://reviews.llvm.org/D39168
llvm-svn: 316316
Haojian Wu [Mon, 23 Oct 2017 09:02:59 +0000 (09:02 +0000)]
Fix a -Wpedantic warning.
llvm-svn: 316315
Haojian Wu [Mon, 23 Oct 2017 08:58:50 +0000 (08:58 +0000)]
[rename] Don't overwrite the template argument when renaming a template function.
Reviewers: ioeric
Reviewed By: ioeric
Subscribers: cierpuchaw, cfe-commits, klimek
Differential Revision: https://reviews.llvm.org/D39120
llvm-svn: 316314
Sam Parker [Mon, 23 Oct 2017 08:05:14 +0000 (08:05 +0000)]
[ARM] Allow unrolling of multi-block loops.
Before, loop unrolling was only enabled for loops with a single
block. This restriction has been removed and replaced by:
- allow a maximum of two exiting blocks,
- a four basic block limit for cores with a branch predictor.
Differential Revision: https://reviews.llvm.org/D38952
llvm-svn: 316313
Ilya Biryukov [Mon, 23 Oct 2017 06:06:21 +0000 (06:06 +0000)]
[clangd] Report proper kinds for 'Keyword' and 'Snippet' completion items.
Reviewers: rwols, malaperle, krasimir, bkramer, sammccall
Reviewed By: rwols, sammccall
Subscribers: klimek, cfe-commits
Differential Revision: https://reviews.llvm.org/D38720
llvm-svn: 316311
Richard Smith [Mon, 23 Oct 2017 03:58:34 +0000 (03:58 +0000)]
For better compatibility with C++11 and C++14, emit a nondiscardable definition
of a static constexpr data member if it's defined 'constexpr' out of line, not
only if it's defined 'constexpr' in the class.
llvm-svn: 316310
Craig Topper [Mon, 23 Oct 2017 03:42:35 +0000 (03:42 +0000)]
[X86] Update a doxygen comment in the disassembler tablegen code. NFC
llvm-svn: 316309
Craig Topper [Mon, 23 Oct 2017 02:26:24 +0000 (02:26 +0000)]
[X86] Fix disassembly of EVEX rounding control and SAE instructions.
Fixes PR31955.
llvm-svn: 316308
Petr Hosek [Mon, 23 Oct 2017 00:51:08 +0000 (00:51 +0000)]
[ELF] When placing orphans, handle case when last section is dead
r315292 introduced a change that's supposed to consistently ignore
"dead" output sections when placing orphans. Unfortunately, that
change doesn't handle the special case when the orphan section is
second to last section and the last section is dead (e.g. because
it's being discarded) introducing a regression in some cases.
This change handles this case by using the same predicate when
checking the last section.
Differential Revision: https://reviews.llvm.org/D39172
llvm-svn: 316307
Rui Ueyama [Sun, 22 Oct 2017 23:33:49 +0000 (23:33 +0000)]
Add R_PPC_ADDR16_HI relocation support
The support of R_PPC_ADDR16_HI improves ld compatibility and makes
things on par with RuntimeDyldELF that already implements this
relocation.
Patch by vit9696.
llvm-svn: 316306
Rui Ueyama [Sun, 22 Oct 2017 23:02:07 +0000 (23:02 +0000)]
Remove a fast lookup table from MergeInputSection.
We used to have a map from section piece offsets to section pieces
as a cache for binary search. But I found that the map took quite a
large amount of memory and didn't make linking faster. So, in this
patch, I removed the map.
This patch saves 566 MiB of RAM (2.019 GiB -> 1.453 GiB) when linking
clang with debug info, and the link time is 4% faster in that test case.
Thanks for Sean Silva for pointing this out.
llvm-svn: 316305
Faisal Vali [Sun, 22 Oct 2017 22:29:52 +0000 (22:29 +0000)]
[c++2a] Update cxx_status w __VA_OPT__ marked as completed in SVN.
llvm-svn: 316304
Saleem Abdulrasool [Sun, 22 Oct 2017 20:51:25 +0000 (20:51 +0000)]
ExecutionEngine: make COFF Thumb2 assertions non-tautological
The overflow detection assertions were tautological due to truncation.
Adjust them to no longer be tautological.
Patch by Alex Langford!
llvm-svn: 316303
Yichao Yu [Sun, 22 Oct 2017 20:28:17 +0000 (20:28 +0000)]
Fix invalid ptrtoint in InstCombine
Summary:
It's unclear if this is the only thing we can do but at least this is consistent with the check
of address space agreement in `isBitCastable`.
The code is used at least in both instcombine and jumpthreading though
I could only find a way to trigger the invalid cast in instcombine.
Reviewers: loladiro, sanjoy, majnemer
Reviewed By: sanjoy
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D34335
llvm-svn: 316302
Benjamin Kramer [Sun, 22 Oct 2017 20:16:28 +0000 (20:16 +0000)]
Create fewer copies of StringMaps. No functionality change intended.
llvm-svn: 316301
Martin Storsjo [Sun, 22 Oct 2017 19:39:26 +0000 (19:39 +0000)]
Make HIDDEN_DIRECTIVE a function-like macro. NFCI.
This avoids a hack for making it a no-op for windows.
Also explicitly check for _WIN32 instead of assuming it.
Differential Revision: https://reviews.llvm.org/D39156
llvm-svn: 316300
Benjamin Kramer [Sun, 22 Oct 2017 19:16:31 +0000 (19:16 +0000)]
[X86] Add missing override. NFC.
llvm-svn: 316299
Sanjay Patel [Sun, 22 Oct 2017 19:10:07 +0000 (19:10 +0000)]
[SimplifyCFG] delay switch condition forwarding to -latesimplifycfg
As discussed in D39011:
https://reviews.llvm.org/D39011
...replacing constants with a variable is inverting the transform done
by other IR passes, so we definitely don't want to do this early.
In fact, it's questionable whether this transform belongs in SimplifyCFG
at all. I'll look at moving this to codegen as a follow-up step.
llvm-svn: 316298
Fangrui Song [Sun, 22 Oct 2017 18:43:23 +0000 (18:43 +0000)]
[utils] Support -mtriple=powerpc64
Summary: test/CodeGen/PowerPC/pr33093.ll uses both powerpc64 (big-endian) and powerpc64le while the former was unsupported.
Subscribers: nemanjai
Differential Revision: https://reviews.llvm.org/D39164
llvm-svn: 316297
Simon Pilgrim [Sun, 22 Oct 2017 18:38:57 +0000 (18:38 +0000)]
Strip trailing whitespace. NFCI.
llvm-svn: 316296
Marina Yatsina [Sun, 22 Oct 2017 17:59:38 +0000 (17:59 +0000)]
Add logic to greedy reg alloc to avoid bad eviction chains
This fixes bugzilla 26810
https://bugs.llvm.org/show_bug.cgi?id=26810
This is intended to prevent sequences like:
movl %ebp, 8(%esp) # 4-byte Spill
movl %ecx, %ebp
movl %ebx, %ecx
movl %edi, %ebx
movl %edx, %edi
cltd
idivl %esi
movl %edi, %edx
movl %ebx, %edi
movl %ecx, %ebx
movl %ebp, %ecx
movl 16(%esp), %ebp # 4 - byte Reload
Such sequences are created in 2 scenarios:
Scenario #1:
vreg0 is evicted from physreg0 by vreg1
Evictee vreg0 is intended for region splitting with split candidate physreg0 (the reg vreg0 was evicted from)
Region splitting creates a local interval because of interference with the evictor vreg1 (normally region spliiting creates 2 interval, the "by reg" and "by stack" intervals. Local interval created when interference occurs.)
one of the split intervals ends up evicting vreg2 from physreg1
Evictee vreg2 is intended for region splitting with split candidate physreg1
one of the split intervals ends up evicting vreg3 from physreg2 etc.. until someone spills
Scenario #2
vreg0 is evicted from physreg0 by vreg1
vreg2 is evicted from physreg2 by vreg3 etc
Evictee vreg0 is intended for region splitting with split candidate physreg1
Region splitting creates a local interval because of interference with the evictor vreg1
one of the split intervals ends up evicting back original evictor vreg1 from physreg0 (the reg vreg0 was evicted from)
Another evictee vreg2 is intended for region splitting with split candidate physreg1
one of the split intervals ends up evicting vreg3 from physreg2 etc.. until someone spills
As compile time was a concern, I've added a flag to control weather we do cost calculations for local intervals we expect to be created (it's on by default for X86 target, off for the rest).
Differential Revision: https://reviews.llvm.org/D35816
Change-Id: Id9411ff7bbb845463d289ba2ae97737a1ee7cc39
llvm-svn: 316295
Craig Topper [Sun, 22 Oct 2017 17:22:29 +0000 (17:22 +0000)]
[X86] More correctly support LIG and WIG for EVEX instructions in the disassembler tables.
This is similar to how we generate the VEX tables.
More fixes are still needed for the instructions that use EVEX.b (broadcast and embedded rounding).
llvm-svn: 316294
Sanjay Patel [Sun, 22 Oct 2017 16:51:03 +0000 (16:51 +0000)]
[SimplifyCFG] try harder to forward switch condition to phi (PR34471)
The missed canonicalization/optimization in the motivating test from PR34471 leads to very different codegen:
int switcher(int x) {
switch(x) {
case 17: return 17;
case 19: return 19;
case 42: return 42;
default: break;
}
return 0;
}
int comparator(int x) {
if (x == 17) return 17;
if (x == 19) return 19;
if (x == 42) return 42;
return 0;
}
For the first example, we use a bit-test optimization to avoid a series of compare-and-branch:
https://godbolt.org/g/BivDsw
Differential Revision: https://reviews.llvm.org/D39011
llvm-svn: 316293
Faisal Vali [Sun, 22 Oct 2017 14:45:08 +0000 (14:45 +0000)]
[C++17] Fix PR34970 - tweak overload resolution for class template deduction-guides in line with WG21's p0620r0.
In order to identify the copy deduction candidate, I considered two approaches:
- attempt to determine whether an implicit guide is a copy deduction candidate by checking certain properties of its subsituted parameter during overload-resolution.
- using one of the many bits (WillHaveBody) from FunctionDecl (that CXXDeductionGuideDecl inherits from) that are otherwise irrelevant for deduction guides
After some brittle gymnastics w the first strategy, I settled on the second, although to avoid confusion and to give that bit a better name, i turned it into a member of an anonymous union.
Given this identification 'bit', the tweak to overload resolution was a simple reordering of the deduction guide checks (in SemaOverload.cpp::isBetterOverloadCandidate), in-line with Jason Merrill's p0620r0 drafting which made it into the working paper. Concordant with that, I made sure the copy deduction candidate is always added.
References:
See https://bugs.llvm.org/show_bug.cgi?id=34970
See http://wg21.link/p0620r0
llvm-svn: 316292
Jan Vesely [Sun, 22 Oct 2017 14:21:59 +0000 (14:21 +0000)]
shared: Implement aligned vector stores (vstorea_half)
Float version passes newly posted piglit tests on turks, float and double pass on carrizo.
v2: scalar vstorea_half
v3: fix typo
Reviewer: Aaron Watry
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 316291
Jan Vesely [Sun, 22 Oct 2017 14:21:56 +0000 (14:21 +0000)]
shared: Implement aligned vector loads (vloada_half)
Passes newly posted piglits on turks and carrizo
v2: add scalar vloada_half
v3: fix typo
Reviewer: Aaron Watry
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 316290
Momchil Velikov [Sun, 22 Oct 2017 11:56:35 +0000 (11:56 +0000)]
[ARM] Dynamic stack alignment for 16-bit Thumb
This patch implements dynamic stack (re-)alignment for 16-bit Thumb. When
targeting processors, which support only the 16-bit Thumb instruction set
the compiler ignores the alignment attributes of automatic variables and may
silently generate incorrect code.
Differential revision: https://reviews.llvm.org/D38143
llvm-svn: 316289
Guy Blank [Sun, 22 Oct 2017 11:43:08 +0000 (11:43 +0000)]
[X86] Add a pass to convert instruction chains between domains.
The pass scans the function to find instruction chains that define
registers in the same domain (closures).
It then calculates the cost of converting the closure to another domain.
If found profitable, the instructions are converted to instructions in
the other domain and the register classes are changed accordingly.
This commit adds the pass infrastructure and a simple conversion from
the GPR domain to the Mask domain.
Differential Revision:
https://reviews.llvm.org/D37251
Change-Id: Ic2cf1d76598110401168326d411128ae2580a604
llvm-svn: 316288
Nitesh Jain [Sun, 22 Oct 2017 09:47:41 +0000 (09:47 +0000)]
[mips] Adds support for R_MIPS_26, HIGHER, HIGHEST relocations in RuntimeDyld.
Reviewers: sdardis
Subscribers: jaydeep, bhushan, llvm-commits
Differential Revision: https://reviews.llvm.org/D38314
llvm-svn: 316287
Nitesh Jain [Sun, 22 Oct 2017 09:37:50 +0000 (09:37 +0000)]
[Compiler-rt][MIPS] Fix cross build for XRAY.
Reviewers: dberris, sdardis
Subscribers: jaydeep, bhushan, llvm-commits
Differential Revision: https://reviews.llvm.org/D38021
llvm-svn: 316286
Craig Topper [Sun, 22 Oct 2017 06:18:26 +0000 (06:18 +0000)]
[X86] Teach the disassembler that some instructions use VEX.W==0 without a corresponding VEX.W==1 instruction and we shouldn't treat them as if VEX.W is ignored.
Fixes PR11304.
llvm-svn: 316285