Danylo Piliaiev [Wed, 3 May 2023 17:39:46 +0000 (19:39 +0200)]
ir3/a7xx: cat5 mode1 has swapped tex/samp ids
Though blob is not seen to even use mode1 on a740, it uses
S2EN variant instead.
Fixes:
dEQP-VK.binding_model.descriptor_buffer.multiple.*
dEQP-VK.binding_model.descriptor_buffer.embedded_imm_samplers.*
dEQP-VK.pipeline.monolithic.descriptor_limits.compute_shader.*
Adapted from Jonathan Marek's changes.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Fri, 9 Jun 2023 10:58:55 +0000 (12:58 +0200)]
isaspec: Make possible to obtain gpu_id in <expr> blocks
Done with ISA_GPU_ID() macro. This makes possible to use
gpu generation in to select between overrides.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Mon, 17 Apr 2023 13:39:09 +0000 (15:39 +0200)]
freedreno/computerator: Fix remaining issues with A7XX
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Mon, 4 Sep 2023 15:53:09 +0000 (17:53 +0200)]
ir3/tests: Use fd_dev_info to infer GPU generation
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Mon, 17 Apr 2023 13:38:00 +0000 (15:38 +0200)]
freedreno: Fully define a730 and a740 device properties
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Tue, 2 May 2023 11:26:06 +0000 (13:26 +0200)]
freedreno: Add a list of raw magic regs
The set of magic regs is different between generations and even
sub-gens. Adding a new one and/or emitting one on specific generation
takes much more code than necessary. Doing this in a single place is
much nicer.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Fri, 11 Aug 2023 13:30:47 +0000 (15:30 +0200)]
freedreno/registers: Generate python files with reg offsets
This would allow us to use register names in python scripts.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Fri, 11 Aug 2023 13:10:59 +0000 (15:10 +0200)]
freedreno/registers: Refactor gen_header.py to allow more options
We want it to also generate .py files with reg definitions.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Lionel Landwerlin [Sat, 2 Sep 2023 15:53:13 +0000 (18:53 +0300)]
intel/nir: rerun lower_tex if it lowers something
nir_lower_tex can lower tg4 coords into tg4 offset which on DG2+ we
also need to lower into constant offsets.
Unfortunately the nir_lower_tex pass is not able to lower the
instructions it itself generates, so the easy fix for when
nir_lower_tex lowers tg4 coords into tg4 offsets is to rerun the pass.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9735
Cc: mesa-stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25015>
Vlad Schiller [Mon, 21 Aug 2023 05:34:36 +0000 (06:34 +0100)]
pvr: Implement VK_KHR_format_feature_flags2
This commit will implement and set VK_KHR_format_feature_flags2
instead of the old ones.
Signed-off-by: Vlad Schiller <vlad-radu.schiller@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24929>
Samuel Pitoiset [Wed, 30 Aug 2023 12:08:09 +0000 (14:08 +0200)]
radv/amdgpu: do not copy the original chain link for IBs
Otherwise, if a secondary CS is grown and then executed without IB2,
the INDIRECT_BUFFER packet would have been copied but it shouldn't.
This fixes a regression that introduced GPU hangs with
gl_vk_meshlet_cadscene on RDNA2.
Fixes:
df0c742543d ("radv/amdgpu: rework growing a CS with the chained IB path slightly")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24891>
Samuel Pitoiset [Fri, 25 Aug 2023 15:26:30 +0000 (17:26 +0200)]
radv/amdgpu: fix executing secondaries without IB2
If a secondary cmdbuf has been grown and is executed without IB2
(eg. on compute queue or when it's not allowed), the ib size ptr
contains chaining info, which means the IB size was wrong.
This fixes CPU crashes when running gl_vk_meshlet_cadscene.
Fixes:
277b2afd708 ("radv/amdgpu: add support for executing DGC cmdbuf with RADV_DEBUG=noibs")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24891>
Lionel Landwerlin [Fri, 11 Aug 2023 09:19:28 +0000 (12:19 +0300)]
intel/measure: track batch buffer sizes
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24628>
Lionel Landwerlin [Fri, 11 Aug 2023 09:14:32 +0000 (12:14 +0300)]
anv: reuse cmd_buffer::total_batch_size
This was left unused after
624ac55721 ("anv: move total_batch_size to
anv_batch"). We're now going to use it to store the total amount of
commands written in a command buffer.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24628>
Lionel Landwerlin [Fri, 11 Aug 2023 09:04:18 +0000 (12:04 +0300)]
anv: rename total_batch_size
This name is confusing, the real thing it represents is the allocated
amount of batch space.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24628>
Chris Spencer [Tue, 29 Aug 2023 19:26:20 +0000 (20:26 +0100)]
anv/android: Enable shared presentable image support
Signed-off-by: Chris Spencer <spencercw@gmail.com>
Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24941>
Chris Spencer [Tue, 29 Aug 2023 21:16:45 +0000 (22:16 +0100)]
android: Add explanatory comment to u_gralloc
Signed-off-by: Chris Spencer <spencercw@gmail.com>
Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24941>
Dmitry Osipenko [Fri, 1 Sep 2023 00:36:15 +0000 (03:36 +0300)]
util/cache_test: Add test for get/put() with disabled cache
The disk_cache_create() now always returns valid cache even when disk
cache is disabled. In a case of disabled cache, the disk cache is NO-OP.
Test whether get/put() work as expected for the disabled cache.
Reviewed-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24985>
Dmitry Osipenko [Fri, 1 Sep 2023 00:13:11 +0000 (03:13 +0300)]
util/cache_test: Fix disabled cache test using SHADER_CACHE_DISABLE_BY_DEFAULT
Previous commit decoupled EGL_ANDROID_blob_cache from the disk cache
and haven't updated the SHADER_CACHE_DISABLE_BY_DEFAULT test-case that
is failing because now cache is always created even if disk cache is
disabled, such cache is NO-OP in this case. Fix the failing test.
Fixes:
39f26642 ("util: Decouple disk cache from EGL_ANDROID_blob_cache")
Reviewed-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24985>
Dmitry Osipenko [Fri, 1 Sep 2023 00:03:22 +0000 (03:03 +0300)]
util/cache_test: Re-add test for disabled cache
Test for disabled cache was removed when we decoupled
EGL_ANDROID_blob_cache from the disk cache because test was failing
since it became outdated. Add the updated test.
Fixes:
39f26642 ("util: Decouple disk cache from EGL_ANDROID_blob_cache")
Reviewed-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24985>
Dave Airlie [Wed, 30 Aug 2023 01:56:56 +0000 (11:56 +1000)]
llvmpipe/cs: further cleanups after tgsi removal.
These was still a few more places that could be polished better.
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25045>
Mike Blumenkrantz [Fri, 1 Sep 2023 17:23:32 +0000 (13:23 -0400)]
zink: fix linear modifier dmabuf imports
these are disguised as INVALID modifiers, but really they're LINEAR
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25002>
Alyssa Rosenzweig [Wed, 30 Aug 2023 22:10:28 +0000 (18:10 -0400)]
nir/opt_if: Simplify if's with general conditions
Dolphin ubershaders have a pattern:
if (x && y) {
} else {
discard;
}
The current code to simplify if's will bail on this pattern, since the condition
is not a comparison. However, if that check is dropped and we allow NIR to
invert this, we get:
if (!(x && y)) {
discard;
} else {
}
which is now in a form for nir_opt_conditional_discard to turn into it
discard_if(!(x && y))
which may be substantially cheaper than the original code.
In general, I see no reason to restrict to conditionals. Assuming the backend is
clever enough to delete empty else blocks (I think most are), then this patch is
a strict win as long as inot instructions are cheaper than empty else blocks.
This matches my intuition for typical GPUs, where simple ALU instructions are
cheaper than control flow. Furthermore, it may be possible in practice for
backends to fold the inot into a richer set of instructions. For example, most
GPUs have a NAND instructions which would fold in the inot in the above code.
So just drop the check, simplify the pass, get the win.
---
Also, to avoid inflating register pressure, make sure we put the inot right
before the if. Android shader-db on is uninspiring due to terrible
coalescing decisions in the current RA. But it does fix the Dolphin smell.
total instructions in shared programs: 1756571 -> 1756568 (<.01%)
instructions in affected programs: 1600 -> 1597 (-0.19%)
helped: 1
HURT: 4
Inconclusive result (value mean confidence interval includes 0).
total bytes in shared programs:
11521172 ->
11521156 (<.01%)
bytes in affected programs: 10080 -> 10064 (-0.16%)
helped: 1
HURT: 4
Inconclusive result (value mean confidence interval includes 0).
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24965>
Mike Blumenkrantz [Wed, 30 Aug 2023 13:49:30 +0000 (09:49 -0400)]
lavapipe: fix pipeline stride propagation
this is on the cso now
affects dEQP-VK.pipeline.fast_linked_library.extended_dynamic_state.before_good_static.large_stride
Fixes:
76725452239 ("gallium: move vertex stride to CSO")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24954>
Mike Blumenkrantz [Wed, 30 Aug 2023 13:38:54 +0000 (09:38 -0400)]
lavapipe: update vbo indices before propagating stride
the vbo index is used to set the stride, so it needs to be updated
affects dEQP-VK.pipeline.pipeline_library.bind_buffers_2.single.stride_0_4_offset_1_0.count_2
Fixes:
76725452239 ("gallium: move vertex stride to CSO")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24954>
Mike Blumenkrantz [Thu, 24 Aug 2023 12:26:10 +0000 (08:26 -0400)]
zink: don't block reordering during ref updates in unordered blits
unordered blits handle all the reorder mechanics already, so any changes
here end up unnecessarily blocking further reordering
test case KHR-GLES3.packed_pixels.varied_rectangle.rgb
ref #9016
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24934>
Mike Blumenkrantz [Wed, 30 Aug 2023 10:54:37 +0000 (06:54 -0400)]
zink: be more precise about flagging rp changes around unordered u_blitter
failing to update rp attachments as needed after unordered blits results in
broken (depth) rendering
Fixes:
3a9f7d70383 ("zink: implement unordered u_blitter calls")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24934>
Leo Liu [Fri, 1 Sep 2023 22:26:43 +0000 (18:26 -0400)]
radeonsi/vcn: fix the incorrect dt_size
Issue: For texture with multiple planes, the planes will point to the
same BO with the total size, so current vcn dt_size is incorrect.
(gdb) p/x *((struct si_resource *)(((struct vl_video_buffer *)out_surf)->resources[0]))
...
buf = 0x5555558daa30,
gpu_address = 0xffff800101000000,
bo_size = 0xa2000,
...
}
(gdb) p/x *((struct si_resource *)(((struct vl_video_buffer *)out_surf)->resources[1]))
...
buf = 0x5555558daa30,
gpu_address = 0xffff800101000000,
bo_size = 0xa2000,
...
}
This is because: in function static struct si_texture *si_texture_create_object(),
if (plane0) {
/* The buffer is shared with the first plane. */
resource->bo_size = plane0->buffer.bo_size;
...
radeon_bo_reference(sscreen->ws, &resource->buf, plane0->buffer.buf);
resource->gpu_address = plane0->buffer.gpu_address;
}
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9728
Cc: mesa-stable
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25013>
Tapani Pälli [Mon, 21 Aug 2023 10:29:43 +0000 (13:29 +0300)]
iris: implement Wa_14018912822
When MSAA is enabled, instead of using BLENDFACTOR_ZERO use CONST_COLOR,
CONST_ALPHA and supply zero by using blend constants.
We need info on blend state entries in the CSO so that we can set them
up properly.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24714>
Tapani Pälli [Wed, 16 Aug 2023 05:20:12 +0000 (08:20 +0300)]
anv: implement Wa_14018912822
When MSAA is enabled, instead of using BLENDFACTOR_ZERO use CONST_COLOR,
CONST_ALPHA and supply zero by using blend constants.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24714>
Samuel Pitoiset [Mon, 4 Sep 2023 08:34:06 +0000 (10:34 +0200)]
ci: do not fail vkd3d-proton job when the expectations match
When the list of expected failures match, the job shouldn't fail.
This also adjusts the first error check to catch segfaults.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25025>
Samuel Pitoiset [Mon, 4 Sep 2023 06:44:51 +0000 (08:44 +0200)]
radv/ci: re-enable vkd3d-polaris10-valve
Like the vkcts job, this was disabled a while ago but it seems to be
working well again.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25025>
Pavel Ondračka [Wed, 23 Aug 2023 11:55:48 +0000 (13:55 +0200)]
r300: use w channel for scalar opcodes if possible
The opcodes write to w by default so using anything else means we can't
schedule anything in the rbg slot anyway becasue we have to replicate the
result from w. We already attempt to do this during the scheduling, but
at that point it is more tricky, so doing it early leads to much better
code. Performance++
RV530 benchmarks:
Lightsmark, 1280x800, fullscreen
before:
N Min Max Median Avg Stddev
x 5 27.32 27.36 27.34 27.34 0.
015811388
after:
N Min Max Median Avg Stddev
x 5 27.53 27.61 27.59 27.576 0.
034351128
Unigine Sanctuary, 1280x800, fullscreen, medium shaders
before:
N Min Max Median Avg Stddev
x 5 10.1211 10.1238 10.1214 10.12192 0.
0011211601
after:
N Min Max Median Avg Stddev
x 5 10.4607 10.4637 10.4619 10.46206 0.
0012441865
RV530 shader-db:
total instructions in shared programs: 129643 -> 128038 (-1.24%)
instructions in affected programs: 45415 -> 43810 (-3.53%)
helped: 514
HURT: 43
total presub in shared programs: 4912 -> 5201 (5.88%)
presub in affected programs: 752 -> 1041 (38.43%)
helped: 40
HURT: 30
total omod in shared programs: 381 -> 383 (0.52%)
omod in affected programs: 6 -> 8 (33.33%)
helped: 1
HURT: 3
total temps in shared programs: 16904 -> 16841 (-0.37%)
temps in affected programs: 1377 -> 1314 (-4.58%)
helped: 81
HURT: 52
total lits in shared programs: 3555 -> 3550 (-0.14%)
lits in affected programs: 294 -> 289 (-1.70%)
helped: 13
HURT: 11
total cycles in shared programs: 194771 -> 193734 (-0.53%)
cycles in affected programs: 79079 -> 78042 (-1.31%)
helped: 452
HURT: 84
GAINED: shaders/glamor/82.shader_test FS
RV370 shader-db:
total instructions in shared programs: 82116 -> 81600 (-0.63%)
instructions in affected programs: 11888 -> 11372 (-4.34%)
helped: 273
HURT: 40
total temps in shared programs: 12438 -> 12441 (0.02%)
temps in affected programs: 692 -> 695 (0.43%)
helped: 36
HURT: 39
total cycles in shared programs: 128140 -> 127630 (-0.40%)
cycles in affected programs: 25838 -> 25328 (-1.97%)
helped: 266
HURT: 41
GAINED: shaders/0ad/12.shader_test FS
GAINED: shaders/CC3-tiberium-wars/314.shader_test FS
GAINED: shaders/lightsmark/16.shader_test FS
GAINED: shaders/sanctuary/159.shader_test FS
GAINED: shaders/sanctuary/162.shader_test FS
GAINED: shaders/sanctuary/51.shader_test FS
GAINED: shaders/sanctuary/54.shader_test FS
GAINED: shaders/trine/fp-422.shader_test FS
Partial fix for: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6661
Reviewed-by: Filip Gawin <filip.gawin@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24889>
Vlad Schiller [Thu, 10 Aug 2023 07:39:17 +0000 (08:39 +0100)]
pvr: Add 'info' PVR_DEBUG flag
This commit will add a new PVR_DEBUG flag that, when used,
it will display information about the display and render
devices in the common code (without adding dependencies)
Signed-off-by: Vlad Schiller <vlad-radu.schiller@imgtec.com>
Reviewed-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24931>
Carsten Haitzler [Mon, 4 Sep 2023 08:55:34 +0000 (09:55 +0100)]
kmsro: Add hdlcd DPU
Arm hdlcd display units do exist on Juno SoC's. This is the
first time Mesa has had to deal with panfrost working on these SoC's,
thus have to add hdlcd support.
Signed-off-by: Carsten Haitzler <carsten.haitzler@foss.arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25027>
David Heidelberg [Mon, 4 Sep 2023 10:55:24 +0000 (16:25 +0530)]
ci: disable Google Freedreno farm, currently timeouting on all jobs
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25030>
Roman Stratiienko [Sat, 2 Sep 2023 19:00:32 +0000 (22:00 +0300)]
v3dv/android: Skip swapchain binding
ANV functionality was used as a reference. As stated in anv_BindImageMemory2:
Ignore this struct on Android, we cannot access swapchain
structures there.
Fixes 2 failing VTS test:
dEQP-VK.wsi.android.swapchain.create#image_swapchain_create_info
dEQP-VK.wsi.android.swapchain.simulate_oom#image_swapchain_create_info
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25028>
Roman Stratiienko [Sat, 2 Sep 2023 18:01:33 +0000 (21:01 +0300)]
v3dv: Migrate to vk_device_memory
It allows the reuse of some generic code, especially AHB logic.
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25028>
Roman Stratiienko [Sat, 2 Sep 2023 15:35:09 +0000 (18:35 +0300)]
v3dv/android: Enable shared presentable image support
Functionality ensures gralloc won't allocate compressed buffer
incompatible with shared presentable image support.
Broadcom does not support compressed buffers and we can just enable the
feature without additional logic. Despite that, we add the logic here
so it can be replaced with the generic code someday.
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25028>
Roman Stratiienko [Sat, 2 Sep 2023 15:18:50 +0000 (18:18 +0300)]
v3dv/android: Use u_gralloc code
Use generic u_gralloc logic instead of custom.
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25028>
Samuel Pitoiset [Fri, 1 Sep 2023 11:52:28 +0000 (13:52 +0200)]
radv: fix capturing indirect dispatches with SQTT
Looks like indirect dispatches require an event marker instead of an
event marker with dims. That makes sense somehow given the blocks size
is not known at record time with indirect dispatches.
This allows RGP to report correct block sizes.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24994>
Qiang Yu [Fri, 1 Sep 2023 07:21:11 +0000 (15:21 +0800)]
aco,radv,radeonsi: rename is_monolithic to merged_shader_compiled_separately
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24990>
Alexander Orzechowski [Sun, 3 Sep 2023 20:28:11 +0000 (16:28 -0400)]
radeonsi: Set PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET for auxiliary contexts
This fixes a regression with context loss hardened compositors such as
wlroots or kwin where instead of continuing execution in a reset
situation, the process would be aborted. Although these applications set
their notification strategy to lose context on reset, radeonsi also
creates auxiliary contexts for its own use observed when
`egl_init_display` and `gbm_create_device` are called from these
compositors. Fix this by allowing a context loss on reset for these
auxiliary contexts.
Note: It seems this has been attempted before for another call site
creating auxiliary contexts, but this location was missed, hence the
fixed commit hash below.
Fixes: #9672
Fixes:
591aaea6486fca44feb65e46ba09aaa708315b50
Signed-off-by: Alexander Orzechowski <alex@ozal.ski>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25023>
Dave Airlie [Thu, 31 Aug 2023 02:07:33 +0000 (12:07 +1000)]
nir/gather: add support for fbfetch and bindless image loads.
If a driver calls gather after lowering the uses_fbfetch_output
needs to be set properly if we have bindless image loads.
Fixes a regression seen calling gather info later in some llvmpipe
work.
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24987>
Timur Kristóf [Mon, 7 Aug 2023 09:19:49 +0000 (11:19 +0200)]
ac/nir/ngg: Extract nogs_export_vertex_params function.
Just for better code readability. No functional changes.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24574>
Timur Kristóf [Tue, 22 Aug 2023 20:39:22 +0000 (22:39 +0200)]
ac/nir/ngg: Wait for attribute ring stores in mesh shaders.
Make sure that both per-vertex and per-primitive attribute
ring stores are finished before position or primitive export
instructions are executed.
This is necessary because we need to ensure that mesh shader
waves work correctly when they have either vertex-only or
primitive-only waves.
Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24574>
Timur Kristóf [Tue, 22 Aug 2023 20:28:43 +0000 (22:28 +0200)]
ac/nir/ngg: Refactor mesh shader primitive export.
Cleanup the code that generates the two channels of the
primitive export instruction, and move storing the built-in
per-primitive outputs out to match how vertex attributes work.
Prepares the mesh shader lowering for a workaround that
affect export instructions.
Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24574>
Timur Kristóf [Tue, 22 Aug 2023 19:51:43 +0000 (21:51 +0200)]
ac/nir/ngg: Wait for attribute stores before VS/TES/GS pos0 export.
This is a HW bug workaround for some (all?) GFX11 chips.
On these chips, rasterization can start before the attribute ring
stores are finished, which can cause issues.
As a workaround, wait for attribute ring stores to finish
before doing the position export.
Mesh shaders will be taken care of in another commit.
Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24574>
Timur Kristóf [Tue, 22 Aug 2023 19:30:05 +0000 (21:30 +0200)]
ac/nir: Slightly refactor how pos0 exports are added when missing.
Prepares for a workaround. Makes it possible for this function
to not emit the pos0 export at all so that it can be emitted
by a subsequent call to the function later.
Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24574>
Timur Kristóf [Tue, 22 Aug 2023 18:22:32 +0000 (20:22 +0200)]
ac/nir: Add done arg to ac_nir_export_position.
This prepares for a workaround where we won't need to add
the done flag to the last export in this function, because
it will be added in a subsequent call to the same function.
Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24574>
Lionel Landwerlin [Fri, 25 Aug 2023 07:48:19 +0000 (10:48 +0300)]
isl/tilememcpy_test: add multiple tile testing
Also verify that there is no out-of-bounds accesses.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Aditya Swarup <aditya.swarup@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13391>
Aditya Swarup [Thu, 28 Jul 2022 00:35:03 +0000 (17:35 -0700)]
Revert "iris: Disable tiled memcpy for Tile4"
This reverts commit
0022a11ff4fbbe89c2511d758f807b286ebb1bd7.
Enable path for Tile4 memcpy functions to be used.
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13391>
Aditya Swarup [Mon, 18 Jul 2022 23:59:46 +0000 (16:59 -0700)]
intel/isl: Linear to Tile-4 conversion unittest
Add unittest to test conversion of data from linear to
Tile-4 format based on bit swizzling conversion info
mentioned in Bspec.
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13391>
Aditya Swarup [Mon, 18 Jul 2022 21:22:12 +0000 (14:22 -0700)]
intel/isl: Convert Tile4 texture to linear format
Add memcpy function to convert Tile-4 4KB texture to linear
format.
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13391>
Aditya Swarup [Mon, 18 Jul 2022 21:18:24 +0000 (14:18 -0700)]
intel/isl: Convert linear texture to Tile4 format
Add memcpy function to convert linear data to Tile 4 format.
Tile 4 format consists of 4KB block divided into chunks of 512B.
Each 512B chunk/block is comprised of 8 64B blocks arranged in
Y-tile format.
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13391>
Aditya Swarup [Mon, 1 Nov 2021 21:41:04 +0000 (14:41 -0700)]
intel/isl: Unittest for linear to Ytile conversion
Add unittests for linear to tiled and tiled to linear texture
conversions for Ytile. The test prints the source/output buffer
in hex format with debug flags to verify the result.
Linear to tile conversion fills the linear buffer with values
based on the OWORD index number i.e., OWORD3 will contain
all values filled as 0x03 and
OWORD3 = 0x03030303030303030303030303030303.
The Y-tile to Linear tile conversion uses a similar logic to place
the tiled values in a manner that will result in a linear buffer with
OWORDs filled according to index number as mentioned above.
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13391>
Rohan Garg [Fri, 1 Sep 2023 11:48:51 +0000 (13:48 +0200)]
blorp: drop undefined macro
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
97d6ceaf04 ("intel: Remove GEN_IS_HASWELL macro")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25011>
Rohan Garg [Fri, 1 Sep 2023 11:48:20 +0000 (13:48 +0200)]
crocus: fix GFX_VERx10 macro
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25011>
Rohan Garg [Fri, 1 Sep 2023 11:29:53 +0000 (13:29 +0200)]
crocus: add a __gen_get_batch_address declaration
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25011>
Rohan Garg [Fri, 1 Sep 2023 10:39:13 +0000 (12:39 +0200)]
anv: use the lineage number for WA
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
d0669f3ede ("intel/dev: switch defect identifiers to use lineage numbers")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25011>
Rohan Garg [Fri, 1 Sep 2023 10:38:35 +0000 (12:38 +0200)]
iris: use the correct WA macros and lineage numbers
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
0ce595a89a ("intel: use generated helpers for Wa_1508744258")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25011>
Rohan Garg [Fri, 1 Sep 2023 09:48:18 +0000 (11:48 +0200)]
anv: drop dead ifdef
The GFX_VERX10 macro doesn't exist and we no longer use
SCRATCH_SURFACE_STATE_POOL_SIZE.
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
b3f6e5dc702 ('anv: remove incorrect ifdef')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25011>
Matt Turner [Sat, 2 Sep 2023 12:22:53 +0000 (08:22 -0400)]
intel: Limit Intel Vulkan RT to x86_64
Note: passed CI repeatedly except for the timing out WHL jobs.
Fixes:
28c1053c07c ("intel: Allow using intel_clc from the system")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25009>
Alyssa Rosenzweig [Sat, 2 Sep 2023 19:43:01 +0000 (15:43 -0400)]
ci: Disable WHL jobs
Timing out all day.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Wed, 30 Aug 2023 00:56:53 +0000 (20:56 -0400)]
ci: Disable known broken Bifrost Vulkan job
Until someone does the work to eliminate faults, PanVK will be inherently flaky
and should not be in CI. deqp-runner can eat a lot of flakes, and then retrying
the whole job eats more flakes, but neither is a substitute for not testing
known broken (and hence flaky) code and both increase runtime unacceptably. the
g52-vk job earned 2 spots on the latest leaderboard for slowest jobs, I clicked
on https://gitlab.freedesktop.org/mesa/mesa/-/jobs/
48142375 to see a jawdropping
54 flakes reported by deqp-runner.
If people insist on keeping the job, then panfrost-g52-vk needs to be demoted to
manual until after someone fixes all these bugs on the driver side. If that's
not going to happen, then there's no point in it being in CI at all. It's broken
code. After a buggy MR, it'll still be broken code. CI doesn't matter if we're
ok with it being broken.
Bottom line is, we can't be running known broken code in CI (bugs = faults =
flakes = unhappy developers), at least for non-robust stacks (panfrost.ko
included). This needs to be policy if it isn't already. Merging this single
character change deals with the hot problem without any fanfare or adverse
effects.
This turns the job into a nightly as David suggested to get it out of the
premerge path until someone is committed to supporting it and does the work to
make it happen.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9721
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24943>
Georg Lehmann [Tue, 8 Aug 2023 11:35:18 +0000 (13:35 +0200)]
aco: implement some exclusive scans with inclusive scans
exclusive scan lowering uses full wave shift, for iadd/ixor it's faster
to do inclusive scans and subtract/xor the thread's source.
Foz-DB Navi21:
Totals from 21 (0.02% of 132657) affected shaders:
Instrs: 10925 -> 10727 (-1.81%)
CodeSize: 58064 -> 56488 (-2.71%)
Latency: 178471 -> 177928 (-0.30%)
InvThroughput: 24374 -> 24145 (-0.94%)
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24555>
Karol Herbst [Tue, 29 Aug 2023 19:59:31 +0000 (21:59 +0200)]
rusticl/memory: only specify PIPE_BIND_SHADER_IMAGE where supported
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24982>
Georg Lehmann [Sat, 12 Aug 2023 22:14:29 +0000 (00:14 +0200)]
nir: add nir_scalar_equal
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24656>
Georg Lehmann [Sat, 12 Aug 2023 22:03:03 +0000 (00:03 +0200)]
nir: add nir_scalar intrinsic helpers
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24656>
David Heidelberg [Wed, 30 Aug 2023 19:11:26 +0000 (21:11 +0200)]
docs: add LAVA farm informations
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24959>
David Heidelberg [Wed, 30 Aug 2023 17:49:20 +0000 (19:49 +0200)]
Revert "ci: disable a660 jobs"
This reverts commit
209ed8eace0ba9095e3ef956a10cd9196407047f.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24959>
Lionel Landwerlin [Wed, 14 Jun 2023 09:31:19 +0000 (12:31 +0300)]
anv: enable standard Y tiles
We kept those tilings disabled up to know. Now that ISL has proper
support for them, remove this.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Jason Ekstrand [Thu, 11 Oct 2018 21:38:31 +0000 (16:38 -0500)]
anv: Align memory VA to support for Ys, Tile64 tiled images
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Aditya Swarup [Thu, 8 Jun 2023 22:22:11 +0000 (15:22 -0700)]
isl: enable Tile64 for 3D images
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Jason Ekstrand [Thu, 22 Feb 2018 03:02:09 +0000 (19:02 -0800)]
intel/isl: Allow Ys tiling
Ys & Yf are both implemented in ISL now, we still have some Yf issues
to investigate. Instead of disabling them in ISL, we disable them in
the two drivers.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Lionel Landwerlin [Mon, 26 Jun 2023 10:03:23 +0000 (13:03 +0300)]
isl: reorder tiling selection
Select tilings in this order :
- recommended Y tilings
- Yf tilings
- Ys/Tile64 tilings
- legacy tilings (W, X) & Linear
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Lionel Landwerlin [Wed, 28 Jun 2023 06:32:54 +0000 (09:32 +0300)]
intel/aux_map: correctly program tiling mode for Ys
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Lionel Landwerlin [Wed, 21 Jun 2023 15:44:27 +0000 (18:44 +0300)]
blorp: allow 3D blits/copies on Ys/Yf/Tile64 tiling
The data in Ys/Yf/Tile64 tiled images is arranged differently for 2D &
3D images. Therefore we cannot assume that we will use 2D images for
blits/copies.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Lionel Landwerlin [Tue, 15 Aug 2023 13:24:59 +0000 (16:24 +0300)]
isl: disable CCS on Ys/Yf
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Lionel Landwerlin [Tue, 27 Jun 2023 11:42:52 +0000 (14:42 +0300)]
isl: disable miptails on gfx12 with yuv formats
A number of CTS tests are failing, like :
dEQP-VK.ycbcr.format.b8g8r8g8_422_unorm.vertex_optimal
Failures are reproduced on simulation.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Lionel Landwerlin [Tue, 27 Jun 2023 11:06:43 +0000 (14:06 +0300)]
isl: disallow miptails on planar formats
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Lionel Landwerlin [Wed, 28 Jun 2023 11:29:30 +0000 (14:29 +0300)]
isl: add Gfx12/12.5 restriction on 3D surfaces & compression
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Jason Ekstrand [Tue, 6 Mar 2018 01:42:11 +0000 (17:42 -0800)]
intel/isl: Disallow CCS on 3D surfaces with miptails
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Jason Ekstrand [Sat, 3 Mar 2018 03:02:17 +0000 (19:02 -0800)]
intel/isl: Start using miptails
This commit adds the code for choosing where to start the miptail and
enables miptails by default unless the client driver passes
info->min_miptail_start_level >= info->levels.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Jason Ekstrand [Sat, 3 Mar 2018 00:43:35 +0000 (16:43 -0800)]
intel/isl: Support miptails in isl_surf_get_uncompressed_surf
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Lionel Landwerlin [Tue, 29 Aug 2023 08:54:47 +0000 (11:54 +0300)]
isl: make isl_surf_get_uncompressed_surf robust to argument accesses
Since the input & output arguments can point to the same location in
memory, if you ever access the input after writing the output you're
in trouble.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Jason Ekstrand [Fri, 2 Mar 2018 20:37:52 +0000 (12:37 -0800)]
intel/isl: Add support for computing offsets with miptails
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Lionel Landwerlin [Fri, 2 Mar 2018 23:30:24 +0000 (15:30 -0800)]
intel/isl: Add a max_miptail_levels field to isl_tile_info
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Jason Ekstrand [Sat, 3 Mar 2018 00:02:58 +0000 (16:02 -0800)]
intel/isl: Add initial data-structure support for miptails
This commit just adds a miptail start field to isl_surf and wires it up
in the RENDER_SURFACE_STATE and 3DSTATE_DEPTH code. We also add a
minimum miptail LOD so that client drivers have a knob to control the
miptails a bit.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Jason Ekstrand [Fri, 25 Aug 2017 18:23:23 +0000 (11:23 -0700)]
intel/isl: Support Yf/Ys tiling in emit_depth_stencil_hiz
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Jason Ekstrand [Fri, 25 Aug 2017 04:16:03 +0000 (21:16 -0700)]
intel/isl: Support Yf/Ys tiling in surf_fill_state
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Jason Ekstrand [Thu, 22 Feb 2018 21:53:03 +0000 (13:53 -0800)]
intel/isl: Support Ys, Yf & Tile64 in isl_surf_get_uncompressed_surf
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Jason Ekstrand [Wed, 7 Jul 2021 15:37:57 +0000 (10:37 -0500)]
intel/isl: Indent uncompressed surface code
We're about to add separate code for Yf/Ys and this helps keep the diff
reasonable.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Jason Ekstrand [Thu, 22 Feb 2018 02:12:30 +0000 (18:12 -0800)]
intel/isl: Fill out the correct phys_total_extent for Ys/Yf/Tile64
With these tilings, everything is aligned to a tile and the tiled
surface size calculations will handle the array stride for us. We need
to provide an accurate 4D size so that 3D and multisampled images get
tiled correctly.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Jason Ekstrand [Thu, 22 Feb 2018 02:05:15 +0000 (18:05 -0800)]
intel/isl: Use the depth field of phys_level0_sa for GFX4_2D 3D surfaces
This makes things a tiny bit stickier in isl_calc_phys_total_extent_el
but will be worth it when we enable Yf and Ys.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Lionel Landwerlin [Sun, 25 Jun 2023 20:31:39 +0000 (23:31 +0300)]
isl: disallow TileYs/Yf on 3D storage images on Gfx9/11
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Lionel Landwerlin [Fri, 23 Jun 2023 21:47:25 +0000 (00:47 +0300)]
isl: add a usage flag to request 2D/3D compatible views
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Lionel Landwerlin [Tue, 8 Aug 2023 11:14:02 +0000 (14:14 +0300)]
isl: disable Yf/Ys/Tile64 tilings for 1D images
The ICL+ PRMs show that this is not a supported thing anymore for
Ys/Yf and there isn't really much use for it in Vulkan/Sparse.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Lionel Landwerlin [Fri, 12 Oct 2018 17:17:02 +0000 (12:17 -0500)]
intel/isl: Disallow Yf, Ys and Tile64 for 3D depth/stencil surfaces
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
Jason Ekstrand [Thu, 22 Feb 2018 00:04:32 +0000 (16:04 -0800)]
intel/isl: Implement correct tile size calculations for Ys/Yf
The tile size calculations use a clever bit of math to make them short
and simple. We add unit tests to assert that they identically match the
tables in the PRM.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>