Arthur Eubanks [Mon, 6 Dec 2021 21:04:57 +0000 (13:04 -0800)]
[NFC] Clarify comment about LoopDeletionPass in the optimization pipeline
Reviewed By: lebedev.ri
Differential Revision: https://reviews.llvm.org/D115179
Kirill Stoimenov [Tue, 7 Dec 2021 02:47:11 +0000 (02:47 +0000)]
[ASan] Refactored SHADOW_OFFSET implementation to use SHADOW_OFFSET_CONST.
Reviewed By: vitalybuka
Differential Revision: https://reviews.llvm.org/D115213
Greg Clayton [Tue, 7 Dec 2021 17:44:22 +0000 (09:44 -0800)]
Modify DataEncoder to be able to encode data in an object owned buffer.
DataEncoder was previously made to modify data within an existing buffer. As the code progressed, new clients started using DataEncoder to create binary data. In these cases the use of this class was possibly, but only if you knew exactly how large your buffer would be ahead of time. This patchs adds the ability for DataEncoder to own a buffer that can be dynamically resized as data is appended to the buffer.
Change in this patch:
- Allow a DataEncoder object to be created that owns a DataBufferHeap object that can dynamically grow as data is appended
- Add new methods that start with "Append" to append data to the buffer and grow it as needed
- Adds full testing of the API to assure modifications don't regress any functionality
- Has two constructors: one that uses caller owned data and one that creates an object with object owned data
- "Append" methods only work if the object owns it own data
- Removes the ability to specify a shared memory buffer as no one was using this functionality. This allows us to switch to a case where the object owns its own data in a DataBufferHeap that can be resized as data is added
"Put" methods work on both caller and object owned data.
"Append" methods work on only object owned data where we can grow the buffer. These methods will return false if called on a DataEncoder object that has caller owned data.
The main reason for these modifications is to be able to use the DateEncoder objects instead of llvm::gsym::FileWriter in https://reviews.llvm.org/D113789. This patch wants to add the ability to create symbol table caching to LLDB and the code needs to build binary caches and save them to disk.
Reviewed By: labath
Differential Revision: https://reviews.llvm.org/D115073
Peter Klausler [Mon, 6 Dec 2021 15:42:13 +0000 (07:42 -0800)]
[flang] Remove runtime check from OpenFile::Close()
In error cases it is possible to CLOSE a unit that has not
been successfully connected, so don't crash when the file descriptor
is negative.
Differential Revision: https://reviews.llvm.org/D115165
Peter Klausler [Sat, 4 Dec 2021 19:30:01 +0000 (11:30 -0800)]
[flang] Avoid potential deadlock in CloseAll()
When closing all open units, don't hold the unit map lock
over the actual close operations; if one of those aborts,
CloseAll() may be called and then deadlock.
Differential Review: https://reviews.llvm.org/D115184
Craig Topper [Tue, 7 Dec 2021 15:12:04 +0000 (07:12 -0800)]
[RISCV] Revise RISCVInstPrinter::printVTypeI to not assume there are 3 invalid vtype bits.
Instead of checking [10:8]. Check for non-zero in 8 and above.
Addresses a post-commit comment from @jrtc27 in D114581.
lh123 [Tue, 7 Dec 2021 17:16:38 +0000 (01:16 +0800)]
[clangd] Print type for VarTemplateDecl in hover.
Print type for VarTemplateDecl in hover.
Reviewed By: sammccall
Differential Revision: https://reviews.llvm.org/D115108
Kazu Hirata [Tue, 7 Dec 2021 17:17:03 +0000 (09:17 -0800)]
[llvm] Use range-based for loops (NFC)
Corentin Jabot [Tue, 7 Dec 2021 17:13:35 +0000 (12:13 -0500)]
Do not check if we are in a discared context in non-immediate contexts
This fixes in a regression introduced by
6eeda06c1.
When deducing the return type of nested function calls, only the
return type of the outermost expression should be ignored.
Instead of assuming all contextes nested in a discared statements
are themselves discarded, only assume that in immediate contexts.
Similarly, only consider contextes immediately in an immediate or
discarded statement as being themselves immediate.
LLVM GN Syncbot [Tue, 7 Dec 2021 17:01:16 +0000 (17:01 +0000)]
[gn build] Port
fa99cb64ff0e
Mircea Trofin [Mon, 6 Dec 2021 22:59:19 +0000 (14:59 -0800)]
[mlgo][regalloc] Add score calculation for training
Add the calculation of a score, which will be used during ML training. The
score qualifies the quality of a regalloc policy, and is independent of
what we train (currently, just eviction), or the regalloc algo itself.
We can then use scores to guide training (which happens offline), by
formulating a reward based on score variation - the goal being lowering
scores (currently, that reward is percentage reduction relative to
Greedy's heuristic)
Currently, we compute the score by factoring different instruction
counts (loads, stores, etc) with the machine basic block frequency,
regardless of the instructions' provenance - i.e. they could be due to
the regalloc policy or be introduced previously. This is different from
RAGreedy::reportStats, which accummulates the effects of the allocator
alone. We explored this alternative but found (at least currently) that
the more naive alternative introduced here produces better policies. We
do intend to consolidate the two, however, as we are actively
investigating improvements to our reward function, and will likely want
to re-explore scoring just the effects of the allocator.
In either case, we want to decouple score calculation from allocation
algorighm, as we currently evaluate it after a few more passes after
allocation (also, because score calculation should be reusable
regardless of allocation algorithm).
We intentionally accummulate counts independently because it facilitates
per-block reporting, which we found useful for debugging - for instance,
we can easily report the counts indepdently, and then cross-reference
with perf counter measurements.
Differential Revision: https://reviews.llvm.org/D115195
Aaron Ballman [Tue, 7 Dec 2021 16:48:07 +0000 (11:48 -0500)]
Add diagnostic groups for attribute extensions
Some users have a need to control attribute extension diagnostics
independent of other extension diagnostics. Consider something like use
of [[nodiscard]] within C++11:
```
[[nodiscard]]
int f();
```
If compiled with -Wc++17-extensions enabled, this will produce warning:
use of the 'nodiscard' attribute is a C++17 extension. This diagnostic
is correct -- using [[nodiscard]] in C++11 mode is a C++17 extension.
And the behavior of __has_cpp_attribute(nodiscard) is also correct --
we support [[nodiscard]] in C++11 mode as a conforming extension. But
this makes use of -Werror or -pedantic-errors` builds more onerous.
This patch adds diagnostic groups for attribute extensions so that
users can selectively disable attribute extension diagnostics. I
believe this is preferable to requiring users to specify additional
flags because it means -Wc++17-extensions continues to be the way we
enable all C++17-related extension diagnostics. It would be quite easy
for someone to use that flag thinking they're protected from some
portability issues without realizing it skipped attribute extensions if
we went the other way.
This addresses PR33518.
spupyrev [Tue, 7 Dec 2021 16:22:29 +0000 (08:22 -0800)]
fixing a broken ext-tsp test
the test requires debug build
example of a failed buildbot:
https://lab.llvm.org/buildbot/#/builders/91/builds/211/steps/8/logs/stdio
Differential Revision: https://reviews.llvm.org/D115255
Florian Hahn [Tue, 7 Dec 2021 16:26:31 +0000 (16:26 +0000)]
[VPlan] Verify plan entry and exit blocks, set correct exit block.
Both the entry and exit blocks of the top-region of a plan must be
VPBasicBlocks. They also must have no predecessors or successors
respectively.
This invariant was broken when splitting a block for sink-after. To fix
the issue, set the exit block of the region *after* sink-after is done.
Reviewed By: Ayal
Differential Revision: https://reviews.llvm.org/D114586
Jay Foad [Tue, 7 Dec 2021 09:35:59 +0000 (09:35 +0000)]
[AMDGPU] Mark time intrinsics as nomem, hassideeffects
Adding IntrHasSideEffects to @llvm.amdgcn.s.memtime and
@llvm.amdgcn.s.memrealtime means that we can stop pretending they read
and write memory, and similarly for the corresponding pseudo
instructions.
This should stop these intrinsics from being rescheduled past all other
instructions, even ones which don't load or store.
See also https://reviews.llvm.org/D58635.
Differential Revision: https://reviews.llvm.org/D115227
Peter Klausler [Mon, 6 Dec 2021 21:26:56 +0000 (13:26 -0800)]
[flang] Fix INQUIRE(FILE=,NAME=)
The file name output was not being copied back to the program
from the runtime.
Differential Revision: https://reviews.llvm.org/D115190
Sanjay Patel [Tue, 7 Dec 2021 15:43:45 +0000 (10:43 -0500)]
[InstSimplify] add logic fold for 'or' with 'xor'+'and'
This replaces the 'or' from
4b30076f16fc with an 'and'.
We have to guard against propagating undef elements from
vector 'not' values:
https://alive2.llvm.org/ce/z/irMwRc
Sanjay Patel [Mon, 6 Dec 2021 18:16:08 +0000 (13:16 -0500)]
[InstCombine] add tests for rem with select operand; NFC
Craig Topper [Tue, 7 Dec 2021 15:12:04 +0000 (07:12 -0800)]
[RISCV] Replace uses of RISCVOpcode<
0b0010011> and RISCVOpcode<
0b0011011> with existing named objects. NFC
These are already instantiated with names as OPC_OP_IMM and
OPC_OP_IMM_32.
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D115172
Lei Zhang [Tue, 7 Dec 2021 15:52:09 +0000 (10:52 -0500)]
[mlir][scf] NFC: create dedicated files for affine utils
These functions are generic utility functions that operates on
affine ops within SCF regions. Moving them to their own files
for a better code structure, instead of mixing with loop
specialization logic.
Reviewed By: nicolasvasilache
Differential Revision: https://reviews.llvm.org/D115245
LLVM GN Syncbot [Tue, 7 Dec 2021 15:31:37 +0000 (15:31 +0000)]
[gn build] Port
f573f6866e18
spupyrev [Mon, 8 Nov 2021 15:02:33 +0000 (07:02 -0800)]
ext-tsp basic block layout
A new basic block ordering improving existing MachineBlockPlacement.
The algorithm tries to find a layout of nodes (basic blocks) of a given CFG
optimizing jump locality and thus processor I-cache utilization. This is
achieved via increasing the number of fall-through jumps and co-locating
frequently executed nodes together. The name follows the underlying
optimization problem, Extended-TSP, which is a generalization of classical
(maximum) Traveling Salesmen Problem.
The algorithm is a greedy heuristic that works with chains (ordered lists)
of basic blocks. Initially all chains are isolated basic blocks. On every
iteration, we pick a pair of chains whose merging yields the biggest increase
in the ExtTSP value, which models how i-cache "friendly" a specific chain is.
A pair of chains giving the maximum gain is merged into a new chain. The
procedure stops when there is only one chain left, or when merging does not
increase ExtTSP. In the latter case, the remaining chains are sorted by
density in decreasing order.
An important aspect is the way two chains are merged. Unlike earlier
algorithms (e.g., based on the approach of Pettis-Hansen), two
chains, X and Y, are first split into three, X1, X2, and Y. Then we
consider all possible ways of gluing the three chains (e.g., X1YX2, X1X2Y,
X2X1Y, X2YX1, YX1X2, YX2X1) and choose the one producing the largest score.
This improves the quality of the final result (the search space is larger)
while keeping the implementation sufficiently fast.
Differential Revision: https://reviews.llvm.org/D113424
Kirill Bobyrev [Tue, 7 Dec 2021 14:46:12 +0000 (15:46 +0100)]
[clangd] Dex Trigrams: Improve query trigram generation
These are the trigrams for queries right now:
- "va" -> {Trigram("va")}
- "va_" -> {} (empty)
This is suboptimal since the resulting query will discard the query information
and return all symbols, some of which will be later be scored expensively
(fuzzy matching score). This is related to
https://github.com/clangd/clangd/issues/39 but does not fix it. Accidentally,
because of that incorrect behavior, when user types "tok::va" there are no
results (the issue is that `tok::kw___builtin_va_arg` does not have "va" token)
but when "tok::va_" is typed, expected result (`tok::kw___builtin_va_arg`)
shows up by accident. This is because the dex query transformer will only
lookup symbols within the `tok::` namespace. There won't be many, so the
returned results will contain symbol we need; this symbol will be filtered out
by the expensive checks and that will be displayed in the editor.
Reviewed By: sammccall
Differential Revision: https://reviews.llvm.org/D113995
gbreynoo [Tue, 7 Dec 2021 14:18:42 +0000 (14:18 +0000)]
[llvm-symbolizer][docs] Update --output-style=JSON example
The fields output when using --output-style=JSON has changed but the
guide wasn't updated. This change fixes up the example.
Differential Revision: https://reviews.llvm.org/D115164
David Green [Tue, 7 Dec 2021 14:18:32 +0000 (14:18 +0000)]
[ARM] Additional tests for qr instructions with constant operands. NFC
Florian Hahn [Tue, 7 Dec 2021 13:46:24 +0000 (13:46 +0000)]
[EarlyCSE] Add test case with inbounds gep where flags can be retained.
Florian Hahn [Tue, 7 Dec 2021 13:46:13 +0000 (13:46 +0000)]
[EarlyCSE] Auto-generate check lines for flags.ll.
The test already checks the full IR. To make updating easier,
auto-generate the check lines.
Carlos Galvez [Tue, 7 Dec 2021 13:35:38 +0000 (13:35 +0000)]
[doc] Fix namespace comment style in Coding Guidelines
The Coding Guidelines specify that the ending brace of a
namespace shall have a comment like:
} // end namespace clang
However the majority of the code uses a different style:
} // namespace clang
Indeed:
$ git grep '// end' | wc -l
6724
$ git grep '// namespace' | wc -l
14348
Besides, this is the style enforced automatically by clang-format,
via the FixNamespaceComments option.
Having inconsistencies between the Coding Guidelines and the
code/tooling creates confusion, can lead to bikeshedding during
reviews and overall delays merging code. Therefore, update the
guidelines to reflect current usage. Updating legacy code to the
new standard should be done in a separate patch, if wanted.
Reviewed By: jyknight
Differential Revision: https://reviews.llvm.org/D115115
Pavel Labath [Tue, 7 Dec 2021 13:10:43 +0000 (14:10 +0100)]
[lldb] Fix flakyness in TestQemuLaunch.test_stdio_redirect
The test was flaky because it was trying to read from the (redirected)
stdout file before the data was been flushed to it. This would not be a
problem for a "normal" debug session, but since here the emulator and
the target binary coexist in the same process (and this is true both for
real qemu and our fake implementation), there
is a window of time between the stub returning an exit packet (which is
the event that the test is waiting for) and the process really exiting
(which is when the normal flushing happens).
This patch adds an explicit flush to work around this. Theoretically,
it's possible that real code could run into this issue as well, but such
a use case is not very likely. If we wanted to fix this for real, we
could add some code which waits for the host process to terminate (in
addition to receiving the termination packet), but this is somewhat
complicated by the fact that this code lives in the gdb-remote process
plugin.
Pavel Labath [Fri, 26 Nov 2021 14:51:09 +0000 (15:51 +0100)]
[lldb/qemu] Add emulator-args setting
This setting allows the user to pass additional arguments to the qemu instance.
While we may want to introduce dedicated settings for the most common qemu
arguments (-cpu, for one), having this setting allows us to avoid creating a
setting for every possible argument.
Differential Revision: https://reviews.llvm.org/D115151
Nicolas Vasilache [Tue, 7 Dec 2021 13:03:24 +0000 (13:03 +0000)]
[mlir][Linalg] NFC - Extend the TilingInterface to allow better composition with out-of-tree dialects.
Reviewed By: gysit
Differential Revision: https://reviews.llvm.org/D115233
Djordje Todorovic [Tue, 7 Dec 2021 12:48:22 +0000 (04:48 -0800)]
[MIPS] Add FPU Delay Slot for MIPS1/2/3
MIPS I, II, and III have delay slots for floating point
comparisons and floating point register transfers (mtc1, mfc1).
Currently, these are not taken into account and thus broken code
may be generated on these targets. This patch inserts nops
as necessary, while attempting to leave the current instruction
if it is safe to stay.
The tests in this patch were updated by @sajattack
Patch by @overdrivenpotato (Marko Mijalkovic <marko.mijalkovic97@gmail.com>)
Differential Revision: https://reviews.llvm.org/D115127
Aaron Ballman [Tue, 7 Dec 2021 12:56:40 +0000 (07:56 -0500)]
Fix Sphinx formatting in release notes
Matthias Springer [Tue, 7 Dec 2021 11:07:13 +0000 (20:07 +0900)]
[mlir][linalg][bufferize] Add FuncOp bufferization pass
This passes bufferizes FuncOp bodies, but not FuncOp boundaries.
Differential Revision: https://reviews.llvm.org/D114671
Louis Dionne [Tue, 7 Dec 2021 12:30:46 +0000 (07:30 -0500)]
[libc++] Bump Dockerfile
Louis Dionne [Mon, 6 Dec 2021 23:09:47 +0000 (18:09 -0500)]
[libc++] Fix atomic test for _BitInt
In
6c75ab5f66b4, Clang deprecated _ExtInt in favor of _BitInt, which
made this test fail. This patch disables the test on older compilers
and uses the new _BitInt type instead.
Differential Revision: https://reviews.llvm.org/D115194
Andrew Savonichev [Mon, 29 Nov 2021 12:59:45 +0000 (15:59 +0300)]
[MCA] Remove the warning about experimental support for in-order CPU
There are not a lot of bug reports for this feature, so let's mark it
stable.
Differential Revision: https://reviews.llvm.org/D114701
Andrew Savonichev [Mon, 15 Nov 2021 10:30:24 +0000 (13:30 +0300)]
[NVPTX] Auto-generate tests for sufrace and texture instructions
The patch adds LIT tests for SULD, SUST, TEX and TLD4 instructions as
a follow up for D112232. There are a number of FIXME marks that
highlight possible bugs or missed instruction variants.
Differential Revision: https://reviews.llvm.org/D114367
Paulo Matos [Mon, 6 Dec 2021 08:51:39 +0000 (09:51 +0100)]
[WebAssembly] Implement table instruction intrinsics
This change implements intrinsics for table.grow, table.fill,
table.size, and table.copy.
Differential Revision: https://reviews.llvm.org/D113420
Peter Waller [Mon, 6 Dec 2021 17:12:55 +0000 (17:12 +0000)]
[AArch64][SVE] Fix fptrunc store for fixed len vector
Restrict duplicate FP_EXTEND/FP_TRUNC -> LOAD/STORE DAG combines to only
larger than NEON types, as these are the ones for which there is custom
lowering.
Update tests so that they go through memory to improve validation.
Differential Revision: https://reviews.llvm.org/D115166
Simon Pilgrim [Tue, 7 Dec 2021 12:05:23 +0000 (12:05 +0000)]
[X86] LowerRotate - pull out repeated splitVectorIntBinary call. NFC.
David Spickett [Tue, 7 Dec 2021 11:55:11 +0000 (11:55 +0000)]
[compiler-rt][libFuzzer] Disable counters test on arm
This test is either very slow or loops forever on 32 bit Arm.
One of a few tests causing timeouts on our buildbots:
https://lab.llvm.org/buildbot/#/builders/190/builds/513
Matthias Springer [Tue, 7 Dec 2021 11:13:24 +0000 (20:13 +0900)]
[mlir][linalg][bufferize] Fix forward declaration
Fraser Cormack [Fri, 3 Dec 2021 11:52:33 +0000 (11:52 +0000)]
[SelectionDAG] Use UnknownSize for VP memory ops
In the style of D113888, this patch updates the various VP memory
operations (load, store, gather, scatter) to use UnknownSize. This is
for the same reason as for masked loads and stores: the number of
elements accessed is not generally known at compile time.
This is somewhat pessimistic in the sense that we may still find
un-canonicalized intrinsics featuring both an all-true mask and an EVL
equal to the vector size. Arguably those should be canonicalized before
the SelectionDAG, so those have been left for future work.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D115036
Matthias Springer [Tue, 7 Dec 2021 08:53:45 +0000 (17:53 +0900)]
[mlir][linalg][bufferize] Bufferize Operation* instead of FuncOp
This change mainly changes the API. There is no mentioning of FuncOps in ComprehensiveBufferize anymore.
Also, bufferize methods of the op interface are called for ops without tensor operands/results if they have a region.
Differential Revision: https://reviews.llvm.org/D115212
Florian Hahn [Tue, 7 Dec 2021 10:52:54 +0000 (10:52 +0000)]
[X86] Add test where block placement separates call from RV marker.
The test shows how block placement can separate a call from the marker
instruction and the ObjC call after CALL_RVMARKER expansion.
Cullen Rhodes [Tue, 7 Dec 2021 09:53:16 +0000 (09:53 +0000)]
[IR] Split vscale_range interface
Interface is split from:
std::pair<unsigned, unsigned> getVScaleRangeArgs()
into separate functions for min/max:
unsigned getVScaleRangeMin();
Optional<unsigned> getVScaleRangeMax();
Reviewed By: sdesmalen, paulwalker-arm
Differential Revision: https://reviews.llvm.org/D114075
Fraser Cormack [Fri, 19 Nov 2021 20:21:47 +0000 (20:21 +0000)]
[VP] Propagate align parameter attr on VP load/store to ISel
This patch fixes a case where the 'align' parameter attribute on the
pointer operands to llvm.vp.load and llvm.vp.store was being dropped
during the conversion to the SelectionDAG. The default alignment
equal to the ABI type alignment of the vector type was kept. It also
updates the documentation to reflect the fact that the parameter
attribute is now properly supported.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D114422
Jaroslav Sevcik [Sat, 4 Dec 2021 20:32:09 +0000 (21:32 +0100)]
[lldb] Fix windows path guessing for root paths
Fix recognizing "<letter>:\" as a windows path.
Differential Revision: https://reviews.llvm.org/D115104
Ties Stuij [Tue, 7 Dec 2021 10:13:17 +0000 (10:13 +0000)]
[ARM] Implement PAC return address signing mechanism for PACBTI-M
This patch implements PAC return address signing for armv8-m. This patch roughly
accomplishes the following things:
- PAC and AUT instructions are generated.
- They're part of the stack frame setup, so that shrink-wrapping can move them
inwards to cover only part of a function
- The auth code generated by PAC is saved across subroutine calls so that AUT
can find it again to check
- PAC is emitted before stacking registers (so that the SP it signs is the one
on function entry).
- The new pseudo-register ra_auth_code is mentioned in the DWARF frame data
- With CMSE also in use: PAC is emitted before stacking FPCXTNS, and AUT
validates the corresponding value of SP
- Emit correct unwind information when PAC is replaced by PACBTI
- Handle tail calls correctly
Some notes:
We make the assembler accept the `.save {ra_auth_code}` directive that is
emitted by the compiler when it saves a register that contains a
return address authentication code.
For EHABI we need to have the `FrameSetup` flag on the instruction and
handle the `t2PACBTI` opcode (identically to `t2PAC`), so we can emit
`.save {ra_auth_code}`, instead of `.save {r12}`.
For PACBTI-M, the instruction which computes return address PAC should use SP
value before adjustment for the argument registers save are (used for variadic
functions and when a parameter is is split between stack and register), but at
the same it should be after the instruction that saves FPCXT when compiling a
CMSE entry function.
This patch moves the varargs SP adjustment after the FPCXT save (they are never
enabled at the same time), so in a following patch handling of the `PAC`
instruction can be placed between them.
Epilogue emission code adjusted in a similar manner.
PACBTI-M code generation should not emit any instructions for architectures
v6-m, v8-m.base, and for A- and R-class cores. Diagnostic message for such cases
is handled separately by a future ticket.
note on tail calls:
If the called function has four arguments that occupy registers `r0`-`r3`, the
only option for holding the function pointer itself is `r12`, but this register
is used to keep the PAC during function/prologue epilogue and clobbers the
function pointer.
When we do the tail call we need the five registers (`r0`-`r3` and `r12`) to
keep six values - the four function arguments, the function pointer and the PAC,
which is obviously impossible.
One option would be to authenticate the return address before all callee-saved
registers are restored, so we have a scratch register to temporarily keep the
value of `r12`. The issue with this approach is that it violates a fundamental
invariant that PAC is computed using CFA as a modifier. It would also mean using
separate instructions to pop `lr` and the rest of the callee-saved registers,
which would offset the advantages of doing a tail call.
Instead, this patch disables indirect tail calls when the called function take
four or more arguments and the return address sign and authentication is enabled
for the caller function, conservatively assuming the caller function would spill
LR.
This patch is part of a series that adds support for the PACBTI-M extension of
the Armv8.1-M architecture, as detailed here:
https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension
The PACBTI-M specification can be found in the Armv8-M Architecture Reference
Manual:
https://developer.arm.com/documentation/ddi0553/latest
The following people contributed to this patch:
- Momchil Velikov
- Ties Stuij
Reviewed By: danielkiss
Differential Revision: https://reviews.llvm.org/D112429
David Spickett [Tue, 7 Dec 2021 10:02:44 +0000 (10:02 +0000)]
[llvm][X86] Add x86 triple to fentry test
When run on AArch64 hardware llc would default to native
arch.
Jay Foad [Tue, 7 Dec 2021 09:53:40 +0000 (09:53 +0000)]
[AMDGPU] Remove redundant mayLoad = 0, mayStore = 0. NFC.
Almost everything in this file is mayLoad = 0, mayStore = 0 by
default anyway.
Cullen Rhodes [Tue, 7 Dec 2021 09:20:42 +0000 (09:20 +0000)]
[IR] Remove unbounded as possible value for vscale_range minimum
The default for min is changed to 1. The behaviour of -mvscale-{min,max}
in Clang is also changed such that 16 is the max vscale when targeting
SVE and no max is specified.
Reviewed By: sdesmalen, paulwalker-arm
Differential Revision: https://reviews.llvm.org/D113294
Gabor Marton [Wed, 1 Dec 2021 20:10:42 +0000 (21:10 +0100)]
[Analyzer] SValBuilder: Simlify a SymExpr to the absolute simplest form
Move the SymExpr simplification fixpoint logic into SValBuilder.
Differential Revision: https://reviews.llvm.org/D114938
Vitaly Buka [Tue, 7 Dec 2021 08:16:28 +0000 (00:16 -0800)]
[sanitizer] Don't lock for StackStore::Allocated()
Vitaly Buka [Tue, 7 Dec 2021 08:10:25 +0000 (00:10 -0800)]
[sanitizer] Fix CompressStackStore VPrint message
LLVM GN Syncbot [Tue, 7 Dec 2021 08:10:43 +0000 (08:10 +0000)]
[gn build] Port
ae53d02f557c
Petr Hosek [Tue, 7 Dec 2021 08:08:51 +0000 (00:08 -0800)]
Revert "Microsoft's floating-point to_chars powered by Ryu and Ryu Printf"
This reverts commit
a8025e06fc0f2fe1bbee9e1a6f15c336bfbdcb05 since
it triggers PR52584 with debug info enabled.
LLVM GN Syncbot [Tue, 7 Dec 2021 06:41:50 +0000 (06:41 +0000)]
[gn build] Port
0fe61ecc2cef
Vitaly Buka [Tue, 7 Dec 2021 06:35:55 +0000 (22:35 -0800)]
[NFC][sanitizer] Non-copyable ScopedBlockSignals
Sameer Sahasrabuddhe [Tue, 7 Dec 2021 06:31:22 +0000 (12:01 +0530)]
CycleInfo: Introduce cycles as a generalization of loops
LLVM loops cannot represent irreducible structures in the CFG. This
change introduce the concept of cycles as a generalization of loops,
along with a CycleInfo analysis that discovers a nested
hierarchy of such cycles. This is based on Havlak (1997), Nesting of
Reducible and Irreducible Loops.
The cycle analysis is implemented as a generic template and then
instatiated for LLVM IR and Machine IR. The template relies on a new
GenericSSAContext template which must be specialized when used for
each IR.
This review is a restart of an older review request:
https://reviews.llvm.org/D83094
Original implementation by Nicolai Hähnle <nicolai.haehnle@amd.com>,
with recent refactoring by Sameer Sahasrabuddhe <sameer.sahasrabuddhe@amd.com>
Differential Revision: https://reviews.llvm.org/D112696
Vitaly Buka [Tue, 7 Dec 2021 06:22:04 +0000 (22:22 -0800)]
[NFC][lsan] Refactor LockThreadRegistry/LockAllocator calls
Vitaly Buka [Tue, 7 Dec 2021 05:17:32 +0000 (21:17 -0800)]
[NFC][sanitizer] Fix typo in comment
Prashant Kumar [Sun, 5 Dec 2021 15:40:41 +0000 (21:10 +0530)]
[MLIR] Simplify division extraction unit testing.
The new `getLocalReprs` function also outputs `dividends` and
`denominators` and hence the CheckDivisionRepresentation fn is
modified to take the newer getLocalReprs function into account.
Signed-off-by: Prashant Kumar <pk5561@gmail.com>
Reviewed By: Groverkss
Differential Revision: https://reviews.llvm.org/D115146
LLVM GN Syncbot [Tue, 7 Dec 2021 05:54:10 +0000 (05:54 +0000)]
[gn build] Port
d9941f74549a
Shraiysh Vaishay [Tue, 7 Dec 2021 04:57:40 +0000 (10:27 +0530)]
[mlir][OpenMP] Added omp.atomic.read lowering
This patch adds lowering from omp.atomic.read to LLVM IR along with the
memory ordering clause. Tests for the same are also added.
Reviewed By: ftynse
Differential Revision: https://reviews.llvm.org/D115134
wren romano [Tue, 7 Dec 2021 01:28:33 +0000 (17:28 -0800)]
[mlir][sparse] Requiring emitCInterface parameter to be explicit
Depends On D115004
Cleans up code legibility by requiring the `emitCInterface` parameter to be explicit at all call-sites, and defining boolean aliases for that parameter.
Reviewed By: aartbik, rriddle
Differential Revision: https://reviews.llvm.org/D115005
Joao Moreira [Tue, 7 Dec 2021 02:34:37 +0000 (10:34 +0800)]
[X86] Fix fentry handling in X86IndirectBranchTracking.cpp
When compiling with indirect branch tracking and fentry (-fcf-protection=branch -mfentry -pg) the X86IndirectBranchTrackingPass will attempt to place endbr in basic blocks, checking for Calls/IsCallReturnTwice. For calling the function IsCallReturnTwice(), the pass attempts to retrieve the first operand of the respective machine instruction. Since FENTRY_CALL is considered a call, and it does not have any argument, the condition inside the pass will attempt to call IsCallReturnTwice on the machine instruction, but since it does not have operands, it will lead into a crash.
Kudos to Alyssa Milburn for helping in the issue triage. The diff brings a test, but to reproduce the problem, follow the steps below.
```
echo "int main() {};" > repro.c
clang repro.c -fcf-protection=branch -mfentry -pg
```
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D111108
Mircea Trofin [Tue, 7 Dec 2021 01:33:13 +0000 (17:33 -0800)]
[NFC][MachineInstr] Pass-by-value DebugLoc in CreateMachineInstr
DebugLoc is cheap to move, passing it by-val rather than const ref to
take advantage of the fact that it is consumed that way by the
MachineInstr ctor, which creates some optimization oportunities.
Differential Revision: https://reviews.llvm.org/D115208
Lang Hames [Tue, 7 Dec 2021 01:22:30 +0000 (12:22 +1100)]
[ORC] Pad section start to account for alignment offset in MachO GDB JIT plugin.
In order to present a well-formed MachO debug object for debugger registration
the first block in each section must have a zero alignment offset (since there
is no way to represent a non-zero offset in a MachO section load command). This
patch updates the MachODebugObjectSynthesizer class to introduce a padding
padding block at the start of the section if necessary to guarantee a zero
alignment offset.
Igor Kudrin [Tue, 7 Dec 2021 03:10:24 +0000 (10:10 +0700)]
[ELF] Do not report undefined weak references in shared libraries
This fixes an issue introduced in D101996.
A weak reference in a shared library could be incorrectly reported if
there is another library that has a strong reference to the same symbol.
Differential Revision: https://reviews.llvm.org/D115041
Kai Luo [Tue, 7 Dec 2021 02:09:18 +0000 (02:09 +0000)]
[MachineVerifier] Make TiedOpsRewritten computable in MIRParser
This patch is to address post-commit comment https://reviews.llvm.org/D80538#anchor-inline-1091625, which make the constraint stronger based on what https://reviews.llvm.org/D80538 does, i.e., "TiedOpsRewritten is set iff leave-ssa and all tied operands share the same register".
Reviewed By: MatzeB
Differential Revision: https://reviews.llvm.org/D114573
Med Ismail Bennani [Tue, 7 Dec 2021 01:55:19 +0000 (17:55 -0800)]
[lldb/test] Fix InvalidScriptedThread windows test failure
This patch should fix a Windows test failure for the
InvalidScriptedThread test:
https://lab.llvm.org/buildbot/#/builders/83/builds/12571
This refactors the test to stop using python `tempfile` since it's not
supported on Windows and creates a logfile at runtime in the test folder.
Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
Luís Ferreira [Tue, 7 Dec 2021 00:52:38 +0000 (00:52 +0000)]
[Demangle] Add support for D function-local parent symbols
Internally `__Sddd` function-local parent symbols are used to solve ambiguities on symbols in
the same scope with the same mangled name.
Reviewed By: dblaikie
Differential Revision: https://reviews.llvm.org/D114309
Luís Ferreira [Tue, 7 Dec 2021 00:52:37 +0000 (00:52 +0000)]
[Demangle] Add support for D special identifiers
Reviewed By: dblaikie
Differential Revision: https://reviews.llvm.org/D114308
not-jenni [Tue, 7 Dec 2021 01:13:51 +0000 (17:13 -0800)]
[mlir][tosa] Add tosa.depthwise_conv2d as tosa.mul canonicalization
For a 1x1 weight and stride of 1, the input/weight can be reshaped and
multiplied elementwise then reshaped back
Reviewed By: rsuderman, KoolJBlack
Differential Revision: https://reviews.llvm.org/D115207
Noah Shutty [Mon, 6 Dec 2021 18:28:07 +0000 (18:28 +0000)]
[Support] [Debuginfod] Move HTTPClient to Debuginfod library.
Following the discussion in D112753, this moves the HTTPClient from Support to Debuginfod library so that tools depending on Support do not automatically depend on Curl as well. This also removes `HTTPClient::initialize()` and `HTTPClient::cleanup()` from `InitLLVM` so these steps should be implemented by user tools instead.
Reviewed By: phosek
Differential Revision: https://reviews.llvm.org/D115131
Mircea Trofin [Tue, 7 Dec 2021 01:17:55 +0000 (17:17 -0800)]
[NFC][MachineInstr] Rename some vars to conform to coding style
Evandro Menezes [Fri, 2 Apr 2021 18:55:19 +0000 (13:55 -0500)]
[RISCV] Add scheduling resources for Vector pseudo instructions.
Add the scheduling resources for the V extension pseudo instructions.
Authored-by: Evandro Menezes <evandro.menezes@sifive.com>
Differential Revision: https://reviews.llvm.org/D113353
Chen Zheng [Tue, 16 Nov 2021 07:50:37 +0000 (07:50 +0000)]
[PowerPC][NFC] add cases for D114062
Matthias Springer [Mon, 6 Dec 2021 10:36:48 +0000 (19:36 +0900)]
[mlir][linalg][bufferize][NFC] Clean up BufferizationState
Make fields private and clean up the interface. In particular, BufferizableOpInterface::bufferize no longer has access to `aliasInfo`. This was potentially dangerous because some of the ops registered in BufferizationAliasInfo may have been deleted.
Differential Revision: https://reviews.llvm.org/D114931
Nico Weber [Mon, 6 Dec 2021 14:33:20 +0000 (09:33 -0500)]
[tsan] Move tsan/rtl build rules into tsan/rtl/CMakeLists.txt
That way, the build rules are closer to the source files they describe.
No intended behavior change.
Differential Revision: https://reviews.llvm.org/D115155
Nico Weber [Tue, 7 Dec 2021 00:12:58 +0000 (19:12 -0500)]
Tweak diagnostic text from
e4eb6216c2e
Ye Luo [Tue, 7 Dec 2021 00:19:08 +0000 (18:19 -0600)]
[OpenMP][libomptarget] amdgpu plugin adds runpath for dependencies
amdgpu plugin depends on libhsa-runtime64 library. Add runpath in case it is not on the LD_LIBRARY_PATH.
Reviewed By: JonChesterfield
Differential Revision: https://reviews.llvm.org/D115198
Med Ismail Bennani [Thu, 2 Dec 2021 02:56:29 +0000 (18:56 -0800)]
[lldb/plugins] Add arm64(e) support to ScriptedProcess
This patch adds support for arm64(e) targets to ScriptedProcess, by
providing the `DynamicRegisterInfo` to the base `lldb.ScriptedThread` class.
This allows create and debugging ScriptedProcess on Apple Silicon
hardware as well as Apple mobile devices.
It also replace the C++ asserts on `ScriptedThread::GetDynamicRegisterInfo`
by some error logging, re-enables `TestScriptedProcess` for arm64
Darwin platforms and adds a new invalid Scripted Thread test.
rdar://
85892451
Differential Revision: https://reviews.llvm.org/D114923
Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
Nico Weber [Tue, 7 Dec 2021 00:08:59 +0000 (19:08 -0500)]
[gn build] Port
3678326d2839
Nico Weber [Tue, 7 Dec 2021 00:08:20 +0000 (19:08 -0500)]
Revert "ext-tsp basic block layout"
This reverts commit
c68f71eb37c2b6ffcf29e865d443a910e73083bd.
Breaks tests on arm hosts, see comments on https://reviews.llvm.org/D113424
Nico Weber [Mon, 6 Dec 2021 23:41:37 +0000 (18:41 -0500)]
Fix incorrect fallthrough in
e4eb6216c2e
Rob Suderman [Mon, 6 Dec 2021 23:33:03 +0000 (15:33 -0800)]
[mlir][tosa] Resubmit add tosa.conv2d as tosa.fully_connected canonicalization
Fixed the tosa.conv2d to tosa.fully_connected canonicalization for incorrect
output channels. Included uptes to tests to include checks for the result
shapes during canonicalization.
This allows conv2d to transform to the simpler fully_connected operation.
Reviewed By: mravishankar
Differential Revision: https://reviews.llvm.org/D115170
Dave Lee [Mon, 6 Dec 2021 21:04:27 +0000 (13:04 -0800)]
[lldb] Remove some trivial scoped timers
While profiling lldb (from swift/llvm-project), these timers were noticed to be short lived and high firing, and so they add noise more than value.
The data points I recorded are:
`FindTypes_Impl`: 49,646 calls, 812ns avg, 40.33ms total
`AppendSymbolIndexesWithName`: 36,229 calls, 913ns avg, 33.09ms total
`FindAllSymbolsWithNameAndType`: 36,229 calls, 1.93µs avg, 70.05ms total
`FindSymbolsWithNameAndType`: 23,263 calls, 3.09µs avg, 71.88ms total
Differential Revision: https://reviews.llvm.org/D115182
Chris Davis [Mon, 6 Dec 2021 23:11:34 +0000 (18:11 -0500)]
Enable pdbpagesize to allow support for PDB file sizes > 4GB
Enable the pdbpagesize flag to allow linking of PDB files > 4GB.
Also includes a couple small fixes to change to uint64_t to support the
larger file sizes. I updated the max file size check in MSFBuilder.cpp
to take into account the page size.
Differential Revision: https://reviews.llvm.org/D115051
LLVM GN Syncbot [Mon, 6 Dec 2021 23:16:18 +0000 (23:16 +0000)]
[gn build] Port
cc3bb8558018
Nico Weber [Mon, 6 Dec 2021 23:15:20 +0000 (18:15 -0500)]
Reland "[gn build] (manually) port
4a16fe1369f3ab (debuginfod)"
This reverts commit
4b63562ebcfa2bc194a778018e212dc3b99528f7.
The debuginfod change relanded in
0e0f1b28fce8
Kirill Stoimenov [Mon, 6 Dec 2021 23:07:21 +0000 (23:07 +0000)]
Revert "[ASan] Added asan_shadow_defines.h, which contatins shadow offset for various platforms."
This reverts commit
2f3bb59f512f8904fb2f0d7cd7bead3172fbc5d1.
Reviewed By: kstoimenov
Differential Revision: https://reviews.llvm.org/D115193
Daniele Castagna [Mon, 6 Dec 2021 23:06:29 +0000 (15:06 -0800)]
[CUDA][SPIRV] Use OpenCLKernel CC for CUDA -> SPIRV
Select the OpenCLKernel calling convention for kernels when compiling
CUDA targeting SPIR-V.
In this way the generated LLVM IR will have a spir_kernel calling
convention that will be translated to an OpEntryPoint when converting
to SPIRV.
Reviewed By: jlebar, tra
Differential Revision: https://reviews.llvm.org/D114407
James Nagurne [Fri, 22 Oct 2021 22:08:16 +0000 (17:08 -0500)]
[llvm][Hexagon] Generalize VLIWResourceModel, VLIWMachineScheduler, and ConvergingVLIWScheduler
The Pre-RA VLIWMachineScheduler used by Hexagon is a relatively generic
implementation that would make sense to use on other VLIW targets.
This commit lifts those classes into their own header/source file with the
root VLIWMachineScheduler. I chose this path rather than adding the
strategy et al. into MachineScheduler to avoid bloating the file with other
implementations.
Target-specific behaviors have been captured and replicated through
function overloads.
- Added an overloadable DFAPacketizer creation member function. This is
mainly done for our downstream, which has the capability to override
the DFAPacketizer with custom implementations. This is an upstreamable
TODO on our end. Currently, it always returns the result of
TargetInstrInfo::CreateTargetScheduleState
- Added an extra helper which returns the number of instructions in the
current packet. This is used in our downstream, and may be useful
elsewhere.
- Placed the priority heuristic values into the ConvergingVLIWscheduler
class instead of defining them as local statics in the implementation
- Added a overridable helper in ConvergingVLIWScheduler so that targets
can create their own VLIWResourceModel
Differential Revision: https://reviews.llvm.org/D113150
wren romano [Fri, 3 Dec 2021 23:58:03 +0000 (15:58 -0800)]
[mlir][sparse] Code cleanup for SparseTensorConversion
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D115004
Noah Shutty [Mon, 6 Dec 2021 21:46:22 +0000 (21:46 +0000)]
[llvm] [Debuginfo] Debuginfod client library.
This adds a Debuginfod client library which queries servers specified by the `DEBUGINFOD_URLS` environment variable for the debuginfo, executable, or a specified source file associated with a given build id.
Reviewed By: dblaikie
Differential Revision: https://reviews.llvm.org/D112758
Kirill Stoimenov [Fri, 3 Dec 2021 22:24:10 +0000 (22:24 +0000)]
[ASan] Added asan_shadow_defines.h, which contatins shadow offset for various platforms.
Reviewed By: vitalybuka
Differential Revision: https://reviews.llvm.org/D115075
Yaxun (Sam) Liu [Thu, 2 Dec 2021 22:49:36 +0000 (17:49 -0500)]
[HIP] Fix -fgpu-rdc for Windows
This patch fixes issues for -fgpu-rdc for Windows MSVC
toolchain:
Fix COFF specific section flags and remove section types
in llvm-mc input file for Windows.
Escape fatbin path in llvm-mc input file.
Add -triple option to llvm-mc.
Put __hip_gpubin_handle in comdat when it has linkonce_odr
linkage.
Reviewed by: Artem Belevich
Differential Revision: https://reviews.llvm.org/D115039