Dave Airlie [Mon, 26 Jul 2021 05:27:52 +0000 (15:27 +1000)]
crocus/gen4: restrict memcpy mapping to gen5
This is due to gen4 + 4.5 having some rather strange swizzling
that we can't actually detect properly in userspace
Fixes:
f3630548f1da ("crocus: initial gallium driver for Intel gfx 4-7")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12058>
Thong Thai [Tue, 13 Jul 2021 16:04:39 +0000 (12:04 -0400)]
frontends/va: change to per-layer rate control
Allows for each layer in a Scalable Video Coding (SVC) video to have its
own rate control setting, when encoding H.264.
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11850>
Thong Thai [Tue, 13 Jul 2021 16:03:59 +0000 (12:03 -0400)]
frontends/omx: change rate ctrl struct to array
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11850>
Thong Thai [Tue, 13 Jul 2021 16:06:17 +0000 (12:06 -0400)]
radeon/vcn/enc: change to per-temporal layer rate control
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11850>
Thong Thai [Tue, 13 Jul 2021 16:06:00 +0000 (12:06 -0400)]
radeon/vce: change rate ctrl struct to array
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11850>
Thong Thai [Tue, 13 Jul 2021 15:59:50 +0000 (11:59 -0400)]
r600: change rate ctrl struct to array
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11850>
Thong Thai [Tue, 13 Jul 2021 15:59:11 +0000 (11:59 -0400)]
gallium: change rate ctrl struct to array
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11850>
Thong Thai [Tue, 13 Jul 2021 15:51:08 +0000 (11:51 -0400)]
frontends/va: handle h264 num_temporal_layers for SVC encoding
Allows for the number of temporal layers to be specified when encoding
Scalable Video Coding (SVC) H.264 videos.
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11850>
Thong Thai [Tue, 13 Jul 2021 15:55:14 +0000 (11:55 -0400)]
radeonsi: enable H.264 temporal encoding support for VCN
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11850>
Thong Thai [Tue, 13 Jul 2021 15:51:39 +0000 (11:51 -0400)]
radeon/vcn/enc: H.264 SVC encode
Implement H.264 temporal, Scalable Video Coding (SVC) for VCN devices by
sending the required parameters to the firmware, and creating H.264 NALU
prefix and SEI scalability_info headers.
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11850>
Thong Thai [Tue, 13 Jul 2021 15:52:11 +0000 (11:52 -0400)]
gallium: update h264 struct to track temporal layers
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11850>
Thong Thai [Tue, 13 Jul 2021 15:55:28 +0000 (11:55 -0400)]
frontends/va: check number of temporal layers supported by encoder
Checks the encoder to determine the number of temporal layers supported,
and returns max_num_temporal_layers_minus1, along with setting the
corresponding control flag if multiple layers are supported.
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11850>
Thong Thai [Tue, 13 Jul 2021 15:55:00 +0000 (11:55 -0400)]
gallium: add temporal layers cap enum
Determine the number of temporal layers the encoder supports. Used for
encoding Scalable Video Coding (SVC) videos.
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11850>
Danylo Piliaiev [Mon, 26 Jul 2021 15:09:12 +0000 (18:09 +0300)]
tu: handle half-reg fs outputs
This would allow to enable translation of RelaxedPrecision spirv
variable decorator into mediump which for us means fp16.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12067>
Karol Herbst [Sun, 25 Jul 2021 00:10:29 +0000 (02:10 +0200)]
nv30: fix emulated vertex index buffers
We ended up applying the offset twice. Quite embarrassing.
This fixes a bunch of vertex shader related issues like the gnome desktop
is less broken and probably a lot of other applications.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5061
Cc: mesa-stable
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12054>
Samuel Pitoiset [Mon, 26 Jul 2021 11:47:13 +0000 (13:47 +0200)]
radv: allow unused VkSpecializationMapEntries
Fixes future CTS: dEQP-VK.pipeline.spec_constant.*.basic.*unused_*
Cc: 21.2 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12062>
Daniel Schürmann [Mon, 12 Jul 2021 09:00:29 +0000 (11:00 +0200)]
nir/shrink_vectors: shrink vecN properly
This patch allows to shrink vecN instructions where
one or more components at any position are unused.
Stat changes for softpipe:
total instructions in shared programs: 2986101 -> 2985416 (-0.02%)
instructions in affected programs: 51216 -> 50531 (-1.34%)
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11411>
Daniel Schürmann [Wed, 7 Jul 2021 14:43:13 +0000 (16:43 +0200)]
nir/shrink_vectors: shrink ALU properly
ALU instructions of which not all components are read,
can be shrunk to the number of read components.
Previously, this would only remove trailing components.
This patch enables to remove components from any position.
Stat changes for softpipe:
total instructions in shared programs: 3001291 -> 2984698 (-0.55%)
instructions in affected programs: 225585 -> 208992 (-7.36%)
total loops in shared programs: 1389 -> 1358 (-2.23%)
loops in affected programs: 36 -> 5 (-86.11%)
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11411>
Daniel Schürmann [Wed, 16 Jun 2021 07:20:01 +0000 (09:20 +0200)]
nir/opt_shrink_vectors: reverse iteration order
This pass should be backwards in order to reach the fixed point
in linear time.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11411>
Daniel Schürmann [Mon, 14 Jun 2021 17:19:23 +0000 (19:19 +0200)]
nir: consider write_mask in nir_ssa_def_components_read()
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11411>
Daniel Schürmann [Thu, 22 Jul 2021 07:51:32 +0000 (09:51 +0200)]
nir/opt_shrink_vectors: don't shrink vectors used by intrinsics
Store intrinsics shrink the sources by creating a new vecN.
Other intrinsics cannot shrink their sources.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11411>
Daniel Schürmann [Thu, 22 Jul 2021 08:25:52 +0000 (10:25 +0200)]
nir/lower_alu_to_scalar: don't skip gaps in write_mask
Otherwise, this may lead to segmentation faults.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11411>
Juan A. Suarez Romero [Wed, 21 Jul 2021 17:29:49 +0000 (19:29 +0200)]
v3dv: assert job->cmd_buffer is valid
In v3dv_write_uniforms_wg_offsets() function, the job's cmd_buffer is a
valid command buffer, so there is no reason to check if its NULL or not.
This fixes CID#1487441 ("Dereference after null check") error.
v1:
- `job->cmd_buffer` is the same as `cmd_buffer` (Alejandro)
v2:
- Use `cmd_buffer` instead of `job->cmd_buffer` (Iago)
Fixes:
31a786c80ad ("v3dv: handle QUNIFORM_FB_LAYERS")
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11999>
Lionel Landwerlin [Sat, 24 Jul 2021 17:04:09 +0000 (20:04 +0300)]
isl: fix mapping of format->stringname
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
ed6e586562f444 ("intel: properly constify isl_format_layouts")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5110
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12051>
Shmerl [Sun, 25 Jul 2021 17:04:14 +0000 (13:04 -0400)]
vulkan/overlay: don't display histogram and range for device and format
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4320
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12056>
Dave Airlie [Fri, 23 Jul 2021 06:22:33 +0000 (16:22 +1000)]
teximage: return correct desktop GL error for compressedteximage
For GL4.6 the spec says to return GL_INVALID_OPERATION for this.
Cc: mesa-stable
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12032>
Alyssa Rosenzweig [Sat, 24 Jul 2021 22:00:39 +0000 (18:00 -0400)]
asahi: Generalize src_offset for non-4byte formats
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053>
Alyssa Rosenzweig [Sat, 24 Jul 2021 22:00:07 +0000 (18:00 -0400)]
asahi: Add integers to agx_vertex_formats
Handles all the easy cases.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053>
Alyssa Rosenzweig [Sat, 24 Jul 2021 21:57:19 +0000 (17:57 -0400)]
agx: Shift vertex buffer stride in the compiler
Required to support non-32-bit vertex formats efficiently.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053>
Alyssa Rosenzweig [Sat, 24 Jul 2021 21:45:38 +0000 (17:45 -0400)]
agx: Add agx_format_shift routine
Required to calculate alignments for vertex buffers correctly.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053>
Alyssa Rosenzweig [Sat, 24 Jul 2021 21:26:02 +0000 (17:26 -0400)]
asahi: Pass instance_divisor to the compiler
Passes dEQP-GLES3.functional.instanced.*
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053>
Alyssa Rosenzweig [Sat, 24 Jul 2021 21:25:40 +0000 (17:25 -0400)]
agx: Define p_extract for type converts
Useful for grabbing the high 32-bit word of a 64-bit value.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053>
Alyssa Rosenzweig [Sat, 24 Jul 2021 21:25:11 +0000 (17:25 -0400)]
agx: Implement instanced arrays
Divide by instance divisor if needed. Same strategy as ACO.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053>
Alyssa Rosenzweig [Sat, 24 Jul 2021 21:24:47 +0000 (17:24 -0400)]
agx: Include divisors in the vertex shader key
Needed to lower the divisions.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053>
Alyssa Rosenzweig [Sat, 24 Jul 2021 21:24:02 +0000 (17:24 -0400)]
agx: Add udiv-by-constant routine
Uses the ridiculousfish algorithm, will be used to lower instanced
arrays into something efficient.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053>
Alyssa Rosenzweig [Sat, 24 Jul 2021 21:23:42 +0000 (17:23 -0400)]
agx: Add agx_ushr helper
Syntax sugar for the underlying bitfield manipulation instruction.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053>
Alyssa Rosenzweig [Sat, 24 Jul 2021 19:12:18 +0000 (15:12 -0400)]
agx: Handle load_instance_id
Preloaded into r6, as predicted.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053>
Alyssa Rosenzweig [Sat, 24 Jul 2021 19:12:03 +0000 (15:12 -0400)]
agx: Drop dated /* TODO: RA */
We skip over vertex ID in RA now, it's fine.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053>
Alyssa Rosenzweig [Sat, 24 Jul 2021 19:04:25 +0000 (15:04 -0400)]
asahi: Enable instancing
Passes dEQP-GLES3.functional.draw.draw_arrays_instanced.lines.single_attribute
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053>
Alyssa Rosenzweig [Sat, 24 Jul 2021 18:56:52 +0000 (14:56 -0400)]
agx: Plug memory leak in register allocator
Fixes:
85e18deb18a ("agx: Assign registers locally")
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reported-by: Coverity
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053>
Alyssa Rosenzweig [Sat, 24 Jul 2021 18:55:16 +0000 (14:55 -0400)]
agx: Use consistent ncomps
Fixes register allocation failure in:
dEQP-GLES3.functional.ubo.single_basic_array.shared.row_major_mat4_fragment
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053>
Alyssa Rosenzweig [Sat, 24 Jul 2021 18:54:34 +0000 (14:54 -0400)]
agx: Dump register file when failing to allocate
Usually shows a bug.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053>
Alyssa Rosenzweig [Sat, 24 Jul 2021 18:39:44 +0000 (14:39 -0400)]
agx: Fix mismatched units in load_ubo
Fixes assertion failure in
dEQP-GLES3.functional.ubo.single_basic_type.shared.highp_float_fragment
Assertion failed: ((value & 1) == 0), function agx_print_sized, file
../src/asahi/compiler/agx_print.c, line 39.
Fixes:
033d4d09fc7 ("agx: Implement load_ubo/kernel_input")
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053>
Alyssa Rosenzweig [Sat, 24 Jul 2021 18:27:35 +0000 (14:27 -0400)]
agx: Don't set helper invocation kill bit
In the future we'll need data flow analysis similar to what we do in
panfrost.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053>
Alyssa Rosenzweig [Sat, 24 Jul 2021 17:55:19 +0000 (13:55 -0400)]
asahi: Assert texture layer is nonzero
The app shouldn't do funny things with layers... currently unsupported,
one issue at a time...
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053>
Alyssa Rosenzweig [Sat, 24 Jul 2021 17:06:32 +0000 (13:06 -0400)]
asahi: Require tiling for cube maps
Makes my dEQP happy.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053>
Alyssa Rosenzweig [Sat, 24 Jul 2021 17:06:11 +0000 (13:06 -0400)]
asahi: Simplify can_tile type signature
dev parameter inherited from panfrost.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053>
Alyssa Rosenzweig [Sat, 24 Jul 2021 16:56:29 +0000 (12:56 -0400)]
asahi: Allow tiled cube maps
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053>
Alyssa Rosenzweig [Sat, 24 Jul 2021 17:01:08 +0000 (13:01 -0400)]
asahi: Use agx_rsrc_offset for linear transfer_map
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053>
Alyssa Rosenzweig [Sat, 24 Jul 2021 16:52:41 +0000 (12:52 -0400)]
asahi: Implement cube map tiling transfers
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053>
Alyssa Rosenzweig [Sat, 24 Jul 2021 16:52:15 +0000 (12:52 -0400)]
asahi: Calculate resource offsets for cube maps
Needed to transfer.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053>
Alyssa Rosenzweig [Sat, 24 Jul 2021 16:51:00 +0000 (12:51 -0400)]
asahi: Calculate cube map stride
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053>
Alyssa Rosenzweig [Sat, 24 Jul 2021 16:23:56 +0000 (12:23 -0400)]
asahi: Set texture dimension field
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053>
Alyssa Rosenzweig [Sat, 24 Jul 2021 16:20:17 +0000 (12:20 -0400)]
asahi: Identify texture dimension field
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053>
Alyssa Rosenzweig [Sat, 24 Jul 2021 17:20:13 +0000 (13:20 -0400)]
asahi: Fix sampler filtering flag
Typo in the XML. Fixes broken filtering. Still chasing an off-by-one.
Fixes:
cad54e2721d ("asahi: Add command buffer XML definitions")
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053>
Alyssa Rosenzweig [Sat, 24 Jul 2021 17:55:05 +0000 (13:55 -0400)]
asahi: Identify texture address field
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053>
Enrico Galli [Fri, 23 Jul 2021 21:47:33 +0000 (14:47 -0700)]
microsoft/spirv_to_dxil: Adding continue opt pass to fix DXIL loop gen
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12048>
Chia-I Wu [Fri, 23 Jul 2021 21:31:30 +0000 (14:31 -0700)]
vulkan/wsi: replace prime_blit_buffer by a bool
venus only needs to know if a WSI image is a prime blit source. In an
upcoming swapchain image rework, the prime blit destination is unknown
when the WSI image is created. Replace prime_blit_buffer by a bool.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12046>
Georg Lehmann [Fri, 25 Jun 2021 15:40:44 +0000 (17:40 +0200)]
aco: Use cpp_msvc_compat_args.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11610>
Georg Lehmann [Fri, 25 Jun 2021 15:39:10 +0000 (17:39 +0200)]
radv: Use c_msvc_compat_args.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11610>
Alyssa Rosenzweig [Fri, 23 Jul 2021 14:31:15 +0000 (10:31 -0400)]
panvk: Fix sampler filter modes on Bifrost
The logic was incorrectly inverted, although it is correct for Midgard
and in OpenGL.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Suggested-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11851>
Alyssa Rosenzweig [Tue, 13 Jul 2021 17:58:10 +0000 (13:58 -0400)]
panfrost: Make panfrost_batch_get_bifrost_tiler per-gen
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11851>
Alyssa Rosenzweig [Tue, 13 Jul 2021 17:42:55 +0000 (13:42 -0400)]
panfrost: Move init_batch to GenXML vtbl
Secretly depends on GenXML.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11851>
Alyssa Rosenzweig [Tue, 13 Jul 2021 16:08:16 +0000 (12:08 -0400)]
panfrost: Use PAN_ARCH for the rest of pan_cmdstream
Mostly trivial substitutions to get rid of dev->arch, dev->quirks, and
pan_is_bifrost()
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11851>
Alyssa Rosenzweig [Tue, 13 Jul 2021 16:02:20 +0000 (12:02 -0400)]
panfrost: Add a concatenation macro for genxml
This is safer, since it allows the thing being concatenated to itself be
an expande macro, which we'll use as a stopgap to construct tiler jobs
with unified code. It's also a bit more readable, I think.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11851>
Alyssa Rosenzweig [Tue, 13 Jul 2021 00:26:12 +0000 (20:26 -0400)]
panfrost: #ifdef fragment RSD packing
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11851>
Alyssa Rosenzweig [Mon, 12 Jul 2021 23:58:22 +0000 (19:58 -0400)]
panfrost: #ifdef pan_merge_empty_fs
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11851>
Alyssa Rosenzweig [Mon, 12 Jul 2021 23:56:52 +0000 (19:56 -0400)]
panfrost: Share blend code across architectures
Midgard code is basically a subset of the Bifrost/Valhall code.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11851>
Alyssa Rosenzweig [Mon, 12 Jul 2021 23:35:03 +0000 (19:35 -0400)]
panfrost: Share sampler code across archs
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11851>
Alyssa Rosenzweig [Mon, 12 Jul 2021 23:32:17 +0000 (19:32 -0400)]
panfrost: Match sampler "nearest" names
Midgard calls this nearest but Bifrost calls it point sample. Of the
two, nearest is the standard term, so change the Bifrost XML to use that
name. That way we can share more code constructing samplers.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11851>
Alyssa Rosenzweig [Mon, 12 Jul 2021 23:20:16 +0000 (19:20 -0400)]
panfrost: Don't make get_index_buffer_bounded per-gen
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11851>
Alyssa Rosenzweig [Mon, 12 Jul 2021 22:36:40 +0000 (18:36 -0400)]
panfrost: Statically determine uses_clamp
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11851>
Alyssa Rosenzweig [Mon, 12 Jul 2021 23:15:46 +0000 (19:15 -0400)]
panfrost: Compile pan_cmdstream per-gen
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11851>
Alyssa Rosenzweig [Mon, 12 Jul 2021 23:09:33 +0000 (19:09 -0400)]
panfrost: Move sysval analysis out of per-gen
Arch-independent.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11851>
Alyssa Rosenzweig [Mon, 12 Jul 2021 23:03:13 +0000 (19:03 -0400)]
panfrost: Make sampler view creation private
Move it up in the file to avoid forward decls.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11851>
Alyssa Rosenzweig [Mon, 12 Jul 2021 22:48:46 +0000 (18:48 -0400)]
panfrost: Move context initalization to the vtable
Now there's only a single genx entrypoint.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11851>
Emma Anholt [Thu, 22 Jul 2021 18:15:19 +0000 (11:15 -0700)]
ci/freedreno: Enable the MSAA deqp tests.
We've had issues with these before when merging to Chrome OS, so let's
make sure we're testing them now that we can do surfaceless pbuffer MSAA.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1859>
Adam Jackson [Tue, 3 Sep 2019 19:57:47 +0000 (15:57 -0400)]
egl/dri2: Stop disabling pbuffer support on msaa configs
We started doing this in:
commit
4d6d55deef291b489af4d7870c6f5eb223c8da5d
Author: Tapani Pälli <tapani.palli@intel.com>
Date: Mon Sep 26 10:03:32 2016 +0300
egl: stop claiming support for pbuffer + msaa
This fixes a crash in egl-create-msaa-pbuffer-surface Piglit test
and same crash in many dEQP EGL tests.
Whatever bug that was papering over appears to be fixed by now, I can
no longer reproduce that crash with piglit. Furthermore, disabling that
bit in the generic dri2 code had the side effect that the surfaceless
platform would advertise EGLConfigs with _no_ supported surface types
(since surfaceless only supports pbuffers).
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1859>
Ryan Neph [Fri, 23 Jul 2021 17:27:03 +0000 (10:27 -0700)]
virgl: disallow null-terminated debug messages
virglrenderer doesn't support null-terminated message strings, so
there's no reason for the guest to allow it.
Signed-off-by: Ryan Neph <ryanneph@google.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12043>
Jason Ekstrand [Fri, 9 Jul 2021 13:09:46 +0000 (08:09 -0500)]
nir: Validate newly documented texture restrictions
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Acked-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11775>
Mike Blumenkrantz [Fri, 7 May 2021 18:06:23 +0000 (14:06 -0400)]
nir/validate: refactor validate_assert to have a return value
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11775>
Erik Faye-Lund [Mon, 12 Jul 2021 20:00:01 +0000 (15:00 -0500)]
dxil: Set coord_components on the txf in lower_int_sampler
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11775>
Jason Ekstrand [Fri, 9 Jul 2021 16:34:23 +0000 (11:34 -0500)]
nir/lower_tex: Rework invalid implicit LOD lowering
Only fragment and some compute shaders support implicit derivatives.
They're totally meaningless without helper invocations and some
understanding of the dispatch pattern. We've got code to lower
nir_texop_tex in these shader stages to use an explicit derivative of 0
but it was pretty badly broken:
1. It only handled nir_texop_tex, not nir_texop_txb or nir_texop_lod.
2. It didn't take min_lod into account
3. It was conflated with adding a missing LOD parameter to opcodes
which expect one such as nir_texop_txf. While not really a bug,
this does make it way harder to reason about the code.
4. Unless you set a flag (which most drivers don't), it left the
opcode nir_texop_tex instead of nir_texop_txl which it should have
been.
This reworks it to go through roughly the same path as other LOD
lowering only with a constant lod of 0 instead of calling out to
nir_texop_lod. We also get rid of the lower_tex_without_implicit_lod
flag because most drivers set it and those that don't are probably
subtly broken. If someone really wants to get nir_texop_tex in their
vertex shaders, they can write a new patch to add the flag back in.
Fixes:
e382890e25c0 "nir: set default lod to texture opcodes that..."
Fixes:
d5ac5d6e836f "nir: Add option to lower tex to txl when..."
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11775>
Alyssa Rosenzweig [Fri, 23 Jul 2021 15:44:35 +0000 (11:44 -0400)]
pan/mdg: Garbage collect silly quirk
As discussed with Jason and Connor, this is probably subtly broken on
Mali T720.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11775>
Jason Ekstrand [Fri, 9 Jul 2021 13:56:17 +0000 (08:56 -0500)]
intel/blorp: Use nir_texop_txl
We set an explicit LOD immediately afterwards so we don't want implicit
mipmap selection.
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11775>
Jason Ekstrand [Wed, 7 Jul 2021 22:44:27 +0000 (17:44 -0500)]
docs,nir: Document NIR texture instructions
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11775>
Jason Ekstrand [Wed, 7 Jul 2021 22:06:46 +0000 (17:06 -0500)]
nir: Suffix all the MCS texture stuff _intel
It's intel-specific, used to get at MSAA compression information.
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11775>
Jason Ekstrand [Fri, 9 Jul 2021 15:57:39 +0000 (10:57 -0500)]
panfrost: Don't handle nir_texop_txf_ms_mcs
It's an intel-specific opcode and will never be seen on panfrost
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11775>
Jason Ekstrand [Fri, 9 Jul 2021 13:32:01 +0000 (08:32 -0500)]
amd: Don't handle nir_tex_src_ms_mcs
It's an intel-specific texture source and will never be seen on AMD.
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11775>
Jason Ekstrand [Wed, 7 Jul 2021 22:06:16 +0000 (17:06 -0500)]
ttn: Don't handle texop_txf_ms_mcs
It's an intel-specific opcode and will never come through TGSI.
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11775>
Juan A. Suarez Romero [Fri, 23 Jul 2021 12:16:10 +0000 (14:16 +0200)]
v3d: handle debug options with debug_named_value
Switch from using debug_control structure to debug_named_value
structure.
The main nice feature is that it provides a "help" option, so using
"V3D_DEBUG=help" will print all the debug options with a brief
description.
Useful to avoid going to https://docs.mesa3d.org/envvars.html everytime
we need to know the available options.
v1:
- Modify a couple of debug option documentation (Alejandro)
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12036>
Alyssa Rosenzweig [Thu, 22 Jul 2021 15:28:44 +0000 (11:28 -0400)]
targets/graw-xlib: Add missing dep_x11
Required to build Mesa on macOS with
-Dbuild-tests=true -Dglx=gallium-xlib
Without this change, the build fails with
In file included from ../src/gallium/targets/graw-xlib/graw_xlib.c:8:
../src/gallium/include/frontend/xlibsw_api.h:5:10: fatal error: 'X11/Xlib.h' file not found
#include <X11/Xlib.h>
With `brew sh` X11 is found but linking fails due to `llvm-ar` missing
in the path. That issue appears to be unrelated to this missing
dependency. X11 is installed via XQuartz, so Homebrew should not be
required.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12022>
Timothy Arceri [Wed, 14 Jul 2021 07:29:46 +0000 (17:29 +1000)]
glsl: relax rule on varying matching for shaders older than 4.20
This expands on commit
c54c42321ea5. See the code comment for full
justifications. At the time of the previous commit Ian wanted to
limit the relaxing of the rule to GLSL 3.30 as that was the highest
version of shaders seen in the wild that were having trouble with
the stricter rules.
However since then I've found that the long standing issue with tess
shaders failing to compile in the game 'Layers Of Fear' is due to
this same issue. The game uses 4.10 shaders and also makes use of
explicit varying locations, so here we relax the rule to 4.20 and
make sure to apply the restriction to shaders using varyings with
explicit locations also.
Fixes:
c54c42321ea5 ("glsl: relax rule on varying matching for shaders older than 4.00")
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11873>
Dave Airlie [Mon, 20 Jul 2020 21:05:17 +0000 (07:05 +1000)]
draw/llvmpipe: multiply polygon offset units by 2
I was trying to fix this test, but noticed brw_clip.c in i965
does a * 2 here, and it seems to fix this test as well.
Fixes:
dEQP-GLES2.functional.polygon_offset.default_displacement_with_units
Fixes:
f9e2c2432686 ("draw,llvmpipe,util: add depth bias calculation for arb_depth_buffer_float")
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12029>
Sagar Ghuge [Wed, 21 Jul 2021 22:24:29 +0000 (15:24 -0700)]
intel/compiler: Handle ternary add in lower_simd_width
We need to lower the add3 instruction simd width otherwise in simd32
mode, we endup writing 4 register wide data which is not allowed.
Reported-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11985>
Sagar Ghuge [Tue, 20 Jul 2021 02:29:03 +0000 (19:29 -0700)]
intel/compiler: Fix missing break in switch
CoverityID: 1487496
Fixes:
cde9ca616d7 "intel/compiler: Make decision based on source type instead of opcode"
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11985>
Alyssa Rosenzweig [Thu, 22 Jul 2021 21:34:07 +0000 (17:34 -0400)]
panfrost,panvk: Remove broken v4 spilling code
Tells you how much use Mali T720 gets that nobody noticed but
Icecream95...
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reported-by: Icecream95 <ixn@disroot.org>
Acked-by: Icecream95 <ixn@disroot.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12027>
Emma Anholt [Wed, 21 Jul 2021 18:50:24 +0000 (11:50 -0700)]
freedreno: Lock access to msm_pipe for RB object suballocation.
Hopefully this fixes the flakes that have happened since the suballoc
changes.
Fixes:
737d4caa83a9 ("freedreno: Suballocate our long-lived ring objects.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12002>
Eric Anholt [Fri, 12 Mar 2021 21:53:33 +0000 (13:53 -0800)]
gallium/ureg: Sort the output decls.
glsl_to_tgsi had been emitting outputs in sorted order, and it seems virgl
has a dependency on that -- it collects outputs into an array and indexes
by the subtracting the ".First" value of the first one seen, even if
that's not the first entry in the array.
Fixes the regressions in deqp-gles2 on virgl with ST_DEBUG=force_nir, and
fixes neverball trace rendering.
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11934>
Jason Ekstrand [Tue, 20 Jul 2021 23:44:15 +0000 (18:44 -0500)]
intel/eu: Don't validate LSC transpose on ops that don't have it
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11991>
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