Otavio Salvador [Thu, 23 Jul 2015 14:02:33 +0000 (11:02 -0300)]
cgtqmx6eval: Use standard boot script
Use more standard boot scripts and also add the capability of
booting via NFS.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Otavio Salvador [Thu, 23 Jul 2015 14:02:32 +0000 (11:02 -0300)]
cgtqmx6eval: Align DCD settings with Congatec's U-boot
Use the same DCD settings from Congatec's U-boot tree for
the P/N 016113 card.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Otavio Salvador [Thu, 23 Jul 2015 14:02:31 +0000 (11:02 -0300)]
cgtqmx6eval: Add SATA support
Add SATA support.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Otavio Salvador [Thu, 23 Jul 2015 14:02:30 +0000 (11:02 -0300)]
cgtqmx6eval: Add splash screen support
Add LVDS and HDMI support.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Otavio Salvador [Thu, 23 Jul 2015 14:02:29 +0000 (11:02 -0300)]
cgtqmx6eval: Add USB support
Add USB support.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Otavio Salvador [Thu, 23 Jul 2015 14:02:28 +0000 (11:02 -0300)]
cgtqmx6eval: Add PMIC support
cgtqmx6eval has a PFUZE100 FSL PMIC connected to I2C2.
Add support for it.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Otavio Salvador [Thu, 23 Jul 2015 14:02:27 +0000 (11:02 -0300)]
cgtqmx6eval: Add thermal support
Add thermal support so that we can see the following message on boot:
CPU: Industrial temperature grade (-40C to 105C) at 33C
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Otavio Salvador [Thu, 23 Jul 2015 14:02:24 +0000 (11:02 -0300)]
cgtqmx6eval: Add ESDHC3 support
cgtqmx6eval has an eMMC connected to ESDHC3.
Add support for it.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Otavio Salvador [Thu, 23 Jul 2015 14:02:23 +0000 (11:02 -0300)]
cgtqmx6eval: Fit into single lines
There is no need to use multiple lines when they fit into a single line.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Otavio Salvador [Thu, 23 Jul 2015 14:02:22 +0000 (11:02 -0300)]
cgtqmx6eval: Improve the error handling
Perfoming an OR operation on the error is not a good approach.
Return the error immediately for each ESDHC instance instead.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Otavio Salvador [Thu, 23 Jul 2015 14:02:21 +0000 (11:02 -0300)]
cgtqmx6eval: Staticize when possible
Declare 'static' when possible.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Otavio Salvador [Thu, 23 Jul 2015 14:02:20 +0000 (11:02 -0300)]
cgtqmx6eval: Use the default CONFIG_SYS_PBSIZE
Entering the maximum number of characters defined by CONFIG_SYS_CBSIZE into
the console and hitting enter afterwards, causes a hang in the system because
CONFIG_SYS_PBSIZE is not capable of storing the extra characters of the error
message:
"Unknown command '' - try 'help'".
Use the default CONFIG_SYS_PBSIZE definition from config_fallbacks.h to solve
this problem.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Otavio Salvador [Thu, 23 Jul 2015 14:02:19 +0000 (11:02 -0300)]
cgtqmx6eval: Use default prompt
Remove the custom prompt and use the default instead.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Peng Fan [Thu, 25 Jun 2015 02:32:26 +0000 (10:32 +0800)]
mmc:fsl_esdhc invalidate dcache before read
DCIMVAC is upgraded to DCCIMVAC for the individual processor
(Cortex-A7) that the DCIMVAC is executed on.
We should follow the linux dma follow. Before DMA read, first
invalidate dcache then after DMA read, invalidate dcache again.
With the DMA direction DMA_FROM_DEVICE, the dcache need be
invalidated again after the DMA completion. The reason is
that we need explicity make sure the dcache been invalidated
thus to get the DMA'ed memory correctly from the physical memory.
Any cache-line fill during the DMA operations such as the
pre-fetching can cause the DMA coherency issue, thus CPU get the stale data.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Fabio Estevam [Tue, 21 Jul 2015 23:37:22 +0000 (20:37 -0300)]
mx6sxsabresd: Use 'int' for return values
The variable 'ret' is used to store the value returned by pfuze_mode_init(),
so it should be of type 'int' instead of 'unsigned int' in order to
correctly handle negative numbers.
Fix the variable type.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Fabio Estevam [Tue, 21 Jul 2015 23:02:49 +0000 (20:02 -0300)]
mx6sabresd: Use 'int' for return values
The variable 'ret' is used to store the value returned by pfuze_mode_init(),
so it should of type 'int' instead of 'unsigned int' in order to correctly
handle negative numbers.
Fix the variable type.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Fabio Estevam [Tue, 21 Jul 2015 22:48:41 +0000 (19:48 -0300)]
warp: Add MAX77696 support
Warp has a MAX77696 PMIC connected via I2C1 bus.
Add support for it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Fabio Estevam [Tue, 21 Jul 2015 22:48:40 +0000 (19:48 -0300)]
power: pmic: Add support for MAX77696 PMIC
Add support for MAX77696 PMIC.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Fabio Estevam [Tue, 14 Jul 2015 01:01:52 +0000 (22:01 -0300)]
thermal: Fix comments
It seems that many comments were copied from the I2C uclass, so adjust
the comments for the thermal class.
Reported-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Simon Glass <sjg@chromium.org>
Adrian Alonso [Tue, 21 Jul 2015 00:04:55 +0000 (19:04 -0500)]
imx: imximage: add new CHECK/CLR BIT command
* Extend imximage DCD version 2 to support DCD commands
CMD_WRITE_CLR_BIT 4 [address] [mask bit] means:
while ((*address & ~mask) != 0);
CMD_CHECK_BITS_SET 4 [address] [mask bit] means:
while ((*address & mask) != mask);
CMD_CHECK_BITS_CLR 4 [address] [mask bit] means:
*address = *address & ~mask;
* Add set_dcd_param_v2 helper function to set DCD
command parameters
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Stefan Roese [Mon, 6 Jul 2015 11:36:33 +0000 (13:36 +0200)]
arm: mx6: tqma6: Add WRU-IV baseboard for the TQMa6 SoM
This patch adds support for the "OHB System AG" baseboard
with is equipped with the TQMa6S SoM.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Markus Niebel <Markus.Niebel@tq-group.com>
Cc: Stefano Babic <sbabic@denx.de>
Stefano Babic [Fri, 17 Jul 2015 09:22:56 +0000 (11:22 +0200)]
Merge branch 'master' of git://git.denx.de/u-boot
Tom Rini [Wed, 15 Jul 2015 14:41:20 +0000 (10:41 -0400)]
Merge git://git.denx.de/u-boot-x86
Bin Meng [Wed, 8 Jul 2015 05:06:41 +0000 (13:06 +0800)]
pci: Disable expansion ROM address decoding when signature check fails
We should not leave the expansion ROM address window open when there
is not a valid ROM.
Suggested-by: Matt Porter <mporter@konsulko.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 8 Jul 2015 05:06:40 +0000 (13:06 +0800)]
pci: Configure expansion ROM during auto config process
Currently PCI expansion ROM address is assigned by a call to
pciauto_setup_rom() outside of the pci auto config process.
This does not work when expansion ROM is on a device behind
PCI bridge where bridge's memory limit register was already
programmed to a value that does not cover the newly assigned
expansion ROM address. To fix this, we should configure the
ROM address during the auto config process.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sat, 16 May 2015 01:33:16 +0000 (09:33 +0800)]
drivers: block: Remove the ata_piix driver
This driver was originally added to support the native IDE mode for
Intel chipset, however it has some bugs like not supporting ATAPI
devices, endianness issue, or even broken build when CONFIG_LAB48.
Given no board is using this driver as of today, rather than fixing
all these issues we just remove it from the source tree.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Thu, 9 Jul 2015 10:37:40 +0000 (18:37 +0800)]
x86: Adjust config option order in defconfig for Crown Bay and Minnowmax
Update crownbay_defconfig and minnowmax_defconfig with 'savedefconfig'
result so that the config option order matches Kconfig.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 6 Jul 2015 07:57:06 +0000 (15:57 +0800)]
tools: ifdtool: Write correct offset on 32-bit machine
On 32-bit machine strtol() returns LONG_MAX which is 0x7fffffff,
which is wrong for u-boot.rom components like u-boot-x86-16bit.bin.
Change to use strtoll() so that it works on both 32-bit and 64-bit
machines.
Reported-by: Fei Wang <wangfei.jimei@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 4 Jul 2015 00:28:28 +0000 (18:28 -0600)]
x86: Add binary blob checksums for Minnowboard MAX
To try to reduce the pain of confusion of binary blobs, add MD5 checksums
for the current versions. This may worsen the situation as new versions
appear, but it should still be possible to obtain these versions, and thus
get a working setup.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 4 Jul 2015 00:28:27 +0000 (18:28 -0600)]
dm: x86: baytrail: Correct PCI region 3 when driver model is used
Commit
afbbd413a fixed this for non-driver-model. Make sure that the driver
model code handles this also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 4 Jul 2015 00:28:26 +0000 (18:28 -0600)]
dm: x86: minnowmax: Move PCI to use driver model
Adjust minnowmax to use driver model for PCI. This requires adding a device
tree node to specify the ranges, removing the board-specific PCI code and
ensuring that the host bridge is configured.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 4 Jul 2015 00:28:25 +0000 (18:28 -0600)]
x86: pci: Tidy up the generic x86 PCI driver
This driver should use the x86 PCI configuration functions. Also adjust its
compatible string to something generic (i.e. without a vendor name).
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 4 Jul 2015 00:28:24 +0000 (18:28 -0600)]
x86: Add ROM image description for minnowmax
The layout of the ROM is a bit hard to discover by reading the code. Add
a table to make it easier.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 4 Jul 2015 00:28:23 +0000 (18:28 -0600)]
dm: spi: Enable environment for minnowmax
Enable a SPI environment and store it in a suitable place.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Simon Glass [Sat, 4 Jul 2015 00:28:22 +0000 (18:28 -0600)]
dm: spi: Correct BIOS protection logic for ICH9
The logic is incorrect and currently has no effect. Fix it so that we can
write to SPI flash, since by default it is write-protected.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Simon Glass [Sat, 4 Jul 2015 00:28:21 +0000 (18:28 -0600)]
dm: spi: Correct status register access width
The status register on ICH9 is a single byte, so use byte access when
writing to it, to avoid updating the control register also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Bin Meng [Mon, 6 Jul 2015 08:31:36 +0000 (16:31 +0800)]
x86: Configure VESA parameters before loading Linux kernel
Store VESA parameters to Linux setup header so that vesafb driver
in the kernel could work.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Jian Luo <jian.luo4@boschrexroth.de>
Bin Meng [Mon, 6 Jul 2015 08:31:35 +0000 (16:31 +0800)]
x86: crownbay: Enable graphics support
Enable graphics support on Intel Crown Bay board With the help of
vgabios for Intel TunnelCreek IGD. Tested with an external LVDS
panel connected to X4 connector and SDVO adapter connected to X9
connector on the board.
Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 6 Jul 2015 08:31:34 +0000 (16:31 +0800)]
x86: Remove MARK_GRAPHICS_MEM_WRCOMB
MARK_GRAPHICS_MEM_WRCOMB is not referenced anywhere in the code,
hence remove it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 6 Jul 2015 08:31:33 +0000 (16:31 +0800)]
x86: Move VGA option rom macros to Kconfig
Move X86_OPTION_ROM_FILE & X86_OPTION_ROM_ADDR to arch/x86/Kconfig
and rename them to VGA_BIOS_FILE & VGA_BIOS_ADDR which depend on
HAVE_VGA_BIOS. The new names are consistent with other x86 binary
blob options like HAVE_FSP/FSP_FILE/FSP_ADDR.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 6 Jul 2015 08:31:32 +0000 (16:31 +0800)]
x86: cmd_mtrr: Improve MTRR list information
Print the meaningful base address and mask of an MTRR range without showing
the memory type encoding or valid bit.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 6 Jul 2015 08:31:31 +0000 (16:31 +0800)]
x86: queensbay: Change CPU_ADDR_BITS to 32
Per CPUID:80000008h result, the maximum physical address bits of
TunnelCreek processor is 32 instead of default 36. This will fix
the incorrect decoding of MTRR range mask.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 6 Jul 2015 08:31:30 +0000 (16:31 +0800)]
x86: Setup fixed range MTRRs for legacy regions
We should setup fixed range MTRRs for some legacy regions like VGA
RAM and PCI ROM areas as uncacheable. Note FSP may setup these to
other cache settings, but we can override this in x86_cpu_init_f().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Jian Luo [Mon, 6 Jul 2015 08:31:29 +0000 (16:31 +0800)]
video: Add 32-bit color depth support for VBE
The TunnelCreek IGD VBE reports 32-bit color depth regardless 24-bit
color depth is configured. Since 24-bit mode already uses 4 bytes
internally, it should be OK to just add this option in switch case.
Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Jian Luo [Mon, 6 Jul 2015 08:31:28 +0000 (16:31 +0800)]
x86: bios: Allow pci config read/write to host bridge in int1a_handler
We should allow pci config read/write to host bridge (b.d.f = 0.0.0)
in the int1a_handler() which is a valid pci device.
Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Jian Luo [Mon, 6 Jul 2015 08:42:06 +0000 (16:42 +0800)]
x86: bios: Synchronize stack between real and protected mode
PCI option rom may use different SS during its execution, so it is not
safe to assume esp pointed to the same location in the protected mode.
Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 6 Jul 2015 08:31:26 +0000 (16:31 +0800)]
video: vesa_fb: Look up VGA device by class instead of id
Per PCI spec, VGA device reports its class as standard 030000h in
its configuration space, so we can use it to determine if we need
run option rom instead of testing the supported vendor/device ids.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 7 Jun 2015 14:50:41 +0000 (08:50 -0600)]
dm: pci: Correct bus number when scanning sub-buses
The sub-bus passed to pciauto_prescan_setup_bridge() is incorrect. Fix it
so that sub-buses are numbered correctly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 7 Jun 2015 14:50:40 +0000 (08:50 -0600)]
dm: pci: Use the correct hose when configuring devices
Only the PCI controller has access to the PCI region information. Make sure
to use the controller (rather than any attached bridges) when configuring
devices.
This corrects a failure to scan and configure devices when driver model is
enabled for PCI.
Also add a comment to explain the problem.
Signed-off-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 23 Jun 2015 04:18:55 +0000 (12:18 +0800)]
x86: queensbay: Change PCIe root ports' interrupt routing
So far interrupt routing works pretty well for any on-chip devices
on Intel Crown Bay. When inserting any PCIe card to any PCIe slot,
Linux kernel is smart enough to do interrupt swizzling and figure
out device's irq using its parent bridge's interrupt routing info
all the way up to its root port. In U-Boot all PCIe root ports'
interrupts were routed to PIRQ E/F/G/H before, while actually all
PCIe downstream ports received INTx are routed to PIRQ A/B/C/D
directly and not configurable. Now we change this mapping so that
any external PCIe device can work correctly.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 23 Jun 2015 04:18:54 +0000 (12:18 +0800)]
x86: crownbay: Enable writing MP table
Enable writing MP table for Intel Crown Bay board.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 23 Jun 2015 04:18:53 +0000 (12:18 +0800)]
x86: Update README.x86 for SMP support
Document U-Boot multi-processor support as well as configuration
tables like SFI and MP tables for SMP OS kernel.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 23 Jun 2015 04:18:52 +0000 (12:18 +0800)]
x86: Generate a valid MultiProcessor (MP) table
Implement write_mp_table() to create a minimal working MP table.
This includes an MP floating table, a configuration table header
and all of the 5 base configuration table entries. The I/O interrupt
assignment table entry is created based on the same information used
in the creation of PIRQ routing table from device tree. A check
duplicated entry logic is applied to prevent writing multiple I/O
interrupt entries with the same information.
Use a Kconfig option GENERATE_MP_TABLE to tell U-Boot whether we
need actually write the MP table at the F seg, just like we did for
PIRQ routing and SFI tables. With MP table existence, linux kernel
will switch to I/O APIC and local APIC to process all the peripheral
interrupts instead of 8259 PICs. This takes full advantage of the
multicore hardware and the SMP kernel.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 23 Jun 2015 04:18:51 +0000 (12:18 +0800)]
x86: Add MultiProcessor (MP) table APIs
The MP table provides a way for the operating system to support
for symmetric multiprocessing as well as symmetric I/O interrupt
handling with the local APIC and I/O APIC. We provide a bunch of
APIs for U-Boot to write the floating table, configuration table
header as well as base and extended table entries.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 23 Jun 2015 04:18:50 +0000 (12:18 +0800)]
x86: Remove inline for lapic access routines
Remove inline for lapic access routines and expose lapic_read()
& lapic_write() as APIs to read/write lapic registers. Also move
stop_this_cpu() to mp_init.c as it has nothing to do with lapic.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 23 Jun 2015 04:18:49 +0000 (12:18 +0800)]
x86: Add I/O APIC register access routines
I/O APIC registers are addressed indirectly. Add io_apic_read() and
io_apic_write() routines to help register access. Two macros for I/O
APIC ID and version register offset are also added.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 23 Jun 2015 04:18:48 +0000 (12:18 +0800)]
x86: Clean up ioapic header file
Remove all the dead/unused macros from asm/ioapic.h.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 23 Jun 2015 04:18:47 +0000 (12:18 +0800)]
x86: Reduce PIRQ routing table size
There is no need to populate multiple irq info entries with the same
bus number and device number, but with different interrupt pin. We
can use the same entry to store all the 4 interrupt pin (INT A/B/C/D)
routing information to reduce the whole PIRQ routing table size.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 23 Jun 2015 04:18:46 +0000 (12:18 +0800)]
x86: Ignore function number when writing PIRQ routing table
In fill_irq_info() pci device's function number is written into
the table, however this is not really necessary. The function
number can be anything as OS doesn't care about this field,
neither does the PIRQ routing specification. Change to always
writing 0 as the function number.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 23 Jun 2015 04:18:45 +0000 (12:18 +0800)]
x86: Write correct bus number for the irq router
We should write correct bus number to the PIRQ routing table for the
irq router from device tree, instead of hard-coded zero.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 23 Jun 2015 04:18:44 +0000 (12:18 +0800)]
x86: queensbay: Correct Topcliff device irqs
There are 4 usb ports on the Intel Crown Bay board, 2 of which are
connected to Topcliff usb host 0 and the other 2 connected to usb
host 1. USB devices inserted in the ports connected to usb host 1
cannot get detected due to wrong IRQ assigned to the controller.
Actually we need apply the PCI interrupt pin swizzling logic to all
devices on the Topcliff chipset when configuring the PIRQ routing.
This was observed on usb ports, but device 6 and 10 irqs are also
wrong. Correct them all together.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 23 Jun 2015 04:18:43 +0000 (12:18 +0800)]
x86: crownbay: Enable DM RTC support
Add a RTC node in the device tree to enable DM RTC support.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 23 Jun 2015 04:18:42 +0000 (12:18 +0800)]
cmd: date: Change to use CONFIG_DM_RTC instead of CONFIG_DM_I2C
Currently CONFIG_DM_I2C is used in cmd_date.c for driver model,
but it should be actually CONFIG_DM_RTC.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 23 Jun 2015 04:18:41 +0000 (12:18 +0800)]
dm: rtc: Support mc146818 driver in driver model
Add driver model support to the mc146818 rtc driver. Also clean up
the driver a little bit for coding convention issues.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 17 Jun 2015 03:15:39 +0000 (11:15 +0800)]
x86: crownbay: Add MP initialization
Intel Crown Bay board has a TunnelCreek processor which supports
hyper-threading. Add /cpus node in the crownbay.dts and enable
the MP initialization.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
(modified to remove error:
overriding the value of OF_CONTROL. Old value: "y", new value: "y")
Bin Meng [Wed, 17 Jun 2015 03:15:38 +0000 (11:15 +0800)]
x86: Clean up lapic codes
This commit cleans up the lapic codes:
- Delete arch/x86/include/asm/lapic_def.h, and move register and bit
defines into arch/x86/include/asm/lapic.h
- Use MSR defines from msr-index.h in enable_lapic() and disable_lapic()
- Remove unnecessary stuff like NEED_LAPIC, X86_GOOD_APIC and
CONFIG_AP_IN_SIPI_WAIT
- Move struct x86_cpu_priv defines to asm/arch-ivybridge/bd82x6x.h, as
it is not apic related and only used by ivybridge
- Fix coding convention issues
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 17 Jun 2015 03:15:37 +0000 (11:15 +0800)]
x86: Move lapic_setup() call into init_bsp()
Currently lapic_setup() is called before calling mp_init(), which
then calls init_bsp() where it calls enable_lapic(), which was
already enabled in lapic_setup(). Hence move lapic_setup() call
into init_bsp() to avoid the duplication.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 17 Jun 2015 03:15:36 +0000 (11:15 +0800)]
x86: Move MP initialization codes into a common place
Most of the MP initialization codes in arch/x86/cpu/baytrail/cpu.c is
common to all x86 processors, except detect_num_cpus() which varies
from cpu to cpu. Move these to arch/x86/cpu/cpu.c and implement the
new 'get_count' method for baytrail and cpu_x86 drivers. Now we call
cpu_get_count() in mp_init() to get the number of CPUs.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 17 Jun 2015 03:15:35 +0000 (11:15 +0800)]
x86: ivybridge: Remove SMP from CPU_SPECIFIC_OPTIONS
Ivybridge is not ready for U-Boot MP initialization yet.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 17 Jun 2015 03:15:34 +0000 (11:15 +0800)]
dm: cpu: Add a new get_count method to cpu uclass
Introduce a new method 'get_count' in the UCLASS_CPU ops to get
the number of CPUs in the system.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 12 Jun 2015 06:52:23 +0000 (14:52 +0800)]
x86: kconfig: Fix minor nits in MAX_CPUS
Move MAX_CPUS definition after SMP so that it shows below SMP in the
menuconfig. Also replace the leading spaces in the MAX_CPUS section
with tabs to conform coding standard.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 12 Jun 2015 06:52:22 +0000 (14:52 +0800)]
x86: kconfig: Make MAX_CPUS and AP_STACK_SIZE depend on SMP
MAX_CPUS and AP_STACK_SIZE are only meaningful when SMP is on.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 12 Jun 2015 06:52:20 +0000 (14:52 +0800)]
x86: dm: Clean up cpu drivers
This commit does the following to clean up x86 cpu dm drivers:
- Move cpu_x86 driver codes from arch/x86/cpu/cpu.c to a dedicated
file arch/x86/cpu/cpu_x86.c
- Rename x86_cpu_get_desc() to cpu_x86_get_desc() to keep consistent
naming with other dm drivers
- Add a new cpu_x86_bind() in the cpu_x86 driver which does exactly
the same as the one in the intel baytrail cpu driver
- Update intel baytrail cpu driver to use cpu_x86_get_desc() and
cpu_x86_bind()
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 12 Jun 2015 06:52:19 +0000 (14:52 +0800)]
dm: cpu: Test against cpu_ops->get_info in cpu_get_info()
In cpu_get_info() it wrongly tests against cpu_ops->get_desc to see
if it is NULL. It should test against cpu_ops->get_info.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng [Fri, 12 Jun 2015 06:52:18 +0000 (14:52 +0800)]
dm: cpu: Fix undefined ENOSYS build error
Include <errno.h> otherwise ENOSYS is undefined.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 7 Jun 2015 14:50:33 +0000 (08:50 -0600)]
dm: spi: Correct minor nits in ICH driver
Tidy up three minor problems in this file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Simon Glass [Sun, 7 Jun 2015 14:50:32 +0000 (08:50 -0600)]
spi: sf: Print the error code on failure
Rather than just 'ERROR', display the error code, which may be useful, at
least with driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Bin Meng [Sun, 7 Jun 2015 03:33:14 +0000 (11:33 +0800)]
x86: fsp: Move FspInitEntry call to board_init_f()
The call to FspInitEntry is done in arch/x86/lib/fsp/fsp_car.S so far.
It worked pretty well but looks not that good. Apart from doing too
much work than just enabling CAR, it cannot read the configuration
data from device tree at that time. Now we want to move it a little
bit later as part of init_sequence_f[] being called by board_init_f().
This way it looks and works better in the U-Boot initialization path.
Due to FSP's design, after calling FspInitEntry it will not return to
its caller, instead it jumps to a continuation function which is given
by bootloader with a new stack in system memory. The original stack in
the CAR is gone, but its content is perserved by FSP and described by
a bootloader temporary memory HOB. Technically we can recover anything
we had before in the previous stack, but that is way too complicated.
To make life much easier, in the FSP continuation routine we just
simply call fsp_init_done() and jump back to car_init_ret() to redo
the whole board_init_f() initialization, but this time with a non-zero
HOB list pointer saved in U-Boot's global data so that we can bypass
the FspInitEntry for the second time.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Tested-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sun, 7 Jun 2015 03:33:13 +0000 (11:33 +0800)]
x86: fsp: Load GDT before calling FspInitEntry
Currently the FSP execution environment GDT is setup by U-Boot in
arch/x86/cpu/start16.S, which works pretty well. But if we try to
move the FspInitEntry call a little bit later to better fit into
U-Boot's initialization sequence, FSP will fail to bring up the AP
due to #GP fault as AP's GDT is duplicated from BSP whose GDT is
now moved into CAR, and unfortunately FSP calls AP initialization
after it disables the CAR. So basically the BSP's GDT still refers
to the one in the CAR, whose content is no longer available, so
when AP starts up and loads its segment register, it blows up.
To resolve this, we load GDT before calling into FspInitEntry.
The GDT is the same one used in arch/x86/cpu/start16.S, which is
in the ROM and exists forever.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Tested-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sun, 7 Jun 2015 03:33:12 +0000 (11:33 +0800)]
x86: Add Kconfig options to be used by arch/x86/cpu/config.mk
Add RESET_SEG_START, RESET_SEG_SIZE and RESET_VEC_LOC Kconfig options
and make arch/x86/cpu/config.mk use these options.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Tested-by: Simon Glass <sjg@chromium.org>
Tom Rini [Mon, 27 Apr 2015 15:34:38 +0000 (11:34 -0400)]
builderthread.py: Keep 'SPL'
On i.MX platforms the SPL binary is called "SPL" so make sure we keep
that.
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tom Rini [Tue, 14 Jul 2015 18:13:23 +0000 (14:13 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-spi
Simon Glass [Thu, 28 Aug 2014 15:43:46 +0000 (09:43 -0600)]
RFC: Deprecate MAKEALL
Since buildman now includes most of the features of MAKEALL it is probably
time to talk about deprecating MAKEALL.
Comments welcome.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tom Rini [Tue, 14 Jul 2015 17:32:21 +0000 (13:32 -0400)]
Prepare v2015.07
Signed-off-by: Tom Rini <trini@konsulko.com>
Andre Przywara [Thu, 2 Jul 2015 00:04:23 +0000 (01:04 +0100)]
scsi: fix compiler warning with DEBUG and 48bit LBAs
Commit
2b42c9317db ("ahci: support LBA48 data reads for 2+TB drives")
introduced conditional code which triggers a warning when compiled
with DEBUG enabled:
In file included from common/cmd_scsi.c:12:0:
common/cmd_scsi.c: In function 'scsi_read':
include/common.h:109:4: warning: 'smallblks' may be used uninitialized in this function [-Wmaybe-uninitialized]
...
Since this is for debug only, take the easy way and initialize the
variable explicitly on declaration to avoid the warning.
(Fix a nearby whitespace error on the way.)
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Andre Przywara <osp@andrep.de>
Tom Rini [Fri, 10 Jul 2015 13:40:59 +0000 (09:40 -0400)]
Merge git://git.denx.de/u-boot-samsung
Tom Rini [Fri, 10 Jul 2015 13:40:48 +0000 (09:40 -0400)]
Merge git://git.denx.de/u-boot-marvell
Masahiro Yamada [Wed, 1 Jul 2015 12:35:49 +0000 (21:35 +0900)]
mtd: fix false positive "Offset exceeds device limit" error
Since commit
09c3280754f8 (mtd, nand: Move common functions from
cmd_nand.c to common place), NAND commands would not work at all
on large devices.
=> nand read
80000000 10000 10000
NAND read: Offset exceeds device limit
=> nand erase 100000 100000
NAND erase: Offset exceeds device limit
The type of the "size" of "struct mtd_info" is uint64_t, while
mtd_arg_off_size() and mtd_arg_off() treat chipsize as int type.
The chipsize is wrapped around if the argument is given with 2GB
or larger.
Acked-by: Heiko Schocher <hs@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Stefan Roese [Mon, 29 Jun 2015 12:58:16 +0000 (14:58 +0200)]
arm: mvebu: db-88f6820-gp: Add USB/EHCI support
This patch enabled the USB/EHCI support for the Marvell
DB-88F6820-GP eval board.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Mon, 29 Jun 2015 12:58:15 +0000 (14:58 +0200)]
usb: Add EHCI support for Armada 38x (mvebu)
This patch adds USB EHCI host support for the common mvebu platform.
Including the Armada 38x.
Tested on DB-88F6280-GP eval board.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Mon, 29 Jun 2015 12:58:14 +0000 (14:58 +0200)]
arm: mvebu: db-88f6820-gp.h: Add SATA/SCSI (AHCI) support
Configure and enable the SATA/SCSI (AHCI) support for the Marvell
DB-88F6820-GP eval board.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Mon, 29 Jun 2015 12:58:13 +0000 (14:58 +0200)]
arm: mvebu: Add SATA/SCSI (AHCI) support for Armada A38x
This patch adds support for the common AHCI controller on the Marvell
Armada 38x.
Tested on the Marvell DB-88F6820-GP eval board.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Mon, 29 Jun 2015 12:58:12 +0000 (14:58 +0200)]
block: ahci: Don't enable port interrupts
This patch changes the initialization of the AHCI controller to not
enable the default interrupts (DEF_PORT_IRQ). As interrupts are
not used in U-Boot in general, this should not break the common AHCI
driver operation.
This change is needed to support the Marvell Armada 38x AHCI
controller. With interrupts enabled, this results in timeouts in
ahci_device_data_io(). Not enabling these interrupts fixes this
problem and the common AHCI driver works fine.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Mon, 29 Jun 2015 12:58:11 +0000 (14:58 +0200)]
arm: mvebu: db-88f6820-gp: Add MMC/SDIO support
This patch adds MMC/SDIO support to the Marvell DB-88F6820-GP board
configuration. Including support for the common partitions and
filesystems.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Mon, 29 Jun 2015 12:58:10 +0000 (14:58 +0200)]
arm: mvebu: Add SDIO/SDHCI support for Armada A38x
Armada A38x implements an SDHCI compatible SDIO controller. This patch
enables the Marvell driver to support this SoC. And enables the
SDIO controller if selected by the board configuration.
Tested on Marvell DB-88F6820-GP board.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Mon, 29 Jun 2015 12:58:09 +0000 (14:58 +0200)]
mmc: sdhci.c: Add config option to use a fixed buffer for transfers
While implementing SDIO/MMC SPL booting for the Marvell Armada 38x, the
following problem occured. The SPL runs in internal SRAM which is
the L2 cache locked to memory. When the MMC buffers now are located
on the stack (or bss), the SDIO controller (SDHCI) can't write into
this L2 cache memory.
This patch introduces a method to use a fixed buffer that will be
used for all transfers by defining CONFIG_FIXED_SDHCI_ALIGNED_BUFFER.
This way, the board can use this buffer address located in SDRAM
for all transfers. This solves this SPL problem on the A38x and
should only be used in the SPL U-Boot version.
Tested for SPL booting on Marvell Armada 38x DB-88F6820-GP board.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Mon, 29 Jun 2015 12:58:08 +0000 (14:58 +0200)]
mmc: sdhci: Use timer based timeout detection in sdhci_send_command()
The loop counter based timeout detection does not work on the Armada
38x based board (DB-88F6820-GP). At least with dcache enabled a
timeout is detected. Without dcache enabled, the timeout does not
occur. Increasing the loop counter solves this issue. But a better
solution is to use a timer based timeout detection instead. This
patch now implements this timer based detection.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Stefan Roese [Wed, 1 Jul 2015 15:38:05 +0000 (17:38 +0200)]
arm: mvebu: db-88f6820-gp: Add MAINTAINERS file
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Simon Glass [Fri, 3 Jul 2015 00:15:44 +0000 (18:15 -0600)]
exynos: i2c: Correct bug in pinmux selection
When driver model is not used the current code does not correctly select
the pinmux for the I2C bus. This bug was introduced by this commit:
8dfcbaa dm: i2c: s3c24x0: adjust to dm-i2c api
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Minkyu Kang [Thu, 2 Jul 2015 01:27:48 +0000 (10:27 +0900)]
arm: adds the status info for odroid-xu3
Adds the 'F:' entry for the board's defconfig
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>