arm64: dts: qcom: sa8155p-adp: Add base dts file

Add base DTS file for SA8155p Automotive Development Platform.
It enables boot to console, adds tlmm reserved range and ufs flash.
It also includes pmic file.

SA8155p-adp board is based on sa8155p Qualcomm Snapdragon SoC.
SA8155p platform is similar to the SM8150, so use this as base
for now.

Cc: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Link: https://lore.kernel.org/r/20210617054548.353293-6-bhupesh.sharma@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: pmm8155au_2: Add base dts file

Add base DTS file for pmm8155au_2 along with GPIOs, power-on, rtc and vadc
nodes.

Cc: Mark Brown <broonie@kernel.org>
Cc: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Link: https://lore.kernel.org/r/20210617054548.353293-5-bhupesh.sharma@linaro.org
[bjorn: Added gpio-ranges to pmm8155au_2_gpios]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: pmm8155au_1: Add base dts file

Add base DTS file for pmm8155au_1 along with GPIOs, power-on, rtc and vadc
nodes.

Cc: Mark Brown <broonie@kernel.org>
Cc: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Link: https://lore.kernel.org/r/20210617054548.353293-4-bhupesh.sharma@linaro.org
[bjorn: Added gpio-ranges to pmm8155au_1_gpios]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8250-edo: Fix up double "pinctrl-1"

When bringing the SDC pins back to edo.dtsi I managed to define
and overwrite pinctrl-1 instead of defining pinctrl-0 and 1. Fix it.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210616161536.206044-1-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8[12]50-pm8150: Move RESIN to pm8150 dtsi

It's not worth duplicating the same node over and over and over and over again,
so let's keep the common bits in the pm8150 DTSI, making only changing the
status and keycode necessary.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210613124822.124039-1-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8250: Add support for SONY Xperia 1 II / 5 II (Edo platform)

Add support for SONY Xperia 1 II and 5 II smartphones (read one/five mark two).
They are based on the Qualcomm SM8250 chipset and both feature 5G modems. There
also exists a third Edo board, namely the Xperia PRO (PDX204), but it's $2500
and no developers have obtained it so far (to my knowledge).

The devices are affected by a scary UFS behaviour where sending a certain UFS
command (which is worked around on downstream) renders the device unbootable,
by effectively erasing the bootloader. Therefore UFS AND UFSPHY are strictly
disabled for now.

Downstream workaround:
https://github.com/kholk/kernel/commit/2e7a9ee1c91a016baa0b826a7752ec45663a0561

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210616002321.74155-4-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8250: Move gpio.h inclusion to SoC DTSI

Almost any board that boots and has a way to interact with it
(say for the rare cases of just-pstore or let's-rely-on-bootloader-setup)
needs to set some GPIOs, so it makes no sense to include gpio.h separately
each time. Hence move it to SoC DTSI.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210616002321.74155-3-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8250: Add SDHCI2 sleep mode pinctrl

Add required pins for SDHCI2, so that the interface can work reliably.
This commit adds sleep_state setup to the SoC DTSI, as it is common for
all boards.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210616002321.74155-2-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8150: Add support for SONY Xperia 1 / 5 (Kumano platform)

Add support for SONY Xperia 1 and 5 smartphones, both based on the
Qualcomm SM8150 chipset. There also exist 5G-capable versions of these
devices, but they weren't sold much (if at all) outside Japan.

The devices are affected by a scary UFS behaviour where sending a certain UFS
command (which is worked around on downstream) renders the device unbootable,
by effectively erasing the bootloader. Therefore UFS AND UFSPHY are strictly
disabled for now.

Downstream workaround:
https://github.com/kholk/kernel/commit/2e7a9ee1c91a016baa0b826a7752ec45663a0561

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Tested-by: Marijn Suijten <marijn.suijten@somainline.org> (On Bahamut)
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210611203301.101067-2-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8150: Disable Adreno and modem by default

Components that rely on proprietary (not to mention signed!) firmware should
not be enabled by default, as lack of the aforementioned firmware could cause
various issues, from random errors to straight-up failing to boot.

Not enabling modem back on the HDK, as it uses a sa8150.

Also fixed a sorting mistake in both boards' dt while at it.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210611203301.101067-1-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8250: Disable Adreno and Venus by default

Components that rely on proprietary (not to mention signed!) firmware should
not be enabled by default, as lack of the aforementioned firmware could cause
various issues, from random errors to straight-up failing to boot.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210612192358.62602-1-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8250: Add GPI DMA nodes

Add and configure GPI DMA nodes to enable the way for peripherals to make
DMA transfers.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210614235630.445501-3-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8250: Fix pcie2_lane unit address

The previous one was likely a mistaken copy from pcie1_lane.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210613185334.306225-1-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8250: Add size/address-cells to dsi[01]

Add the aforementioned properties in the SoC DTSI so that everybody doesn't
have to copy that into their device DTs, effectively reducing code
duplication.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210613114356.82358-1-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8250: Don't disable MDP explicitly

DPU/MDSS is borderline useless without MDP, so disabling
both of them makes little sense. With this change, enabling
mdss will be enough.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210613110635.46537-1-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

dt-bindings: arm: qcom: Add compatible for SA8155p-adp board

SA8155p-adp board is based on Qualcomm Snapdragon sa8155p
SoC which is similar to the sm8150 SoC.

Add support for the same in dt-bindings.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Link: https://lore.kernel.org/r/20210615074543.26700-5-bhupesh.sharma@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

dt-bindings: arm: qcom: Add compatible for sm8150-mtp board

sm8150-mtp board is based on Qualcomm Snapdragon sm8150
SoC.

Add support for the same in dt-bindings.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Link: https://lore.kernel.org/r/20210615074543.26700-4-bhupesh.sharma@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sc7180: Add xo clock for eMMC and Sd card

The calculations for the DLL register values are based on the clock rate
of the reference clock. Provide the reference clock in the definition of
the two SDHCI controllers to not rely on the default values.

Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org>
Link: https://lore.kernel.org/r/1623309107-27833-1-git-send-email-sbhanu@codeaurora.org
[bjorn: Rewrote commit message]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: sc7280: Add interconnect provider DT nodes

Add the DT nodes for the network-on-chip interconnect buses found
on sc7280-based platforms.

Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
Link: https://lore.kernel.org/r/1619517059-12109-4-git-send-email-okukatla@codeaurora.org
[bjorn: Sorted nodes and dropped include]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: msm8916-huawei-g7: Add NFC

The Huawei Ascend G7 supports NFC using the NXP PN547, which is
supported by the nxp-nci-i2c driver in mainline. It seems to detect
NFC tags using "nfctool" just fine, although it seems like there
are not really any useful applications making use of the Linux NFC
subsystem. :(

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20210514104328.18756-5-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: msm8916-huawei-g7: Add display regulator

The display on the Huawei Ascend G7 is supplied by a TI TPS65132
regulator. The panel needs a driver in mainline first, but the
TPS65132 is already supported in mainline by the tps65132 driver.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20210514104328.18756-4-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: msm8916-huawei-g7: Add sensors

The Huawei Ascend G7 has 3 sensors, all supported by existing kernel drivers:

  1. Kionix KX023-1025 accelerometer (kxcjk-1023)
  2. Asahi Kasei AK09911 magnetometer (ak8975)
  3. Avago APDS9930 proximity/light sensor (tsl2772)

Add them to the huawei-g7 device tree.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20210514104328.18756-3-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: msm8916-huawei-g7: Add touchscreen

The Huawei Ascend G7 has a Synaptics "C199HW-006" touchscreen,
supplied by pm8916_l17 and pm8916_l16. Add it to the device tree
and reduce the maximum allowed voltage for pm8916_l16 to 1.8V since
we really should not use more for an I/O supply.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20210514104328.18756-2-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: msm8916: Add device tree for Huawei Ascend G7

The Huawei Ascend G7 is a smartphone from Huawei based on MSM8916.
It's fairly similar to the other MSM8916 devices, the only notable
exception are the "cd-gpios" for detecting if a SD card was inserted:
It looks like Huawei forgot to re-route this to gpio38, so the correct
GPIO seems to be gpio56 on this device.

Note: The original firmware from Huawei can only boot 32-bit kernels.
To boot arm64 kernels it is necessary to flash 64-bit TZ/HYP firmware
with EDL, e.g. taken from the DragonBoard 410c. This works because Huawei
forgot to set up (firmware) secure boot for some reason.

Also note that Huawei no longer provides bootloader unlock codes.
This can be bypassed by patching the bootloader from a custom HYP firmware,
making it think the bootloader is unlocked. I use a modified version of
qhypstub [1], that patches a single instruction in the Huawei bootloader.

The device tree contains initial support for the Huawei Ascend G7 with:
  - UART (untested, probably available via some test points)
  - eMMC/SD card
  - Buttons
  - Notification LED (combination of 3 GPIO LEDs)
  - Vibrator
  - WiFi/Bluetooth (WCNSS)
  - USB

[1]: https://github.com/msm8916-mainline/qhypstub

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20210514104328.18756-1-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sc7180-trogdor: Update flash freq to match reality

This spi flash part is actually being clocked at 37.5MHz, not 25MHz,
because of the way the clk driver is rounding up the rate that is
requested to the nearest supported frequency. Let's update the frequency
here, and remove the TODO because this is the fastest frequency we're
going to be able to use here.

Reviewed-by: Douglas Anderson <dianders@chromium.org>
Cc: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20210519054030.3217704-1-swboyd@chromium.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sc7180: Add wakeup delay for adau codec

Add wakeup delay for fixing PoP noise during capture begin.

Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Judy Hsiao <judyhsiao@chromium.org>
Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
Link: https://lore.kernel.org/r/20210513122429.25295-1-srivasam@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sdm845: Remove cros-pd-update on Cheza

This compatible string isn't present upstream. Let's drop the node as it
isn't used.

Reviewed-by: Douglas Anderson <dianders@chromium.org>
Cc: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20210601185959.3101132-2-swboyd@chromium.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sc7180: Remove cros-pd-update on Trogdor

This compatible string isn't present upstream. Let's drop the node as it
isn't used.

Reviewed-by: Douglas Anderson <dianders@chromium.org>
Cc: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20210601185959.3101132-1-swboyd@chromium.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sc7180: Disable PON on Trogdor

We don't use the PON module on Trogdor devices. Instead the reboot
reason is sort of stored in the 'eventlog' and the bootloader figures
out if the boot is abnormal and records that there. Disable the PON node
and then drop the power key disabling because that's a child node that
will no longer be enabled if the PON node is disabled.

Reviewed-by: Douglas Anderson <dianders@chromium.org>
Cc: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20210601184417.3020834-1-swboyd@chromium.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sc7180: Modify SPI_CLK voltage level for trogdor

On coachz it could be observed that SPI_CLK voltage level was only
1.4V during active transfers because the drive strength was too
weak. The line hadn't finished slewing up by the time we started
driving it down again. Using a drive strength of 8 lets us achieve the
correct voltage level of 1.8V.

Though the worst problems were observed on coachz hardware, let's do
this across the board for trogdor devices. Scoping other boards shows
that this makes the clk line look nicer on them too and doesn't
introduce any problems.

Only the clk line is adjusted, not any data lines. Because SPI isn't a
DDR protocol we only sample the data lines on either rising or falling
edges, not both. That means the clk line needs to toggle twice as fast
as data lines so having the higher drive strength is more important
there.

Signed-off-by: Wenchao Han <hanwenchao@huaqin.corp-partner.google.com>
[dianders: Adjust author real name; adjust commit message]
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20210510075253.1.Ib4c296d6ff9819f26bcaf91e8a08729cc203fed0@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: add initial device-tree for Microsoft Surface Duo

Microsoft Surface Duo is based on SM8150 chipset. This new Device Tree
is a copy of sm8150-mtp with a the addition of the volume up key and
relevant i2c nodes.

Signed-off-by: Felipe Balbi <felipe.balbi@microsoft.com>
Link: https://lore.kernel.org/r/20210603122923.1919624-1-balbi@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sdm845-mtp: enable IPA

Enable IPA on the SDM845 MTP.

Signed-off-by: Alex Elder <elder@linaro.org>
Link: https://lore.kernel.org/r/20200519123258.29228-1-elder@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sc7180: SD-card GPIO pin set bias-pull up

Some SC7180 based boards do not have external pull-up for cd-gpio.
Set this pin to internal pull-up for sleep config to avoid frequent
regulator toggle events.

Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Sujit Kautkar <sujitka@chromium.org>
Link: https://lore.kernel.org/r/20210602121313.v3.2.I52f30ddfe62041b7e6c3c362f0ad8f695ac28224@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sc7180: Move sdc pinconf to board specific DT files

Move sdc1/sdc2 pinconf from SoC specific DT file to board specific DT
files

Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Sujit Kautkar <sujitka@chromium.org>
Link: https://lore.kernel.org/r/20210602121313.v3.1.Ia83c80aec3b9535f01441247b6c3fb6f80b0ec7f@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: msm8916-samsung-a2015: Add NFC

The Samsung Galaxy A3/A5 both have a Samsung S3FWRN5 NFC chip that
works quite well with the s3fwrn5 driver in the Linux NFC subsystem.

The clock setup for the NFC chip is a bit special (although this
seems to be a common approach used for Qualcomm devices with NFC):

The NFC chip has an output GPIO that is asserted whenever the clock
is needed to function properly. On the A3/A5 this is wired up to
PM8916 GPIO2, which is then configured with a special function
(NFC_CLK_REQ or BB_CLK2_REQ).

Enabling the rpmcc RPM_SMD_BB_CLK2_PIN clock will then instruct
PM8916 to automatically enable the clock whenever the NFC chip
requests it. The advantage is that the clock is only enabled when
needed and we don't need to manage it ourselves from the NFC driver.

Note that for some reason Samsung decided to connect the I2C pins
to GPIOs where no hardware I2C bus is available, so we need to
fall back to software bit-banging with i2c-gpio.

Cc: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20210604172742.10593-5-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: msm8916-samsung-a2015: Add rt5033 battery

The Samsung Galaxy A3/A5 use a Richtek RT5033 PMIC as battery
fuel gauge, charger, flash LED and for some regulators. For now,
only add the fuel gauge/battery device to the device tree,
so we can check the remaining battery percentage.

The other RT5033 drivers need some more work first before
they can be used properly.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20210604172742.10593-4-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: msm8916-samsung-a5u: Add touch key regulator

On the Samsung Galaxy A5 the touch key is supplied by a single fixed
regulator (enabled via GPIO 97) that supplies both MCU and LED.
Add it to the device tree.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20210604172742.10593-3-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: msm8916-samsung-a3u: Add touch key regulators

The touch key MCU and LED is supplied by two separate fixed regulators
that can be enabled through GPIO 86 and 60. Add them to the device tree.

Signed-off-by: Michael Srba <Michael.Srba@seznam.cz>
[stephan: extend commit message]
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20210604172742.10593-2-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: msm8916-samsung-a2015: Add touch key

The Samsung Galaxy A3/A5 both have two capacitive touch keys,
connected to an ABOV MCU. It implements the same interface as
implemented by the tm2-touchkey driver and works just fine with
the coreriver,tc360-touchkey compatible. It's probably actually some
Samsung-specific interface that they implement with different MCUs.

Note that for some reason Samsung decided to connect this to GPIOs
where no hardware I2C bus is available, so we need to fall back
to software bit-banging using i2c-gpio.

The vdd/vcc-supply is board-specific and will be added separately
for a3u/a5u.

Co-developed-by: Michael Srba <Michael.Srba@seznam.cz>
Signed-off-by: Michael Srba <Michael.Srba@seznam.cz>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20210604172742.10593-1-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: pm6150: Add thermal zone for PMIC on-die temperature

Add a thermal zone for the pm6150 on-die temperature. The system should
try to shut down orderly when the temperature reaches the critical trip
point at 115°C, otherwise the PMIC will perform a HW power off at 145°C.

Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Link: https://lore.kernel.org/r/20210603081215.v2.1.Id4510e9e4baaa3f6c9fdd5cdf4d8606e63c262e3@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sc7180: add label for secondary mi2s

Adds label for MI2S secondary block to allow follower projects to override
for the four speaker support which uses I2S SD1 line on gpio52 pin.

Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Judy Hsiao <judyhsiao@chromium.org>
Link: https://lore.kernel.org/r/20210601022117.4071117-1-judyhsiao@chromium.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sc7280: Add "google,senor" to the compatible

The sc7280 IDP board is also called senor in the Chrome OS builds.
Add the "google,senor" compatible so coreboot/depthcharge knows what
device tree blob to pick

Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Link: https://lore.kernel.org/r/1619674827-26650-2-git-send-email-rnayak@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

dt-bindings: arm: qcom: Document google,senor board

Document the google,senor board based on sc7280 SoC

Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Link: https://lore.kernel.org/r/1619674827-26650-1-git-send-email-rnayak@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sc7280: Add nodes to boot WPSS

Add miscellaneous nodes to boot the Wireless Processor Subsystem (WPSS) on
SC7280 SoCs.

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/1619508824-14413-6-git-send-email-sibis@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

dt-bindings: mailbox: Add WPSS client index to IPCC

Add WPSS remote processor client index to Inter-Processor Communication
Controller (IPCC) block.

Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/1619508824-14413-2-git-send-email-sibis@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sc7180: Move rmtfs memory region

Move rmtfs memory region so that it does not overlap with system
RAM (kernel data) when KAsan is enabled. This puts rmtfs right
after mba_mem which is not supposed to increase beyond 0x94600000

Reviewed-by: Sibi Sankar <sibis@codeaurora.org>
Signed-off-by: Sujit Kautkar <sujitka@chromium.org>
Link: https://lore.kernel.org/r/20210514113430.1.Ic2d032cd80424af229bb95e2c67dd4de1a70cb0c@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sc7280: Add clock controller nodes

Add support for the video, gpu, display, lpass clock controller
device nodes for SC7280 SoC.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1618020280-5470-3-git-send-email-tdas@codeaurora.org
[bjorn: Dropped includes, as they are not present in v5.13-rc1]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sc7280: Add cpufreq hw node

Add cpufreq HW device node to scale 4-Silver/3-Gold/1-Gold+
cores on SC7280 SoCs.

Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1618020280-5470-2-git-send-email-tdas@codeaurora.org
[bjorn: Dropped reg-names]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sc7180: coachz: Add thermal config for skin temperature

Add ADC and thermal monitor configuration for skin temperature,
plus a thermal zone that monitors the skin temperature and uses
the big cores as cooling devices.

CoachZ rev1 is stuffed with an incompatible thermistor for the
skin temperature, disable the thermal zone for rev1 to avoid
the use of bogus temperature values.

Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Link: https://lore.kernel.org/r/20210414111007.v1.1.I1a438604a79025307f177347d45815987b105cb5@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sc7180: Fix sc7180-qmp-usb3-dp-phy reg sizes

As per Dmitry Baryshkov [1]:
a) The 2nd "reg" should be 0x3c because "Offset 0x38 is
   USB3_DP_COM_REVISION_ID3 (not used by the current driver though)."
b) The 3rd "reg" "is a serdes region and qmp_v3_dp_serdes_tbl contains
   registers 0x148 and 0x154."

I think because the 3rd "reg" is a serdes region we should just use
the same size as the 1st "reg"?

[1] https://lore.kernel.org/r/ee5695bb-a603-0dd5-7a7f-695e919b1af1@linaro.org

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Cc: Stephen Boyd <swboyd@chromium.org>
Cc: Jeykumar Sankaran <jsanka@codeaurora.org>
Cc: Chandan Uddaraju <chandanu@codeaurora.org>
Cc: Vara Reddy <varar@codeaurora.org>
Cc: Tanmay Shah <tanmay@codeaurora.org>
Cc: Rob Clark <robdclark@chromium.org>
Fixes: 58fd7ae621e7 ("arm64: dts: qcom: sc7180: Update dts for DP phy inside QMP phy")
Reported-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20210315103836.1.I9a97120319d43b42353aeac4d348624d60687df7@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8250: fix display nodes

Use sm8250 compatibles instead of sdm845 compatibles

Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210329120051.3401567-5-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: c630: Add no-hpd to DSI bridge node

We should indicate that we're not using the HPD pin on this device, per
the binding document. Otherwise if code in the future wants to enable
HPD in the bridge when this property is absent we'll be enabling HPD
when it isn't supposed to be used. Presumably this board isn't using hpd
on the bridge.

Reviewed-by: Douglas Anderson <dianders@chromium.org>
Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Cc: Douglas Anderson <dianders@chromium.org>
Cc: Steev Klimaszewski <steev@kali.org>
Fixes: 956e9c85f47b ("arm64: dts: qcom: c630: Define eDP bridge and panel")
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20210324231424.2890039-1-swboyd@chromium.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: Harmonize DWC USB3 DT nodes name

In accordance with the DWC USB3 bindings the corresponding node
name is suppose to comply with the Generic USB HCD DT schema, which
requires the USB nodes to have the name acceptable by the regexp:
"^usb(@.*)?" . Make sure the "snps,dwc3"-compatible nodes are correctly
named.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210324204836.29668-8-Sergey.Semin@baikalelectronics.ru
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: trogdor: Add no-hpd to DSI bridge node

We should indicate that we're not using the HPD pin on this device, per
the binding document. Otherwise if code in the future wants to enable
HPD in the bridge when this property is absent we'll be wasting power
powering hpd when we don't use it on trogdor boards. We didn't notice
this before because the kernel driver blindly disables hpd, but that
won't be true for much longer.

Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Cc: Douglas Anderson <dianders@chromium.org>
Fixes: 7ec3e67307f8 ("arm64: dts: qcom: sc7180-trogdor: add initial trogdor and lazor dt")
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20210324025534.1837405-1-swboyd@chromium.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: msm8994-angler: Fix gpio-reserved-ranges 85-88

Reserve GPIO pins 85-88 as these aren't meant to be accessible from the
application CPUs (causes reboot). Yet another fix similar to
9134586715e3, 5f8d3ab136d0, which is needed to allow angler to boot after
3edfb7bd76bd ("gpiolib: Show correct direction from the beginning").

Fixes: feeaf56ac78d ("arm64: dts: msm8994 SoC and Huawei Angler (Nexus 6P) support")

Signed-off-by: Petr Vorel <petr.vorel@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210415193913.1836153-1-petr.vorel@gmail.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: msm8996: Make CPUCC actually probe (and work)

Fix the compatible to make the driver probe and tell the
driver where to look for the "xo" clock to make sure everything
works.

Then we get a happy (eh, happier) 8996:

somainline-sdcard:/home/konrad# cat /sys/kernel/debug/clk/pwrcl_pll/clk_rate
1152000000

Don't backport without "arm64: dts: qcom: msm8996: Add CPU opps", as
the system fails to boot without consumers for these clocks.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210527192958.775434-1-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: msm8996: Add CPU opps

Add the operating points capabilities of the kryo CPUs, that can be
used for frequency scaling. There are two differents operating point
tables, one for the big cluster and one for the LITTLE cluster.

This frequency scaling support can then be used as a passive cooling
device (cpufreq cooling device).

Only add nominal fmax for now, since there is no dynamic control of
VDD APC (s11..) which is statically set at its nominal value.

link: https://patchwork.kernel.org/project/linux-arm-msm/patch/1595253740-29466-6-git-send-email-loic.poulain@linaro.org/
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
[konrad: drop the thermals part, rebase and remove spaces within <>]
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210527194455.782108-2-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sc7180: Add CoachZ rev3

CoachZ rev3 uses a 100k NTC thermistor for the charger temperatures,
instead of the 47k NTC that is stuffed in earlier revisions. Add .dts
files for rev3.

The 47k NTC currently isn't supported by the PM6150 ADC driver.
Disable the charger thermal zone for rev1 and rev2 to avoid the use
of bogus temperature values.

This also gets rid of the explicit DT files for rev2 and handles
rev2 in the rev1 .dts instead. There was some back and forth
downstream involving the 'dmic_clk_en' pin, after that was sorted
out the DT for rev1 and rev2 is the same.

Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20210322094628.v4.3.I95b8a63103b77cab6a7cf9c150f0541db57fda98@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sc7180: Add pompom rev3

The only kernel visible change with respect to rev2 is that pompom
rev3 changed the charger thermistor from a 47k to a 100k NTC to use
a thermistor which is supported by the PM6150 ADC driver.

Disable the charger thermal zone for pompom rev1 and rev2 to avoid
the use of bogus temperature values from the unsupported thermistor.

Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20210322094628.v4.2.I4138c3edee23d1efa637eef51e841d9d2e266659@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sc7180: lazor: Simplify disabling of charger thermal zone

Commit f73558cc83d1 ("arm64: dts: qcom: sc7180: Disable charger
thermal zone for lazor") disables the charger thermal zone for
specific lazor revisions due to an unsupported thermistor type.
The initial idea was to disable the thermal zone for older
revisions and leave it enabled for newer ones that use a
supported thermistor. Finally the thermistor won't be changed
on newer revisions, hence the thermal zone should be disabled
for all lazor (and limozeen) revisions. Instead of disabling
it per revision do it once in the shared .dtsi for lazor.

Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20210322094628.v4.1.I6d587e7ae72a5a47253bb95dfdc3158f8cc8a157@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sc7180: Remove QUP-CORE ICC path

We had introduced the QUP-CORE ICC path to put proxy votes from
QUP wrapper on behalf of earlycon, if other users of QUP-CORE turn
off this clock before the real console is probed, unclocked access
to HW was seen from earlycon.

With ICC sync state support proxy votes are no longer need as ICC
will ensure that the default bootloader votes are not removed until
all it's consumer are probed.

We can safely remove ICC path for QUP-CORE clock from QUP wrapper
device.

Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Signed-off-by: Akash Asthana <akashast@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Link: https://lore.kernel.org/r/20210324101836.25272-3-rojay@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8350: fix the node unit addresses

Some node unit addresses were put wrongly in the dts, resulting in
below warning when run with W=1

arch/arm64/boot/dts/qcom/sm8350.dtsi:693.34-702.5: Warning (simple_bus_reg): /soc@0/thermal-sensor@c222000: simple-bus unit address format error, expected "c263000"
arch/arm64/boot/dts/qcom/sm8350.dtsi:704.34-713.5: Warning (simple_bus_reg): /soc@0/thermal-sensor@c223000: simple-bus unit address format error, expected "c265000"
arch/arm64/boot/dts/qcom/sm8350.dtsi:1180.32-1185.5: Warning (simple_bus_reg): /soc@0/interconnect@90e0000: simple-bus unit address format error, expected "90c0000"

Fix by correcting to the correct address as given in reg node

Reviewed-by: Robert Foss <robert.foss@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210513060733.382420-1-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8350: use interconnect enums

Add interconnect enums instead of numbers now that interconnect is in
mainline.

Reviewed-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210513060705.382184-1-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8150: Add DMA nodes

With this patch, DMA has a chance of probing and doing something
useful.

Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Felipe Balbi <felipe.balbi@microsoft.com>
Link: https://lore.kernel.org/r/20210417061951.2105530-3-balbi@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: msm8916-alcatel-idol347: enable touchscreen

Enable the MStar msg2638 touchscreen.

Reviewed-by: Stephan Gerhold <stephan@gerhold.net>
Signed-off-by: Vincent Knecht <vincent.knecht@mailoo.org>
Link: https://lore.kernel.org/r/20210528114345.543761-1-vincent.knecht@mailoo.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: msm8996: Rename speedbin node

The speedbin value blown in the efuse is used to determine is used to
determine the voltage and frequency value for different IPs, including
GPU, CPUs... So it's really not a gpu specific information.

This patch simply renames 'gpu_speed_bin' node to 'speedbin'.

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210527194455.782108-1-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: ipq8074: disable USB phy by default

One of the QUSB USB PHY-s has been left enabled by
default, this is probably just a mistake as other
USB PHY-s are disabled by default.

It makes no sense to have it enabled by default as
not all board implement USB ports, so disable it.

Reviewed-by: Kathiravan T <kathirav@codeaurora.org>
Signed-off-by: Robert Marko <robimarko@gmail.com>
Link: https://lore.kernel.org/r/20210526150125.1816335-1-robimarko@gmail.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: msm8996: Add DMA to QUPs and UARTs

Add BAM DMA nodes and add required properties to devices
to enable DMA operations.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210525200246.118323-5-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: msm8996: Strictly limit USB2 host to USB2 speeds

As the name implies, the USB2 controller should only operate at
USB2 speeds. Make sure it does just that by pinning it to USB
High-Speed (USB2) mode.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210525200246.118323-3-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sc7280: Add ADC channel nodes for PMIC temperatures to sc7280-idp

Add channel nodes for the on die temperatures of PMICS
pmk8350, pm8350, pmr735a and pmr735b.

Signed-off-by: satya priya <skakit@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Link: https://lore.kernel.org/r/1621937466-1502-11-git-send-email-skakit@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sc7280: Include PMIC DT files for sc7280-idp

The sc7280-idp has four PMICs, include their .dtsi files.

Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: satya priya <skakit@codeaurora.org>
Link: https://lore.kernel.org/r/1621937466-1502-10-git-send-email-skakit@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: pmk8350: Correct the GPIO node

Add gpio ranges and correct the compatible to add
"qcom,spmi-gpio" as this pmic is on spmi bus.

Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: satya priya <skakit@codeaurora.org>
Link: https://lore.kernel.org/r/1621937466-1502-9-git-send-email-skakit@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: pmk8350: Add peripherals for pmk8350

Add PON, RTC, VADC and ACD_TM support for PMK8350.

Signed-off-by: satya priya <skakit@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Link: https://lore.kernel.org/r/1621937466-1502-8-git-send-email-skakit@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: pmr735a: Correct the GPIO node

Add gpio ranges and correct the compatible to add
"qcom,spmi-gpio" as this pmic is on spmi bus.

Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: satya priya <skakit@codeaurora.org>
Link: https://lore.kernel.org/r/1621937466-1502-7-git-send-email-skakit@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: pmr735a: Add temp-alarm support

Add temp-alarm support for PMR735A pmic.

Signed-off-by: satya priya <skakit@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Link: https://lore.kernel.org/r/1621937466-1502-6-git-send-email-skakit@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: pm8350c: Correct the GPIO node

Add gpio ranges and correct the compatible to add
"qcom,spmi-gpio" as this pmic is on spmi bus.

Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: satya priya <skakit@codeaurora.org>
Link: https://lore.kernel.org/r/1621937466-1502-5-git-send-email-skakit@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: pm8350c: Add temp-alarm support

Add temp-alarm support for PM8350C pmic.

Signed-off-by: satya priya <skakit@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Link: https://lore.kernel.org/r/1621937466-1502-4-git-send-email-skakit@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: pm7325: Add pm7325 base dts file

Add base DTS file for pm7325 along with GPIOs and temp-alarm nodes.

Signed-off-by: satya priya <skakit@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Link: https://lore.kernel.org/r/1621937466-1502-3-git-send-email-skakit@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sm8350: Add label for thermal-zones node

Add label "thermal_zones" for thermal-zones node.

Signed-off-by: satya priya <skakit@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Link: https://lore.kernel.org/r/1621937466-1502-2-git-send-email-skakit@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: SC7280: Add thermal zone support

Adding thermal zone and cooling maps support in SC7280.

Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Rajeshwari Ravindra Kamble <rkambl@codeaurora.org>
Link: https://lore.kernel.org/r/1620367641-23383-4-git-send-email-rkambl@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: SC7280: Add device node support for TSENS

Adding device node for TSENS controller and critical interrupt support in SC7280.

Signed-off-by: Rajeshwari Ravindra Kamble <rkambl@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Link: https://lore.kernel.org/r/1620367641-23383-3-git-send-email-rkambl@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: msm8996: Add usb3 interrupts

Add hs_phy_irq and ss_phy_irq to usb3.

Tested-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Link: https://lore.kernel.org/r/dvfyYKA9vnJdunbQ1CL-dgjXtv_1wYpRnezdc3PHoCyrgmfi5KP0Dn4MtaumQEpHIQAHL9tTdqcaCK7YJWyrdWXCrPeGd4uMh-nFeu7xQYw=@protonmail.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: msm8996: Clean up the SDHCI2 node

Fix the indentation, add pinctrl and move status="disabled"
down.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210228130831.203765-11-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: pmi8994: Add WLED node

Add and configure WLED node to enable backlight
control on WLED-enabled devices.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210228130831.203765-10-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: msm8996: Add DSI0 nodes

Add required nodes to support DSI displays connected to the
primary interface.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210228130831.203765-9-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: pm8994: Add RESIN node

Add a RESIN node to support RESIN-connected buttons on some
devices.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210228130831.203765-8-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: msm8996: Disable Venus by default

Disable Venus by default to allow booting without closed firmware and
enable it on the boards that didn't previously disable it. This commit
brings no functional difference.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210228130831.203765-7-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: msm8996: Disable MDSS and Adreno by default

Disable them by default to allow for booting without a display
and proprietary firmware. Then, enable them on boards that didn't
previously disable them. Hence, this commit brings no functional
difference.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210228130831.203765-6-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: msm8996: Add BLSP2_I2C5 and BLSP2_I2C6

Add the fifth and sixth I2C host on the second BLSP, used for
various board-specific peripherals.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210228130831.203765-5-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: msm8996: Add SDHCI1

Add SDHCI1 device to allow for usage of (more often than not) eMMC.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210228130831.203765-4-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: msm8996: Enlarge tcsr_mutex_regs size

Set the tcsr_mutex_regs size to 0x40000 to allow for accessing
all required registers that will be needed to support modem.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210228130831.203765-3-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: msm8996-*: Clean up QUP and UART names

QUP and UART names start from 1. There are 6 QUPs and 2 UARTs
per BLSP. Let's not further confuse programmers by stating
otherwise.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210228130831.203765-2-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: msm8996: Sanitize pins

In order to prepare for feature development, the DTs
have to be workable with.. To achieve that:

- Rename msmgpio to tlmm (consistency with newer DTs)
- Rid msm8996-pins.dtsi and add the contents to msm8996.dtsi
- Modernize the pin nodes, make them more concise
- Add generic pin configuration for some hardware
- Fix up some names in preparation for BLSP/UART name cleaning..

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210228130831.203765-1-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: Add board support for HK10

Add initial support for IPQ8074 SoC based HK10-C1
and HK10-C2 evaluation boards.

Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
Link: https://lore.kernel.org/r/1614328110-28866-2-git-send-email-gokulsri@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: msm8996: Disable ADSP and add power domains

Disable ADSP by default and enable it in devices that use it.
Also add CX power domain.

Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Link: https://lore.kernel.org/r/Epn1vFjJb0oQhqMYxspzL6X1N6MPcDT1f9oVVOjXc@cp3-web-020.plabs.ch
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: remove camera_mem region

qcom camera driver allocates the ICP firmware memory
dynamically, so the carveout region is unnecessary.

Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Sergey Senozhatsky <senozhatsky@chromium.org>
Link: https://lore.kernel.org/r/20210525133242.188603-1-senozhatsky@chromium.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sdm845-xiaomi-beryllium: Add audio support

This patch adds audio support for Xiaomi Poco F1 phone. Phone's primary
Mic and 3.5mm Headphone jack are handled through the SDM845 sound card
and WCD9340 codec.

Tested-by: Amit Pundir <amit.pundir@linaro.org>
Reviewed-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Joel Selvaraj <jo@jsfamily.in>
Link: https://lore.kernel.org/r/BN6PR2001MB17966ED1D787FA3F4B90A1A7D95B9@BN6PR2001MB1796.namprd20.prod.outlook.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sdm845-oneplus-common: enable ipa

Enable the ipa node so that we can bring up mobile data.

Signed-off-by: Caleb Connolly <caleb@connolly.tech>
Link: https://lore.kernel.org/r/20210502014146.85642-5-caleb@connolly.tech
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sdm845-oneplus-common: guard rmtfs-mem

The rmtfs_mem region is a weird one, downstream allocates it
dynamically, and supports a "qcom,guard-memory" property which when set
will reserve 4k above and below the rmtfs memory.

A common from qcom 4.9 kernel msm_sharedmem driver:

/*
 * If guard_memory is set, then the shared memory region
 * will be guarded by SZ_4K at the start and at the end.
 * This is needed to overcome the XPU limitation on few
 * MSM HW, so as to make this memory not contiguous with
 * other allocations that may possibly happen from other
 * clients in the system.
*/

When the kernel tries to touch memory that is too close the
rmtfs region it may cause an XPU violation. Such is the case on the
OnePlus 6 where random crashes would occur usually after boot.

Reserve 4k above and below the rmtfs_mem to avoid hitting these XPU
Violations.

This doesn't entirely solve the random crashes on the OnePlus 6/6T but
it does seem to prevent the ones which happen shortly after modem
bringup.

Fixes: 288ef8a42612 ("arm64: dts: sdm845: add oneplus6/6t devices")
Signed-off-by: Caleb Connolly <caleb@connolly.tech>
Link: https://lore.kernel.org/r/20210502014146.85642-4-caleb@connolly.tech
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

arm64: dts: qcom: sc7180: add nodes for idp display

Add nodes for IDP display. The display is Visionox RM69299.

Signed-off-by: Harigovindan P <harigovi@codeaurora.org>
Link: https://lore.kernel.org/r/20200629135144.8265-1-harigovi@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>