Daniel Stone [Sun, 12 Mar 2023 17:01:44 +0000 (17:01 +0000)]
Revert "ci: Disable Collabora LAVA farm"
This reverts commit
c1aa876747a37d42b67ff1f53675890b05b40d1a.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21864>
Kai Wasserbäch [Sat, 11 Feb 2023 17:38:01 +0000 (18:38 +0100)]
fix: gallivm: fix LLVM #include of Host.h, moved to TargetParser
Upstream moved Host.h from Support to TargetParser in LLVM 17.
This shouldn't lead to a FTBFS, since there is a forwarding include left
behind. Sadly the added deprecation warning #pragma is invalid and thus
causes a build failure right away. But since we would have to follow the
move anyway in the future, just do it right away.
Reference: https://github.com/llvm/llvm-project/commit/
d768bf994f508d7eaf9541a568be3d71096febf5
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Closes: #8275
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21263>
Konstantin Seurer [Sat, 4 Mar 2023 16:18:25 +0000 (17:18 +0100)]
radv/rt: Properly handle pNext of pipeline library stages
Fixes
dEQP-VK.pipeline.pipeline_library.graphics_library.misc.non_graphics.shader_module_info_rt_lib.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21707>
Konstantin Seurer [Sat, 4 Mar 2023 16:17:13 +0000 (17:17 +0100)]
vulkan: Add vk_shader_module_init
This will be used for allocating shader modules using ralloc by RADV.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21707>
Konstantin Seurer [Sat, 4 Mar 2023 15:51:40 +0000 (16:51 +0100)]
radv/rt: Use vk_pipeline_hash_shader_stage for RT stages
Fixes
dEQP-VK.pipeline.pipeline_library.graphics_library.misc.non_graphics.shader_module_info_rt.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21707>
David Heidelberg [Fri, 10 Mar 2023 07:55:31 +0000 (08:55 +0100)]
ci/iris: update apl and glk expectations, after enabling Wayland support
After enabling the Wayland platform for x86_64,
multiple new tests were triggered, some of which timed out.
Also wayland-dEQP-EGL.functional.negative_api.create_pixmap_surface now pass.
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21786>
David Heidelberg [Mon, 13 Feb 2023 19:43:21 +0000 (20:43 +0100)]
ci: build Wayland support for the amd64
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21786>
Alyssa Rosenzweig [Tue, 7 Mar 2023 16:38:36 +0000 (11:38 -0500)]
agx: Lower discard late
Fixes regression with Dolphin's ubershaders.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21855>
Mike Blumenkrantz [Wed, 8 Mar 2023 17:20:27 +0000 (12:20 -0500)]
zink: ignore renderdoc if ZINK_RENDERDOC isn't in use
this otherwise has some weird side effects
Fixes:
48a0478126f ("zink: add renderdoc handling")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21816>
Alyssa Rosenzweig [Fri, 10 Mar 2023 02:01:02 +0000 (21:01 -0500)]
ail: Restructure generated tests
Currently, the generated tests consist of some boilerplate, generated
test cases, and at the very end the actual test. This is bad for readability,
because the actual code is all the way at the bottom. It's also bad for
clang-format linting: even though the test cases are /* clang-format off */,
they still take an exceptionally long time to parse when linting. I suspect this
is a clang-format bug, but it's easy enough to workaround.
To solve these issues, restructure so that the test cases are in separate files
(containing the actual data), but the manually written test functions are
consolidated into a new family of generated layout tests. This is probably
cleaner.
Parallel clang-format linting is now 10x faster on the M1, which means it's
now practical to lint in my "publish branch" hook.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21854>
José Roberto de Souza [Tue, 9 Aug 2022 17:26:54 +0000 (10:26 -0700)]
anv: Integrate gem vm bind and unbind kmd backend functions
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21698>
José Roberto de Souza [Thu, 9 Feb 2023 16:57:11 +0000 (08:57 -0800)]
anv: Add gem VM bind and unbind to backend
Not using it yet, that will be done in the next patch.
Xe only supports submission using VM.
For i915 the backend functions are just a noop.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21698>
José Roberto de Souza [Thu, 9 Feb 2023 16:50:57 +0000 (08:50 -0800)]
anv: Implement gem close and mmap for Xe backend
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21698>
José Roberto de Souza [Thu, 9 Feb 2023 16:44:04 +0000 (08:44 -0800)]
anv: Implement Xe functions to create and destroy VM
Also using the vm_id to create gem buffers.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21698>
José Roberto de Souza [Thu, 9 Feb 2023 16:24:17 +0000 (08:24 -0800)]
anv: Implement gem_create for Xe backend
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21698>
Isabella Basso [Fri, 10 Mar 2023 20:20:10 +0000 (17:20 -0300)]
nir/algebraic: remove duplicate bool conversion lowerings
While [1] added some boolean conversion lowering patterns, those were
already dealt with on [2].
[1] -
b86305bb ("nir/algebraic: collapse conversion opcodes (many patterns)")
[2] -
d7e0d47b ("nir/algebraic: nir: Add a bunch of b2[if] optimizations")
Fixes:
b86305bb ("nir/algebraic: collapse conversion opcodes (many patterns)")
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Signed-off-by: Isabella Basso <isabellabdoamaral@usp.br>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20965>
Isabella Basso [Fri, 10 Mar 2023 20:20:10 +0000 (17:20 -0300)]
nir/algebraic: make patterns for float conversion lowerings imprecise
As noted on [1], lowering patterns of the form
floatS -> floatB -> floatS ==> floatS
cannot require precision since this may cause flush denorming.
[1]
3f779013 ("nir: Add an algebraic optimization for float->double->float")
Fixes:
b86305bb ("nir/algebraic: collapse conversion opcodes (many patterns)")
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Signed-off-by: Isabella Basso <isabellabdoamaral@usp.br>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20965>
Isabella Basso [Fri, 10 Mar 2023 20:20:09 +0000 (17:20 -0300)]
nir/algebraic: extend lowering patterns for conversions on smaller bit sizes
Conversions on smaller bit sizes should also be collapsed when composed.
This also adds more patterns on the
intS -> intB -> floatB ==> intS -> floatB
lowering so as to deal with any int size C > B instead of a fixed intB.
Closes: #7776
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Signed-off-by: Isabella Basso <isabellabdoamaral@usp.br>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20965>
Isabella Basso [Fri, 10 Mar 2023 20:20:09 +0000 (17:20 -0300)]
nir/algebraic: extend mediump patterns
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Suggested-by: Italo Nicola <italonicola@collabora.com>
Signed-off-by: Isabella Basso <isabellabdoamaral@usp.br>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20965>
Isabella Basso [Fri, 10 Mar 2023 20:20:07 +0000 (17:20 -0300)]
nir/algebraic: insert patterns inside optimizations list
Some patterns were outside the list of optimizations.
Fixes:
b86305bb ("nir/algebraic: collapse conversion opcodes (many patterns)")
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Signed-off-by: Isabella Basso <isabellabdoamaral@usp.br>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20965>
Alyssa Rosenzweig [Tue, 7 Mar 2023 00:19:41 +0000 (19:19 -0500)]
nir/lower_point_size: Use shader_instructions_pass
Sleepy code deletion mood.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21750>
Alyssa Rosenzweig [Wed, 1 Mar 2023 19:29:17 +0000 (14:29 -0500)]
agx: Switch to scoped_barrier
Rather than ingesting separate control and memory barriers, ingest only the
combined and optimized scoped_barrier intrinsic. For barriers originating from
GLSL, this makes it easier to ensure correctness. For barriers originating from
SPIR-V, this is required for translation at all, as spirv_to_nir knows only
scoped barriers. So this gets us closer to Vulkan and OpenCL.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21752>
David Heidelberg [Sat, 4 Mar 2023 13:46:01 +0000 (14:46 +0100)]
ci/lava: every LAVA job doesn't want to run gles2 deqp, drop it
Very annoying when adding new job and not getting failure due to missing
`DEQP_VER: `
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21702>
David Heidelberg [Fri, 10 Mar 2023 14:10:44 +0000 (15:10 +0100)]
ci/panfrost: correct the job name, as it runs on gles2
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21702>
David Heidelberg [Sat, 4 Mar 2023 13:33:02 +0000 (14:33 +0100)]
ci/amd: move skqp and va jobs on raven from XOrg to the XWayland
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21702>
David Heidelberg [Tue, 17 Jan 2023 18:01:36 +0000 (19:01 +0100)]
ci: add and utilize dalboz devices
New 10 devices - asus-CM1400CXA-dalboz hosted on Collabora farm.
1x Move VA-API tests to the dalboz (more resources). One timeout dropped.
9x Run VKCTS on dalboz.
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21702>
Sil Vilerino [Fri, 10 Mar 2023 03:59:45 +0000 (22:59 -0500)]
d3d12: Fix video decode for interlaced streams with reference only textures required
Fixes:
d8206f628659d468c870430daa271d5bec6e860d ("d3d12: Add video decode implementation of pipe_video_codec")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21832>
Alyssa Rosenzweig [Sun, 26 Feb 2023 03:29:42 +0000 (22:29 -0500)]
agx: Use nir_lower_mem_access_bit_sizes
Lowers away 64-bit loads, which we'll create in the sysval lowering for
dynamically indexed UBOs/VBOs. The lowering generates pack_64_2x32 instructions,
so lower those too.
No shader-db changes.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21674>
Alyssa Rosenzweig [Fri, 3 Mar 2023 05:29:49 +0000 (00:29 -0500)]
agx: Implement extract_[ui]16
Instead of lowering to bitwise ops. Yet another way of subdividing in NIR.
Probably insignificant but makes it easy to check that the pass ordering from the
previous pass is right. It does let us get much better codegen for
unpacksnorm2x16, whatever that's worth.
No shader-db changes.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21674>
Alyssa Rosenzweig [Sun, 19 Feb 2023 04:33:12 +0000 (23:33 -0500)]
agx: Fix subdivision coalescing
As intended. We can't CSE with partial null destinations in the way, so we
shouldn't eliminate dead destinations until after CSE has run. But we should
still eliminate dead instructions to ensure CSE doesn't move things around
needlessly, hurting register pressure.
Noticed while debugging live range splitting.
No GLES3.0 shader-db changes.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21674>
Alyssa Rosenzweig [Fri, 3 Mar 2023 05:12:00 +0000 (00:12 -0500)]
agx: Make partial DCE optional
Our dead code elimination pass does two things:
1. delete instructions that are entirely unnecessary
2. delete unnecessary destinations of necessary instructions
To deal with pass ordering issues, we sometimes want to do #1 without #2.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21674>
Alyssa Rosenzweig [Mon, 27 Feb 2023 04:33:02 +0000 (23:33 -0500)]
agx: Don't set lower_pack_split
We should handle nir_op_unpack_32_2x16_split_* natively, since we can generate
better code with agx_subdivide (coalescing the ops away) than the bitshift
lowering.
That said, we do need some extra instructions for the floating point
conversions.
No shader-db changes (which makes sense because we're targetting the GLES3.0
shader-db, which doesn't have the packing GLSL functions).
The real motivation of this change isn't optimizing some GLSL pack functions,
though, it's avoiding a code regression from using NIR's memory bit size
lowering in a future MR. That lowering will turn things like "load i16vec4" into
"load i32vec2 + unpack_32_2x16", so we need to be able to coalesce that unpack.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21674>
Daniel Stone [Sat, 11 Mar 2023 11:59:31 +0000 (11:59 +0000)]
ci: Disable Collabora LAVA farm
Looks like a power or network issue.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21851>
Eric Engestrom [Sat, 11 Mar 2023 09:01:23 +0000 (09:01 +0000)]
ci: take valve farm offline
It seems to be experiencing networking issues
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21851>
Daniel Stone [Thu, 9 Mar 2023 19:07:36 +0000 (19:07 +0000)]
ci: Actually run Piglit on LAVA
At some point in a refactoring long ago, our 'Piglit' runs on arm64
started actually being dEQP-GLES2 runs. Oh dear.
Surprisingly, there are a number of expectation changes; added every
fail I saw from a long overnight stress test.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21851>
Alyssa Rosenzweig [Wed, 28 Dec 2022 20:57:01 +0000 (15:57 -0500)]
pan/mdg: Remove reference to removed macro
This will soon be more confusing than helpful.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20445>
Alyssa Rosenzweig [Wed, 28 Dec 2022 21:15:21 +0000 (16:15 -0500)]
panfrost: Remove MALI_POSITIVE macro
Now unused.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20445>
Alyssa Rosenzweig [Wed, 28 Dec 2022 21:14:49 +0000 (16:14 -0500)]
panfrost: Inline the last MALI_POSITIVE use
Big shrug on this one.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20445>
Alyssa Rosenzweig [Wed, 28 Dec 2022 21:03:04 +0000 (16:03 -0500)]
panfrost: Remove FBD tag enum from XML
This was a hack to avoid modelling the full data structure.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20445>
Alyssa Rosenzweig [Wed, 28 Dec 2022 21:14:14 +0000 (16:14 -0500)]
panfrost: Use framebuffer pointer XML
Rather than manipulating the raw pointers. This is cleaner.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20445>
Alyssa Rosenzweig [Wed, 28 Dec 2022 21:01:55 +0000 (16:01 -0500)]
panfrost: Add XML for framebuffer pointers
We shouldn't have to open-code these. They are real data structures, model them
as such in the architecture XML files.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20445>
Alyssa Rosenzweig [Wed, 28 Dec 2022 20:43:48 +0000 (15:43 -0500)]
panfrost: Handle fixed-point packing in GenXML
Minimum/maximum LOD and LOD bias are unsigned and signed fixed point formats
respectively. They are not unsigned integers. Introduce fixed-point types into
our GenXML and use them in the XML, rather than packing in sidebands. This makes
the XML more correct and fixes pretty-printing of texture and sampler
descriptors.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20445>
Alyssa Rosenzweig [Wed, 28 Dec 2022 20:53:41 +0000 (15:53 -0500)]
panfrost: Don't use DECODE_FIXED16 for sample position
Strictly this is a signed fixed-point, anyway.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20445>
Alyssa Rosenzweig [Wed, 28 Dec 2022 20:26:45 +0000 (15:26 -0500)]
docs/panfrost: Move description of instancing
Connor Abbott wrote a nice explanation of how instance divisors work on Mali.
Let's add it to the driver docs instead of letting it languish in a forgotten
header file.
This is mostly pasted from the existing header in tree, with a few local changes
applied.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20445>
Alyssa Rosenzweig [Wed, 28 Dec 2022 20:28:50 +0000 (15:28 -0500)]
panfrost: Remove some unused definitions
Nowadays, formats are defined with GenXML, not the old panfrost-job.h, so most
of the format #defines in panfrost-job.h are unused. That said, a few are still
in use as a backdoor for compressed format queries to avoid a GenXML dependency.
That's not great but cleaning that up isn't the subject of this MR.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20445>
Felix DeGrood [Fri, 10 Mar 2023 16:34:02 +0000 (16:34 +0000)]
intel/perf: Hide extended metrics by default
XE architecture enables many more metrics, perhaps too many for
the average user. Reduce reported metrics to smaller subset,
known as non-extended metrics, by default. Can re-enable extended
metrics with env var INTEL_EXTENDED_METRICS=1
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21841>
Alyssa Rosenzweig [Fri, 3 Mar 2023 04:05:50 +0000 (23:05 -0500)]
asahi,agx: Implement buffer textures with gnarly NIR
Implement buffer textures in full generality. There are a few issues here:
* OpenGL requires buffer textures support a minimum size of 65536 elements,
however 1D textures in AGX are (at most) 8192 elements.
* OpenGL 4.0 (and OpenGL ES) require buffer textures to support the "RGB32"
texture formats. These are 3 packed channels of 32-bits each. In general,
non-power-of-two texel sizes are problematic. AGX does not support any such
formats and we rely on the GL frontend to lower to a padded format (RGBX) if
necessary. Such a lowering cannot work for buffer textures, however, so we
need to find a way to implement RGB32 buffer textures.
We solve these issues in the follow way:
* Use 2D texture descriptors for buffer textures, with a large fixed
power-of-two size along one axis. Then large texel indices may be accessed at
a small vec2 texel coordinate, and since the fixed dimension is a
power-of-two, that vector may be recovered by simply shifting and masking.
This effectively avoids size restriction. We do need to clamp texel indices to
the buffer size to avoid faulting on OOB reads, since we may read past the end
of the buffer (if the app binds a non-page-aligned offset into the buffer).
* Use a general purpose memory load for RGB32 buffer textures. Lower the texture
load instruction to a memory load from the buffer and some address arithmetic.
There's no format conversion needed for RGB32, other than maybe filling in a
format-appropriate alpha, so this is straightforward. Again, we need to clamp
the texel index for robustness with OOB reads.
Each of these solutions brings its own problem.
* Using 2D textures instead of 1D requires physically rounding up the buffer
size when packing the descriptor, so we can no longer implement textureSize()
by reading off the texture descriptor like normal.
* We don't know at compile-time whether a given texture load will read from an
RGB32 buffer texture or not, so we need to emit code for both. In Vulkan, we
can't key the shader to this property, either, since it's descriptor set state
and not pipeline state.
And each of these problems in turn brings its own solution:
* The texture descriptor is linear, so the "compression buffer address" field is
ignored by the hardware. We stash the real buffer size there so that
textureSize becomes a load from the texture descriptor like usual, without
requiring a sideband (which would complicate bindless textures).
* If we determine a texture descriptor contains RGB32 data, then it will never
be interpreted by the hardware and hence does not need to be a valid texture
descriptor. So, we extend the hardware's format enum to contain a
software-defined RGB32 format enum. Then, when lowering texture buffer loads,
we either read it as a typed RGB32 memory load or as a texture load depending
on the value of the format field in the texture descriptor.
All of this is accomplished with a big NIR pass generating a pile of strange
looking code. But it should be good enough in practice for this silly feature.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21672>
Alyssa Rosenzweig [Fri, 3 Mar 2023 04:02:05 +0000 (23:02 -0500)]
asahi, agx: Implement dummy samplers
In NIR, texelFetch (txf) does not use a sampler, but in AGX, it does -- even
though the contents of the sampler are semantically irrelevant. Rather than
requiring the state tracker to bind a sampler anyway (indicated for texture
buffers with PIPE_CAP_TEXTURE_BUFFER_SAMPLER), just add a dummy sampler
ourselves if txf is used and there are otherwise no samplers. This is helpful
because PIPE_CAP_TEXTURE_BUFFER_SAMPLER isn't honoured by Rusticl or seemingly
mesa/st's PBO code, and after implementing this dummy sampler workaround in
Panfrost for Rusticl, I realized this CAP is silly and shouldn't exist in the
first place. (And I regret pushing for its reinclusion.)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21672>
Guilherme Gallo [Thu, 9 Mar 2023 17:46:56 +0000 (14:46 -0300)]
ci/baremetal: Wrap artifact download curl with xtrace
Setting `set -x`can be useful to known via trace which URL baremetal
used to download artifacts.
Today its only printed the command with the environment variables.
Also, this commit fixes multiple `section_end` for the related Gitlab
sections.
Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21804>
Guilherme Gallo [Wed, 8 Mar 2023 16:34:00 +0000 (13:34 -0300)]
ci: Fix release build use for performance jobs
This commit ensures that we are using mesa release builds in performance
jobs.
To achieve that, some modifications were made on top of
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21492.
- Append the `BUILDTYPE` variable into the S3 artifact name
(MINIO_ARTIFACT_NAME environment variable) to allow for better
artifact management.
- The ./artifacts directory has been added to the list of artifact
directories for build-common. This ensures that the debian-release and
debian-arm64-release jobs are the only ones necessary for running
performance jobs. These jobs only produce artifacts via
prepare-artifacts.sh when we are under performance workflow.
- Make lava-submit.sh behave similar to baremetal jobs regarding
MINIO_ARTIFACT_NAME variable. For example, users can now easily
differentiate between mesa-arm64.tar.zstd and
mesa-arm64-release.tar.zstd by looking inside the `Downloading
artifacts from s3` Gitlab section.
Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21804>
José Roberto de Souza [Tue, 14 Feb 2023 16:10:03 +0000 (08:10 -0800)]
iris: Move i915 submit_batch() to i915 backend
No changes in behavior intented here.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21700>
José Roberto de Souza [Fri, 21 Oct 2022 16:46:18 +0000 (09:46 -0700)]
iris: Add batch_check_for_reset() to kmd backend
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21700>
José Roberto de Souza [Mon, 13 Feb 2023 17:07:54 +0000 (09:07 -0800)]
iris: Add gem_mmap() to kmd backend
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21700>
José Roberto de Souza [Wed, 23 Nov 2022 20:32:02 +0000 (12:32 -0800)]
build: Block build of HASVK, Crocus and i915 in non-x86 architectures
HASVK, Crocus and i915 drivers only supports integrated GPUs.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21773>
José Roberto de Souza [Fri, 10 Feb 2023 16:04:37 +0000 (08:04 -0800)]
intel/perf: Disable it for Xe KMD
Xe still don't have support for performance metrics.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21773>
José Roberto de Souza [Thu, 9 Mar 2023 19:00:10 +0000 (11:00 -0800)]
iris: Don't mark protected bo as reusable
The check in alloc_bo_from_cache() was skiping any try to get a bo
from cache but after use a protected bo was still being put in some
cache bucket and could be used for cases that don't require a
protected bo.
Using a protected bo in cases that don't require it can have
performance implications.
So here returning NULL when trying to get a cache bucket for a
protected bo, this will cause bo->real.reusable to be set to false
avoiding the bo to be reused.
Fixes:
9402ac8023a0 ("iris: handle protected BO creation")
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21824>
Alyssa Rosenzweig [Sat, 4 Mar 2023 18:16:54 +0000 (13:16 -0500)]
asahi: Don't allow linear depth/stencil buffers
We don't have a way to tell the ZLS hardware to use linear buffers, so if a
buffer could be used for depth/stencil, we have to twiddle. This isn't a problem
in practice, since depth/stencil buffers can't be shared across processes or
mapped directly as linear.
Fixes faults in depthstencil-render-miplevels, which was picking linear for one
buffer because of a STAGING bind flag. But that won't work :-)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21753>
Daniel Stone [Fri, 10 Mar 2023 13:38:30 +0000 (13:38 +0000)]
ci/android: Use a more aggressive timeout for the job
This job sometimes - very, very, rarely - fails to start Cuttlefish,
the Android VM environment. Given that we don't have any structural
monitoring and restarting (unlike LAVA/BM/B2C) for this, just stick a
more aggressive timeout on the job, so it'll be retried if it fails to
start.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21837>
Ian Romanick [Wed, 12 Oct 2022 21:21:02 +0000 (14:21 -0700)]
nir/lower_int64: Optionally lower ufind_msb using uadd_sat
v2: Fix inverted condition for applying the optimization. Noticed by
Ken.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19042>
Ian Romanick [Mon, 10 Oct 2022 20:42:56 +0000 (13:42 -0700)]
nir/algebraic: Optimize some ifind_msb to ufind_msb
On Intel platforms, the uclz lowering if ufind_msb is either one
instruction better (Gfx7 and newer) or two instructions better (all
older platforms) than the ifind_msb implementations.
On platforms that use lower_find_msb_to_reverse, there should be no
difference.
All Haswell and newer Intel platforms had similar results. (Ice Lake shown)
total instructions in shared programs:
19938662 ->
19938634 (<.01%)
instructions in affected programs: 850 -> 822 (-3.29%)
helped: 2 / HURT: 0
total cycles in shared programs:
858467067 ->
858465538 (<.01%)
cycles in affected programs: 10080 -> 8551 (-15.17%)
helped: 2 / HURT: 0
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19042>
Ian Romanick [Wed, 12 Oct 2022 21:52:19 +0000 (14:52 -0700)]
nir: Restrict ufind_msb and ufind_msb_rev to 32- or 64-bit sources
4d802df3aac353970aae93699223fb15b24f8408 loosened the type restrictions
on these opcodes to enable support for 64-bit ballot operations. In
doing so, it enabled 8-bit and 16-bit sizes as well.
It's impossible to get these sizes through GLSL or SPIR-V. None of the
lowering in nir_opt_algebraic can handle non-32-bit sizes. Almost no
drivers can handle non-32-bit sizes.
It doesn't seem possible to enforce anything other than "one bit size"
or "all bit sizes" in nir_opcodes.py. The only way it seems possible to
enforce this is in nir_validate. This is not ideal, but it be what it
be.
v2: Remove restriction on find_lsb. It is acutally possible to get this
via GLSL by doing findLSB() on a lowp value. findMSB declares its
parameter as highp, so that path is still impossible.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19042>
Ian Romanick [Mon, 24 Oct 2022 20:26:31 +0000 (13:26 -0700)]
nir/algebraic: Do not generate 8- or 16-bit find_msb
The next commit will add validation to restrict this instruction (and
others) to only 32-bit or 64-bit sources.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19042>
Ian Romanick [Wed, 8 Mar 2023 17:35:07 +0000 (09:35 -0800)]
nir/builder: Do not generate 8- or 16-bit find_msb
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19042>
Ian Romanick [Mon, 10 Oct 2022 20:21:52 +0000 (13:21 -0700)]
nir: intel/compiler: Move ufind_msb lowering to NIR
Fossil-db results:
All Intel platforms had similar results. (Ice Lake shown)
Cycles in all programs:
9098346105 ->
9098333765 (-0.0%)
Cycles helped: 6
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19042>
Ian Romanick [Wed, 12 Oct 2022 20:50:01 +0000 (13:50 -0700)]
nir/algebraic: Only lower ufind_msb with 32-bit sources
The 31-ufind_msb_rev(x) lowering only produces the correct result for
32-bit sources. ufind_msb_rev can also have 64-bit sources, and most
platforms are expected to lower this to 32-bit instructions with extra
logic operations.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19042>
Ian Romanick [Wed, 12 Oct 2022 22:32:01 +0000 (15:32 -0700)]
intel/compiler: Tighter src and dest size bounds checking for some opcodes
Enforce the sizes listed in the Skylake PRM:
BFREV:
source types: *D
destination types: *D
CBIT:
source types: UB, UW, UD
destination types: UD
FBH:
source types: D, UD
destination types: UD
FBL:
source types: UD
destination types: UD
LZD:
source types: D, UD
destination types: UD
v2: Update BFREV commit message documentation. Suggested by Ken.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19042>
Ian Romanick [Mon, 10 Oct 2022 20:35:01 +0000 (13:35 -0700)]
nir: intel/compiler: Move ifind_msb lowering to NIR
Unlike ufind_msb, ifind_msb is only defined in NIR for 32-bit values, so
no @32 annotation is required.
No shader-db or fossil-db changes on any Intel platform.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19042>
Ian Romanick [Mon, 10 Oct 2022 20:41:59 +0000 (13:41 -0700)]
intel/compiler: Lower find_lsb in NIR
No shader-db or fossil-db changes on any Intel platform.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19042>
Ian Romanick [Wed, 12 Oct 2022 21:51:22 +0000 (14:51 -0700)]
nir: ifind_msb_rev can only have int32 sources
Just like ifind_msb.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19042>
antonino [Mon, 6 Feb 2023 15:16:04 +0000 (16:16 +0100)]
zink: fix stipple pattern in oblique lines
Stipple lines now appear correctly when they are oblique.
Previously the number of steps of the stipple counter between two vertices
was calculated as the euclidian distance between them in screen space, however
the length occupied by pixel along a line is only `1` for lines that are either
vertical or horizontal and will be anywhere between `1` and `sqrt(2)`
for other cases.
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21290>
Alyssa Rosenzweig [Mon, 27 Feb 2023 02:53:16 +0000 (21:53 -0500)]
agx: Handle indirect texture/samplers
Get the texture/sampler index from the texture/sampler_offset source (which
is an offset from 0 thanks to the lower_index_to_offset lowering) and feed it in
as corresponding 16-bit texture instruction sources.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21704>
Alyssa Rosenzweig [Mon, 27 Feb 2023 02:52:35 +0000 (21:52 -0500)]
agx: Pack indirect texture/sampler handles
For indirect indexing into the binding table. Note this does not handle packing
the bindless forms, since that's a bit more involved.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21704>
Erik Faye-Lund [Thu, 9 Mar 2023 13:27:14 +0000 (14:27 +0100)]
docs/zink: fixup wording of the GL 4.6 requirements
Seems the copy-pasta was strong in this one. Whoops!
Fixes:
5deac5c1565 ("docs: document zink GL 4.6 requirements")
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21813>
Erik Faye-Lund [Thu, 9 Mar 2023 13:25:19 +0000 (14:25 +0100)]
docs/zink: remove some trailing spaces
These went unnoticed until now, let's fix them.
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21813>
Erik Faye-Lund [Thu, 9 Mar 2023 13:23:14 +0000 (14:23 +0100)]
docs/zink: use vk-feat role for features
This gives us links to the features, instead of just mentioning them.
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21813>
Erik Faye-Lund [Thu, 9 Mar 2023 13:22:11 +0000 (14:22 +0100)]
docs: implement new vk-feat role
This makes it easy to link to a specific Vulkan feature from the docs.
Useful for the Zink docs.
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21813>
Pino Toscano [Thu, 9 Mar 2023 21:21:43 +0000 (22:21 +0100)]
symbols-check: support OSes based on GNU toolchain
Some of the symbols listed in PLATFORM_SYMBOLS are not only specific
to Linux, but rather specific to the GNU toolchain. Hence, use them
when inspecting ELF binaries produced by a GNU toolchain: this means
on Hurd ('GNU'), and on e.g. kFreeBSD ('GNU/kFreeBSD').
Signed-off-by: Pino Toscano <toscano.pino@tiscali.it>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21825>
Mike Blumenkrantz [Fri, 10 Mar 2023 12:07:27 +0000 (07:07 -0500)]
Revert "Revert "ci: disable mesa-swrast runner jobs""
This reverts commit
7ae0d9d2e8a9f0993b056a332e6182e5c655be73.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21836>
Eric Engestrom [Fri, 10 Mar 2023 10:33:05 +0000 (10:33 +0000)]
v3dv: split out broadcom_shader_stage_to_gl() calls to improve readability
This is an inline function with a compile-constant switch, so I expect
the compiler wouldn't produce any better code like this, but for humans
it's easier to read when function calls are not embedded into other
function calls.
Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21835>
Eric Engestrom [Thu, 23 Feb 2023 10:49:37 +0000 (10:49 +0000)]
meson: inline gtest_test_protocol now that it's always 'gtest'
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21485>
Eric Engestrom [Thu, 23 Feb 2023 10:48:58 +0000 (10:48 +0000)]
meson: allow feature options to take true/false to mean enabled/disabled
This reduces the pain of Meson having picked inconsistent value names.
See also https://github.com/mesonbuild/meson/pull/11279 where Meson devs
argue that allowing `foo=false` could be interpreted by users to mean
either `disabled` or `auto`, which I personally don't see.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21485>
Eric Engestrom [Thu, 23 Feb 2023 10:47:03 +0000 (10:47 +0000)]
meson: bump minimum version to 0.60
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21485>
Sagar Ghuge [Wed, 8 Mar 2023 20:31:51 +0000 (12:31 -0800)]
intel/compiler: Add swsb_stall debug option
When enabled, on gfx12 plus, we will add the sync nop instruction after
each instruction to make sure that current instruction depends on the
previous instruction explicitly.
This option will help us to get a hint if something is missing or broken
in software scoreboard pass.
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21797>
Alyssa Rosenzweig [Fri, 10 Mar 2023 01:40:53 +0000 (20:40 -0500)]
agx: Fix clang-formatting
Not sure how this one slipped in.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21828>
Emma Anholt [Thu, 9 Mar 2023 20:56:44 +0000 (12:56 -0800)]
Revert "ci: disable mesa-swrast runner jobs"
This reverts commit
aef0f3efdfbcaaea78f2eb2315b064d92117abae.
We've got a new set of runners now (mesa-swrast-4, 5, and 7 because
counting is hard)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21826>
Lionel Landwerlin [Thu, 2 Mar 2023 09:22:03 +0000 (11:22 +0200)]
iris: trace frames with u_trace
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21648>
Lionel Landwerlin [Thu, 2 Mar 2023 09:20:44 +0000 (11:20 +0200)]
docs: fix invalid link
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21648>
Kenneth Graunke [Wed, 8 Mar 2023 10:05:24 +0000 (02:05 -0800)]
intel/eu: Simplify brw_F32TO16 and brw_F16TO32
Now that we aren't using them on Gfx8+ we can drop a lot of cruft.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21783>
Kenneth Graunke [Wed, 8 Mar 2023 04:41:55 +0000 (20:41 -0800)]
intel/fs: Move packHalf2x16 handling to lower_pack()
This mainly lets the software scoreboarding pass correctly mark the
instructions, without needing to resort to fragile manual handling in
the generator.
We can also make small improvements. On Gfx 8LP-12.0, we no longer have
the restrictions about DWord alignment, so we can simply write each half
into its intended location, rather than writing it to the low DWord and
then shifting it in place.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21783>
Kenneth Graunke [Wed, 8 Mar 2023 04:51:19 +0000 (20:51 -0800)]
intel/fs: Use F32TO16/F16TO32 helpers in fquantize16 handling
I originally thought that we were intentionally emitting the legacy
opcodes here to make them opaque to the optimizer, so that it wouldn't
eliminate the explicit type conversions, as they're actually required
to do the quantization. But...we don't actually optimize those away
currently anyway. So...go ahead and use the helpers for consistency.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21783>
Kenneth Graunke [Thu, 9 Mar 2023 04:18:56 +0000 (20:18 -0800)]
Revert "intel/fs: Fix inferred_sync_pipe for F16TO32 opcodes"
With the previous patch, we no longer need to special case this, as we
emit a MOV with an HF source, rather than F16TO32 with an UW source,
on all platforms that need scoreboarding.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21783>
Kenneth Graunke [Wed, 8 Mar 2023 04:47:02 +0000 (20:47 -0800)]
intel/fs: Use new F16TO32 helpers for unpack_half_split_* opcodes
This gets us a MOV at the IR level on Gfx8+ which should be more
optimizable than F16TO32. It also removes confusion about which
pipe which the instruction will run on.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21783>
Kenneth Graunke [Wed, 8 Mar 2023 04:42:43 +0000 (20:42 -0800)]
intel/fs: Delete a TODO about using brw_F32TO16.
We can just use the new builder helpers to get the optimization
advantages of a MOV on Gfx8+ while also getting the necessary F32TO16
on Gfx7.x and yet not worry too hard about it.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21783>
Kenneth Graunke [Wed, 8 Mar 2023 04:40:11 +0000 (20:40 -0800)]
intel/fs: Add builder helpers for F32TO16/F16TO32 that work on Gfx7.x
These take care of emitting the F32TO16/F16TO32 instructions on Gfx7.x
but otherwise just emit a type converting MOV on Gfx8+.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21783>
Kenneth Graunke [Wed, 8 Mar 2023 10:29:06 +0000 (02:29 -0800)]
intel/fs: Fix inferred_sync_pipe for F16TO32 opcodes
For converting half-float to float, we currently emit BRW_OPCODE_F16TO32
with a UW source, to match legacy Gfx7 behavior. In the generator, this
becomes a MOV with a HF source on Gfx8+. Unfortunately, this UW source
confuses the scoreboarding pass into thinking it's an integer source,
leading to incorrect SWSB annotations on Alchemist.
We should ultimately fix the IR to stop being so...legacy...here, but
this is the simplest fix for stable branches.
Fixes misrendering in Elden Ring and likely Sekiro: Shadows Die Twice.
Cc: mesa-stable
Tested-by: Chuansheng Liu <chuansheng.liu@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
References: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8018
References: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8375
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21783>
Mark Janes [Tue, 7 Feb 2023 22:16:33 +0000 (14:16 -0800)]
intel: use generated workaround helpers for Wa_1409600907
Wa_1409600907 was enabled for gen12+. It should not be applied for
platforms after gen12.0. Use generated helpers to ensure application
to all relevant platforms.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21743>
Chia-I Wu [Wed, 8 Mar 2023 23:46:02 +0000 (15:46 -0800)]
radv: set RADEON_FLAG_GTT_WC for external mem on vram
We used to set RADEON_FLAG_GTT_WC when wsi_info is set. This changes it
to set the flag for any external mem on vram, extending the logic for
apps using external memory directly.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21803>
David Heidelberg [Sat, 4 Mar 2023 18:37:51 +0000 (19:37 +0100)]
ci/weston: add background PID
Needed for process tracking for LAVA.
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21711>
David Heidelberg [Sat, 4 Mar 2023 17:01:49 +0000 (18:01 +0100)]
ci/weston: before testing, verify that XWayland is really running
When Xorg already running, Weston XWayland should pick DISPLAY=:1
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21711>
David Heidelberg [Thu, 9 Mar 2023 11:36:25 +0000 (12:36 +0100)]
ci/lava: implement the priority
Before: kernelci 38; Mesa3D 75
Priority now:
- 38 ‒ kernelci
- 40 ‒ after merge and performance
- 50 ‒ user runs
- 75 ‒ marge-bot (MUST be prioritized)
Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21812>