nvir/gm107: Initialize SchedDataCalculatorGM107 member score.

Fix defect reported by Coverity Scan.

Uninitialized pointer field (UNINIT_CTOR)
uninit_member: Non-static class member score is not initialized in
this constructor nor in any functions that it calls.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7324>

freedreno/ir3: Fix crash in shader compile fail path

Fixes: 74140c2e859 ("freedreno/ir3: convert over to ralloc")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7612>

freedreno/ir3: Add pass to deal with load_uniform base offsets

With indirect load_uniform, we can only encode 10b of constant base
offset.  This pass detects problematic cases and peels out the high
bits of the base offset.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7612>

intel/blorp: Delete clear color conversions during copies

With the last commit, there are no more users of this code.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5388>

i965: Disable color fast-clears for miptree copy

During a blorp_copy between two color surfaces, the source and
destination formats are re-interpreted to UINT (if possible) to avoid
losing bits.

If either surface has CCS_E, then extra steps are taken to support
fast-cleared blocks with this format re-interpretation. Each clear value
is packed in the original format, then unpacked in the new UINT format.
This is then placed into the surface state object for some platforms.
There are couple problems here:

1. This is only being done for CCS_E, but MCS also supports fast-clears.

2. These steps aren't enough for fast-clears on gen11. On gen11, the
   clear color isn't part of the surface state object that BLORP
   creates. Instead it's stored in a separate BO, that the surface state
   object references. Since that BO doesn't get updated during
   blorp_copy, the incorrect/unconverted clear color is used for the copy
   operation.

I didn't measure any performance gain from this code, so this patch
simply disables the feature.

Makes i965 pass the nv_copy_image-simple piglit test on gen11.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5388>

iris: Disable color fast-clears in iris_copy_region

During a blorp_copy between two color surfaces, the source and
destination formats are re-interpreted to UINT (if possible) to avoid
losing bits.

If either surface has CCS_E, then extra steps are taken to support
fast-cleared blocks with this format re-interpretation. Each clear value
is packed in the original format, then unpacked in the new UINT format.
This is then placed into the surface state object for some platforms.
There are couple problems here:

1. This is only being done for CCS_E, but MCS also supports fast-clears.

2. These steps aren't enough for fast-clears on gen11+. On gen11+, the
   clear color isn't part of the surface state object that BLORP
   creates. Instead it's stored in a separate BO, that the surface state
   object references. Since that BO doesn't get updated during
   blorp_copy, the incorrect/unconverted clear color is used for the copy
   operation.

I didn't measure any performance gain from this code, so this patch
simply disables the feature.

Makes iris pass the nv_copy_image-simple piglit test on gen11+.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5388>

panfrost: Fix stack shift calculation

Fixes flickering in Neverwinter Nights.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3789
Fixes: e6152091ca9 ("panfrost: Use canonical characterization of tls_size")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7613>

panfrost: Fix out-of-bounds read on SFBD

Fixes glmark2 -bshadow, which uses a depth-only render target.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Robin Murphy <robin.murphy@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7557>

panfrost: Remove panfrost_can_linear

Always permit falling back to linear, now that linear Z/S is supported
on SFBD.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Robin Murphy <robin.murphy@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7557>

panfrost: Implement linear Z/S for SFBD

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Robin Murphy <robin.murphy@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7557>

iris: Use converted depth in clear_depth_stencil

Until recently, the depth value from glClearBufferfv wasn't clamped.

Before then, this patch enabled the driver to fail the clearbuffer-depth
piglit test with INTEL_DEBUG=nofc. This is because convert_depth_value
relies on the assumption that the depth value is clamped.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7410>

iris: Add and use convert_depth_value

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7410>

mesa: Clamp some depth values in glClearBufferfi

OpenGL 3.0 spec, section 4.2.3 "Clearing the Buffers":

   depth and stencil are the values to clear the depth and stencil
   buffers to, respectively. Clamping and type conversion for
   fixed-point depth buffers are performed in the same fashion as for
   ClearDepth.

Enables iris to pass the clearbuffer-depth-stencil piglit test.

Cc: mesa-stable
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7410>

mesa: Clamp some depth values in glClearBufferfv

OpenGL 3.0 spec, section 4.2.3 "Clearing the Buffers":

   If buffer is DEPTH, drawbuffer must be zero, and value points to the
   single depth value to clear the depth buffer to. Clamping and type
   conversion for fixed-point depth buffers are performed in the same
   fashion as for ClearDepth.

Enables iris to pass the clearbuffer-depth piglit test.

v2. Add spec citation. (Eric Anholt)
v3. Don't clamp floating point formats. (Eric Anholt)

Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7410>

mesa: Add and use _mesa_has_depth_float_channel

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7410>

nir: allow reordering of loads from read-only modes

fossil-db (Navi):
Totals from 710 (0.51% of 138917) affected shaders:
SGPRs: 45007 -> 44791 (-0.48%)
VGPRs: 36116 -> 36284 (+0.47%); split: -0.03%, +0.50%
CodeSize: 3811540 -> 3795332 (-0.43%); split: -0.43%, +0.00%
MaxWaves: 8018 -> 8005 (-0.16%)
Instrs: 758383 -> 755084 (-0.44%); split: -0.44%, +0.01%
Cycles: 5786240 -> 5758848 (-0.47%); split: -0.48%, +0.00%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7600>

nir: add nir_var_mem_ubo to nir_var_read_only_modes

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7600>

nir: add strength reduction pattern for imod/irem with pow2 divisor.

Affected games are Detroit : Become Human and Doom : Eternal.

Totals from 6262 (4.54% of 138013) affected shaders (RAVEN):
SGPRs: 678472 -> 678640 (+0.02%)
VGPRs: 498288 -> 498360 (+0.01%)
CodeSize: 67064196 -> 65926000 (-1.70%)
MaxWaves: 19390 -> 19382 (-0.04%)
Instrs: 13175372 -> 12932517 (-1.84%)
Cycles: 1444043256 -> 1443022576 (-0.07%); split: -0.08%, +0.01%
VMEM: 929560 -> 908726 (-2.24%); split: +0.39%, -2.63%
SMEM: 406207 -> 400062 (-1.51%); split: +0.46%, -1.97%
VClause: 215168 -> 215031 (-0.06%)
SClause: 443312 -> 442324 (-0.22%); split: -0.25%, +0.03%
Copies: 1350793 -> 1344326 (-0.48%); split: -0.52%, +0.04%
Branches: 506432 -> 506370 (-0.01%); split: -0.02%, +0.01%
PreSGPRs: 619652 -> 619619 (-0.01%)
PreVGPRs: 473212 -> 473168 (-0.01%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/175>

zink: update shader modules in gfx program when flagged dirty

for shader keys to work right, these need to actually update the shader
module that's being used

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7193>

zink: put those shader keys to work fixing up fragment shaders

eliminate gl_SampleMask writes when necessary to mimic GL behavior

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7193>

zink: fill in params for fs shader keys and flag shader for rebuild

we need to check for rebuild any time fb samples becomes 0 in order to remove
any writes to gl_SampleMask

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7193>

zink: move shader key structs into their own header

this is going to get messy as we fill them out, so at least we can
keep things split up a bit for organizational sake

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7193>

zink: refcount the shader cache

we want to be able to reuse this between programs with matching slot
maps, and refcounting allows that without having to copy the table

also add some docs about all the different shader caching structs

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7193>

zink: initial implementation of shader keys

these are cached per-program for now since we have to ensure that the slot map
always matches up between shader states

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7193>

pan/bi: Add support for tex offsets

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7530>

pan/bi: Allow lane selections on component 4 and above

The lane selection only cares about intra-32b swizzling. Add a modulo
on the test to allow selecting lanes when the swizzle is above 4 (needed
for MKVEC.v4i8 lane selection).

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7530>

pan/bi: Allow vec16 in bi_print_swizzle()

Ideally we should choose "abcd" instead of "xyzw" when accessing a
vector that has more than 4 components, but bi_instruction does not
provide this information, so let's keep things simple for now.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7530>

pan/bi: Add support for derivative instructions

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7530>

pan/bi: Add support for the CLPER instructions

Those are needed to implement derivatives.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7530>

pan/bi: Rename CLPER into CLPER_V7 and add CLPER_V6

The encoding is different between v6 and v7.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7530>

pan/bi: Expose FAU slots

Instead of adding a BIR_INDEX_ per FAU index, let's group some of those
together.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7530>

pan/bi: Store the architecture in the compiler context

Some instructions differ between v6 and v7 and we'll need to know which
architecture we're compiling for if we want to generate the right
instructions.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7530>

panfrost: Get rid of the Pixel Format descriptor

We use opaque uint to encode formats everywhere else, so let's make
things consistent and convert the only user to an opaque int too.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7530>

panfrost: Fix panfrost_format_to_bifrost_blend()

panfrost_format_to_bifrost_blend() shouldn't return a pipe_format, but
a mali_format.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7530>

pan/bi: Force BLEND src0 to r0

Blend shaders expect the input color to be passed through r0-r3, let's
enforce that when we allocate registers.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7530>

pan/bi: Extract shadowmap comparator

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7530>

aco/tests: add some more clamp combining tests

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7045>

aco/tests: expand optimize.const_comparison_ordering tests

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7045>

aco/tests: initialize debug function

aco_log() will print the message to stderr.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7045>

aco: disallow various v_add_u32 opts if modifiers are used

Check for clamp, SDWA or DPP. The optimization isn't possible with SDWA
and DPP, so it would have been skipped anyway. Doing any of these with a
clamp modifier present would be incorrect.

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7045>

aco: fix combine_constant_comparison_ordering() NaN check with 16/64-bit

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7045>

aco: don't combine precise max(min()) to med3

fossil-db (Navi):
Totals from 241 (0.18% of 137413) affected shaders:
CodeSize: 856280 -> 856308 (+0.00%); split: -0.00%, +0.00%
Instrs: 164220 -> 164514 (+0.18%); split: -0.00%, +0.18%
Cycles: 1031916 -> 1033092 (+0.11%); split: -0.00%, +0.11%
VMEM: 77855 -> 78514 (+0.85%); split: +0.85%, -0.01%
SMEM: 20501 -> 20593 (+0.45%); split: +0.46%, -0.01%
Copies: 9791 -> 9790 (-0.01%); split: -0.03%, +0.02%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7045>

radeonsi: remove AMD_DEBUG=zerovram flag

The same feature is available by using: radeonsi_zerovram=true

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7525>

radeonsi: remove unused NO_RB_PLUS flag

It's not used since https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/1751.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7525>

radv: add img debug flag

This is similar to AMD_DEBUG=tex, but for radv.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5734>

radeonsi: use ac_surface_print_info in si_print_texture_info

Pieces of information not printed by ac_surface_print_info are still
printed in si_print_texture_info.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5734>

amd/common: introduce ac_surface_print_info

This is mostly copied from si_print_texture_info, with the si-specific
bits removed. Moving it into common code will allow to use it from both
radeonsi and radv.

Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5734>

meson: verify that d3d12.h exists when building the d3d12 driver

Without this header-file, we can't build the driver. So let's verify
that it exists, and can be used by the C++ compiler.

This should make it a bit more clear what's wrong if someone attempts to
build this using MinGW or on Linux.

Fixes: 2ea15cd661c ("d3d12: introduce d3d12 gallium driver")
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7575>

microsoft/compiler: correct typo

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7578>

microsoft/compiler: inline some struct-declarations

We don't need to refer to these by name anywhere, so let's just inline
these for readability reasons.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7578>

microsoft/compiler: move c++ higher up

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7578>

microsoft/compiler: remove unused struct

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7578>

aco: optimize v_add(v_bcnt(a, 0), b) to v_bcnt(a, b)

The first operand of v_bcnt should always be a VGPR because if it's
a SGPR, isel selects s_bcnt1 but I added a sanity check to prevent
any problems.

fossils-db (Vega10):
Totals from 23 (0.02% of 139517) affected shaders:
CodeSize: 106828 -> 106664 (-0.15%)
Instrs: 20242 -> 20201 (-0.20%)
Cycles: 213112 -> 211352 (-0.83%)
VMEM: 3200 -> 3184 (-0.50%)
SMEM: 928 -> 927 (-0.11%)

Helps Control, Assassins Creeds Origins and Youngblood.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7568>

driconf: remove the redundant glx-extension-disabling options

Now that we introduced the generic glx_extension_override option,
we can remove the glx_disable_oml_sync_control,
glx_disable_sgi_video_sync, and glx_disable_ext_buffer_age ones.

It seems like the only user for them was the vmwgfx, and only for
Gnome and Compiz which are covered by the default mesa driconf. This
means that it is unlikely for a user to have these options set in
their local driconf file.

Suggested-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Martin Peres <martin.peres@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7252>

radeonsi: Add auxiliary plane support.

This adds support for multiple DRM planes for a single format plane
and uses that to enable DCC support with modifiers.

With the implicit flush patches we can also enable displayable DCC
both with and without DCC as the X server and compositors know not
to do frontbuffer rendering onto images with multiple DRM planes.

For now we require that the extra planes are essentially fixed though.
We require that the offset/stride are the same as ac_surface computes
and that all planes are in the same buffer. This is mainly for
simplicity and could be somewhat more relaxed in the future given
a strong usecase.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6176>

radeonsi: Do not try to disable displayable DCC with modifiers.

We do flushing on glFlush etc., so we don't need explicit flush,
but we still need to avoid frontbuffer rendering.

For modifiers there was logic put in apps that basically prevent
frontbuffer rendering if multipe planes are involved.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6176>

radeonsi: Do not disable DCC when we have it as a modifier.

Because other processes might be expecting DCC.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6176>

radeonsi: Add modifier support.

This adds basic modifier support in radeonsi.

Support for import/export of DCC comes in a later patch as that
needs support for multiple memory planes.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6176>

radeonsi: Check pitch and offset for validity.

And lack of overflows, which should help for security.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6176>

amd/common: Add modifier tests.

This primarily tests that:
 - multiple GPUs with the same GPU modifier parameters result
   in the same tiling layout.
 - The size & alignment calculations don't change for a given
   modifier & image parameters.

It does this primarily based on addrlib. Radeonsi has used addrlib
for the retiling of displayable DCC for a while already, so the
DCC tiling should be pretty reliable.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6176>

amd/common: Add support for modifiers.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6176>

drm-uapi: Add AMD modifiers.

This adds modifiers for GFX9+ AMD GPUs.

As the modifiers need a lot of parameters I split things out in
getters and setters.
  - Advantage: simplifies the code a lot
  - Disadvantage: Makes it harder to check that you're setting all
                  the required fields.

The tiling modes seem to change every generatio, but the structure
of what each tiling mode is good for stays really similar. As such
the core of the modifier is
 - the tiling mode
 - a version. Not explicitly a GPU generation, but splitting out
   a new set of tiling equations.

Sometimes one or two tiling modes stay the same and for those we
specify a canonical version.

Then we have a bunch of parameters on how the compression works.
Different HW units have different requirements for these and we
actually have some conflicts here.

e.g. the render backends need a specific alignment but the display
unit only works with unaligned compression surfaces. To work around
that we have a DCC_RETILE option where both an aligned and unaligned
compression surface are allocated and a writer has to sync the
aligned surface to the unaligned surface on handoff.

Finally there are some GPU parameters that participate in the tiling
equations. These are constant for each GPU on the rendering/texturing
side. The display unit is very flexible however and supports all
of them :|

Some estimates:
 - Single GPU, render+texture: ~10 modifiers
 - All possible configs in a gen, display: ~1000 modifiers
 - Configs of actually existing GPUs in a gen: ~100 modifiers

For formats with a single plane everything gets put in a separate
DRM plane. However, this doesn't fit for some YUV formats, so if
the format has >1 plane, we let the driver pack the surfaces into
1 DRM plane per format plane.

This way we avoid X11 rendering onto the frontbuffer with DCC, but
still fit into 4 DRM planes.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6176>

radeonsi: Add displayable DCC flushing without explicit flushes.

Flushes non-explicit shared textures that need retiling on

* glFlush
* glSync
* glSignalSemaphoreEXT
* DRI fences.
* The first time we create a non-explicit handle for it.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6176>

amd/addrlib: Use signed char for INT_8.

Some architectures like aarch64 and ppc64el have char = unisgned char.
This breaks meta equation generation for DCC coords, as addrlib tries
to filter all the Z bits > -1 which ends up being all the Z bits > 255.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7593>

radv: Do the sample check for tiling earlier.

The LINEAR optimization is not allowed for MSAA images.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7594>

turnip: Fix file descriptor return.

Fix defect reported by Coverity Scan.

Logically dead code (DEADCODE)
dead_error_line: Execution cannot reach the expression -1 inside this statement: return ret ? -1 : handle.fd;

Fixes: cec0bc73e55 ("turnip: rework fences to use syncobjs")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7498>

radeonsi: enable GL_EXT_demote_to_helper_invocation

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7586>

ac/llvm: fix demote inside conditional branches

The big comment explains it.

v2: don't kill if subgroup ops are used

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7586>

nir: optimize nir_lower_discard_to_demote to lower discard/demote both ways

This is smarter and also lowers demote to discard if helper invocations are
not needed.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7586>

nir: gather shader_info::needs_all_helper_invocations

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7586>

nir: rename needs_helper_invocations to needs_quad_helper_invocations

This indicates that only quad operations use helper invocations.
Also handle quad_swizzle_amd.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7586>

nir: optionally shuffle local invocation IDs for compute quad derivatives

Used by radeonsi. local_invocation_index is lowered only when quad
derivatives are enabled.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7586>

radeon: fix license in header

Incorrect license was added previously.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7561>

gallium/draw: Fix rasterizer_discard for wide points/lines.

Fixes the rasterizer_discard failures for softpipe, because the wide paths
(which we hit for points in the CTS) were dropping the discard state when
making the no_cull shadow state.

Cc: mesa-stable
Reviewed-by: Brian Paul <brianp@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7558>

mesa: Fix vertex_format_to_pipe_format index.

Corrects the index into the vertex_formats table for `integer` and
`normalized` values other than 0 or 1.

Fixes: e6448f993b1 ("mesa: translate into gallium vertex formats in mesa/main")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7554>

nir: handle float atomics in copy propagation pass

Without this patch, copy propagation pass can optimize out
buffer loads out of compare & swap loop, which then leads
to infinite loop.

Triggered by a change to atomicCompSwap float test in piglit.

Fixes: 8424cd8fbd1 ("nir: Account for atomics in copy propagation.")
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7538>

freedreno/drm: Add some locking asserts

Also fix evil-twin table_lock which they turned up.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7580>

radv/winsys: set has_dedicated_vram in the null winsys

NGG is disabled if this is false.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7577>

nir: Fix nir_validate fail after nir_lower_tex

It is UB to initialize unions on the stack and rely on bits not covered
by the initialized union member to be zero.  Lets just simplify it and
move the entire nir_const_value off the stack.

While we're in there, sprinkle around some const.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3778
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7579>

Add EGL xcb platform

This enables GL applications to be written without any involvement of
Xlib.

EGL X11 platform is actually already xcb-only underneath, so this commit
just add the necessary interface changes so eglDisplay can be created
from a xcb_connection_t.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Yuxuan Shui <yshuiv7@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6474>

anv: fix a build race between generating a header and using it

anv_batch_chain.c includes genX_bits.h but doesn't ensure it gets
generated first. This causes build failures, as observed here:
https://autobuilder.yoctoproject.org/typhoon/#/builders/86/builds/1501/steps/8/logs/step2d

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Alexander Kanavin <alex.kanavin@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7412>

d3d12: fix code after simple-shader helper changes

Fixes: 4e9328e3b6a ("nir_builder: Return a new builder from nir_builder_init_simple_shader().")
Fixes: 5f992802f51 ("nir/builder: Drop the mem_ctx arg from nir_builder_init_simple_shader().")
Fixes: eda3e4e055e ("nir/builder: Add a name format arg to nir_builder_init_simple_shader().")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7574>

zink: fix build on windows

guard the drm includes that are not available on this platform

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7432>

aco: optimize v_add_u32(v_mul_lo_u16) -> v_mad_u32_u16

fossils-db (Vega10):
Totals from 779 (0.56% of 139517) affected shaders:
CodeSize: 1187928 -> 1187508 (-0.04%); split: -0.04%, +0.00%
Instrs: 247353 -> 244608 (-1.11%); split: -1.11%, +0.00%
Cycles: 1127472 -> 1116420 (-0.98%); split: -0.98%, +0.00%
VMEM: 139720 -> 138297 (-1.02%); split: +0.00%, -1.02%
SMEM: 51069 -> 50735 (-0.65%); split: +0.04%, -0.69%
Copies: 11548 -> 11547 (-0.01%); split: -0.03%, +0.03%

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7425>

aco: select v_mul_lo_u16 for 16-bit multiplications that can't overflow

Only on GFX8-9 because GFX10 doesn't zero the upper 16 bits.

No fossils-db changes.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7425>

aco: select v_mad_u32_u16 for 16-bit multiplications on GFX9+

No fossils-db changes.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7425>

aco: optimize v_mad_u32_u16 with acc=0 to v_mul_u32_u24

v_mad_u32_u16 will be selected by isel to keep the range analysis
information around and to combine more v_add_u32+v_mad_u32_u16
together. When it's not possible to optimize that pattern, fallback
to v_mul_u32_u24 which is VOP2 instead of VOP3.

No fossils-db changes.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7425>

aco: add a new Operand flag to indicate that is 16-bit

To indicate that the upper 16-bits are always 0 and that optimizing
v_mad_u32_u16 to v_mul_u32_u24 is valid.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7425>

aco: introduce a generic label for labelling instructions

When one instruction doesn't fit into the existing labels, use
the generic one.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7425>

util/u_process: implement util_get_process_name for Windows

There's not yet any users of this function on Windows, but it prints a
warning during builds, and seems easy enough to implement. So let's add
a trivial implementation.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7548>

ci: sort packages installed via apt-get

Also remove duplicates.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7553>

v3dv: move authenticated display fd acquisition to swapchain creation time

So far, we have only been supporting X11, so we assumed that we were running
inside X11 and would always try to get an authenticated fd from Xorg during
device initialization. While this works for desktop Raspbian, it is not
really correct and it is not what we want to do when we start considering
other WSIs.

Initially, one could think we can still do this by guarding the WSI code
under the proper instance extension check. This, however, doesn't work
reliably, as the Vulkan loader can call vkEnumerateDevices without enabling
surface extensions on the instance, which then can lead to us not
initializing any display_fd and failing with VK_ERROR_INITIALIZATION_FAILED,
which is not correct, so while we can try to acquire the display_fd here,
it might not always work, and we should definitely not fail initialization
of the physical device for that.

Instead, with this change we move acquisition of display_fd to swapchain
creation time where required extensions need to be enabled in the instance.
This was also suggested by Daniel Stone during review of a work-in-progress
implementation for the Wayland WSI.

There is a special case to consider though: applications like Zink that
don't use Vulkan's swapchains at all but still allocate images that they
intend to use for WSI. We need to handle these by checking that we have
indeed acquired a display_fd before doing any memory allocation for WSI,
and acquiring one at that time if that's not the case.

This change also removes the render_fd and display_fd fields from the
logical device (which we were copying from the physical device), because
now there is no guarantee that we have acquired a display_fd at the
time we create a logical device. Instead, we now put a reference to the
physical device on the logical device from which we can access these.

Finally, this also fixes a regression introduced with VK_KHR_display, where
if that extension is enabled but we are running inside a compositor, we would
acquire a display_fd that is not authenticated and try to use that instead
of acquiring an authenticated display_fd from the display server.

Fixes: b1188c9451 (v3dv: VK_KHR_display extension support)

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7546>

v3dv: fix typo

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7546>

aco: combine more s_add+s_lshl to s_lshl<n>_add by ignoring uses

Even if the s_lshl is used more that once, it can still be combined.

fossils-db (Vega10):
Totals from 771 (0.55% of 139517) affected shaders:
SGPRs: 46216 -> 46304 (+0.19%); split: -0.02%, +0.21%
VGPRs: 38488 -> 38464 (-0.06%)
SpillSGPRs: 1894 -> 1875 (-1.00%); split: -3.12%, +2.11%
CodeSize: 5681856 -> 5679844 (-0.04%); split: -0.07%, +0.03%
MaxWaves: 5320 -> 5323 (+0.06%)
Instrs: 1093960 -> 1093474 (-0.04%); split: -0.09%, +0.05%
Cycles: 47198380 -> 47258872 (+0.13%); split: -0.06%, +0.19%
VMEM: 176036 -> 176283 (+0.14%); split: +0.16%, -0.02%
SMEM: 53397 -> 53255 (-0.27%); split: +0.03%, -0.30%
VClause: 23156 -> 23152 (-0.02%); split: -0.03%, +0.01%
SClause: 35716 -> 35726 (+0.03%); split: -0.00%, +0.03%
Copies: 139395 -> 139871 (+0.34%); split: -0.04%, +0.39%
Branches: 33808 -> 33798 (-0.03%); split: -0.04%, +0.01%
PreSGPRs: 35381 -> 35331 (-0.14%); split: -0.20%, +0.06%

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7539>

aco/tests: add some tests for combining s_add+s_lshl to s_lshl<n>_add

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7539>

prog_to_nir: Revert name initialization change

Commit eda3e4e055e240a14c6ad4bdbde544c6348fc01d moved the creation of
s->info.name to shader creation time, rather than after the compile.
A few lines after creating the shader, prog_to_nir clobbers s->info
entirely, losing the name.

This dropped the "ARB" indicator that iris uses to switch math to the
legacy non-IEEE mode used by ARB_vertex_program/fragment_program.

Revert that hunk and go back to doing things the way they were.

Fixes: eda3e4e055e ("nir/builder: Add a name format arg to nir_builder_init_simple_shader().")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3777
Acked-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7564>

intel/compiler: Fix passthrough TCS regressions from program rename

In commit eda3e4e055e240a14c6ad4bdbde544c6348fc01d, Eric added names
to various programs.  In that patch, he also renamed our passthrough
TCS shader from "passthrough" to "passthrough TCS".  The passthrough
TCS directly supplies the VUE headers rather than doing the whole
"patch parameters are in backwards order" reswizzling dance.

We failed to detect this and started trying to supply vec4s starting
at component 3, leading to a stack smash on an array of 7 sources,
not to mention the values were being put in the wrong place.

Easy fix: update the code for the new name.

Fixes: eda3e4e055e ("nir/builder: Add a name format arg to nir_builder_init_simple_shader().")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3777
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7564>

microsoft/compiler: Add dxil_nir_lower_16bit_conv prototype.

Fix missing-prototypes build error.

src/microsoft/compiler/dxil_nir_algebraic.c:5761:1: error: no previous prototype for ‘dxil_nir_lower_16bit_conv’ [-Werror=missing-prototypes]
 5761 | dxil_nir_lower_16bit_conv(nir_shader *shader)
      | ^~~~~~~~~~~~~~~~~~~~~~~~~

Fixes: b9c61379ab4 ("microsoft/compiler: translate nir to dxil")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7559>

glsl: Fix typos in comments.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7415>

glsl: Initialize ir_variable member field data.is_xfb.

Fix defect reported by Coverity Scan.

Uninitialized scalar field (UNINIT_CTOR)
uninit_member: Non-static class member field data.is_xfb is not
initialized in this constructor nor in any functions that it calls.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7414>