mesa: Add ARB_vertex_attrib_binding

update_array() and update_array_format() are changed to update the new
attrib and binding states, and the client arrays become derived state.

Reviewed-by: Eric Anholt <eric@anholt.net>

glapi: Add infrastructure for ARB_vertex_attrib_binding

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: Make handle_bind_buffer_gen() non-static

...and rename it to _mesa_bind_buffer_gen().

This is so the function can be called from _mesa_BindVertexBuffer().

This patch also adds a caller parameter so we can report the right
entry point in error messages.

Based on a patch by Eric Anholt.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: Rename gl_array_object::VertexAttrib to _VertexAttrib

This will become derived state as part of the ARB_vertex_attrib_binding
support.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: Split out the format code from update_array()

Split out the code for updating the array format into a new function
called update_array_format(). This function will be called by both
update_array() and the new glVertexAttrib*Format() entry points in
ARB_vertex_attrib_binding.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: Restore gl_array_object::NewArray

This will be used by the ARB_vertex_attrib_binding implementation.
This reverts commit db38e9a0e179441f59274f6f2a751912c29872e2.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965: Use has_surface_tile_offset in depth/stencil alignment workaround.

Currently, has_surface_tile_offset is equivalent to gen == 4 && !is_g4x.

We already use it for related checks in brw_wm_surface_state.c, so it
makes sense to use it here too.  It's simpler and more future-proof.

Broadwell also lacks surface tile offsets.  With this patch, I won't
need to update any generation checking; I can simply not set the flag.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

gallium: fix build on GNU/kFreeBSD

Patch from Debian package

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Andreas Boll <andreas.boll.dev@gmail.com>

configure.ac: fix build on GNU/kFreeBSD

Based on existing patch from Debian package.

Debian bug: http://bugs.debian.org/524690

Reviewed-by: Andreas Boll <andreas.boll.dev@gmail.com>

mesa: add arm64 support

Patch from Ubuntu package

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Andreas Boll <andreas.boll.dev@gmail.com>

r600/compute: silence unused var warning

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

i965/gen6: Don't allow SIMD16 dispatch in 4x PERPIXEL mode with computed depth.

Hardware docs say we can only use SIMD8 dispatch in this condition.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

configure.ac: Drop no-out-of-tree notice.

We do support out of tree builds now.

Tested-by: Colin Walters <walters@verbum.org>

mesa: Build program as part of libmesa.

mesa: Clean up use of top_srcdir/top_builddir.

i965: Use unreachable() to silence a compiler warning.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

mesa: Add unreachable() macro.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

gallivm: fix indirect addressing of inputs

We weren't adding the soa offsets when constructing the indices
for the gather functions. That meant that we were always returning
the data in the first element.
(Copied straight from the same fix for temps.)
While here fix up a couple of broken comments in the fetch functions,
plus don't name a straight float type float4 which is just confusing.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Zack Rusin <zackr@vmware.com>

r600/llvm: Fix isampleBuffer on preEG

r600/llvm: Fix texbuf for pre EG gen

mesa: for GLSL_DUMP_ON_ERROR, also dump the info log

Since it's helpful to know why the shader did not compile.
Also, call fflush() for Windows.

Reviewed-by: José Fonseca <jfonseca@vmware.com>

st/vdpau: resolve delayed rendering for GL interop v2

Otherwise OutputSurface interop has funny results sometimes.
This fixes interop with the mpv media player.

v2 (chk): add proper locking

Signed-off-by: Christian König <christian.koenig@amd.com>

docs: Mark off ARB_sample_shading; minor tidyup.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>

i965/fs: Gen4-5: Implement alpha test in shader for MRT

V2: Add comment explaining what emit_alpha_test() is for;
    fix spurious temp and bogus whitespace.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965/fs: Gen4-5: Setup discard masks for MRT alpha test

The same setup is required here as when the user-provided shader
explicitly uses KIL or discard.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Gen4-5: Include alpha func/ref in program key

V2: Better explanation of the rationale for doing this.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Gen4-5: Don't enable hardware alpha test with MRT

We have to do this in the shader instead, since these gens lack an
independent RT0 alpha value in their render target write messages.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Combine {brw,gen7}_update_texture_buffer_surface() functions.

Now that brw_update_texture_buffer_surface() uses the virtual
emit_buffer_surface_state() function, it works for Gen7+ too.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>

i965: Unvirtualize brw_create_constant_surface; delete Gen7+ variant.

Now that brw_create_constant_surface uses a virtual function internally,
it doesn't need to be virtual itself.  We can delete the Gen7+ variant
and simplify things.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>

i965: Use the new emit_buffer_surface_state() vtable entry.

This will allow us to combine the Gen4-6 and Gen7 variants of these
functions.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>

i965: Virtualize emit_buffer_surface_state().

This entails adding "mocs" and "rw" parameters to the Gen4-5 version.
I made it actually pay attention to the rw flag (even though it is
always false), but mocs is always ignored.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>

i965: Fix compiler warning.

fix: intel_screen.c:1320:4: warning: initialization from
incompatible pointer type [enabled by default]

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Tell the unit states how many binding table entries we have.

Before the series with 3c9dc2d31b80fc73bffa1f40a91443a53229c8e2 to
dynamically assign our binding table indices, we didn't really track our
binding table count per shader, so we never filled in these fields.

Affects cairo-gl trace runtime by -2.47953% +/- 1.07281% (n=20)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Fix context initialization after 2f896627175384fd5

You can't return stack-initialized values and expect anything good to
happen.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com
Reviewed-by: Matt Turner <mattst88@gmail.com>

gallivm: optimize lp_build_minify for sse

SSE can't handle true vector shifts (with variable shift count),
so llvm is turning them into a mess of extracts, scalar shifts and inserts.
It is however possible to emulate them in lp_build_minify with float muls,
which should be way faster (saves over 20 instructions per 8-wide
lp_build_minify). This wouldn't work for "generic" 32bit shifts though
since we've got only 24bits of mantissa (actually for left shifts it would
work by using sse41 int mul instead of float mul but not for right shifts).
Note that this has very limited scope for now, since this is only used with
per-pixel lod (otherwise we're avoiding the non-constant shift count by doing
per-quad shifts manually), and only 1d textures even then (though the latter
should change).

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

nouveau: Use _NEW_SCISSOR instead of hooking through dd_function_table

This will enable removing the dd_function_table::Scissor hook in the
near future.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

nouveau: Use _NEW_VIEWPORT instead of hooking through dd_function_table

This will enable removing the dd_function_table::DepthRange hook in the
near future.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

radeon / r200: Don't pass unused parameters to radeon_viewport

The x, y, width, and height parameters aren't used by radeon_viewport,
so don't pass them.  This should make future changes to the
dd_function_table::Viewport interface a little easier.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jordan Justen <jljusten@gmail.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Cc: Courtney Goeltzenleuchter <courtney@lunarg.com>

i915: Bring sanity to the Viewport function

The i830 and the i915 driver have the same dd_function_table::Viewport
function... it just has two names and lives in two places.  Using a
single implementation allows cleaning up the saved_viewport nonsense
too.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jordan Justen <jljusten@gmail.com>
Cc: Courtney Goeltzenleuchter <courtney@lunarg.com>

i965: Eliminate the saved_viewport wrapper

The i965 driver never installed a dd_function_table::Viewport function,
so this wrapper never actually did anything.

No piglit regressions on IVB on DRI2.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jordan Justen <jljusten@gmail.com>
Cc: Courtney Goeltzenleuchter <courtney@lunarg.com>

mesa: Remove last BEOS checks

* Goodbye BeOS, we hardly knew thee
* As BeOS was gcc2 only, there was little chance
  of this being useful.
* Doesn't effect Haiku in any meaningful way

Reviewed-by: Brian Paul <brianp@vmware.com>

util/u_format: take normalized flag in consideration in util_format_is_rgba8_variant

Just happened to notice it was missing while looking at it.

glsl: Don't generate misleading debug names when packing gs inputs.

Previously, when packing geometry shader input varyings like this:

    in float foo[3];
    in float bar[3];

lower_packed_varyings would declare a packed varying like this:

    (declare (shader_in flat) (array ivec4 3) packed:foo[0],bar[0])

That's confusing, since the packed varying acutally stores all three
values of foo and all three values of bar.

This patch causes it to generate the more sensible declaration:

    (declare (shader_in flat) (array ivec4 3) packed:foo,bar)

Note that there should be no functional change for users of geometry
shaders, since the packed name is only used for generating debug
output.  But this should reduce confusion when using INTEL_DEBUG=gs.

Reviewed-by: Eric Anholt <eric@anholt.net>

gallivm: Remove llvm::DisablePrettyStackTrace for LLVM >= 3.4.

LLVM 3.4 r193971 removed llvm::DisablePrettyStackTrace and made the
pretty stack trace opt-in rather than opt-out.

The default value of DisablePrettyStackTrace has changed to true in LLVM
3.4 and newer.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60929
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

target/haiku-softpipe: Fix viewport issues

* Call mesa viewport call on winndow resize
* Add initial postprocessing code
* Pass hgl_context to private statetracker
  as it is more useful than GalliumContext
* Use Lock and Unlock functions to standardize
  GalliumContext locking
* Create texture resources in texture validation

Acked-by: Brian Paul <brianp@vmware.com>

mesa: remove __alpha__ && CCPML check

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: remove OPENSTEP stuff

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: remove macintosh preprocessor stuff

IIRC, this is MacOS 9.x stuff.

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: remove __QUICKDRAW__ tests

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: remove WGLAPI macro

WGLAPI was defined in glheader.h but wasn't used anywhere.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Expose brw_reg_from_fs_reg() to other files.

This will be useful for Broadwell code as well.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Combine gen6_clip_state.c and gen7_clip_state.c.

The changes between Gen6-7 are minimal, and can easily be solved with
an extra generation check.  This cuts a lot of duplicated code.

It also helps prevent even more duplication for Broadwell.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

dri/nouveau: Fix nouveau_init_screen2 breakage.

Fix incorrect init ordering in nouveau_init_screen2 caused by
083f66fdd6451648fe355b64b02b29a6a4389f0d.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71172

i965/gen7: Add instruction latency estimates for untyped atomics and reads.

The latency information has been obtained empirically from
measurements taken on Haswell and Ivy Bridge.

Acked-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/gen7: Handle atomic instructions from the VEC4 back-end.

This can deal with all the 15 32-bit untyped atomic operations the
hardware supports, but only INC and PREDEC are going to be exposed
through the API for now.

v2: Represent atomics as GLSL intrinsics.  Add support for variably
    indexed atomic counter arrays.
v3: Add comment on why we don't need to assign uniform storage for
    atomic counters.

Reviewed-by: Paul Berry <stereotype441@gmail.com>

i965/gen7: Handle atomic instructions from the FS back-end.

This can deal with all the 15 32-bit untyped atomic operations the
hardware supports, but only INC and PREDEC are going to be exposed
through the API for now.

v2: Represent atomics as GLSL intrinsics.  Add support for variably
    indexed atomic counter arrays.  Fix interaction with fragment
    discard.
v3: Add comment on why we don't need to assign uniform storage for
    atomic counters.

Reviewed-by: Paul Berry <stereotype441@gmail.com>

i965: Add a 'has_side_effects' back-end instruction predicate.

This patch fixes the three dead code elimination passes and the
VEC4/FS instruction scheduling passes so they leave instructions with
side effects alone.

At some point it might be interesting to have the instruction
scheduler calculate the exact memory dependencies between atomic ops,
but they're rare enough that it seems unlikely that it will make any
practical difference.

Reviewed-by: Paul Berry <stereotype441@gmail.com>

clover: Calculate optimal work group size when it's not specified by the user.

Inspired by a patch sent to the mailing list by Tom Stellard, but
using a different algorithm to calculate the optimal block size that
has been found to be considerably more effective.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

clover: Constify some command_queue arguments.

clover: Workaround compiler bug present in GCC 4.7.0-4.7.2.

Variadic template aliases make these versions of GCC very confused,
write down the full type spec instead.

st/xorg: handle updates to DamageUnregister API

xserver 1.14.99.2 simplified the DamageUnregister API, by
dropping the drawable argument.
Follow xf86-video-intel and xf86-video-vmware approach and
handle the new API by checking XORG_VERSION_CURRENT.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71110
Reported-by: Michał Górny <mgorny@gentoo.org>
Reported-by: Vinson Lee <vlee@freedesktop.org>
Tested-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

mesa: remove Watcom C support

Reviewed-by: Eric Anholt <eric@anholt.net>

mesa: remove Centerline C support from gl.h

Reviewed-by: Eric Anholt <eric@anholt.net>

mesa: remove BUILD_FOR_SNAP bits

Reviewed-by: Eric Anholt <eric@anholt.net>

mesa: remove SciTech stuff from gl.h

Reviewed-by: Eric Anholt <eric@anholt.net>

r600g: properly unbind a DSA state being deleted in r600_delete_dsa_state

Tested-by: Christian König <christian.koenig@amd.com>

docs/GL3: document radeonsi support, minor cleanup

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

radeonsi: implement ARB_vertex_type_2_10_10_10_rev

r600g,radeonsi: properly expose texture buffer formats

This exposes GL_ARB_texture_buffer_object_rgb32.

radeonsi: implement texture buffer objects

GLSL 1.40 is done.

radeonsi: report our border color behavior

radeonsi: bind a dummy constant buffer in place of NULL buffers

radeonsi: implement uniform buffer objects

tgsi/scan: set maximum index for each constant buffer

radeonsi: try to fix IA_MULTI_VGT_PARAM programming

This doesn't make any difference on Bonaire, but it might help on Hawaii.

winsys/radeon: use type-3 NOPs for CS padding on CIK

The type-2 NOPs are said to be unstable. It doesn't make a difference here.

clover: fix build with LLVM 3.4

dso_list was added as an argument for createInternalizePass in 3.4, and then
it was removed again in the same llvm version.

Tested-by: Mike Lothian <mike@fireburn.co.uk>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

draw: move type construction out of loop

We can create clip_ptr_type once instead of n times inside the loop.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

i965: Add driconf option clamp_max_samples

The new option clamps GL_MAX_SAMPLES to a hardware-supported MSAA mode.
If negative, then no clamping occurs.

v2: (for Paul)
  - Add option to i965 only, not to all DRI drivers.
  - Do not realy on int->uint cast to convert negative
    values to large positive values. Explicitly check for
    clamp_max_samples < 0.
v3: (for Ken)
   - Don't allow clamp_max_samples to alter context version.
   - Use clearer for-loop and correct comment.
   - Rename variables.
v4: (for Ken)
   - Merge identical if-branches.

Reviewed-and-tested-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>

i965: Fix logic_op check.

Fixes "Macro compares unsigned to 0" defect reported by Coverity.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i915: Fix logic_op check.

Fixes "Macro compares unsigned to 0" defect reported by Coverity.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965: Initialize vec4_visitor member variables.

Fixes "Uninitialized pointer field" defect reported by Coverity.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>

gallium/targets: remove vdpau-softpipe

Reviewed-by: Christian König <christian.koenig@amd.com>

gallium/targets: remove xvmc-softpipe

Reviewed-by: Christian König <christian.koenig@amd.com>

gallium/targets: remove r300/vdpau

Reviewed-by: Christian König <christian.koenig@amd.com>

gallium/targets: remove r300/xvmc

Reviewed-by: Christian König <christian.koenig@amd.com>

gallium/targets: remove radeonsi/xorg

Reviewed-by: Christian König <christian.koenig@amd.com>

gallium/targets: remove r600/xorg

Reviewed-by: Christian König <christian.koenig@amd.com>

freedreno/a3xx/texture: min/max lod

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/a3xx: update envytools headers

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/a3xx: fix VS out / FS in linking

Actually link VS out / FS in based on semantic info, keeping in mind
that position/pointsize can also be an input to the FS.  This fixes a
few fragment shaders which were using gl_Position.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/a3xx: allow num_samplers != num_textures

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/a3xx/compiler: highp frag shader

Fixes use of full-precision in fragment shader (ie. don't clobber r0.x
since that can be used by future bary instructions for varying fetch).
And makes use of full-precision the default in fragment shader (but can
be overriden via FD_MESA_DEBUG=fraghalf).

Seems like half precision is often not enough for texture coordinates.
The blob compiler is clever enough to keep texture coords in full
precision registers while using half precision for everything else.  But
we aren't quite that clever yet, so better to default to full precision.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/a3xx/compiler: relative addressing fixes.

Handle some relative addressing constraints: cannot handle const or
relative in cat5 and src2 of cat3.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno: we do actually support sqrt

Signed-off-by: Rob Clark <robclark@freedesktop.org>

i965: Enable ARB_sample_shading on intel hardware >= gen6

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Ken Graunke <kenneth@whitecape.org>

i965/gen7: Enable the features required for GL_ARB_sample_shading

- Enable GEN7_WM_MSDISPMODE_PERSAMPLE, GEN7_WM_POSOFFSET_SAMPLE,
  GEN7_WM_OMASK_TO_RENDER_TARGET as per extension's specification.
- Only enable one of GEN7_WM_8_DISPATCH_ENABLE or GEN7_WM_16_DISPATCH_ENABLE
  when GEN7_WM_MSDISPMODE_PERSAMPLE is enabled. Refer IVB PRM Vol. 2, Part 1,
  Page 288 for details.

V2:
    - Use shared function _mesa_get_min_invocations_per_fragment().
    - Use brw_wm_prog_data variables: uses_pos_offset, uses_omask.

V3:
    - Enable simd16 dispatch with per sample shading.
    - Make changes to give preference to 'simd16 only' mode over
      'simd8 only' mode in case of non 1x per sample shading.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>

i965/gen6: Enable the features required for GL_ARB_sample_shading

- Enable GEN6_WM_MSDISPMODE_PERSAMPLE, GEN6_WM_POSOFFSET_SAMPLE,
  GEN6_WM_OMASK_TO_RENDER_TARGET as per extension's specification.
- Only enable one of GEN6_WM_8_DISPATCH_ENABLE or GEN6_WM_16_DISPATCH_ENABLE
  when GEN6_WM_MSDISPMODE_PERSAMPLE is enabled.
  Refer SNB PRM Vol. 2, Part 1, Page 279 for details.

V2:
    - Use shared function _mesa_get_min_invocations_per_fragment().
    - Use brw_wm_prog_data variables: uses_pos_offset, uses_omask.

V3:
    - Enable simd16 dispatch with per sample shading.
    - Make changes to give preference to 'simd16 only' mode over
      'simd8 only' mode in case of non 1x per sample shading.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>

i965: Add FS backend for builtin gl_SampleMask[]

V2:
   - Update comments
   - Add a special backend instructions to compute sample_mask.
   - Add a new variable uses_omask in brw_wm_prog_data.

V3:
   - Make changes to support simd16 mode.
   - Delete redundant AND instruction and handle the register
     stride in FS backend instruction.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>

i965: Add FS backend for builtin gl_SampleID

V2:
   - Update comments
   - Add compute_sample_id variables in brw_wm_prog_key
   - Add a special backend instruction to compute sample_id.

V3:
   - Make changes to support simd16 mode.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>