Dave Airlie [Thu, 5 Feb 2015 10:52:19 +0000 (12:52 +0200)]
glsl/ir: Add printing support for doubles
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Dave Airlie [Thu, 5 Feb 2015 09:50:43 +0000 (11:50 +0200)]
glsl/ir: Add builtin function support for doubles
v2: add d2b, more ir_constant stuff (Ilia)
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Tue, 10 Feb 2015 08:02:09 +0000 (03:02 -0500)]
glsl: fix uniform linking logic in the presence of structs
Add a enter/leave record callback so that the offset may be aligned to
the proper value. Otherwise only leaf fields are called, and the first
field needs to be aligned to the outer struct's base alignment while the
last field needs to be aligned to the inner struct's base alignment.
This removes most usage of the last field/record type values passed into
visit_field.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Ilia Mirkin [Sat, 14 Feb 2015 03:03:47 +0000 (22:03 -0500)]
glsl: teach std140_base_alignment about samplers
These functions are about to be used more aggressively for determining
uniform layout. Samplers may be inside of structs, and it's easier to
reuse the existing base alignment logic.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 5 Feb 2015 09:44:02 +0000 (11:44 +0200)]
glsl: Uniform linking support for doubles
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Dave Airlie [Thu, 5 Feb 2015 09:38:44 +0000 (11:38 +0200)]
glsl: Add double builtin type generation
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Dave Airlie [Wed, 11 Jun 2014 03:36:12 +0000 (13:36 +1000)]
glsl: add ARB_gpu_shader_fp64 to the glsl extensions. (v2)
v2: add define bit (Tapani Pälli)
Patch makes following Piglit tests pass:
arb_gpu_shader_fp64/preprocessor/define.vert
arb_gpu_shader_fp64/preprocessor/define.frag
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Dave Airlie [Wed, 11 Jun 2014 03:28:32 +0000 (13:28 +1000)]
mesa: add double uniform support. (v5)
This adds support for the new uniform interfaces
from ARB_gpu_shader_fp64.
v2:
support ARB_separate_shader_objects ProgramUniform*d* (Ian)
don't allow boolean uniforms to be updated (issue 15) (Ian)
v3: fix size_mul
v4: Teach uniform update to take into account double precision (Topi)
v5: add transpose for double case (Ilia)
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Dave Airlie [Sun, 8 Feb 2015 00:24:48 +0000 (19:24 -0500)]
glsl: Add double builtin type
This causes a lot of warnings about unchecked type in
switch statements - fix them later.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Dave Airlie [Wed, 11 Jun 2014 03:27:22 +0000 (13:27 +1000)]
mesa: add ARB_gpu_shader_fp64 extension info (v2)
This just adds the entries to extensions.c and mtypes.h
v2: use core profile only (Ian)
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Dave Airlie [Wed, 11 Jun 2014 03:17:36 +0000 (13:17 +1000)]
glapi: add ARB_gpu_shader_fp64 (v2)
Just add the xml file covering this extension,
and dummy interface files in mesa, and fix up
sanity tests.
v2:
Enable ProgramUniform*d* from ARB_separate_shader_objects (Ian)
use 40 instead of 43 for dispatch_sanity.cpp (Chris)
uncomment PU sanity tests.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Thu, 19 Feb 2015 03:36:13 +0000 (22:36 -0500)]
freedreno: add missing PIPE_CAP_RESOURCE_FROM_USER_MEMORY to switch
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Tue, 2 Dec 2014 05:32:57 +0000 (00:32 -0500)]
freedreno/a3xx: add ARB_instanced_arrays support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Thu, 2 Oct 2014 03:13:22 +0000 (23:13 -0400)]
freedreno/a3xx: add support for vertexid and instanceid sysvals
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Wed, 22 Oct 2014 04:42:04 +0000 (00:42 -0400)]
freedreno: pass number of instances to draw
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Mon, 16 Feb 2015 07:28:50 +0000 (02:28 -0500)]
freedreno/a3xx: add ETC2 decoding support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Mon, 16 Feb 2015 07:27:37 +0000 (02:27 -0500)]
st/mesa: pass etc2 textures to driver if supported
If the driver actually supports ETC2, don't decode it in software.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Ilia Mirkin [Thu, 19 Feb 2015 03:23:12 +0000 (22:23 -0500)]
llvmpipe,softpipe: only support ETC1, not the upcoming ETC2
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Mon, 16 Feb 2015 07:25:52 +0000 (02:25 -0500)]
gallium: add ETC2 format support
No actual decoding is added, similar faking mechanism to bptc.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Ilia Mirkin [Mon, 16 Feb 2015 06:33:11 +0000 (01:33 -0500)]
freedreno/a3xx: add hardware ETC1 support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Eric Anholt [Wed, 11 Feb 2015 22:40:47 +0000 (14:40 -0800)]
gallium/dri: Shut up a compiler warning.
The compiler doesn't see that buffers is set in the !image case and used
in the !image case.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Eric Anholt [Fri, 30 Jan 2015 22:10:58 +0000 (14:10 -0800)]
nir: Recognize and reduce duplicated fsats.
No effect on vc4 shader-db.
v2: Rebase to master (no TGSI->NIR present)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
Eric Anholt [Fri, 30 Jan 2015 21:53:39 +0000 (13:53 -0800)]
nir: Add a flag for lowering fsat.
vc4 cse/algebraic-disabled stats:
total instructions in shared programs: 44356 -> 44354 (-0.00%)
instructions in affected programs: 55 -> 53 (-3.64%)
v2: Rebase to master (no TGSI->NIR present)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
Eric Anholt [Fri, 30 Jan 2015 21:49:48 +0000 (13:49 -0800)]
nir: Add a flag for lowering ffma.
vc4 cse/algebraic-disabled stats:
total uniforms in shared programs: 13966 -> 13791 (-1.25%)
uniforms in affected programs: 435 -> 260 (-40.23%)
total instructions in shared programs: 44732 -> 44356 (-0.84%)
instructions in affected programs: 9599 -> 9223 (-3.92%)
v2: Rebase to master (no TGSI->NIR present)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
Eric Anholt [Wed, 28 Jan 2015 18:52:53 +0000 (10:52 -0800)]
nir: Add a flag for lowering fneg/ineg.
vc4 cse/algebraic-disabled stats:
total instructions in shared programs: 44911 -> 44732 (-0.40%)
instructions in affected programs: 11371 -> 11192 (-1.57%)
v2: Fix broken iabs(isub(0, a)) transformation.
v3: Rebase to master (no TGSI->NIR present)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
Eric Anholt [Wed, 28 Jan 2015 18:39:29 +0000 (10:39 -0800)]
nir: Add a flag for lowering fsqrt(x) to frcp(frsqrt(x)).
vc4 cse/algebraic-disabled stats:
total uniforms in shared programs: 13972 -> 13966 (-0.04%)
uniforms in affected programs: 408 -> 402 (-1.47%)
total instructions in shared programs: 44973 -> 44911 (-0.14%)
instructions in affected programs: 1551 -> 1489 (-4.00%)
v2: Rebase to master (no TGSI->NIR present)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
Eric Anholt [Wed, 28 Jan 2015 18:32:57 +0000 (10:32 -0800)]
nir: Add lowering of POW instructions if the lower flag is set.
This could be done in a separate pass like we do in GLSL IR, but it seems
to me like having the definitions of the transformations in the two
directions next to each other makes a lot of sense.
v2: Reorder the comment about the transformation.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Wed, 28 Jan 2015 00:22:54 +0000 (16:22 -0800)]
nir: Conditionalize the POW reconstruction on shader compiler options.
Mesa has a shader compiler struct flagging whether GLSL IR's opt_algebraic
and other passes should try and generate certain types of opcodes or
patterns. Extend that to NIR by defining our own struct, which is
automatically generated from the Mesa struct in glsl_to_nir and provided
directly by the driver in TGSI-to-NIR.
v2: Split out the previous two prep patches.
v3: Rebase to master (no TGSI->NIR present)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v2)
Eric Anholt [Tue, 3 Feb 2015 00:20:06 +0000 (16:20 -0800)]
nir: Add an optional expression controlling nir_algebraic xforms.
This will be used so that we can customize the transforms for the target
GPU, so we don't un-lower expressions that had already been lowered (or
introduce new lowering transformations that not all GPUs want)
v2: Drop the complication of having the condition->index dictionary, since
we don't actually expect there to be many different conditions (change
by Kenneth).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Tue, 3 Feb 2015 00:13:49 +0000 (16:13 -0800)]
nir: Add a nir_shader_compiler_options struct pointed to by the shaders.
This will be used to give the optimization passes a chance to customize
behavior for the particular target device.
v2: Rebase to master (no TGSI->NIR present)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
Jordan Justen [Tue, 17 Feb 2015 17:57:35 +0000 (09:57 -0800)]
i965/simd8vs: Fix SIMD8 atomics (read-only)
An update for
d9cd982d556be560af3bcbcdaf62b6b93eb934a5.
A similar change was needed for CS to allow the piglit test
tests/spec/arb_compute_shader/execution/simple-barrier-atomics.shader_test
to pass.
The previous change (
d9cd982d) should fix cases that write atomics,
such as atomicCounterIncrement, and this change will fix cases than
only read atomics, such as atomicCounter.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Chia-I Wu [Wed, 18 Feb 2015 20:26:29 +0000 (13:26 -0700)]
ilo: fix PCB alloc asserts on Gen7.5 GT3
GT3 has two slices and all limits are doubled.
Chia-I Wu [Tue, 17 Feb 2015 23:10:10 +0000 (16:10 -0700)]
ilo: fix compiler warnings
Fix -Wmaybe-uninitialized warnings. The change to
ilo_blit_resolve_slices_for_hiz() is a potential bug fix.
Adam Jackson [Wed, 28 Jan 2015 21:28:12 +0000 (16:28 -0500)]
i915: For the love of all that is holy, stop saying "IGD"
a001 and a011 are pineview chips. Say so.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Adam Jackson <ajax@redhat.com>
Emil Velikov [Mon, 16 Feb 2015 19:11:33 +0000 (19:11 +0000)]
auxiliary/vl: honour the DRI2PROTO_CFLAGS
Otherwise for non-default installations the build will fail to find the
headers and error out.
Cc: "10.5" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Mon, 16 Feb 2015 18:22:16 +0000 (18:22 +0000)]
auxiliary/vl: Build vl_winsys_dri.c only when needed.
With commit
c39dbfdd0f7(auxiliary/vl: bring back the VL code for the dri
targets) we did not fully consider users of dri-swrast alone. Thus we
ended up trying to compile the dri2 specific code on platform which lack
it - Cygwin for example.
Cc: "10.5" <mesa-stable@lists.freedesktop.org>
Reported-by: Jon TURNEY <jon.turney@dronecode.org.uk>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Jon TURNEY <jon.turney@dronecode.org.uk>
Emil Velikov [Thu, 12 Feb 2015 15:27:28 +0000 (15:27 +0000)]
automake: Use AM_DISTCHECK_CONFIGURE_FLAGS
Currently we use DISTCHECK_CONFIGURE_FLAGS, which is reserved for
the user. As with other variables, one should use the AM_ variable
within the makefile.
Cc: "10.5" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Emil Velikov [Thu, 22 Jan 2015 17:35:40 +0000 (17:35 +0000)]
glx: do not leak the dri2 extension information
The XExtensionInfo is allocated dynamically (if the pointer is NULL)
in the XEXT_GENERATE_FIND_DISPLAY macro. On the other hand the
macro XEXT_GENERATE_CLOSE_DISPLAY does not check/free the memory.
Follow the example set by dri1 and appledri, and use a static variable.
Spotted while hunting "still reachable" leaks in Waffle.
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Michel Dänzer [Tue, 17 Feb 2015 08:03:35 +0000 (17:03 +0900)]
Revert "radeon/llvm: enable unsafe math for graphics shaders"
This reverts commit
0e9cdedd2e3943bdb7f3543a3508b883b167e427.
It caused the grass to disappear in The Talos Principle.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89069
Cc: "10.5 10.4" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Ilia Mirkin [Wed, 11 Feb 2015 05:36:47 +0000 (00:36 -0500)]
st/mesa: add ARB_pipeline_statistics_query support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Ben Widawsky [Wed, 3 Dec 2014 02:33:12 +0000 (18:33 -0800)]
i965: implement ARB_pipeline_statistics_query
NOTE: The implementation was initially one patch, this. All the history is kept
here, even though all the core mesa changes were moved to the parent of this
patch.
This patch implements ARB_pipeline_statistics_query. This addition to GL does
not add a new API. Instead, it adds new tokens to the existing query APIs. The
work to hook up the new tokens is trivial due to it's similarity to the previous
work done for the query APIs. I've implemented all the new tokens to some
degree, but have stubbed out the untested ones at the entry point for Begin().
Doing this should allow the remainder of the code to be left in.
The new tokens give GL clients a way to obtain stats about the GL pipeline.
Generally, you get the number of things going in, invocations, and number of
things coming out, primitives, of the various stages. There are two immediate
uses for this, performance information, and debugging various types of
misrendering. I doubt one can use these for debugging very complex applications,
but for piglit tests, it should be quite useful.
Tessellation shaders, and compute shaders are not addressed in this patch
because there is no upstream implementation. I've implemented how I believe
tessellation shader stats will work for Intel hardware (though there is a bit of
ambiguity). Compute shaders are a bit more interesting though, and I don't yet
know what we'll do there.
For the lazy, here is a link to the relevant part of the spec:
https://www.opengl.org/registry/specs/ARB/pipeline_statistics_query.txt
Running the piglit tests
http://lists.freedesktop.org/archives/piglit/2014-November/013321.html
(http://cgit.freedesktop.org/~bwidawsk/piglit/log/?h=pipe_stats)
yield the following results:
> piglit-run.py -t stats tests/all.py output/pipeline_stats
> [5/5] pass: 5 Running Test(s): 5
v2:
- Don't allow pipeline_stats to be per stream (Ilia). This may (not sure) be
needed for AMD_transform_feedback4, which we do not support.
> If AMD_transform_feedback4 is supported then GEOMETRY_SHADER_PRIMITIVES_-
> EMITTED_ARB counts primitives emitted to any of the vertex streams for
> which STREAM_RASTERIZATION_AMD is enabled.
- Remove comment from GL3.txt because it is only used for extensions that are
part of required versions (Ilia)
- Move the new tokens to a new XML doc instead of using the main GL4x.xml (Ilia)
- Add a fallthrough comment (Ilia)
- Only divide PS invocations by 4 on HSW+ (Ben)
v3:
- Add ARB_pipeline_statistics_query to relnotes.html
- Add ARB_pipeline_statistics_query.xml to the Makefile.am, and master XML (Ilia)
- Correct extension number (Ilia)
- Add link to xml in the main GL API xml (Ilia)
- remove special GS case from gen6_end_query (Ian)
- Make lookup table static so gcc doesn't initialized it on every call (Ian)
- Use if (_mesa_has_geometry_shaders(ctx)) instead of explicit checks (Ian)
- Core mesa parts moved into a prep patch (Ilia)
v4:
- Change to 10.6 relnotes since we missed 10.5 window
- Moved compute shader stuff into the switch statement (Jordan)
- Jordan: Add compute shader support
v5:
- Fixed relnote style (Ilia)
v6:
- Rebased on master which beat me to adding the first relnotes - essentially
this undoes v5 (which had a typo anyway)
- Some code style fixes (Ken)
- Remove some excess comments (Ken)
- Unify tessellation failure style - unreachable (Ken)
- Fix workaround comment for PS invocations (Ken)
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ben Widawsky [Fri, 2 Jan 2015 20:13:53 +0000 (12:13 -0800)]
mesa: Add support for the ARB_pipeline_statistics_query extension
This was originally part of a single patch which added the extension, and
implemented it for i965 classic. For information about the evolution of the
patch, please see the subsequent commit.
One difference here as compared to the original mega patch is this does build
support for the compute shader query. Since it cannot be tested on any platform,
it will always return NULL for now. Jordan has already written a patch to
address this, and when that patch lands, this logic can be modified.
v2: Fix typo in subject (Brian Paul)
Add checks for desktop gl (Ilia)
Fail for any callers for now (Ilia)
Update QueryCounterBits for new tokens (Ilia)
Jordan: Use _mesa_has_compute_shaders
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
v3: Rebased on patch which adds the proper information to unstub tessellation
shaders.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Sat, 14 Feb 2015 20:53:42 +0000 (12:53 -0800)]
mesa: Add _mesa_has_compute_shaders
v2 (Ben): Change GLboolean to bool as requested by Ian
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Fabian Bieler [Sun, 21 Sep 2014 01:40:42 +0000 (13:40 +1200)]
mesa: Add ARB_tessellation_shader to extension table.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Kenneth Graunke [Thu, 15 Jan 2015 09:41:14 +0000 (01:41 -0800)]
i965: Prefer Meta over the BLT for BlitFramebuffer.
There's some debate about whether we should use Meta or BLORP,
but either should run circles around the BLT engine.
In particular, this means that Gen8+ will use the 3D engine for blits,
like we do on Gen6-7.
Improves performance in "copypixrate -blit -back" (from Mesa demos)
by 232.037% +/- 3.15795% (n=10) on Broadwell GT3e.
v2: Rebase on Laura's changes.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: "10.5" <mesa-stable@lists.freedesktop.org>
Matt Turner [Mon, 10 Nov 2014 01:27:52 +0000 (17:27 -0800)]
i965/fs: Add algebraic optimizations for MAD.
total instructions in shared programs: 5764176 -> 5763808 (-0.01%)
instructions in affected programs: 25121 -> 24753 (-1.46%)
helped: 164
HURT: 2
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Mon, 27 Oct 2014 05:08:15 +0000 (22:08 -0700)]
i965/fs: Emit MAD instructions when possible.
Previously we didn't emit MAD instructions since they cannot take
immediate arguments, but with the opt_combine_constants() pass we can
handle this properly.
total instructions in shared programs: 5920017 -> 5733278 (-3.15%)
instructions in affected programs: 3625153 -> 3438414 (-5.15%)
helped: 22017
HURT: 870
GAINED: 91
LOST: 49
Without constant pooling, this patch is a complete loss:
total instructions in shared programs: 5912589 -> 5987888 (1.27%)
instructions in affected programs: 3190050 -> 3265349 (2.36%)
helped: 1564
HURT: 17827
GAINED: 27
LOST: 101
And since the constant pooling patch by itself hurt a bunch of things,
from before constant pooling to this patch the results are:
total instructions in shared programs: 5895414 -> 5747946 (-2.50%)
instructions in affected programs: 3617993 -> 3470525 (-4.08%)
helped: 20478
HURT: 4469
GAINED: 54
LOST: 146
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Mon, 27 Oct 2014 05:07:06 +0000 (22:07 -0700)]
i965/fs: Allow immediates in MAD and LRP instructions.
And then the opt_combine_constants() pass will pull them out into
registers. This will allow us to do some algebraic optimizations on MAD
and LRP.
total instructions in shared programs: 5946656 -> 5931320 (-0.26%)
instructions in affected programs: 778247 -> 762911 (-1.97%)
helped: 3780
HURT: 6
GAINED: 12
LOST: 12
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Wed, 12 Feb 2014 19:00:46 +0000 (11:00 -0800)]
i965/fs: Add pass to combine immediates.
total instructions in shared programs: 5885407 -> 5940958 (0.94%)
instructions in affected programs: 3617311 -> 3672862 (1.54%)
helped: 3
HURT: 23556
GAINED: 31
LOST: 165
... but will allow us to always emit MAD instructions.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Mon, 27 Oct 2014 05:10:53 +0000 (22:10 -0700)]
i965/fs: Remove force_writemask_all assertion for execsize < 8.
This doesn't seem to be necessary.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86974
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Thu, 27 Feb 2014 00:15:52 +0000 (16:15 -0800)]
i965/cfg: Add function to generate a dot file of the dominator tree.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Thu, 27 Feb 2014 00:07:52 +0000 (16:07 -0800)]
i965/cfg: Add function to generate a dot file of the CFG.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Wed, 19 Feb 2014 00:35:56 +0000 (16:35 -0800)]
i965/cfg: Calculate the immediate dominators.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Wed, 19 Feb 2014 00:38:07 +0000 (16:38 -0800)]
i965/cfg: Allow cfg::dump to be called without a visitor.
The fs_visitor's dump_instruction() implementation calls cfg_t()
indirectly through calculate_live_intervals, so if you have an infinite
loop in the CFG code, you can't call cfg::dump(fs_visitor *) to debug
it.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Wed, 18 Feb 2015 02:01:41 +0000 (18:01 -0800)]
i965: Allow exec_list sentinels as arguments to insert functions.
To insert an instruction at the end of a basic block, we typically do
something like
inst = block->last_non_control_flow_inst();
inst->insert_after(block, new_inst);
But blocks can consist of a single control flow instruction, so inst
will actually be the exec_list's head sentinel. We shouldn't use it as
if it were a regular instruction, but it is safe to insert something after
it.
This patch avoids assert-failing because an exec_list sentinel wasn't in
the basic block's instruction list.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Alan Coopersmith [Mon, 16 Feb 2015 00:20:25 +0000 (16:20 -0800)]
Make _mesa_swizzle_and_convert argument types in .c match those in .h
Caused Solaris Studio compilers to fail to build with errors about
incompatible function redefinitions.
Signed-off-by: Alan Coopersmith <alan.coopersmith@oracle.com>
Cc: "10.5" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Alan Coopersmith [Mon, 16 Feb 2015 00:19:06 +0000 (16:19 -0800)]
Use __typeof instead of typeof with Solaris Studio compilers
While the C compiler accepts typeof, C++ requires __typeof.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86944
Signed-off-by: Alan Coopersmith <alan.coopersmith@oracle.com>
Cc: "10.5" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Alan Coopersmith [Mon, 16 Feb 2015 00:16:15 +0000 (16:16 -0800)]
Avoid fighting with Solaris headers over isnormal()
When compiling in C99 or C++11 modes, Solaris defines isnormal() as
a macro via <math.h>, which causes the function definition to become
too mangled to compile.
Signed-off-by: Alan Coopersmith <alan.coopersmith@oracle.com>
Cc: "10.5" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Alan Coopersmith [Sun, 15 Feb 2015 22:46:29 +0000 (14:46 -0800)]
Remove extraneous ; after DECL_TYPE usage
The macro is defined to provide a trailing ; so this caused the expansion
to end in ";;" which made the Solaris Studio compilers issue warnings for
every line of:
"builtin_type_macros.h", line 113: Warning: extra ";" ignored.
for every file that included the header, filling build logs with thousands
of useless warnings.
Signed-off-by: Alan Coopersmith <alan.coopersmith@oracle.com>
Cc: "10.5" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Alan Coopersmith [Thu, 1 Jan 2015 20:55:27 +0000 (12:55 -0800)]
Bracket arguments to tr so they work with Solaris tr
https://www.gnu.org/savannah-checkouts/gnu/autoconf/manual/autoconf-2.69/html_node/Limitations-of-Usual-Tools.html#index-g_t_0040command_007btr_007d-1842
Without this fix, egl fails to build on Solaris, with the error:
<command-line>:0:22: error: '_EGL_PLATFORM_x11' undeclared (first use in this function)
egldisplay.c:207:31: note: in expansion of macro '_EGL_NATIVE_PLATFORM'
native_platform = _EGL_NATIVE_PLATFORM;
^
Signed-off-by: Alan Coopersmith <alan.coopersmith@oracle.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Cc: "10.5" <mesa-stable@lists.freedesktop.org>
Kenneth Graunke [Wed, 17 Dec 2014 02:33:39 +0000 (18:33 -0800)]
glsl: Reduce memory consumption of copy propagation passes.
opt_copy_propagation and opt_copy_propagation_elements create new ACP
and Kill sets each time they enter a new control flow block. For if
blocks, they also copy the entire existing ACP set contents into the
new set.
When we exit the control flow block, we discard the new sets. However,
we weren't freeing them - so they lived on until the pass finished.
This can waste a lot of memory (57MB on one pessimal shader).
This patch makes the pass allocate ACP entries using this->acp as the
memory context, and Kill entries out of this->kill. It also steals
kill entries when moving them from the inner kill list to the parent.
It then frees the lists, including their contents.
v2: Move ralloc_free(this->acp) just before this->acp = orig_acp
(suggested by Eric Anholt).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: "10.5 10.4" <mesa-stable@lists.freedesktop.org>
Chris Forbes [Tue, 9 Sep 2014 09:28:46 +0000 (21:28 +1200)]
i965: Add device limits for tess threads & URB entries
This should cover all platforms prior to Skylake.
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Ben Widawsky <ben@bwidawsk.net>
Dave Airlie [Wed, 18 Feb 2015 00:13:20 +0000 (10:13 +1000)]
r600g/sb: treat undefined values like constants
When we schedule an instructions with undefined value, we
eventually will use 0, which is a constant, however sb wasn't
taking this into account and creating ops with illegal scalar
swizzles.
this replaces my fix for op3 in t slots.
Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Kenneth Graunke [Tue, 10 Feb 2015 11:36:48 +0000 (03:36 -0800)]
i915c: Use the actual MIN instruction.
Matt Turner noticed that the hardware has always had a MIN
instruction, but the driver always used MAX+MOV for no
apparent reason.
This should cut an instruction, and a temporary, allowing
more programs to run in hardware.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Tue, 10 Feb 2015 11:36:47 +0000 (03:36 -0800)]
i915g: Use the actual MIN instruction.
Matt Turner noticed that the hardware has always had a MIN
instruction, but the driver always used MAX+MOV for no
apparent reason.
This should cut an instruction, and a temporary, allowing
more programs to run in hardware.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Fri, 6 Feb 2015 08:36:26 +0000 (00:36 -0800)]
i965: Add a function to disassemble an instruction from the 4 dwords.
I used this a while back when debugging GPU hangs, and it seems like it
could be useful, so I figured I'd add it so people can use it in the
debugger.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Sat, 10 Jan 2015 07:07:56 +0000 (23:07 -0800)]
i965: Do Sandybridge workaround flushes before each primitive.
Sandybridge requires the post-sync non-zero workaround in a ton of
places, and if you ever miss one, the GPU usually hangs.
Currently, we try to track exactly when a workaround flush is
necessary (via the brw->batch.need_workaround_flush flag). This is
tricky to get right, and we've botched it several times in the past.
This patch unconditionally performs the post-sync non-zero flush at the
start of each primitive's state upload (including BLORP). We drop the
needs_workaround_flush flag, and drop all the other callers, as the
flush has already been performed.
We have no data to indicate that simply flushing all the time will
hurt performance, and it has the potential to help stability.
v2: Add post-sync workaround to initial GPU state upload to be extra
cautious (suggested by Chad Versace).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Laura Ekstrand [Mon, 16 Feb 2015 22:29:57 +0000 (14:29 -0800)]
main: Fixed _mesa_GetCompressedTexImage_sw to copy slices correctly.
Previously array textures were not working with GetCompressedTextureImage,
leading to failures in the test
arb_direct_state_access/getcompressedtextureimage.c.
Tested-by: Laura Ekstrand <laura@jlekstrand.net>
Reviewed-by: Brian Paul <brianp@vmware.com>
Cc: "10.4, 10.5" <mesa-stable@lists.freedesktop.org>
Ian Romanick [Wed, 11 Feb 2015 17:23:41 +0000 (09:23 -0800)]
i965/vec4: Silence unused parameter warnings
brw_vec4_copy_propagation.cpp:243:59: warning: unused parameter 'reg' [-Wunused-parameter]
int arg, struct copy_entry *entry, int reg)
^
brw_vec4_generator.cpp:869:57: warning: unused parameter 'inst' [-Wunused-parameter]
vec4_generator::generate_unpack_flags(vec4_instruction *inst,
^
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Tue, 10 Feb 2015 16:58:01 +0000 (08:58 -0800)]
mesa/main: Silence unused parameter warning
Just remove the _mesa_free_lighting_data function. The body has been
empty since the shine table was moved into the tnl module (commit
ba1d921).
main/light.c:1216:46: warning: unused parameter 'ctx' [-Wunused-parameter]
_mesa_free_lighting_data( struct gl_context *ctx )
^
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Tue, 10 Feb 2015 16:05:12 +0000 (08:05 -0800)]
util/hash: Silence comparison between signed and unsigned integer warnings in tests
delete_management.c:56:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (i = 0; i < size; i++) {
^
delete_management.c:69:27: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (i = size - 100; i < size; i++) {
^
delete_management.c:79:31: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
assert(key_value(entry->key) >= size - 100 &&
^
delete_management.c:79:70: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
assert(key_value(entry->key) >= size - 100 &&
^
insert_many.c:56:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (i = 0; i < size; i++) {
^
insert_many.c:62:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (i = 0; i < size; i++) {
^
insert_many.c:67:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
assert(ht->entries == size);
^
random_entry.c:62:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (i = 0; i < size; i++) {
^
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Tue, 10 Feb 2015 16:02:28 +0000 (08:02 -0800)]
util/hash: Silence unused parameter warnings in tests
delete_and_lookup.c:37:21: warning: unused parameter ‘key’ [-Wunused-parameter]
badhash(const void *key)
^
delete_and_lookup.c:43:10: warning: unused parameter ‘argc’ [-Wunused-parameter]
main(int argc, char **argv)
^
delete_and_lookup.c:43:23: warning: unused parameter ‘argv’ [-Wunused-parameter]
main(int argc, char **argv)
^
collision.c:34:10: warning: unused parameter ‘argc’ [-Wunused-parameter]
main(int argc, char **argv)
^
collision.c:34:23: warning: unused parameter ‘argv’ [-Wunused-parameter]
main(int argc, char **argv)
^
destroy_callback.c:50:10: warning: unused parameter ‘argc’ [-Wunused-parameter]
main(int argc, char **argv)
^
destroy_callback.c:50:23: warning: unused parameter ‘argv’ [-Wunused-parameter]
main(int argc, char **argv)
^
insert_many.c:46:10: warning: unused parameter ‘argc’ [-Wunused-parameter]
main(int argc, char **argv)
^
insert_many.c:46:23: warning: unused parameter ‘argv’ [-Wunused-parameter]
main(int argc, char **argv)
^
insert_and_lookup.c:34:10: warning: unused parameter ‘argc’ [-Wunused-parameter]
main(int argc, char **argv)
^
insert_and_lookup.c:34:23: warning: unused parameter ‘argv’ [-Wunused-parameter]
main(int argc, char **argv)
^
null_destroy.c:32:10: warning: unused parameter ‘argc’ [-Wunused-parameter]
main(int argc, char **argv)
^
null_destroy.c:32:23: warning: unused parameter ‘argv’ [-Wunused-parameter]
main(int argc, char **argv)
^
random_entry.c:52:10: warning: unused parameter ‘argc’ [-Wunused-parameter]
main(int argc, char **argv)
^
random_entry.c:52:23: warning: unused parameter ‘argv’ [-Wunused-parameter]
main(int argc, char **argv)
^
remove_null.c:34:10: warning: unused parameter ‘argc’ [-Wunused-parameter]
main(int argc, char **argv)
^
remove_null.c:34:23: warning: unused parameter ‘argv’ [-Wunused-parameter]
main(int argc, char **argv)
^
replacement.c:34:10: warning: unused parameter ‘argc’ [-Wunused-parameter]
main(int argc, char **argv)
^
replacement.c:34:23: warning: unused parameter ‘argv’ [-Wunused-parameter]
main(int argc, char **argv)
^
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Tue, 10 Feb 2015 15:57:08 +0000 (07:57 -0800)]
glcpp: Silence GCC warning
glcpp/glcpp.c:124:1: warning: ‘static’ is not at beginning of declaration [-Wold-style-declaration]
const static struct option
^
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Marek Olšák [Sun, 15 Feb 2015 17:12:06 +0000 (18:12 +0100)]
radeonsi: fix a crash if a stencil ref state is set before a DSA state
+ minor indentation fixes
Discovered by Axel Davy.
This can't be reproduced with any app, because all state trackers set a DSA
state first.
Cc: 10.5 10.4 10.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Axel Davy <axel.davy@ens.fr>
Marek Olšák [Tue, 10 Feb 2015 15:02:54 +0000 (16:02 +0100)]
r600g,radeonsi: implement GL_AMD_pinned_memory
v2: update release notes
Reviewed-by: Christian König <christian.koenig@amd.com>
Marek Olšák [Wed, 11 Feb 2015 19:25:16 +0000 (20:25 +0100)]
winsys/radeon: test the userptr ioctl to see if it's present
There is no other way to check for support.
Reviewed-by: Christian König <christian.koenig@amd.com>
Marek Olšák [Tue, 10 Feb 2015 21:27:21 +0000 (22:27 +0100)]
winsys/radeon: allow unaligned size for user-memory buffers
This is not required, but being user-friendly doesn't hurt.
Reviewed-by: Christian König <christian.koenig@amd.com>
Marek Olšák [Tue, 10 Feb 2015 15:41:53 +0000 (16:41 +0100)]
winsys/radeon: allow mapping a user buffer
OpenGL requires this.
Reviewed-by: Christian König <christian.koenig@amd.com>
Marek Olšák [Tue, 10 Feb 2015 13:00:57 +0000 (14:00 +0100)]
gallium: add interface and state tracker support for GL_AMD_pinned_memory
v2: add alignment restrictions to docs, fix indentation in headers
Reviewed-by: Christian König <christian.koenig@amd.com>
Marek Olšák [Tue, 10 Feb 2015 00:39:41 +0000 (01:39 +0100)]
mesa: implement GL_AMD_pinned_memory
It's not possible to query the current buffer binding, because the extension
doesn't define GL_..._BUFFER__BINDING_AMD.
Drivers should check the target parameter of Drivers.BufferData. If it's
equal to GL_EXTERNAL_VIRTUAL_MEMORY_BUFFER_AMD, the memory should be pinned.
That's all there is to it.
A piglit test is on the piglit mailing list.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Christian König [Thu, 5 Feb 2015 17:34:51 +0000 (18:34 +0100)]
winsys/radeon: add user pointer support
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Marek Olšák [Tue, 10 Feb 2015 00:35:23 +0000 (01:35 +0100)]
mesa: fix AtomicBuffer typo in _mesa_DeleteBuffers
Cc: 10.5 10.4 10.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
Marek Olšák [Tue, 10 Feb 2015 13:16:56 +0000 (14:16 +0100)]
radeonsi: initialize TC_L2_dirty to false after buffer allocation
I forgot to do this, though "true" should have no effect on correctness.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Fri, 6 Feb 2015 17:00:50 +0000 (18:00 +0100)]
radeonsi: small fix in SPI state
Cc: 10.5 10.4 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Sat, 7 Feb 2015 12:19:38 +0000 (13:19 +0100)]
r600g,radeonsi: use fences to implement PIPE_QUERY_GPU_FINISHED
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89014
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Fri, 6 Feb 2015 16:18:11 +0000 (17:18 +0100)]
r600g,radeonsi: demote TIMESTAMP_DISJOINT query to be a software query
The query result is always constant.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Dave Airlie [Tue, 17 Feb 2015 00:05:45 +0000 (10:05 +1000)]
st/glsl_to_tgsi: fix whitespace
everytime I open this file in emacs with show trailing whitespace
or git add from it my screen flares with red.
Just do a general cleanup, makes working on fp64 support not as
jarring.
I'm not saying this is perfect, its just better than before.
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Ilia Mirkin [Tue, 17 Feb 2015 01:25:16 +0000 (11:25 +1000)]
glsl/tests: add IMAGE type.
This fixes a warning when running make check.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Chia-I Wu [Mon, 16 Feb 2015 20:45:03 +0000 (04:45 +0800)]
ilo: always set up BLEND_STATE on Gen8
There is now an DW0 that seems to be always referenced.
Chia-I Wu [Mon, 16 Feb 2015 20:54:17 +0000 (04:54 +0800)]
ilo: fix alpha test on Gen8
Shoudl use GEN8_BLEND_DW0_ALPHA_TEST_ENABLE instead of
GEN6_RT_DW1_ALPHA_TEST_ENABLE (and others).
Ben Widawsky [Mon, 16 Feb 2015 04:06:59 +0000 (20:06 -0800)]
i965/simd8vs: Fix SIMD8 atomics
The short version: we need to set bits in R0.7 which provide a mask to be used
for PS kill samples/pixels. Since the VS has no such concept, we just need to
set all 1.
The longer version...
Execution for SIMD8 atomics is defined as follows:
SIMD8: The low 8 bits of the execution mask are ANDed with 8 bits of the
Pixel/Sample Mask from the message header. For the typed messages, the Slot
Group in the message descriptor selects either the low or high 8 bits. For the
untyped messages, the low 8 bits are always selected. The resulting mask is used
to determine which slots are read into the destination GRF register (for read),
or which slots are written to the surface (for write). If the header is not
present, only the low 8 bits of the execution mask are used.
The message header for untyped messages is defined in R0.7 "This field contains
the 16-bit pixel/sample mask to be used for SIMD16 and SIMD8 messages. All 16
bits are used for SIMD16 messages. For typed SIMD8 messages, Slot Group selects
which 8 bits of this field are used. For untyped SIMD8 messages, the low 8 bits
of this field are used." Furthermore, "The message header for the untyped
messages only needs to be delivered for pixel shader threads, where the
execution mask may indicate pixels/samples that are enabled only due to
derivative (LOD) calculations, but the corresponding slot on the surface must
not be accessed." We're not using a pixel shader here, but AFAICT, this mask is
used for all stages.
This leaves two options, Remove the header, or make the VS code emit the correct
thing for the header. I believe one of the goals of using SIMD8 VS was to get as
much code reuse as possible, and so I chose the latter. Since the VS has no such
thing as kill instructions, the mask is derived simple as all 1's.
v2:
Add a comment to the code (stolen from Curro on the mailing list)
Change the control flow style (Curro + Jason)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=87258
Cc: Kristian Høgsberg <krh@bitplanet.net>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Brian Paul [Mon, 16 Feb 2015 15:38:56 +0000 (08:38 -0700)]
mesa: move assertion after declarations in texstore.c
To fix MSVC build.
Brian Paul [Tue, 10 Feb 2015 19:17:18 +0000 (12:17 -0700)]
mesa: silence uninitialized var warning in get_tex_rgba_uncompressed()
Reviewed-by: Matt Turner <mattst88@gmail.com>
Neil Roberts [Tue, 25 Nov 2014 17:52:27 +0000 (17:52 +0000)]
meta: Fix saving the results of the current occlusion query
When restoring the current state in _mesa_meta_end it was previously trying to
copy the on-going sample count of the current occlusion query into the new
query after restarting it so that the driver will continue adding to the
previous value. This wouldn't work for two reasons. Firstly, the query might
not be ready yet so the Result member will usually be zero. Secondly the saved
query is stored as a pointer to the query object, not a copy of the struct, so
it is actually restarting the exact same object. Copying the result value is
just copying between identical addresses with no effect. The call to
_mesa_BeginQuery will have always reset it back to zero.
This patch fixes it by making it actually wait for the query object to be
ready before grabbing the previous result. The downside of doing this is that
it could introduce a stall but I think this situation is unlikely so it might
not matter too much. A better solution might be to introduce a real
suspend/resume mechanism to the driver interface. This could be implemented in
the i965 driver by saving the depth count multiple times like it does in the
i945 driver.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88248
Reviewed-by: Carl Worth <cworth@cworth.org>
Cc: "10.5" <mesa-stable@lists.freedesktop.org>
Francisco Jerez [Thu, 12 Feb 2015 08:20:49 +0000 (10:20 +0200)]
i965/vec4: Override destination register writemask in sampler message send.
This line was removed by accident in commit
16b911257440afbd77a6eb762e28df62e3c19bc7 causing a regression in the
ES3-CTS.gtf.GL3Tests.shadow.shadow_execution_vert Khronos conformance
test. It's necessary because the swizzle_result() code below expects
all four components of the vector to be valid.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89094
Tested-by: Lu Hua <huax.lu@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Iago Toral Quiroga [Fri, 13 Feb 2015 07:29:32 +0000 (08:29 +0100)]
i965: Fix a crash in the texture gradient lowering pass with cube samplers
We need to swizzle the rhs to match the number of components in the writemask,
otherwise we'll hit an assertion in ir_assignment.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Iago Toral Quiroga [Fri, 13 Feb 2015 11:56:26 +0000 (12:56 +0100)]
mesa: Fix element count for byte-swaps in texstore, readpix and texgetimage
Some old format conversion code in pack.c implemented byte-swapping like this:
GLint comps = _mesa_components_in_format(dstFormat);
GLint swapSize = _mesa_sizeof_packed_type(dstType);
if (swapSize == 2)
_mesa_swap2((GLushort *) dstAddr, n * comps);
else if (swapSize == 4)
_mesa_swap4((GLuint *) dstAddr, n * comps);
where n is the pixel count. But this is incorrect for packed formats,
where _mesa_sizeof_packed_type is already returning the size of a pixel
instead of the size of a single component, so multiplying this by the
number of components in the format results in a larger element count
for _mesa_swap than we want.
Unfortunately, we followed the same implementation for byte-swapping
in the rewrite of the format conversion code for texstore, readpixels
and texgetimage.
This patch computes the correct element counts for _mesa_swap calls
by computing the bytes per pixel in the image and dividing that by the
swap size to obtain the number of swaps required per pixel. Then multiplies
that by the number of pixels in the image to obtain the swap count that
we need to use.
Also, when handling byte-swapping in texstore_rgba, we were ignoring
the image's depth. This patch fixes this too.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Cc: "10.5" <mesa-stable@lists.freedesktop.org>
Iago Toral Quiroga [Fri, 13 Feb 2015 09:23:26 +0000 (10:23 +0100)]
mesa: Handle transferOps in texstore_rgba
In the recent rewrite of the format conversion code we did not handle this.
This patch adds the missing support.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89068
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Cc: "10.5" <mesa-stable@lists.freedesktop.org>
Matt Turner [Fri, 9 Jan 2015 06:56:44 +0000 (22:56 -0800)]
i965/fs: Handle U/UW-type immediates in the generator.
Matt Turner [Fri, 9 Jan 2015 06:55:16 +0000 (22:55 -0800)]
i965/fs: Handle W/UW-type immediates in dump_instructions().