platform/kernel/u-boot.git
11 years agopowerpc/85xx: Add P1023RDB board support
Chunhe Lan [Fri, 14 Jun 2013 08:21:48 +0000 (16:21 +0800)]
powerpc/85xx: Add P1023RDB board support

P1023RDB Specification:
-----------------------
Memory subsystem:
   512MB DDR3 (Fixed DDR on board)
   64MB NOR flash
   128MB NAND flash

Ethernet:
   eTSEC1: Connected to Atheros AR8035 GETH PHY
   eTSEC2: Connected to Atheros AR8035 GETH PHY

PCIe:
   Three mini-PCIe slots

USB:
   Two USB2.0 Type A ports

I2C:
   AT24C08 8K Board EEPROM (8 bit address)

Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/mpc85xx:Disable Debug TLB entry before init_tlbs
Prabhakar Kushwaha [Thu, 13 Jun 2013 04:44:00 +0000 (10:14 +0530)]
powerpc/mpc85xx:Disable Debug TLB entry before init_tlbs

init_tlbs() initialize all the TLB entries required for the system.

So disable DEBUG TLB entry before TLB entries initialization.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/pixis: Fix pixis help message
York Sun [Fri, 31 May 2013 15:48:04 +0000 (08:48 -0700)]
powerpc/pixis: Fix pixis help message

"pixis_reset help" command prints the message without a new line "\n",
which makes the prompt on the same line.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/CoreNet: Allow pbl images to take u-boot images != 512K
Chris Packham [Sun, 26 May 2013 22:51:46 +0000 (10:51 +1200)]
powerpc/CoreNet: Allow pbl images to take u-boot images != 512K

Instead of assuming that SYS_TEXT_BASE is 0xFFF80000 calculate the initial
pbl command offset by subtracting the image size from the top of the
24-bit address range. Also increase the size of the memory buffer to
accommodate a larger output image.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc: mpc85xx/mpc86xx: Fix off-by-one boundary checking with ARRAY_SIZE
Axel Lin [Sun, 26 May 2013 07:00:30 +0000 (15:00 +0800)]
powerpc: mpc85xx/mpc86xx: Fix off-by-one boundary checking with ARRAY_SIZE

If a variable is used as array subscript, it's valid value range is
0 ... ARRAY_SIZE -1.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agoMakefile: move the common makefile line to public area
Ying Zhang [Mon, 20 May 2013 06:07:26 +0000 (14:07 +0800)]
Makefile: move the common makefile line to public area

Move the common makefile line shared by the SPL and non-SPL to the public area,
so that we can avoid excessive SPL symbols. Some of them will be used by the
SPL later.

This patch is on top of the patch "common/Makefile: Add new symbol
CONFIG_SPL_ENV_SUPPORT for environment in SPL".

Signed-off-by: Ying Zhang <b40530@freescale.com>
Acked-by: Tom Rini <trini@ti.com>
Acked-by: Tom Rini <trini@ti.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agocommon/Makefile: Add new symbol CONFIG_SPL_ENV_SUPPORT for environment in SPL
Ying Zhang [Mon, 20 May 2013 06:07:25 +0000 (14:07 +0800)]
common/Makefile: Add new symbol CONFIG_SPL_ENV_SUPPORT for environment in SPL

There will need the environment in SPL for reasons other than network
support (in particular, hwconfig contains info for how to set up DDR).

Add a new symbol CONFIG_SPL_ENV_SUPPORT to replace CONFIG_SPL_NET_SUPPORT
for environment in common/Makefile.

Signed-off-by: Ying Zhang <b40530@freescale.com>
Reviewed-by: Tom Rini <trini@ti.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/mpc85xx: modify the functionality clear_bss and aligning the end address...
Ying Zhang [Fri, 7 Jun 2013 09:25:16 +0000 (17:25 +0800)]
powerpc/mpc85xx: modify the functionality clear_bss and aligning the end address of the BSS

There will clear the BSS in the function clear_bss(), the reset address of
the BSS started from the __bss_start, and increased by four-byte increments,
finally stoped depending on the address is equal to the _bss_end. If the end
address __bss_end is not alignment to 4byte, it will be an infinite loop.

1. The reset action stoped depending on the reset address is greater
than or equal the end address of the BSS.
2. The end address of the BSS should be 4byte aligned. Because the reset unit
is 4 Bytes.

This patch is on top of the patch "powerpc/mpc85xx: support application
without resetvec segment in the linker script".

Signed-off-by: Ying Zhang <b40530@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/mpc85xx: support application without resetvec segment in the linker script
Ying Zhang [Mon, 20 May 2013 06:07:23 +0000 (14:07 +0800)]
powerpc/mpc85xx: support application without resetvec segment in the linker script

For SD/SPI 2-stage bootloader, the On-Chip Rom code loads the SPL into L2 SRAM,
then jump to it to begin execution. After that, the SPL loads the final uboot
image into DDR, then jump to it to begin execution. The segment .resetvec in
the SPL and in final U-boot is useless.

So, add new symbols CONFIG_SYS_MPC85XX_NO_RESETVEC for this application.
If CONFIG_SYS_MPC85XX_NO_RESETVEC is set, the segment .resetvec is excluded
and the segment .bootpg is placed in the previous 4K of the segment .text.

Signed-off-by: Ying Zhang <b40530@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agoboard/p1010rdb: Fix PCIe TLB creation on CONFIG_PCI define
Prabhakar Kushwaha [Fri, 17 May 2013 08:52:34 +0000 (14:22 +0530)]
board/p1010rdb: Fix PCIe TLB creation on CONFIG_PCI define

PCIe TLB should be created with CONFIG_PCI defined

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agoboard/b4860qds: Relax NOR flash teadc timing parameter
Prabhakar Kushwaha [Fri, 17 May 2013 08:10:52 +0000 (13:40 +0530)]
board/b4860qds: Relax NOR flash teadc timing parameter

Relax parameters to give address latching more time to setup.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/mpc85xx: work around erratum A-006593
Scott Wood [Wed, 15 May 2013 22:50:13 +0000 (17:50 -0500)]
powerpc/mpc85xx: work around erratum A-006593

Erratum A-006593 is "Atomic store may report failure but still allow
the store data to be visible".

The workaround is: "Set CoreNet Platform Cache register CPCHDBCR0 bit
21 to 1'b1.  This may have a small impact on synthetic write bandwidth
benchmarks but should have a negligible impact on real code."

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agofsl_ifc: add support for different IFC bank count
Mingkai Hu [Thu, 16 May 2013 02:18:13 +0000 (10:18 +0800)]
fsl_ifc: add support for different IFC bank count

Calculate reserved fields according to IFC bank count

1. Move csor_ext register behind csor register and fix res offset
2. Move ifc bank count to config_mpc85xx.h to support 8 bank count
3. Guard fsl_ifc.h with CONFIG_FSL_IFC macro to eliminate the compile
   error on some devices that does not have IFC controller.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/t4qds: Slave module for boot from SRIO and PCIE
Liu Gang [Tue, 7 May 2013 08:30:50 +0000 (16:30 +0800)]
powerpc/t4qds: Slave module for boot from SRIO and PCIE

When a T4 board boots from SRIO or PCIE, it needs to finish these processes:
1. Set all the cores in holdoff status.
2. Set the boot location to one PCIE or SRIO interface by RCW.
3. Set a specific TLB entry for the boot process.
4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot.
5. Set a specific TLB entry in order to fetch ucode and ENV from
   master.
6. Set a LAW entry with the TargetID one of the PCIE ports for
   ucode and ENV.
7. Slave's u-boot image should be generated specifically by
   make xxxx_SRIO_PCIE_BOOT_config.
   This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.

For more information about the feature of Boot from SRIO/PCIE, please
refer to the document doc/README.srio-pcie-boot-corenet.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/t4qds: Enable master module for Boot from SRIO and PCIE
Liu Gang [Tue, 7 May 2013 08:30:49 +0000 (16:30 +0800)]
powerpc/t4qds: Enable master module for Boot from SRIO and PCIE

T4 can support the feature of Boot from SRIO/PCIE, and the macro
"CONFIG_SRIO_PCIE_BOOT_MASTER" will enable the master module of this feature
when building the u-boot image.

You can get some description about this macro in README file, and for more
information about the feature of Boot from SRIO/PCIE, please refer to the
document doc/README.srio-pcie-boot-corenet.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/b4860qds: Slave module for boot from SRIO and PCIE
Liu Gang [Tue, 7 May 2013 08:30:48 +0000 (16:30 +0800)]
powerpc/b4860qds: Slave module for boot from SRIO and PCIE

When a b4860qds board boots from SRIO or PCIE, it needs to finish these
processes:
1. Set all the cores in holdoff status.
2. Set the boot location to one PCIE or SRIO interface by RCW.
3. Set a specific TLB entry for the boot process.
4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot.
5. Set a specific TLB entry in order to fetch ucode and ENV from
   master.
6. Set a LAW entry with the TargetID one of the PCIE ports for
   ucode and ENV.
7. Slave's u-boot image should be generated specifically by
   make xxxx_SRIO_PCIE_BOOT_config.
   This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.

For more information about the feature of Boot from SRIO/PCIE, please
refer to the document doc/README.srio-pcie-boot-corenet.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/b4860qds: Enable master module for boot from SRIO and PCIE
Liu Gang [Tue, 7 May 2013 08:30:47 +0000 (16:30 +0800)]
powerpc/b4860qds: Enable master module for boot from SRIO and PCIE

B4860QDS can support the feature of Boot from SRIO/PCIE, and the macro
"CONFIG_SRIO_PCIE_BOOT_MASTER" will enable the master module of this feature
when building the u-boot image.

You can get some description about this macro in README file, and for more
information about the feature of Boot from SRIO/PCIE, please refer to the
document doc/README.srio-pcie-boot-corenet.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/boot: Change the macro of Boot from SRIO and PCIE master module
Liu Gang [Tue, 7 May 2013 08:30:46 +0000 (16:30 +0800)]
powerpc/boot: Change the macro of Boot from SRIO and PCIE master module

Currently, the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" can enable
the master module of Boot from SRIO and PCIE on a platform. But this
is not a silicon feature, it's just a specific booting mode based on
the SRIO and PCIE interfaces. So it's inappropriate to put the macro
into the file arch/powerpc/include/asm/config_mpc85xx.h.

Change the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" to
"CONFIG_SRIO_PCIE_BOOT_MASTER", remove them from
arch/powerpc/include/asm/config_mpc85xx.h file, and add those macros
in configuration header file of each board which can support the
master module of Boot from SRIO and PCIE.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/doc: Update the README.srio-pcie-boot-corenet
Liu Gang [Tue, 7 May 2013 08:30:45 +0000 (16:30 +0800)]
powerpc/doc: Update the README.srio-pcie-boot-corenet

1. Misalignment will be found in the doc/README.srio-pcie-boot-corenet
   file when the tabs are set to 8 characters. And the standard for
   u-boot should be 8 character tabs! So this issue should be amended.

2. Add a NOTE for the ENV parameters of the Slave.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/mpc85xx:Fix "boot page TLB" entry size for NAND SPL
Prabhakar Kushwaha [Tue, 7 May 2013 05:49:55 +0000 (11:19 +0530)]
powerpc/mpc85xx:Fix "boot page TLB" entry size for NAND SPL

e500v2 processor does not support 8K page size TLB entries.

So create new TLB entry only during NAND SPL boot.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years ago85xx: Change case of MPC85XX_PORBMSR_ROMLOC_SHIFT
Andy Fleming [Thu, 20 Jun 2013 19:54:33 +0000 (14:54 -0500)]
85xx: Change case of MPC85XX_PORBMSR_ROMLOC_SHIFT

All the other constants use lowercase 'x' in "MPC85xx", so we
duplicate that here.

Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc: Use lower case for the core names
Fabio Estevam [Sun, 21 Apr 2013 16:11:02 +0000 (13:11 -0300)]
powerpc: Use lower case for the core names

Freescale documentation presents the PowerPC core names in lower case, such as
"e300", "e500", "e600", etc.

Change the upper case occurrences into lower case so that the core names
reported in U-boot can match the ones from the documentation.

While at it also fix a checkpatch error:

ERROR: space prohibited before that close parenthesis ')'
#53: FILE: arch/powerpc/cpu/mpc86xx/cpu.c:81:
+ printf("e600 Core %d", (msscr0 & 0x20) ? 1 : 0 );

Reported-by: Heinz Wrobel <heinz.wrobel@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/BSC9132: Add IFC bank count
York Sun [Fri, 19 Apr 2013 02:31:01 +0000 (19:31 -0700)]
powerpc/BSC9132: Add IFC bank count

BSC9132 has 3 IFC banks.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agoboard/bsc9131rdb: Update default boot environment settings
Priyanka Jain [Thu, 4 Apr 2013 09:10:32 +0000 (14:40 +0530)]
board/bsc9131rdb: Update default boot environment settings

BSC9131RDB has 1GB DDR.
Out of this, only 880MB is passed on to Linux via bootm_size.
Remaining
-16MB is reserved for PowerPC-DSP shared control area
-128MB is reserved for DSP private area.

Also 256MB, out of this 880MB is required for data communication between
PowerPC and DSP core.
For this bootargs are modified to pass parameter to create 1 hugetlb
page of 256MB via default_hugepagesz, hugepagesz and hugepages

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agoboard/bsc9131rdb: Add DSP side tlb and laws
Priyanka Jain [Thu, 4 Apr 2013 04:01:54 +0000 (09:31 +0530)]
board/bsc9131rdb: Add DSP side tlb and laws

BSC9131RDB is a Freescale Reference Design Board for
BSC9131 SoC which is a integrated device that contains
one powerpc e500v2 core and one DSP starcore.

To support DSP starcore
-Creating LAW and TLB for DSP-CCSR space.
-Creating LAW for DSP-core subsystem M2 memory

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agoboard/bsc9131rdb: Add targets for Sysclk 100MHz
Priyanka Jain [Mon, 1 Apr 2013 06:42:45 +0000 (12:12 +0530)]
board/bsc9131rdb: Add targets for Sysclk 100MHz

BSC9131RDB supports Sysclk
-66MHz if jumper J16 is close (default state)
-100MHz if jumper J16 is open

Add targets
-BSC9131RDB_NAND_SYSCLK100 : for NAND boot at Sysclk 100MHz
-BSC9131RDB_SPIFLASH_SYSCLK100: for SPI boot at Sysclk 100MHz

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agoboard/bsc9132qds:Add NAND boot support using new SPL format
Prabhakar Kushwaha [Tue, 16 Apr 2013 07:58:40 +0000 (13:28 +0530)]
board/bsc9132qds:Add NAND boot support using new SPL format

- Add NAND boot target
   - defines constants
   - Add spl_minimal.c to initialise DDR
   - update TLB, LAW entries as per NAND boot

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agoboard/bsc9131rdb:Add NAND boot support using new SPL format
Prabhakar Kushwaha [Tue, 16 Apr 2013 07:58:25 +0000 (13:28 +0530)]
board/bsc9131rdb:Add NAND boot support using new SPL format

- Add NAND boot target
   - defines constants
   - Add spl_minimal.c to initialise DDR
   - update TLB entries as per NAND boot

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agoboard/p1010rdb:Add NAND boot support using new SPL format
Prabhakar Kushwaha [Tue, 16 Apr 2013 07:58:12 +0000 (13:28 +0530)]
board/p1010rdb:Add NAND boot support using new SPL format

- defines constants
  - Add spl_minimal.c to initialise DDR
  - update TLB entries as per NAND boot
  - remove nand_spl support for P1010RDB

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/mpc85xx: new SPL support for IFC NAND
Prabhakar Kushwaha [Tue, 16 Apr 2013 07:57:59 +0000 (13:27 +0530)]
powerpc/mpc85xx: new SPL support for IFC NAND

Linker script is not able find start.o binary. So add its absolute path in
u-boot-spl.lds. This change is similar to u-boot-nand.lds

common/Makefile: Avoid compiling unnecssary files

fsl_ifc_spl.c : It is is responsible for reading u-boot binary from
NAND flash and copying into DDR. It also transfer control from NAND SPL
to u-boot image present in DDR.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/mpc85xx:No NOR boot, do not compile IFC errata A003399
Prabhakar Kushwaha [Tue, 16 Apr 2013 07:57:44 +0000 (13:27 +0530)]
powerpc/mpc85xx:No NOR boot, do not compile IFC errata A003399

IFC errata A003399 is valid for IFC NOR boot i.e.if no on-board NOR flash or
no NOR boot, do not compile its workaround.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agopowerpc/mpc85xx: explicit cast the SDRAM size to type phys_size_t
Mingkai Hu [Fri, 12 Apr 2013 07:56:28 +0000 (15:56 +0800)]
powerpc/mpc85xx: explicit cast the SDRAM size to type phys_size_t

To avoid sign extension problem, use explicit casting to cast
the SDRAM size to type phys_size_t, or else, if the SDRAM size
is 2G(0x80000000), it will be extended to 0xffffffff80000000
when phys_size_t is type 'unsigned long long'.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years ago85xx: Change clock-frequency compatible to 2.0
Andy Fleming [Mon, 17 Jun 2013 20:10:28 +0000 (15:10 -0500)]
85xx: Change clock-frequency compatible to 2.0

Accidentally applied an earlier version of the patch, which set
the compatible to "fsl,qoriq-clockgen-2", lacking the final
".0".

Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
11 years agoNET: Fix system hanging if NET device is not installed
Jim Lin [Fri, 17 May 2013 09:41:03 +0000 (17:41 +0800)]
NET: Fix system hanging if NET device is not installed

If we try to boot from NET device, NetInitLoop in net.c will be invoked.
If NET device is not installed, eth_get_dev() function will return
eth_current value, which is NULL.
When NetInitLoop is called, "eth_get_dev->enetaddr" will access
restricted memory area and therefore cause hanging.
This issue is found on Tegra30 Cardhu platform after adding
CONFIG_CMD_NET and CONFIG_CMD_DHCP in config header file.

Signed-off-by: Jim Lin <jilin@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
11 years agoimage: Use ENOENT instead of ENOMEDIUM for better compatibility
Simon Glass [Sun, 16 Jun 2013 14:46:49 +0000 (07:46 -0700)]
image: Use ENOENT instead of ENOMEDIUM for better compatibility

This error may not be defined on some platforms such as MacOS so host
compilation will fail. Use one of the more common errors instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Andreas Bießmann <andreas.devel@googlemail.com>
Tested-by: Lubomir Popov <lpopov@mm-sol.com>
11 years agoMerge branch 'master' of git://www.denx.de/git/u-boot-mmc
Tom Rini [Fri, 14 Jun 2013 20:06:49 +0000 (16:06 -0400)]
Merge branch 'master' of git://denx.de/git/u-boot-mmc

11 years agoPrepare v2013.07-rc1 v2013.07-rc1
Tom Rini [Fri, 14 Jun 2013 15:01:39 +0000 (11:01 -0400)]
Prepare v2013.07-rc1

Signed-off-by: Tom Rini <trini@ti.com>
11 years agoARM: tegra: make use of negative ENV_OFFSET on NVIDIA boards
Stephen Warren [Tue, 11 Jun 2013 21:14:03 +0000 (15:14 -0600)]
ARM: tegra: make use of negative ENV_OFFSET on NVIDIA boards

Use a negative value of CONFIG_ENV_OFFSET for all NVIDIA reference boards
that store the U-Boot environment in the 2nd eMMC boot partition. This
makes U-Boot agnostic to the size of the eMMC boot partition, which can
vary depending on which eMMC device was actually stuffed into the board.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agoenv_mmc: allow negative CONFIG_ENV_OFFSET
Stephen Warren [Tue, 11 Jun 2013 21:14:02 +0000 (15:14 -0600)]
env_mmc: allow negative CONFIG_ENV_OFFSET

A negative value of CONFIG_ENV_OFFSET is treated as a backwards offset
from the end of the eMMC device/partition, rather than a forwards offset
from the start.

This is useful when a single board may be stuffed with different eMMC
devices, each of which has a different capacity, and you always want the
environment to be stored at the very end of the device (or eMMC boot
partition for example).

One example of this case is NVIDIA's Ventana reference board.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agommc: report capacity for the selected partition
Stephen Warren [Tue, 11 Jun 2013 21:14:01 +0000 (15:14 -0600)]
mmc: report capacity for the selected partition

Enhance the MMC core to calculate the size of each MMC partition, and
update mmc->capacity whenever a partition is selected. This causes:

mmc dev 0 1 ; mmcinfo

... to report the size of the currently selected partition, rather than
always reporting the size of the user partition.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agoREADME: document CONFIG_ENV_IS_IN_MMC
Stephen Warren [Tue, 11 Jun 2013 21:14:00 +0000 (15:14 -0600)]
README: document CONFIG_ENV_IS_IN_MMC

Describe the meaning of CONFIG_ENV_IS_IN_MMC, and all related defines that
must or can be set when using that option.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk>
Acked-by: Tom Rini <trini@ti.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agofsl_esdhc: Do not clear interrupt status bits until data processed
Andrew Gabbasov [Tue, 11 Jun 2013 15:34:22 +0000 (10:34 -0500)]
fsl_esdhc: Do not clear interrupt status bits until data processed

After waiting for the command completion event, the interrupt status
bits, that occured to be set by that time, are cleared by writing them
back. It is supposed, that it should be command related bits (command
complete and may be command errors).

However, in some cases the DMA already completes by that time before
the full transaction completes. The corresponding DINT bit gets set
and then cleared before even entering the loop, waiting for data part
completion. That waiting loop never gets this bit set, causing the
operation to hang. This is reported to happen, for example, for write
operation of 1 sector to upper area (block #7400000) of SanDisk Ultra II
8GB card.

The solution could be to explicitly clear only command related interrupt
status bits. However, since subsequent processing does not rely on
any command bits state, it could be easier just to remove clearing
of any bits at that point, leaving them all until all data processing
completes. After that the whole register will be cleared at once.

Also, on occasion, interrupts masking moved to before writing the command,
just for the case there should be no chance of interrupt between the first
command and interrupts masking.

Reported-by: Dirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agommc: fsl_esdhc: Fix hang after 'save' command
Fabio Estevam [Tue, 28 May 2013 18:09:42 +0000 (15:09 -0300)]
mmc: fsl_esdhc: Fix hang after 'save' command

Since commit 48e0b2bd (powerpc/esdhc: Correct judgement for DATA PIO mode)
we see mx6 systems to hang after doing a 'save' command.

Revert this commit since the original 'ifdef' logic from 7b43db92
(drivers/mmc/fsl_esdhc.c: fix compiler warnings) was the correct one.

Reported-by: Tapani Utriainen <tapani@technexion.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agommc write bug fix
Ruud Commandeur [Wed, 22 May 2013 11:19:43 +0000 (13:19 +0200)]
mmc write bug fix

This patch fixes a bug related to mmc writes.

When doing fatwrites on an SD-Card, MMC bus problems can occur. Depending
on the size of the file, "MMC0: Bus busy timeout!" is reported, resulting
in an SD-Card that is no longer responding.
It appears to be, that set_cluster can be called with a size being zero.
That can be with a file that has a size being an exact multiple
(including 0) of the clustersize, but also for files that are smaller than
the size of one cluster.
The same problem occurs if the "mmc write" command is given with a block
count being 0.

By adding a check for the block count being zero in mmc_write_blocks
(drivers/mmc.c), this problem is solved.

Signed-off-by: Ruud Commandeur <rcommandeur@clb.nl>
Cc: Tom Rini <trini@ti.com>
Cc: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Mats Karrman <Mats.Karrman@tritech.se>
Cc: Andy Fleming <afleming@gmail.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agommc: sdhci: Enable 8-bit bus width only for 3.0 spec onwards
Jagannadha Sutradharudu Teki [Tue, 21 May 2013 09:31:36 +0000 (15:01 +0530)]
mmc: sdhci: Enable 8-bit bus width only for 3.0 spec onwards

CAP register don't have any information for 8-bit buswidth support
on 2.0 sdhci spec, only from 3.0 onwards bit[18] got this information.

Due to this misassignment in sdhci, mmc is setting 8-bit buswidth using
mmc_set_bus_width even if controller doesn't support.
Below change has code information.
"mmc: Properly determine maximum supported bus width"
(sha1: 7798f6dbd5e1a3030ed81a81da5dfb57c3307cac)

Bug log: <mmc plus and emmc cards)
-------
zynq-uboot> mmcinfo
Error detected in status(0x208100)!
Device: zynq_sdhci
Manufacturer ID: fe
.....

So enable 8-bit support only for 3.0 spec using CAP and for below 3.0
assign mmc->host_caps = MMC_MODE_8BIT on respective platform driver
if host have a support.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agommc: fix env in mmc with redundant compile error
Bo Shen [Wed, 15 May 2013 01:38:16 +0000 (09:38 +0800)]
mmc: fix env in mmc with redundant compile error

The commit d196bd8 (env_mmc: add support for redundant environment)
introduce the following compile error when enable redundant
environment support with MMC
---8<---
env_mmc.c:149: error: 'env_t' has no member named 'flags'
env_mmc.c:248: error: 'env_t' has no member named 'flags'
env_mmc.c:248: error: 'env_t' has no member named 'flags'
env_mmc.c:250: error: 'env_t' has no member named 'flags'
env_mmc.c:250: error: 'env_t' has no member named 'flags'
env_mmc.c:252: error: 'env_t' has no member named 'flags'
env_mmc.c:252: error: 'env_t' has no member named 'flags'
env_mmc.c:254: error: 'env_t' has no member named 'flags'
env_mmc.c:254: error: 'env_t' has no member named 'flags'
env_mmc.c:267: error: 'env_t' has no member named 'flags'
make[1]: *** [env_mmc.o] Error 1
--->8---

Add this patch to fix it

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Reviewed-by: Michael Heimpold <mhei@heimpold.de>
Signed-off-by: Andy Fleming <afleming@freescale.com>
11 years agoMerge branch 'master' of git://git.denx.de/u-boot-spi
Tom Rini [Thu, 13 Jun 2013 19:18:35 +0000 (15:18 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-spi

11 years agoMerge branch 'master' of git://git.denx.de/u-boot-arm
Tom Rini [Thu, 13 Jun 2013 19:16:15 +0000 (15:16 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-arm

Small conflict over DRA7XX updates and adding SRAM_SCRATCH_SPACE_ADDR

Conflicts:
arch/arm/include/asm/arch-omap5/omap.h

Signed-off-by: Tom Rini <trini@ti.com>
11 years agosf: winbond: Correct the nr_blocks used for W25Q32DW
Jagannadha Sutradharudu Teki [Fri, 24 May 2013 20:43:41 +0000 (02:13 +0530)]
sf: winbond: Correct the nr_blocks used for W25Q32DW

This patch corrected the nr_blocks used for W25Q32DW SPI flash.

nr_blcoks are incorrectly assigned on below patch
"sf: winbond: add W25Q32DW"
(sha1: 772ba15474f73adc942e817cc072b6e9750836cc)

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
11 years agosf: winbond: Add support for W25Q80BW
Jagannadha Sutradharudu Teki [Mon, 27 May 2013 07:20:50 +0000 (12:50 +0530)]
sf: winbond: Add support for W25Q80BW

Add support for Winbond W25Q80BW SPI flash.

This patch corrected the flash name, nr_blocks and
also commit message header from below patch.
"sf: winbond: add W25Q32"
(sha1: c969abc47033d6f810d3c9dbdb994ea9d691d038)

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
11 years agosf: spansion: Update the name for S25FL256S flash
Jagannadha Sutradharudu Teki [Sat, 25 May 2013 17:33:11 +0000 (23:03 +0530)]
sf: spansion: Update the name for S25FL256S flash

As the per the ID tabl the flash is under Uniform 64-kB sector
architecture, hence updated with proper name.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
11 years agospi: tegra20_sflash: Remove redundant code to set bus and cs of struct spi_slave
Axel Lin [Thu, 13 Jun 2013 08:21:42 +0000 (16:21 +0800)]
spi: tegra20_sflash: Remove redundant code to set bus and cs of struct spi_slave

It's done in spi_alloc_slave(), thus remove the redundant code.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
11 years agospi: tegra114_spi: Convert to use spi_alloc_slave()
Axel Lin [Thu, 13 Jun 2013 08:17:47 +0000 (16:17 +0800)]
spi: tegra114_spi: Convert to use spi_alloc_slave()

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
11 years agospi: armada100_spi: Remove unnecessary NULL test for dout and din
Axel Lin [Tue, 11 Jun 2013 13:57:31 +0000 (21:57 +0800)]
spi: armada100_spi: Remove unnecessary NULL test for dout and din

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
11 years agoMerge branch 'master' of git://git.denx.de/u-boot-usb
Tom Rini [Wed, 12 Jun 2013 20:33:49 +0000 (16:33 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-usb

11 years agoarm: pxa: config option for PXA270 turbo mode
Sergey Yanovich [Tue, 21 May 2013 19:49:41 +0000 (23:49 +0400)]
arm: pxa: config option for PXA270 turbo mode

PXA270 CPU has turbo mode. The mode is 2.5 times faster than the
default run mode. Activating the mode early significantly speeds
up boot process.

Signed-off-by: Sergey Yanovich <ynvich@gmail.com>
11 years agoarm: pxa: Add support for ICP DAS LP-8x4x
Sergey Yanovich [Mon, 20 May 2013 21:26:00 +0000 (01:26 +0400)]
arm: pxa: Add support for ICP DAS LP-8x4x

LP-8x4x is a programmable automation controller by ICP DAS. It is
shipped with outdated U-Boot v1.3.0

This patch adds enough supports to boot the board:
 - 128M of 128M SDRAM
 - 32M of 48M NOR Flash memory
 - 1 of 4 Serial consoles (PXA FFUART)
 - 2 of 2 Ethernet controllers (DM9000)

Signed-off-by: Sergey Yanovich <ynvich@gmail.com>
Series-to: u-boot
Series-cc: marex

11 years agousb, composite: after unregister gadget driver set composite to NULL
Heiko Schocher [Tue, 4 Jun 2013 09:21:32 +0000 (11:21 +0200)]
usb, composite: after unregister gadget driver set composite to NULL

Without this, second usb_composite_register() call fails always
with -EINVAL.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Marek Vasut <marex@denx.de>
11 years agousb: ehci: add missing cache managment
Stephen Warren [Fri, 24 May 2013 21:03:17 +0000 (15:03 -0600)]
usb: ehci: add missing cache managment

Commit 8f62ca6 "usb: ehci: Support interrupt transfers via periodic list"
didn't include any cache management in the new interrupt transfer path.
It also added an extra write to or_asynclistaddr in usb_lowlevel_init(),
without having flushed out the data there.

Add the missing cache management calls, so that the code works again.

This allows the USB keyboard on Tegra's Seaboard/Springbank boards to
work.

Cc: Patrick Georgi <patrick@georgi-clan.de>
Cc: Vincent Palatin <vpalatin@chromium.org>
Cc: Julius Werner <jwerner@chromium.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
11 years agousb: gadget: add Faraday FOTG210 USB gadget support
Kuo-Jung Su [Wed, 15 May 2013 07:29:24 +0000 (15:29 +0800)]
usb: gadget: add Faraday FOTG210 USB gadget support

The Faraday FOTG210 is an OTG chip which could operate
as either an EHCI Host or a USB Device at a time.

Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com>
CC: Marek Vasut <marex@denx.de>
11 years agousb: ehci: add Faraday USB 2.0 EHCI support
Kuo-Jung Su [Wed, 15 May 2013 07:29:23 +0000 (15:29 +0800)]
usb: ehci: add Faraday USB 2.0 EHCI support

This patch adds support to both Faraday FUSBH200 and FOTG210,
the differences between Faraday EHCI and standard EHCI are
listed bellow:

1. The PORTSC starts at 0x30 instead of 0x44.
2. The CONFIGFLAG(0x40) is not only un-implemented, and
   also has its address space removed.
3. Faraday EHCI is a TDI design, but it doesn't
   compatible with the general TDI implementation
   found at both U-Boot and Linux.
4. The ISOC descriptors differ from standard EHCI in
   several ways. But since U-boot doesn't support ISOC,
   we don't have to worry about that.

Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com>
CC: Marek Vasut <marex@denx.de>
11 years agousb: hub: make minimum power-on delay configurable
Kuo-Jung Su [Wed, 15 May 2013 07:29:22 +0000 (15:29 +0800)]
usb: hub: make minimum power-on delay configurable

This patch makes the minimum power-on delay for USB HUB
become configurable. The original design waits at least
100 msec here, but some EHCI controlers(e.g. Faraday EHCI)
are known to require much longer delay interval.

Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com>
CC: Marek Vasut <marex@denx.de>
11 years agousb: ehci: add weak-aliased function for PORTSC
Kuo-Jung Su [Wed, 15 May 2013 07:29:21 +0000 (15:29 +0800)]
usb: ehci: add weak-aliased function for PORTSC

There is at least one non-EHCI compliant controller (i.e. Faraday EHCI)
not only leave RESERVED and CONFIGFLAG registers un-implemented
but also has their address spaces removed.

As an result, the PORTSC register of Faraday EHCI always
starts from 0x30 instead of 0x44 in standard EHCI.

So that we'll need a weak-aliased function for abstraction.

Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com>
CC: Marek Vasut <marex@denx.de>
11 years agousb: ehci: prevent bad PORTSC register access
Kuo-Jung Su [Wed, 15 May 2013 07:29:20 +0000 (15:29 +0800)]
usb: ehci: prevent bad PORTSC register access

1. The 'index' of ehci_submit_root() is not always > 0.

   e.g.
   While it gets invoked from usb_get_descriptor(),
   the 'index' is always a '0'. (See ch.9 of USB2.0)

2. The PORTSC register is not always required, and thus it
   should only report a port error when necessary.
   It would cause a port scan failure if the ehci_submit_root()
   always gets terminated by a port error.

Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com>
CC: Marek Vasut <marex@denx.de>
11 years agousb: gadget: Use unaligned access for wMaxPacketSize
Vivek Gautam [Mon, 13 May 2013 10:23:38 +0000 (15:53 +0530)]
usb: gadget: Use unaligned access for wMaxPacketSize

Use get_unaligned() while fetching wMaxPacketSize to avoid
voilating any alignment rules.

Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Piotr Wilczek <p.wilczek@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Lukasz Dalek <luk0104@gmail.com>
Cc: Marek Vasut <marex@denx.de>
11 years agousb: Use get_unaligned() in usb_endpoint_maxp() for wMaxPacketSize
Vivek Gautam [Mon, 13 May 2013 10:23:37 +0000 (15:53 +0530)]
usb: Use get_unaligned() in usb_endpoint_maxp() for wMaxPacketSize

Use unaligned access to fetch wMaxPacketSize in usb_endpoint_maxp()
api.
In its absence we see following data abort message:
==============================================================
data abort

    MAYBE you should read doc/README.arm-unaligned-accesses

pc : [<bf794e24>]          lr : [<bf794e1c>]
sp : bf37c7b0  ip : 0000002f     fp : 00000000
r10: 00000000  r9 : 00000002     r8 : bf37fecc
r7 : 00000001  r6 : bf7d8931     r5 : bf7d891c  r4 : bf7d8800
r3 : bf7d65b0  r2 : 00000002     r1 : bf7d65b4  r0 : 00000027
Flags: nZCv  IRQs off  FIQs off  Mode SVC_32
Resetting CPU ...

resetting ...
==============================================================

Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Cc: Ilya Yanok <ilya.yanok@cogentembedded.com>
Cc: Marek Vasut <marex@denx.de>
11 years agousb: asix: Move software resets to basic_init
Julius Werner [Sat, 11 May 2013 20:35:02 +0000 (13:35 -0700)]
usb: asix: Move software resets to basic_init

The ASIX driver calls a basic_init() function during get_info(), so that
not all initialization tasks need to be redone on every init().
Unfortunately, the most important one is still triggered too often: the
driver does a full port and MII reset on every asix_init(), requiring up
to several seconds to reestablish the link.

This patch confines that software reset into the asix_basic_init()
function so that it will only be executed once. This saves about a
second of boot time on systems using BOOTP.

Note: this patch was previously submitted many moons ago as:

   usb: usbeth: asix: Do a fast init if link already established

That patch seens to have been lost or forgotten, so this is a rebased
version. It is tested on snow with a Asix USB dongle (Cisco).

Signed-off-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
11 years agousb: Correct CLEAR_FEATURE code in ehci-hcd
Simon Glass [Sat, 11 May 2013 02:49:00 +0000 (19:49 -0700)]
usb: Correct CLEAR_FEATURE code in ehci-hcd

This commit broke USB2 on link (Chromebook Pixel):

  020bbcb usb: hub: Power-cycle on root-hub ports

However the root cause seems to be a missing mask and missing 'break'
in ehci-hcd.c. This patch fixes both.

On link, 'usb start' with a USB keyboard and memory stick inserted now
finds both. The keyboard works as expected. Also ext2ls shows a directory
listing from the memory stick.

Signed-off-by: Simon Glass <sjg@chromium.org>
11 years agousb: workaround non-working keyboards.
Vincent Palatin [Sat, 11 May 2013 02:48:59 +0000 (19:48 -0700)]
usb: workaround non-working keyboards.

If the USB keyboard is not answering properly the first request on its
interrupt endpoint, just skip it and try the next one.

This workarounds an issue with a wireless mouse dongle which presents
itself both as a keyboard and a mouse but has a non-functional keyboard
interface.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
(cherry picked from commit 012bbf0ce0301be2482857e3f03b481dd15c2340)
Rebased to upstream/master:
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
11 years agousb: properly re-initialize the USB keyboard.
Vincent Palatin [Sat, 11 May 2013 02:48:58 +0000 (19:48 -0700)]
usb: properly re-initialize the USB keyboard.

Allow to reconfigure properly the USB keyboard driver when we enumerate
several times the USB devices and its position in the device tree has
changes.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
11 years agoMerge branch 'master' of git://git.denx.de/u-boot-74xx-7xx
Tom Rini [Tue, 11 Jun 2013 22:11:47 +0000 (18:11 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-74xx-7xx

11 years agoppc: ppmc7xx: Fix possible out-of-bound access
Marek Vasut [Mon, 20 May 2013 03:01:40 +0000 (05:01 +0200)]
ppc: ppmc7xx: Fix possible out-of-bound access

The flash_info_t->start[] field is limited in size by CONFIG_SYS_MAX_FLASH_SECT
macro, which is set to 19 for this board in the board config file. If we inspect
the board/ppmc7xx/flash.c closely, especially the flash_get_size() function, we
can notice the "switch ((long)flashtest)" at around line 80 having a few results
which will set flash_info_t->sector_count to value higher than 19, for example
"case AMD_ID_LV640U" will set it to 128. Notice that right underneath, iteration
over flash_info_t->start[] happens and the upper bound for the interation is
flash_info_t->sector_count. Now if the sector_count is 128 as it is for the
AMD_ID_LV640U case, but the CONFIG_SYS_MAX_FLASH_SECT limiting the start[] is
only 19, an access past the start[] array much happen. Moreover, during this
iteration, the field is written to, so memory corruption is inevitable.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Richard Danter <richard.danter@windriver.com>
11 years agopowerpc: fix 8xx and 82xx type-punning warnings with GCC 4.7
Scott Wood [Sat, 18 May 2013 01:01:54 +0000 (20:01 -0500)]
powerpc: fix 8xx and 82xx type-punning warnings with GCC 4.7

C99's strict aliasing rules are insane to use in low-level code such as a
bootloader, but as Wolfgang has rejected -fno-strict-aliasing in the
past, add a union so that 16-bit accesses can be performed.

Compile-tested only.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Acked-by: Wolfgang Denk <wd@denx.de>
11 years agocosmetic: arm: fix comments in arch/arm/lib/crt0.S
Masahiro Yamada [Wed, 15 May 2013 08:33:16 +0000 (17:33 +0900)]
cosmetic: arm: fix comments in arch/arm/lib/crt0.S

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
11 years agoMerge branch 'u-boot-ti/master' into 'u-boot-arm/master'
Albert ARIBAUD [Mon, 10 Jun 2013 16:28:37 +0000 (18:28 +0200)]
Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'

11 years agoarm/km: make local functions static
Holger Brunck [Mon, 6 May 2013 13:04:51 +0000 (15:04 +0200)]
arm/km: make local functions static

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
11 years agoarm: da830: moved pinmux configurations to the arch tree
Vishwanathrao Badarkhe, Manish [Wed, 29 May 2013 21:55:11 +0000 (21:55 +0000)]
arm: da830: moved pinmux configurations to the arch tree

Move pinmux configurations for the DA830 SoCs from board file
to the arch tree so that it can be used for all da830 based devices.
Also, avoids duplicate pinmuxing in case of NAND.

Signed-off-by: Vishwanathrao Badarkhe, Manish <manishv.b@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Acked-by: Christian Riesch <christian.riesch@omicron.at>
11 years agoARM: DRA7: Add Maintainer
Lokesh Vutla [Fri, 7 Jun 2013 00:59:02 +0000 (00:59 +0000)]
ARM: DRA7: Add Maintainer

Adding Maintainer for DRA7xx.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
11 years agoOMAP5: Enable access to auxclk registers
Lubomir Popov [Wed, 15 May 2013 04:41:01 +0000 (04:41 +0000)]
OMAP5: Enable access to auxclk registers

auxclk0 and auxclk1 are utilized on some OMAP5 boards.
Define the infrastructure needed for accessing them
without using magic numbers.

Also remove unrelated TPS62361 defines from clocks.h

Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
11 years agoARM: OMAP: I2C: New read, write and probe functions
Lubomir Popov [Sat, 1 Jun 2013 06:44:38 +0000 (06:44 +0000)]
ARM: OMAP: I2C: New read, write and probe functions

New i2c_read, i2c_write and i2c_probe functions, tested on OMAP4
(4430/60/70), OMAP5 (5430) and AM335X (3359); should work on older
OMAPs and derivatives as well. The only anticipated exception would
be the OMAP2420, which shall require driver modification.
- Rewritten i2c_read to operate correctly with all types of chips
  (old function could not read consistent data from some I2C slaves).
- Optimised i2c_write.
- New i2c_probe, performs write access vs read. The old probe could
  hang the system under certain conditions (e.g. unconfigured pads).
- The read/write/probe functions try to identify unconfigured bus.
- Status functions now read irqstatus_raw as per TRM guidelines
  (except for OMAP243X and OMAP34XX).
- Driver now supports up to I2C5 (OMAP5).

Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
Tested-by: Heiko Schocher <hs@denx.de>
11 years agoarm: Remove OMAP2420H4 and all omap24xx support
Tom Rini [Tue, 4 Jun 2013 12:02:06 +0000 (12:02 +0000)]
arm: Remove OMAP2420H4 and all omap24xx support

The omap2420H4 was the only mainline omap24xx board.  Prior to being
fixed by Jon Hunter in time for v2013.04 it had been functionally broken
for a very long time.  Remove this board as there's not been interest in
it in U-Boot for quite a long time.

Signed-off-by: Tom Rini <trini@ti.com>
11 years agoda830: add MMC support
Vishwanathrao Badarkhe, Manish [Wed, 22 May 2013 03:38:48 +0000 (03:38 +0000)]
da830: add MMC support

Add MMC support for da830 boards in order to perform
mmc operations(read,write and erase).

Signed-off-by: Vishwanathrao Badarkhe, Manish <manishv.b@ti.com>
11 years agoARM: OMAP5: Power: Add more functionality to Palmas driver
Lubomir Popov [Thu, 6 Jun 2013 04:16:40 +0000 (04:16 +0000)]
ARM: OMAP5: Power: Add more functionality to Palmas driver

Add some useful functions, and the corresponding definitions.

Add support for powering on the dra7xx_evm SD/MMC LDO
(courtesy Lokesh Vutla <lokeshvutla@ti.com>).

Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
Reviewed-by: Tom Rini <trini@ti.com>
11 years agoARM: DRA7xx: EMIF: Change settings required for EVM board
Sricharan R [Thu, 30 May 2013 03:19:39 +0000 (03:19 +0000)]
ARM: DRA7xx: EMIF: Change settings required for EVM board

DRA7 EVM board has the below configuration. Adding the
settings for the same here.

   2Gb_1_35V_DDR3L part * 2 on EMIF1
   2Gb_1_35V_DDR3L part * 4 on EMIF2

Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
11 years agoARM: DRA7xx: clocks: Update PLL values
Lokesh Vutla [Thu, 30 May 2013 03:19:38 +0000 (03:19 +0000)]
ARM: DRA7xx: clocks: Update PLL values

Update PLL values.
SYS_CLKSEL value for 20MHz is changed to 2. In other platforms
SYS_CLKSEL value 2 represents reserved. But in sys_clk array
ind 1 is used for 13Mhz. Since other platforms are not using
13Mhz, reusing index 1 for 20MHz.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
11 years agoARM: DRA7xx: Update pinmux data
Lokesh Vutla [Thu, 30 May 2013 03:19:37 +0000 (03:19 +0000)]
ARM: DRA7xx: Update pinmux data

Updating pinmux data as specified in the latest DM

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Balaji T K <balajitk@ti.com>
11 years agommc: omap_hsmmc: Update pbias programming
Balaji T K [Thu, 6 Jun 2013 05:04:32 +0000 (05:04 +0000)]
mmc: omap_hsmmc: Update pbias programming

Update pbias programming sequence for OMAP5 ES2.0/DRA7

Signed-off-by: Balaji T K <balajitk@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
11 years agoARM: DRA7xx: Correct SRAM END address
Sricharan R [Thu, 30 May 2013 03:19:35 +0000 (03:19 +0000)]
ARM: DRA7xx: Correct SRAM END address

NON SECURE SRAM is 512KB in DRA7xx devices.
So fixing it here.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
11 years agoARM: DRA7xx: Correct the SYS_CLK to 20MHZ
Sricharan R [Thu, 30 May 2013 03:19:34 +0000 (03:19 +0000)]
ARM: DRA7xx: Correct the SYS_CLK to 20MHZ

The sys_clk on the dra evm board is 20MHZ.
Changing the configuration for the same.
And also moving V_SCLK, V_OSCK defines to
arch/clock.h for OMAP4+ boards.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
11 years agoARM: DRA7xx: Change the Debug UART to UART1
Sricharan R [Thu, 30 May 2013 03:19:33 +0000 (03:19 +0000)]
ARM: DRA7xx: Change the Debug UART to UART1

Serial UART is connected to UART1. So add the change
for the same.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
11 years agoARM: DRA7xx: Do not enable srcomp for DRA7xx Soc's
Lokesh Vutla [Thu, 30 May 2013 03:19:32 +0000 (03:19 +0000)]
ARM: DRA7xx: Do not enable srcomp for DRA7xx Soc's

Slew rate compensation cells are not present for DRA7xx
Soc's. So return from function srcomp_enable() if soc is not
OMAP54xx.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
11 years agoARM: OMAP5: DRA7xx: support class 0 optimized voltages
Nishanth Menon [Thu, 30 May 2013 03:19:31 +0000 (03:19 +0000)]
ARM: OMAP5: DRA7xx: support class 0 optimized voltages

DRA752 now uses AVS Class 0 voltages which are voltages in efuse.

This means that we can now use the optimized voltages which are
stored as mV values in efuse and program PMIC accordingly.

This allows us to go with higher OPP as needed in the system without
the need for implementing complex AVS logic.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
11 years agoARM: DRA7xx: clocks: Fixing i2c_init for PMIC
Lokesh Vutla [Thu, 30 May 2013 03:19:30 +0000 (03:19 +0000)]
ARM: DRA7xx: clocks: Fixing i2c_init for PMIC

In DRA7xx Soc's voltage scaling is done using GPI2C.
So i2c_init should happen before scaling. I2C driver
uses __udelay which needs timer to be initialized.
So moving timer_init just before voltage scaling.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
11 years agoARM: DRA7xx: power Add support for tps659038 PMIC
Lokesh Vutla [Thu, 30 May 2013 03:19:29 +0000 (03:19 +0000)]
ARM: DRA7xx: power Add support for tps659038 PMIC

TPS659038 is the power IC used in DRA7XX boards.
Adding support for this and also adding pmic data
for DRA7XX boards.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
11 years agoARM: DRA7xx: Add control id code for DRA7xx
Lokesh Vutla [Thu, 30 May 2013 03:19:28 +0000 (03:19 +0000)]
ARM: DRA7xx: Add control id code for DRA7xx

The registers that are used for device identification
are changed from OMAP5 to DRA7xx.
Using the correct registers for DRA7xx.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
11 years agoARM: OMAP4+: pmic: Make generic bus init and write functions
Lokesh Vutla [Thu, 30 May 2013 02:54:33 +0000 (02:54 +0000)]
ARM: OMAP4+: pmic: Make generic bus init and write functions

Voltage scaling can be done in two ways:
-> Using SR I2C
-> Using GP I2C
In order to support both, have a function pointer in pmic_data
so that we can call as per our requirement.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
11 years agoARM: OMAP2+: Rename asm/arch/clocks.h asm/arch/clock.h
Lokesh Vutla [Thu, 30 May 2013 02:54:32 +0000 (02:54 +0000)]
ARM: OMAP2+: Rename asm/arch/clocks.h asm/arch/clock.h

To be consistent with other ARM platforms,
renaming asm/arch-omap*/clocks.h to asm/arch-omap*/clock.h

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
11 years agoARM: OMAP5: clocks: Do not enable sgx clocks
Sricharan R [Thu, 30 May 2013 02:54:31 +0000 (02:54 +0000)]
ARM: OMAP5: clocks: Do not enable sgx clocks

SGX clocks should be enabled only for OMAP5 ES1.0.
So this can be removed.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
11 years agoARM: OMAP4+: Cleanup header files
Lokesh Vutla [Thu, 30 May 2013 02:54:30 +0000 (02:54 +0000)]
ARM: OMAP4+: Cleanup header files

After having the u-boot clean up series, there are
many definitions that are unused in header files.
Removing all those unused ones.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
11 years agoOMAP5: Fix bug in omap5_es1_prcm struct
Lubomir Popov [Sun, 26 May 2013 10:03:17 +0000 (10:03 +0000)]
OMAP5: Fix bug in omap5_es1_prcm struct

The newly introduced function setup_warmreset_time(), called
from within prcm_init(), tries to write to the prm_rsttime
OMAP5 register. The struct member holding this register's
address is however initialized for OMAP5 ES2.0 only. On ES1.0
devices this uninitialized value causes a second (warm) reset
at startup.

Add .prm_rsttime address init to the ES1.0 struct.

Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
Acked-by: Tom Rini <trini@ti.com>