asahi: Merge fragment control XML

Same struct specified twice and merged in the hw.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21081>

asahi: Remove redundant tri merge disable bit

Cargoculted from Metal.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21081>

asahi: DRY dirty tracking conditions

Ella did this in agxv and it made a lot more sense than the copypasta I did.
Should get copypropped to similar code.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21081>

asahi: Implement nontrivial rasterizer discard

For vertex shaders with side effects, as seen with transform feedback.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21081>

asahi: Prefer blit-based texture transfer

This speeds up glReadPixels. Instead of reading from the write-combined
framebuffer and converting colours on the CPU, this blits on the GPU to a
writeback staging resource with the colour conversion for free, and memcpies
from the writeback staging resource on the CPU.

In general, due to textures being write combined and tiled/compressed by default
by staging resources being linear writeback, blit-based texture transfer should
win out (you were going to blit anyway), particularly when format conversion is
involved

33% reduction in wall clock time for grim at 4K. No change in deqp-gles2
runtime.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21063>

asahi: Make STAGING resources linear

As intended by the flag.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21063>

asahi: Use writeback when it looks beneficial

When playing the My Little Pony theme song at 1080p on T8103, with mpv's GPU
compositing but software decoding, CPU usage drops from 200% to 50% due to
proper caching of the staging resource.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21063>

asahi: Refuse to transfer out-of-bounds mip levels

Fixes ail asserts on a pile of dEQP3 tests.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21063>

agx: Support uniform registers as LODs

This will avoid regressing moves when we lower sampler LOD bias. Corresponding
disassembler change: https://github.com/dougallj/applegpu/pull/22

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20833>

asahi: Correct alignment for USC Uniform packets

We only need 4 byte alignment, not 8 bytes. This isn't a big difference in
practice, but it probably reduces padding in some cases. More importantly, it
corrects our XML to match what the hardware actually does, which is great.
(There is exactly enough room for a 40-bit address with 4 byte alignment.)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21118>

asahi/nir_lower_sysvals: Split large ranges

It is our responsibility to ensure uniform ranges don't exceed 64 uniforms.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21118>

asahi: Strengthen agx_usc_uniform contract

Check the size explicitly, instead of just implicitly in the GenXML pack: it is
the responsibility of the caller to split up larger uploads. While this is
nominally more complicated, agx_usc_uniform is called in the draw hot path
whereas the actual splitting decision can usually be done at compile-time.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21118>

asahi: Fix encoding of uniform size

Only 6-bits, with zero=64 like a groups() encoding.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Suggested-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21118>

asahi: Set layout->mipmapped_z for 3D textures

There's a corner case where 3D textures have extra padding compared to 2D
arrays. We need to communicate that to ail.

Fixes
dEQP-GLES3.functional.texture.specification.texstorage3d.size.3d_32x16x64_4_levels.
That test now uses the same layout as Metal.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21114>

ail: Test 63x63 cube map

This has a subtle interaction with page-aligned layers. Written while debugging
dEQP-GLES3.functional.texture.filtering.cube.combinations.nearest_nearest_repeat_clamp

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21114>

ail: Test mipmapped_z behaviour

The mipmapped_z = true case is checked against Metal, the false case is smoke
testing the old behaviour (which is still used for 2D arrays).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21114>

ail: Add layout->mipmapped_z input

For 3D images, the full miptree depends on the depth of the image, in contrast
to 2D arrays. We need to account for this to calculate the correct layer
strides.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21114>

ci: disable Collabora's LAVA lab for maintance

This is to inform you of some planned downtime in the LAVA lab as follows:

    Start: 2023-02-04 06:00 GMT
    End: 2023-02-06 12:00 GMT

Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21119>

nir: Eliminate nir_op_f2b

Builds on the work of !15121.  This gets to delete even more code
because many drivers shared a lot of code for i2b and f2b.

No shader-db or fossil-db changes on any Intel platform.

v2: Rebase on 1a35acd8d9006c9.

v3: Update a comment in nir_opcodes_c.py. Suggested by Konstantin.

v4: Another rebase. Remove f2b stuff from Midgard.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20509>

nir/builder: Handle f2b conversions specially in nir_type_convert

No shader-db or fossil-db changes on any Intel platform.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20509>

nir/builder: Eliminate nir_f2b helper (and use of nir_f2b32 helper)

There were only two users. Replace each with nir_fneu instead.

This is now a squash of what was two separate commits.
nir_lower_pstipple_block is called after nir_lower_bool_to_int32, so
nir_fneu32 has to be used here or there will be regresssions in stipple
tests on llvmpipe.

v2: Rebase on !20869.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Suggested-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20509>

zink: add back VK_DESCRIPTOR_BINDING_PARTIALLY_BOUND_BIT for bindless

this was accidentally lost in refactor

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21100>

zink: handle missing line rasterization modes with ds3

it's annoying to validate this at runtime since it has to happen during draw,
but storing the "usable" ds3 mode separately from the pipeline state should
be a reasonable enough compromise for perf here...hopefully

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21100>

zink: cache and reuse dummy inputattachment for fbfetch

apparently an actual null descriptor is illegal here, and it's wasted cpu
anyway, so just cache the dummy surface on init and use that data when
fbfetch isn't active but the layout requires it

Fixes: 7ab5c5d36d2 ("zink: use EXT_descriptor_buffer with ZINK_DESCRIPTORS=db")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21100>

zink: fix more cases of heap/memtype suballocator mismatch

suballocation must happen based on the memtype, so also add some asserts to
ensure the slab bos are always what the caller expects

Fixes: f6d3a5755f6 ("zink: zink_heap isn't 1-to-1 with memoryTypeIndex")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21100>

zink: free descriptor buffer maps on batch state destroy

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21100>

zink: fix sparse residency query and minLOD feature checks

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21013>

venus: lazily query and cache gralloc front rendering usage

When skiavk is the default system ui renderer, venus icd gets preloaded
into Zygote. However, Zygote access to render node is normally denied by
selinux except for legacy bootanimation purpose. This change fixes venus
icd loading to avoid invoking cros gralloc driver loading by moving the
perform op outside, so that we still get the memory footprint win.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21107>

ci/llvmpipe: Drop skip of InteractionFunctionCalls2.

This one is down to <5 seconds here these days.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21084>

ci/swrast: Drop skips for tests whose perf had been fixed.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21084>

gallivm: Do the same codegen improvement for constant-index array loads.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21084>

gallivm: Fix codegen performance for constant-index register array stores.

Instead of generating num_components*simdwidth scattered stores, if
there's no indirect then we can just look up the pointer to the
base_offset and do a simd store there.

dEQP-VK.subgroups.ballot_broadcast.compute.subgroupbroadcast_i64vec4 goes
from 30s to ~2s.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21084>

gallivm: Fix the type of array nir_registers.

This now matches how they get dereffed by get_soa_array_offsets() -- each
array element has num_components vecs inside of it, rather than each
components has an array in it.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21084>

gallivm: Enable GALLIVM_DEBUG (mostly) on non-DEBUG builds.

This is what let me do the performance work in my recent gallivm MRs.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21086>

llvmpipe: Enable LP_DEBUG on normal builds.

I don't typically include DEBUG because it sometimes has expensive debug
code, but these options are not that.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21086>

meson: combine checks for linker --gc-sections support

We first do an incomplete check for whether the linker supports
--gc-sections, then potentially add C and C++ arguments assuming that it
works, then later do a complete check to see if it actually works and
use --gc-sections. This means we can end up putting functions and data
in separate sections when we can't gc them.

Combine the checks, do less work, and be more accurate.

fixes: f51ce21e4e0bf7efabe58afb4a2cd6b9f98d9505
       ("meson: Drop adding -Wl,--gc-sections to project c/cpp arguments.")

Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21083>

panfrost: Implement GL_EXT_render_snorm on Bifrost+

It turns out it's really easy.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20684>

ci/lvp: Drop the subgroupbroadcast skips.

These have the same runtime as the others in the group, and with these
optimizations they no longer time out.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21001>

gallivm: Use first active invocation in some image/ssbo accesses.

These should be looking at that rather than blindly using invocation 0
(which may be junk when in control flow).

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21001>

gallivm: Use cttz instead of a loop for first_active_invocation().

This should be way faster to compile by not spamming so many loops at
LLVM, and faster to execute if LLVM didn't figure out what that loop
meant.

It looks vector reduce ops aren't really a thing, just a convenience in
the IR.  We should be able to do better by counting zeroes in the
exec_mask != 0 result.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21001>

gallivm: Return 0 first_active_invocation when we know that up front.

46 -> 30 seconds on
dEQP-VK.subgroups.ballot_broadcast.compute.subgroupbroadcast_i16vec4 by
not spamming LLVM with so many loops.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21001>

gallivm: Refactor out a shared "get the first active invocation" loop.

Dynamic texture indices had a similar "find an active channel" loop,
though it happened to use the last active channel rather than the first.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21001>

gallivm: Optimize emit_read_invocation's first-invocation loop.

We don't need to deref invoc inside -- invoc is uniform in active
channels, so we can find our first active invocation in the loop, and then
dereference invocation once outside.

50 -> 46 seconds on
dEQP-VK.subgroups.ballot_broadcast.compute.subgroupbroadcast_i16vec4

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21001>

asahi: Lower texcoords late

This uses the new pass to lower tex coordinates late, which gets us one step
closer to preprocessing NIR at CSO create time instead of variant create time.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21065>

asahi: Run nir_lower_fragcolor during preprocessing

This pass needs to run early (because it depends on early I/O), but it doesn't
actually need the shader key. Why not? If we overestimate the number of render
targets, extra store_output intrinsics will be generated, but they will be
deleted by AGX tilebuffer lowering later.

Note we'll probably want something smarter than this for fragment epilogues in
the future to avoid piles of unnecessary moves.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21065>

nir: Add a late texcoord replacement pass

Add a second NIR pass for lowering point/texture coordinate replacement (i.e.
point sprites). Why a second one? The current pass works on derefs/variables,
which is good for drivers that don't lower I/O at all (like Zink, where the pass
originates). However, it is problematic for hardware drivers: the inputs to this
pass depend on the shader key, so we want to run the pass as late as possible to
minimize the cost of building/compiling the associated shader variants. In
particular, we need to be able to lower point sprites after lowering I/O if we
would like to lower I/O when preprocessing NIR.

The logic for early lowering and late lowering is considerably different (the
late lowering is a lot simpler), so I've split this out into a second pass
rather than trying to weld them together into one.

This pass will be used on Asahi, which currently uses the early pass. It may be
useful for other drivers as well. (Actually, it's been shipping on Asahi for a
little while now, just hasn't been sent upstream yet.)

Tested with Neverball.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Emma Anholt <emma@anholt.net>
Acked-by: Asahi Lina <lina@asahilina.net>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21065>

radv: Work around shader_call_data variables in raygen shaders

Closes: #5326
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20930>

ci/lavapipe: use dxvk for the traces

Since the job is manual, this stayed overlooked.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20875>

ci: uprev piglit (etag md5 checksumming support)

Support for FDO etag http header.

Includes line-smooth-stipple test improvements.

Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Acked-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20875>

aco: remove early_rast wait insert

It's done in nir position export.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>

nir,ac/llvm,aco,radv,radeonsi: remove nir_export_vertex_amd

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>

nir,ac/llvm,aco: remove nir_export_primitive_amd

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>

ac/nir/ngg,radv: ms use ac_nir_export_(primitive|position|parameter)

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>

ac/nir/ngg: gs use ac_nir_export_(position|parameter)

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>

ac/nir/ngg: prepare gather_vs_outputs to be used by gs

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>

ac/nir/ngg,radv,radeonsi: nogs use ac_nir_export_(position|parameter)

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>

ac/nir/ngg: change clipdist_neg_mask_var type to uint32

ACO does not support 8bit ALU ops.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>

ac/nir/ngg: fix clip dist culling mask uninitialized

Fixes: f75452918b2 ("ac/nir/ngg: support clipdist culling")
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>

ac/nir,radv,radeonsi: gs copy shader use ac_nir_export_(position|parameter)

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>

ac/nir,radv,radeonsi: legacy vs use ac_nir_export_(position|parameter)

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>

radeonsi: set nr_pos_exports outside of llvm translation

This can save an abi interface when we share position export
code with RADV.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>

radeonsi: remove the extra handling for VS/TES primitive id

We have moved si_nir_assign_param_offsets before output lowering
pass, so there won't be primitive id store output when VS/TES here.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>

radeonsi: update outputs written nir info

We may remove some outputs when si_nir_kill_outputs and
ac_nir_optimize_outputs, so update the outputs written
info for output lower pass to skip manipulating these
outputs.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>

radeonsi: clamp vertex color in legacy gs instead of gs copy shader

gs copy shader is going to emit nir_export_amd directly so this vertex
color clamp pass which apply to nir_store_output will not work.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>

amd,radeonsi: implement nir_load_force_vrs_rates_amd in driver abi

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>

ac/nir: add force_vrs to ac_nir_export_position

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>

ac/nir: add ac_nir_export_parameter

For last VGT stage to export parameter outputs.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>

ac/nir: add ac_nir_export_position

Used by last VGT stage to export position related outputs.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>

ac/nir: gs and nogs use ac_nir_export_primitive

Mesh shader primitive export is left unchanged because it needs
extra changes for per primitive output export when export
primitive.

Mesh shader will use second channel of primitive export.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>

aco: implement nir_export_amd

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>

ac/llvm: implement nir_export_amd

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>

nir: add nir_export_amd intrinsic

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20691>

ac/nir/cull: Alway remove zero-area triangles in face culling.

The face culling algorithm should have been disabled for
conservative overestimation because it already
(mistakenly) removed some close-to-zero area triangles.

Now that the driver disables it in that case,
let's always remove zero-area triangles.
This only costs +2 SALU instructions.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20987>

radv: Disable NGG culling when conservative overestimation is used.

Even when small primitive culling is disabled, the face culling algorithm
in ac_nir_cull can delete tiny triangles when their area is almost zero.

Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20987>

anv: handle ATTACHMENT_OPTIMAL layout

Closes: #8216
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21066>

util: Implement util_iround with lrintf unconditionally

Because the place that called util_iround are always ensured
that INT_MIN <= f <= INT_MAX

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19978>

zink: enable bindless texture with ZINK_DESCRIPTORS=db

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21085>

zink: implement descriptor buffer handling of bindless texture

pretty straightforward, just lazily allocating the context-based db
and then writing updates to it on-demand

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21085>

zink: add a flag to indicate whether a descriptor buffer is bound

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21085>

zink: break out descriptor binding into separate function

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21085>

zink: set VK_PIPELINE_CREATE_DESCRIPTOR_BUFFER_BIT_EXT on compute pipelines

same as gfx

Fixes: 7ab5c5d36d2 ("zink: use EXT_descriptor_buffer with ZINK_DESCRIPTORS=db")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21085>

zink: skip updating descriptor buffer sets that aren't active

this is a no-op and illegal

Fixes: 7ab5c5d36d2 ("zink: use EXT_descriptor_buffer with ZINK_DESCRIPTORS=db")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21085>

zink: fix bindless struct member comments

this was a bit confusing having the overall substruct comment which
was occasionally wrong

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21085>

zink: make bindless buffer_infos a union

prep for descriptor buffer handling

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21085>

zink: enable PIPE_CAP_ALLOW_GLTHREAD_BUFFER_SUBDATA_OPT

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21073>

amd/ci: update sanctuary trace sha1

I guess it's because RB+ blending is now more precise.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>

radeonsi: set sampler COMPAT_MODE in the corresponding branch

no functional change

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>

radeonsi: call ac_init_llvm_once before any util_queue initialization

The winsys uses util_queue, which calls atexit, so do it before the winsys
is created.

Cc: stable
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>

amd/llvm: fix LLVM 15 & 16 crashes in SelectionDAG.cpp

Cc: stable
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>

radeonsi: set NEVER as the depth compare func if depth compare is disabled

Fixes: 0c6e56c391a262bef - mesa: (more) correctly handle incomplete depth textures

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>

amd/registers: remove confusing definitions from gfx10-rsrc.json

this will never be used and shouldn't have been added

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>

amd: document OOB behavior on gfx11

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>

amd: fix typo in shadowed uconfig registers on gfx11

It used an invalid offset, which hung.

Fixes: f24f8665dbe2a - ac: implement register shadowing for gfx11

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>

amd: sort and re-indent packet definitions

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>

amd: update late_alloc_wave64 for gfx11

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>

amd: update the cache size for gfx1103_r1

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>

amd: change pbb_max_alloc_count for gfx11

based on PAL

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>

amd: unify and tune the attribute ring size for gfx11

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>

radeonsi: never set INTERPOLATE_COMP_Z

based on PAL

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>

radeonsi: determine alpha_to_coverage robustly in si_update_framebuffer_blend_rasterizer

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21041>