kernel/u-boot.git
11 years agomx6qsabrelite: README: No need to pass 'u-boot.imx'
Fabio Estevam [Wed, 20 Mar 2013 04:07:58 +0000 (04:07 +0000)]
mx6qsabrelite: README: No need to pass 'u-boot.imx'

The u-boot.imx binary is generated by default, so no need to pass it in the
'make' line.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
11 years agomx28evk: Introduce a new target for saving env vars to NAND
Fabio Estevam [Thu, 7 Mar 2013 11:28:19 +0000 (11:28 +0000)]
mx28evk: Introduce a new target for saving env vars to NAND

Introduce 'mx28evk_nand' target for saving environment variables into NAND.

The mx28evk board does not come with a NAND flash populated from the
factory. It comes with an empty slot (U23), which allows the insertion of a
48-pin TSOP flash device.

Tested with a K9LBG08U0D.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Otavio Salvador <otavio@ossystems.com.br>
11 years agomx6qsabre{sd,auto}: Add boot mode select
Otavio Salvador [Sat, 16 Mar 2013 08:05:07 +0000 (08:05 +0000)]
mx6qsabre{sd,auto}: Add boot mode select

Adds support for 'bmode' command which let user to choose where to
boot from; this allows U-Boot to load system from another storage
without messing with jumpers.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
11 years agomx6qsabresd: Fix card detection for invalid card id case
Otavio Salvador [Sat, 16 Mar 2013 08:05:06 +0000 (08:05 +0000)]
mx6qsabresd: Fix card detection for invalid card id case

This changes the code so in case an unkown value is passed it will
return as invalid.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
11 years agomx6qsabresd: Document the mapping of USDHC[2-4]
Otavio Salvador [Sat, 16 Mar 2013 08:05:05 +0000 (08:05 +0000)]
mx6qsabresd: Document the mapping of USDHC[2-4]

This documents the SD card identifier so it is easier for user to spot
which card number will be used, if need.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
11 years agoAdd initial support for Wandboard dual lite and solo.
Fabio Estevam [Fri, 15 Mar 2013 10:43:48 +0000 (10:43 +0000)]
Add initial support for Wandboard dual lite and solo.

Wandboard is a development board that has two variants: one version based
on mx6 dual lite and another one based on mx6 solo.

For more details about Wandboard, please refer to: http://www.wandboard.org/

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
11 years agoi.MX6: mx6qsabrelite: discard override of CONFIG_ARP_TIMEOUT
Eric Nelson [Sat, 9 Mar 2013 13:26:32 +0000 (13:26 +0000)]
i.MX6: mx6qsabrelite: discard override of CONFIG_ARP_TIMEOUT

Nothing on the SABRE Lite board warrants a shorter than normal
ARP timeout.

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
11 years agoi.MX6: Add hdmidet command to detect attached HDMI monitor
Eric Nelson [Sat, 9 Mar 2013 07:06:09 +0000 (07:06 +0000)]
i.MX6: Add hdmidet command to detect attached HDMI monitor

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>
11 years agomx28evk: Disable CONFIG_CMD_I2C
Fabio Estevam [Fri, 8 Mar 2013 04:47:10 +0000 (04:47 +0000)]
mx28evk: Disable CONFIG_CMD_I2C

When loading a Freescale 2.6.35 on a mx28evk the following issue is seen:

sgtl5000_hw_read: read reg error : Reg 0x00
Device with ID register 0 is not a SGTL5000

Disabling CONFIG_CMD_I2C makes the sgtl5000 probe to succeed.

Mainline kernel does not show this problem.

Until the real cause is not identified, disable 'CONFIG_CMD_I2C' for the
time being.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
11 years agoimx-common: timer: fix 32-bit overflow
Knut Wohlrab [Mon, 4 Mar 2013 04:16:02 +0000 (04:16 +0000)]
imx-common: timer: fix 32-bit overflow

The i.MX6 common timer uses the 32-bit variable tbl (time base lower)
to record the overflow of the 32-bit counter. I.e. if the counter
overflows, the variable tbl does overflow, too.

To capture this overflow, use the variable tbu (time base upper), too.
Return the combined value of tbl and tbu.

lastinc is unused then, remove it.

Signed-off-by: Knut Wohlrab <knut.wohlrab@de.bosch.com>
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Stefano Babic <sbabic@denx.de>
11 years agoconfigs: mx28evk: Use single-line comments
Fabio Estevam [Sun, 27 Jan 2013 05:52:05 +0000 (05:52 +0000)]
configs: mx28evk: Use single-line comments

No need to use multi-line style comments for single-line contents.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Otavio Salvador <otavio@ossystems.com.br>
11 years agomxs: spl_mem_init: Align DDR2 init with FSL bootlets source
Fabio Estevam [Thu, 28 Feb 2013 12:59:19 +0000 (12:59 +0000)]
mxs: spl_mem_init: Align DDR2 init with FSL bootlets source

Currently the following kernel hang happens when loading a 2.6.35 kernel from
Freeescale on a mx28evk board:

RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
Bus freq driver module loaded
IMX usb wakeup probe
usb h1 wakeup device is registered
mxs_cpu_init: cpufreq init finished
...

Loading the same kernel using the bootlets from the imx-bootlets-src-10.12.01
package, the hang does not occur.

Comparing the DDR2 initialization from the bootlets code against the U-boot
one, we can notice some mismatches, and after applying the same initialization
into U-boot the 2.6.35 kernel can boot normally.

Also tested with 'mtest' command, which runs succesfully.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Tested-by: Marek Vasut <marex@denx.de>
11 years agoMerge branch 'u-boot-tegra/master' into 'u-boot-arm/master'
Albert ARIBAUD [Fri, 15 Mar 2013 19:50:43 +0000 (20:50 +0100)]
Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master'

11 years agoMerge branch 'u-boot-imx/master' into 'u-boot-arm/master'
Albert ARIBAUD [Fri, 15 Mar 2013 14:18:31 +0000 (15:18 +0100)]
Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'

11 years agonitrogen: Use unsigned long to specify the total RAM size
fabio.estevam@freescale.com [Thu, 14 Mar 2013 02:32:55 +0000 (02:32 +0000)]
nitrogen: Use unsigned long to specify the total RAM size

When building for the nitrogen boards with 2GiB the following warning happens:

nitrogen6x.c:89:38: warning: integer overflow in expression [-Woverflow]

2GiB can not fit in 32-bits, so use ulong instead.

Reported-by: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
11 years agonitrogen6x: Fix RAM size variable
Fabio Estevam [Thu, 14 Mar 2013 02:32:54 +0000 (02:32 +0000)]
nitrogen6x: Fix RAM size variable

Fix the following build error when buildig nitrogen6s1g:

nitrogen6x.c:89:17: error: 'CONFIG_DDR_MB' undeclared (first use in
this function)
nitrogen6x.c:89:17: note: each undeclared identifier is reported only
once for each function it appears in

Reported-by: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
11 years agoTegra114: Dalmore: Add pad config tables/code based on pinmux code
Tom Warren [Mon, 11 Mar 2013 23:43:49 +0000 (16:43 -0700)]
Tegra114: Dalmore: Add pad config tables/code based on pinmux code

Pad config registers exist in APB_MISC_GP space, and control slew
rate, drive strengh, schmidt, high-speed, and low-power modes for
all of the pingroups in Tegra30. This builds off of the pinmux
way of constructing init tables to configure select pads (SDIOCFG,
for instance) during pinmux_init().

Currently, no padcfg entries exist. SDIO3CFG will be added when the
MMC driver is added as per the TRM to work with the SD-card slot on
Dalmore E1611.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
11 years agoTegra114: fdt: Move aliases from dtsi to dts file as per other Tegras
Tom Warren [Tue, 12 Mar 2013 00:07:21 +0000 (17:07 -0700)]
Tegra114: fdt: Move aliases from dtsi to dts file as per other Tegras

All other Tegra boards have their alias nodes in the .dts file

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
11 years agoTegra114: Dalmore: Always use DEFAULT instead of DISABLE for lock bits
Tom Warren [Wed, 13 Mar 2013 22:40:33 +0000 (15:40 -0700)]
Tegra114: Dalmore: Always use DEFAULT instead of DISABLE for lock bits

The pinmux code issues a warning if the caller attempts to disable the
lock bit in a pinmux register, since this is impossible (once it's
locked, the only way to unlock it is to reset the device/pmt controller).

The I2C/DDC/CEC/USB macros expect a lock setting to be passed in,
and the previous setting of DISABLE caused the pinmux table parsing
code to issue the warning. Changing the lock bits in these table
entries to DEFAULT (i.e. don't touch it) fixes this.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
11 years agoTegra114: Fix/update GP padcfg register struct
Tom Warren [Wed, 13 Mar 2013 22:13:47 +0000 (15:13 -0700)]
Tegra114: Fix/update GP padcfg register struct

Differences in padcfg registers (some removed, some added) between
Tegra30 and Tegra114 weren't picked up when I first ported this file.

Signed-off-by: Tom Warren <twarren@nvidia.com>
11 years agoTegra114: pinmux: Fix bad CAM_MCLK func 3 table entry
Tom Warren [Wed, 13 Mar 2013 22:00:54 +0000 (15:00 -0700)]
Tegra114: pinmux: Fix bad CAM_MCLK func 3 table entry

This caused CAM_MCLK's pinmux reg to be locked out, since the
table parsing code couldn't find a matching entry for VI_ALT3
and wrote garbage to the register.

Signed-off-by: Tom Warren <twarren@nvidia.com>
11 years agoARM: tegra: enable a common set of disk-related commands everywhere
Stephen Warren [Thu, 28 Feb 2013 15:03:48 +0000 (15:03 +0000)]
ARM: tegra: enable a common set of disk-related commands everywhere

Enable a common set of partition types, filesystems, and related
commands in tegra-common.h, so that they are available on all Tegra
boards. This allows boot.scr (loaded and executed by the default
built-in environment) on those boards to assume that certain features
are always available.

Do this in tegra-common.h, so that individual board files can undefine
the features if they really don't want any of them.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
11 years agodisk: define HAVE_BLOCK_DEVICE if CONFIG_CMD_PART
Stephen Warren [Thu, 28 Feb 2013 15:03:47 +0000 (15:03 +0000)]
disk: define HAVE_BLOCK_DEVICE if CONFIG_CMD_PART

Various code that is conditional upon HAVE_BLOCK_DEVICE is required by
code conditional upon CONFIG_CMD_PART. So, enable HAVE_BLOCK_DEVICE if
CONFIG_CMD_PART is enabled.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Tom Rini <trini@ti.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
11 years agodisk: define HAVE_BLOCK_DEVICE in a common place
Stephen Warren [Thu, 28 Feb 2013 15:03:46 +0000 (15:03 +0000)]
disk: define HAVE_BLOCK_DEVICE in a common place

This set of ifdefs is used in a number of places. Move its definition
somewhere common so it doesn't have to be repeated.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Tom Rini <trini@ti.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
11 years agoARM: tegra: make bounce buffer option common
Stephen Warren [Thu, 28 Feb 2013 15:03:45 +0000 (15:03 +0000)]
ARM: tegra: make bounce buffer option common

All Tegra devices will need CONFIG_BOUNCE_BUFFER. Move it to
tegra-common.h to ensure it's always set.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
11 years agoTegra30: MMC: Enable DT MMC driver support for Tegra30 Cardhu boards
Tom Warren [Tue, 26 Feb 2013 19:36:22 +0000 (12:36 -0700)]
Tegra30: MMC: Enable DT MMC driver support for Tegra30 Cardhu boards

Tested on my Cardhu-A04 tablet, eMMC and SD-Card work fine, can load
a kernel off of an SD card OK, card detect works, and the env is now
stored in eMMC (end of the 2nd 'boot' sector, same as Tegra20).

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
11 years agoTegra30: mmc: Add Tegra30 SDMMC compatible entry to fdtdec & driver
Tom Warren [Mon, 4 Mar 2013 21:07:18 +0000 (14:07 -0700)]
Tegra30: mmc: Add Tegra30 SDMMC compatible entry to fdtdec & driver

Tegra30 SD/MMC controller differs enough from Tegra20 that it
needs its own entry in the compat_names/compat_id tables and in
the Tegra MMC driver.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
11 years agommc: Tegra: Add SD bus power/voltage function and MMC pad init call.
Tom Warren [Tue, 26 Feb 2013 19:31:26 +0000 (12:31 -0700)]
mmc: Tegra: Add SD bus power/voltage function and MMC pad init call.

Tegra30 requires the SD Bus Voltage & Power bits be set in the SD
Power Control register. Tegra20 works w/o them set, but do it anyway
for those SoCs as it's part of the SD spec. Also call a common
board pad init routine (pad_init_mmc) in mmc_reset(), used by
Tegra30 only for now.

Note that Tegra20 SD/MMC HW differs enough from Tegra20 that a
new compatible entry is used in the fdt compat_names/id tables.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
11 years agoTegra30: MMC: Add SD bus power-rail and SDMMC pad init routines
Tom Warren [Tue, 26 Feb 2013 19:26:55 +0000 (12:26 -0700)]
Tegra30: MMC: Add SD bus power-rail and SDMMC pad init routines

T30 requires specific SDMMC pad programming, and bus power-rail bringup.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
11 years agoTegra: MMC: Added/update SDMMC registers/base addresses for T20/T30
Tom Warren [Tue, 26 Feb 2013 18:17:43 +0000 (11:17 -0700)]
Tegra: MMC: Added/update SDMMC registers/base addresses for T20/T30

Removed SDMMC base addresses from tegra.h since they're no longer used.
Added additional vendor-specific SD/MMC registers and bus power defines.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
11 years agoTegra30: fdt: Add SDMMC (sdhci) nodes for T30 boards (Cardhu for now)
Tom Warren [Tue, 26 Feb 2013 18:14:17 +0000 (11:14 -0700)]
Tegra30: fdt: Add SDMMC (sdhci) nodes for T30 boards (Cardhu for now)

Took these values directly from the kernel dts files.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
11 years agoTegra30: Cardhu: Add pad config tables/code based on pinmux code
Tom Warren [Wed, 6 Mar 2013 23:16:22 +0000 (16:16 -0700)]
Tegra30: Cardhu: Add pad config tables/code based on pinmux code

Pad config registers exist in APB_MISC_GP space, and control slew
rate, drive strengh, schmidt, high-speed, and low-power modes for
all of the pingroups in Tegra30. This builds off of the pinmux
way of constructing init tables to configure select pads (SDIOCFG,
for instance) during pinmux_init().

Currently, only SDIO1CFG is changed as per the TRM to work with
the SD-card slot on Cardhu.

Thanks to StephenW for the suggestion/original idea.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
11 years agoTegra114: pinmux: Update pinmux tables & code, fix a bug w/SDMMC3 init
Tom Warren [Fri, 1 Mar 2013 21:38:20 +0000 (14:38 -0700)]
Tegra114: pinmux: Update pinmux tables & code, fix a bug w/SDMMC3 init

Use the latest tables & code from our internal U-Boot repo.
The SDMMC3_CD, CLK_LB_IN and CLK_LB_OUT offsets in the pingroup
table were off by a few indices, causing the pinmux init code to
write bad data to the PINMUX_AUX_ regs. This also enabled the lock
bit, which made it impossible to reconfig the pads correctly for
SDMMC3 (SD card on Dalmore) operation. Also fixes SPI_CS2_N,
USB_VBUS_EN0, HDMI_CEC and UART2_RXD/TXD muxes.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
11 years agoTegra30: Cardhu: Remove unneeded cardhu.c.mmc file
Tom Warren [Thu, 28 Feb 2013 06:30:03 +0000 (06:30 +0000)]
Tegra30: Cardhu: Remove unneeded cardhu.c.mmc file

This was an older debug/developmental file that got added
accidentally. Not needed/used in any Cardhu build.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
11 years agoTegra114: fdt: Sync DT nodes with kernel DT files (GPIO, tegra_car)
Tom Warren [Wed, 27 Feb 2013 05:52:52 +0000 (05:52 +0000)]
Tegra114: fdt: Sync DT nodes with kernel DT files (GPIO, tegra_car)

Minor edit to tegra_car node, add gpio node.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
11 years agoTegra: Remove unused CONFIG_SYS_CPU_OSC_FREQUENCY define
Tom Warren [Tue, 26 Feb 2013 12:18:48 +0000 (12:18 +0000)]
Tegra: Remove unused CONFIG_SYS_CPU_OSC_FREQUENCY define

This wasn't used anywhere in any Tegra build.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
11 years agoTegra: Add twarren as maintainer for Tegra30 and Tegra114 SoCs
Tom Warren [Tue, 26 Feb 2013 07:59:30 +0000 (07:59 +0000)]
Tegra: Add twarren as maintainer for Tegra30 and Tegra114 SoCs

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
11 years agoARM: tegra: implement WAR for Tegra114 CPU reset vector
Stephen Warren [Thu, 28 Feb 2013 12:40:09 +0000 (12:40 +0000)]
ARM: tegra: implement WAR for Tegra114 CPU reset vector

A Tegra114 HW bug prevents the main CPU vector from being modified under
certain circumstances. Tegra114 A01P and later with a patched boot ROM
set the CPU reset vector to 0x4003fffc (end of IRAM). This allows placing
an arbitrary jump instruction at that location, in order to redirect to
the desired reset vector location. Modify Tegra114's start_cpu() to make
use of this feature. This allows CPUs with the patched boot ROM to boot.

Based-on-work-by: Jimmy Zhang <jimmzhang@nvidia.com>.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
11 years agoTegra30: fdt: Sync DT nodes with kernel DT files (I2C, SPI, GPIO, clock)
Tom Warren [Thu, 21 Feb 2013 13:33:23 +0000 (13:33 +0000)]
Tegra30: fdt: Sync DT nodes with kernel DT files (I2C, SPI, GPIO, clock)

Minor edits to clock, apbdma and SPI, make I2C match kernel DT, and add gpio

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
11 years agoTegra: fdt: Remove memreserve line from Cardhu/Seaboard DT files
Tom Warren [Thu, 21 Feb 2013 12:40:29 +0000 (12:40 +0000)]
Tegra: fdt: Remove memreserve line from Cardhu/Seaboard DT files

Not used, and wrong in Cardhu's case

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
11 years agoTegra: MMC: Add DT support to MMC driver for all T20 boards
Tom Warren [Thu, 21 Feb 2013 12:31:30 +0000 (12:31 +0000)]
Tegra: MMC: Add DT support to MMC driver for all T20 boards

tegra_mmc_init() now parses the DT info for bus width, WP/CD GPIOs, etc.
Tested on Seaboard, fully functional.

Tamonten boards (medcom-wide, plutux, and tec) use a different/new
dtsi file w/common settings.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
11 years agoTegra: fdt: Add/enhance sdhci (mmc) nodes for all T20 DT files
Tom Warren [Thu, 21 Feb 2013 12:31:29 +0000 (12:31 +0000)]
Tegra: fdt: Add/enhance sdhci (mmc) nodes for all T20 DT files

Linux dts files were used for those boards that didn't already
have sdhci info populated. Tamonten has their own dtsi file with
common sdhci nodes (sourced from Linux).

Signed-off-by: Tom Warren <twarren@nvidia.com>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
11 years agoTegra: fdt: tamonten: Add common tamonten.dtsi file from linux
Tom Warren [Thu, 21 Feb 2013 12:31:28 +0000 (12:31 +0000)]
Tegra: fdt: tamonten: Add common tamonten.dtsi file from linux

Tamonten boards (medcom-wide, plutux, and tec) use a different/new
dtsi file w/common settings.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Thierry Reding <thierry.reding@avionic-design.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
11 years agoTegra: fdt: Change /include/ to #include for C preprocessor
Tom Warren [Thu, 21 Feb 2013 12:31:27 +0000 (12:31 +0000)]
Tegra: fdt: Change /include/ to #include for C preprocessor

dts Makefile has the arch & board include paths added to DTS_CPPFLAGS.
This allows the use of '#include "xyz"' in the dts/dtsi file which
helps the C preprocessor find common dtsi include files.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
11 years agoTegra114: I2C: Enable I2C driver on Dalmore E1611 eval board
Tom Warren [Fri, 8 Feb 2013 07:25:32 +0000 (07:25 +0000)]
Tegra114: I2C: Enable I2C driver on Dalmore E1611 eval board

Tested all 5 'buses', i2c probe enumerates device addresses on bus
0, 1 and 2.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
11 years agoTegra114: fdt: Update DT files with I2C info for T114/Dalmore
Tom Warren [Fri, 8 Feb 2013 07:25:31 +0000 (07:25 +0000)]
Tegra114: fdt: Update DT files with I2C info for T114/Dalmore

T114, like T30, does not have a separate/different DVC (power I2C)
controller like T20 - all 5 I2C controllers are identical, but
I2C5 is used to designate the controller intended for power
control (PWR_I2C in the schematics). PWR_I2C is set to 400KHz.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
11 years agoTegra: I2C: Add T114 clock support to tegra_i2c driver
Tom Warren [Fri, 8 Feb 2013 07:25:30 +0000 (07:25 +0000)]
Tegra: I2C: Add T114 clock support to tegra_i2c driver

T114 has a slightly different I2C clock, with a new (extra) divisor
in standard/fast mode and HS mode. Tested on my Dalmore, and the I2C
clock is 100KHz +/- 3Hz on my Saleae Logic analyzer.

Added a new entry in compat_names for T114 I2C since it differs
from the previous Tegra SoCs. A flag is set when T114 I2C HW is
found so new features like the extra clock divisor can be used.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
11 years agoTegra114: I2C: Take DVFS out of reset to allow I2C5 (PWR_I2C) to work
Tom Warren [Wed, 27 Feb 2013 11:10:01 +0000 (11:10 +0000)]
Tegra114: I2C: Take DVFS out of reset to allow I2C5 (PWR_I2C) to work

I2C driver can now probe dev 0 (PWR_I2C, where the PMU, etc. lives).
This is needed so that the SDIO slot power can be brought up for
the MMC driver, so it has to precede those commits.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
11 years agotegra: usb: move [start|stop]_port into ehci_hcd_[init|stop]
Lucas Stach [Thu, 7 Feb 2013 07:16:30 +0000 (07:16 +0000)]
tegra: usb: move [start|stop]_port into ehci_hcd_[init|stop]

The ehci_hcd entry points were just calling into the Tegra USB
functions. Now that they are in the same file we can just move over the
implementation.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
11 years agotegra: usb: move implementation into right directory
Lucas Stach [Thu, 7 Feb 2013 07:16:29 +0000 (07:16 +0000)]
tegra: usb: move implementation into right directory

This moves the Tegra USB implementation into the drivers/usb/host
directory. Note that this merges the old
/arch/arm/cpu/armv7/tegra20/usb.c file into ehci-tegra.c. No code
changes, just moving stuff around.

v2: While at it also move some defines and the usb.h header file to make
usb driver usable for Tegra30.
NOTE: A lot more work is required to properly init the PHYs and PLL_U on
Tegra30, this is just to make porting easier and it does no harm here.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
11 years agotegra: usb: various small cleanups
Lucas Stach [Thu, 7 Feb 2013 07:16:28 +0000 (07:16 +0000)]
tegra: usb: various small cleanups

Remove unneeded headers, function prototype and stale comment, that
doesn't match the actual codebase anymore.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
11 years agotegra: usb: move controller init into start_port
Lucas Stach [Thu, 7 Feb 2013 07:16:27 +0000 (07:16 +0000)]
tegra: usb: move controller init into start_port

There is no need to init a USB controller before the upper layers indicate
that they are actually going to use it.

board_usb_init now only parses the device tree and sets up the common pll.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
11 years agotegra: usb: remove unneeded function parameter
Lucas Stach [Thu, 7 Feb 2013 07:16:26 +0000 (07:16 +0000)]
tegra: usb: remove unneeded function parameter

Just a dead parameter, never actually used.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
11 years agotegra: usb: make controller init functions more self contained
Lucas Stach [Thu, 7 Feb 2013 07:16:25 +0000 (07:16 +0000)]
tegra: usb: make controller init functions more self contained

There is no need to pass around all those parameters. The init functions
are able to easily extract all the needed setup info on their own.

This allows to move out the controller init into ehci_hcd_init later
on, without having to save away global state for later use  and thus
bloating the file global state.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
11 years agotegra: usb: set USB_PORTS_MAX to correct value
Lucas Stach [Thu, 7 Feb 2013 07:16:24 +0000 (07:16 +0000)]
tegra: usb: set USB_PORTS_MAX to correct value

Both Tegra20 and Tegra30 have a max of 3 USB controllers.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
11 years agoARM: tegra: enable some CPU errata workarounds
Stephen Warren [Tue, 26 Feb 2013 12:28:28 +0000 (12:28 +0000)]
ARM: tegra: enable some CPU errata workarounds

Tegra20 has a Cortex A9 r1p1, and Tegra30 has a Cortex A9 r2p9. As such,
some CPU errata exist, and must be worked around.

These must be worked around in the bootloader, since in general, the
kernel (especially a multi-platform kernel) needs to support being
launched in non-secure mode (normal world), and hence may not be able
to write to the CP15 register to enable these workarounds.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
11 years agoARM: implement some Cortex-A9 errata workarounds
Stephen Warren [Tue, 26 Feb 2013 12:28:27 +0000 (12:28 +0000)]
ARM: implement some Cortex-A9 errata workarounds

Various errata exist in the Cortex-A9 CPU, and may be worked around by
setting some bits in a CP15 diagnostic register. Add code to implement
the workarounds, enabled by new CONFIG_ options.

This code was taken from the Linux kernel, v3.8, arch/arm/mm/proc-v7.S,
and modified to remove the logic to conditionally apply the WAR (since we
know exactly which CPU we're running on given the U-Boot configuration),
and use r0 instead of r10 for consistency with the rest of U-Boot's
cpu_init_cp15().

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
11 years agoAdd Boundary Devices Nitrogen6X boards
Eric Nelson [Mon, 11 Mar 2013 08:44:53 +0000 (08:44 +0000)]
Add Boundary Devices Nitrogen6X boards

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
11 years agoRefactor linker-generated arrays
Albert ARIBAUD [Mon, 25 Feb 2013 00:59:00 +0000 (00:59 +0000)]
Refactor linker-generated arrays

Refactor linker-generated array code so that symbols
which were previously linker-generated are now compiler-
generated. This causes relocation records of type
R_ARM_ABS32 to become R_ARM_RELATIVE, which makes
code which uses LGA able to run before relocation as
well as after.

Note: this affects more than ARM targets, as linker-
lists span possibly all target architectures, notably
PowerPC.

Conflicts:
arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
board/ait/cam_enc_4xx/u-boot-spl.lds
board/davinci/da8xxevm/u-boot-spl-da850evm.lds
board/davinci/da8xxevm/u-boot-spl-hawk.lds
board/vpac270/u-boot-spl.lds

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
11 years agoarm: make __bss_start and __bss_end__ compiler-generated
Albert ARIBAUD [Mon, 25 Feb 2013 00:58:59 +0000 (00:58 +0000)]
arm: make __bss_start and __bss_end__ compiler-generated

Turn __bss_start and __bss_end__ from linker-generated
to compiler-generated symbols, causing relocations for
these symbols to change type, from R_ARM_ABS32 to
R_ARM_RELATIVE.

This should have no functional impact, as it affects
references to __bss_start and __bss_end__ only before
relocation, and no such references are done.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
11 years agoRemove linker lists (LGAs) from SPL linker scripts
Albert ARIBAUD [Mon, 25 Feb 2013 00:58:58 +0000 (00:58 +0000)]
Remove linker lists (LGAs) from SPL linker scripts

Many SPL linker scripts needlessly include linker lists (aka LGAs).
Remove them whenever possible; keep it only in the seven am335x_evm
variants (am335x_evm, am335x_evm_uart[1-5], am335x_evm_spiboot),
where there is actual content in output section .u_boot_list.

This commit keeps all u-boot.bin and u-boot-spl.bin in ARM targets
byte-identical.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
11 years agoarm: omap: map u_boot_lists section to .sram
Albert ARIBAUD [Mon, 25 Feb 2013 00:58:57 +0000 (00:58 +0000)]
arm: omap: map u_boot_lists section to .sram

Output section .u_boot_list was left unmapped in
u-boot-spl.lds for omap-common, causing the location
counter to roll back to bteween .rodata and .data,
making __image_copy_end and _end symbols wrong.

Mapping output section .u_boot_list to memory .sram
fixes these symbols' mapping.

This modifies the SPL binary but has no functional
impact, as __image_copy_end and _end are never used
in SPLs and u_boot_list is empty for all 29 boards
affected (omap4_sdp4430 eco5pk igep0030 am335x_evm_uart3
omap3_beagle am3517_crane igep0032 mt_ventoux pcm051
am3517_evm omap3_evm_quick_mmc am335x_evm_uart2
am335x_evm_spiboot am335x_evm_uart1 omap3_evm igep0030_nand
omap3_overo igep0020 am335x_evm omap4_panda omap5_evm
am335x_evm_uart4 devkit8000 tricorder mcx twister
omap3_evm_quick_nand am335x_evm_uart5 igep0020_nand).

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
11 years agoMerge branch 'u-boot-atmel/master' into 'u-boot-arm/master'
Albert ARIBAUD [Tue, 12 Mar 2013 16:27:44 +0000 (17:27 +0100)]
Merge branch 'u-boot-atmel/master' into 'u-boot-arm/master'

11 years agoARM: sam9x5: fix ethernet pins in MII mode
Jesse Gilles [Wed, 27 Feb 2013 23:42:49 +0000 (23:42 +0000)]
ARM: sam9x5: fix ethernet pins in MII mode

Fix pin setting in MII mode

Signed-off-by: Jesse Gilles <jgilles@multitech.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
11 years agoARM: at91sam9x5: Using CPU string directly
Bo Shen [Thu, 7 Mar 2013 21:23:22 +0000 (21:23 +0000)]
ARM: at91sam9x5: Using CPU string directly

As the CPU name is not configurable, using CPU string directly

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
11 years agoARM: at91: change nand flash table
Bo Shen [Wed, 20 Feb 2013 00:16:25 +0000 (00:16 +0000)]
ARM: at91: change nand flash table

Change nand flash partition table according to www.at91.com/linux4sam

more information: http://www.at91.com/linux4sam/bin/view/Linux4SAM/GettingStarted#Linux4SAM_NandFlash_demo_Memory

Signed-off-by: Bo Shen <voice.shen@atmel.com>
[minor commit message changes]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
11 years agoarm: at91/configs: add bootz to configuration
Nicolas Ferre [Wed, 20 Feb 2013 00:16:24 +0000 (00:16 +0000)]
arm: at91/configs: add bootz to configuration

Support to boot zImage

Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
[Add bootz for at91rm9200, at91sam9263, at91sam9rl]
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
11 years agoarm: at91/configs: add libfdt to configuration
Nicolas Ferre [Wed, 20 Feb 2013 00:16:23 +0000 (00:16 +0000)]
arm: at91/configs: add libfdt to configuration

support to boot device tree Linux kernel

Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
[Add libftd for at91rm9200, at91sam9263, at91sam9rl]
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
11 years agoMerge u-boot/master into u-boot-ti/master
Tom Rini [Mon, 11 Mar 2013 16:02:40 +0000 (12:02 -0400)]
Merge u-boot/master into u-boot-ti/master

In master we had already taken a patch to fix the davinci GPIO code for
CONFIG_SOC_DM646X and in u-boot-ti we have additional patches to support
DA830 (which is CONFIG_SOC_DA8XX && !CONFIG_SOC_DA850).  Resolve these
conflicts manually and comment the #else/#endif lines for clarity.

Conflicts:
arch/arm/include/asm/arch-davinci/gpio.h
drivers/gpio/da8xx_gpio.c

Signed-off-by: Tom Rini <trini@ti.com>
11 years agoarm: dra7xx: Add silicon id support for DRA752 soc
Lokesh Vutla [Tue, 12 Feb 2013 21:29:03 +0000 (21:29 +0000)]
arm: dra7xx: Add silicon id support for DRA752 soc

Adding CPU detection support for the DRA752 ES1.0 soc.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
11 years agoarm: dra7xx: Add dra7xx_evm build support
Lokesh Vutla [Sun, 17 Feb 2013 23:34:35 +0000 (23:34 +0000)]
arm: dra7xx: Add dra7xx_evm build support

Adding the build support for dra7xx_evm.
Reusing omap5_evm.h config by moving it to omap5_common.h

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
11 years agoarm: dra7xx: Add board files for DRA7XX socs
Lokesh Vutla [Tue, 12 Feb 2013 21:29:08 +0000 (21:29 +0000)]
arm: dra7xx: Add board files for DRA7XX socs

Adding new board files for DRA7XX socs.
The pad registers layout is changed completely from OMAP5
So introducing the new structure here and also adding the
minimal data.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishant Kamat <nskamat@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
[trini: Adapt omap_mmc_init call for last 2 params]
Signed-off-by: Tom Rini <trini@ti.com>
11 years agoarm: dra7xx: Add DDR related data for DRA752 ES1.0
Lokesh Vutla [Tue, 12 Feb 2013 21:29:07 +0000 (21:29 +0000)]
arm: dra7xx: Add DDR related data for DRA752 ES1.0

DRA752 uses DDR3. Populating the corresponding structures
with DDR3 data.
Writing into MA registers if only MA is present in that soc.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
11 years agoarm: dra7xx: Add control module changes
Lokesh Vutla [Tue, 12 Feb 2013 21:29:06 +0000 (21:29 +0000)]
arm: dra7xx: Add control module changes

Control module register addresses are changed from OMAP5
to DRA7XX socs.
So adding the necessary changes for the same.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
11 years agoarm: dra7xx: clock: Add the dplls data
Lokesh Vutla [Tue, 12 Feb 2013 21:29:05 +0000 (21:29 +0000)]
arm: dra7xx: clock: Add the dplls data

A new DPLL DDR is added in DRA7XX socs. Now clocks to
EMIF CD is from DPLL DDR. So DPLL DDR should be locked
before initializing RAM.
Also adding other dpll data which are different from OMAP5 ES2.0.
SYS_CLK running at 20MHz is introduced in DRA7xx socs.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
11 years agoarm: dra7xx: clock: Add the prcm changes
Lokesh Vutla [Sun, 17 Feb 2013 23:33:37 +0000 (23:33 +0000)]
arm: dra7xx: clock: Add the prcm changes

PRCM register addresses are changed from OMAP5 ES2.0 to DRA7XX.
So adding the necessary register changes for DRA7XX socs.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
11 years agoARM: OMAP5: srcomp: enable slew rate compensation cells after powerup
Lokesh Vutla [Tue, 12 Feb 2013 01:33:45 +0000 (01:33 +0000)]
ARM: OMAP5: srcomp: enable slew rate compensation cells after powerup

After power-up SRCOMP cells are by-passed by default in OMAP5.
Software has to enable these SRCOMP sells.
For ES2: All 5 SRCOMP cells needs to be enabled.
For ES1: Only 4 SRCOMP cells in core power domain are enabled.
 The 1 in wkup domain is not enabled because smart i/os
 of wkup domain work with default compensation code.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Tom Rini <trini@ti.com>
11 years agoARM: OMAP5: Add DDR changes required for OMAP543X ES2.0 SOCs
Lokesh Vutla [Tue, 12 Feb 2013 01:33:44 +0000 (01:33 +0000)]
ARM: OMAP5: Add DDR changes required for OMAP543X ES2.0 SOCs

Add pre calculated timing settings of LPDDR2 and DDR3 memories
present in OMAP5430 and OMAP5432 ES2.0 versions.

Also adding the DDR pad io settings required for
OMAP543X SOCs here.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Tom Rini <trini@ti.com>
11 years agoARM: OMAP4/5: clocks: Add the required OPP settings as per the latest addendum
SRICHARAN R [Tue, 12 Feb 2013 01:33:43 +0000 (01:33 +0000)]
ARM: OMAP4/5: clocks: Add the required OPP settings as per the latest addendum

Change OPP settings as per the latest 0.5 version of
addendum for OMAP5430 ES2.0. omap4/hw_data.c is touched
here to add dummy dividers.

While here correcting OPP_NOM mpu, core frequency for
OMAP4430 ES2.x

Note that OMAP5430 ES1.0 support is still kept alive and
would be removed in a cleanup later.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Cc: Tom Rini <trini@ti.com>
Cc: Nishanth Menon <nm@ti.com>
11 years agoARM: OMAP5: clock: Add the prcm register changes required for ES2.0
SRICHARAN R [Tue, 12 Feb 2013 01:33:42 +0000 (01:33 +0000)]
ARM: OMAP5: clock: Add the prcm register changes required for ES2.0

PRCM register addresses are changed from ES1.0 to ES2.0 due to
PER power domain getting moved to CORE power domain.

So adding the nessecary register changes for the same.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Tom Rini <trini@ti.com>
11 years agoARM: OMAP5: Add silicon id support for ES2.0 revision.
SRICHARAN R [Tue, 12 Feb 2013 01:33:41 +0000 (01:33 +0000)]
ARM: OMAP5: Add silicon id support for ES2.0 revision.

Adding the CPU detection suport for OMAP5430 and
OMAP5432 ES2.0 SOCs.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Cc: Tom Rini <trini@ti.com>
Cc: Nishanth Menon <nm@ti.com>
11 years agoARM: OMAP5: Clean up iosettings code
Lokesh Vutla [Mon, 4 Feb 2013 04:22:05 +0000 (04:22 +0000)]
ARM: OMAP5: Clean up iosettings code

There is some code duplication in the ddr io settings code.
This is avoided by moving the data to a Soc specific place and
letting the code generic.

This avoids unnessecary code addition for future socs.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
11 years agoARM: OMAP4+: Make control module register structure generic
Lokesh Vutla [Mon, 4 Feb 2013 04:22:04 +0000 (04:22 +0000)]
ARM: OMAP4+: Make control module register structure generic

A seperate omap_sys_ctrl_regs structure is defined for
omap4 & 5. If there is any change in control module for
any of the ES versions, a new structure needs to be created.
In order to remove this dependency, making the register
structure generic for all the omap4+ boards.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
11 years agoARM: OMAP4+: Cleanup emif specific files
Lokesh Vutla [Mon, 4 Feb 2013 04:22:03 +0000 (04:22 +0000)]
ARM: OMAP4+: Cleanup emif specific files

Removing the duplicated code in ddr3 initialization.
Also creating structure for lpddr2 mode registers to
avoid unnessecary revision checks.

These change reduces code addition for future Socs.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
11 years agoARM: OMAP4+: Clean up the pmic code
SRICHARAN R [Mon, 4 Feb 2013 04:22:02 +0000 (04:22 +0000)]
ARM: OMAP4+: Clean up the pmic code

The pmic code is duplicated for OMAP 4 and 5.
Instead move the data to Soc specific place and
share the code.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
11 years agoARM: OMAP4+: Cleanup the clocks layer
SRICHARAN R [Mon, 4 Feb 2013 04:22:01 +0000 (04:22 +0000)]
ARM: OMAP4+: Cleanup the clocks layer

Currently there is quite a lot of code which
is duplicated in the clocks code for OMAP 4 and 5
Socs. Avoiding this here by moving the clocks
data to a SOC specific place and the sharing the
common code.

This helps in addition of a new Soc with minimal
changes.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
11 years agoARM: OMAP4+: Change the PRCM structure prototype common for all Socs
SRICHARAN R [Mon, 4 Feb 2013 04:22:00 +0000 (04:22 +0000)]
ARM: OMAP4+: Change the PRCM structure prototype common for all Socs

The current PRCM structure prototype directly matches the hardware
register layout. So there is a need to change this for every new silicon
revision which has register space changes.

Avoiding this by making the prototye generic and populating the register
addresses seperately for all Socs.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
11 years agoARM: OMAP4+: emif: Detect SDRAM from SDRAM config register
Lokesh Vutla [Mon, 4 Feb 2013 04:21:59 +0000 (04:21 +0000)]
ARM: OMAP4+: emif: Detect SDRAM from SDRAM config register

Now SDRAM initialization is done on the basis of omap revision.
Instead this should be done on basis of SDRAM type read from
EMIF_SDRAM_CONFIG register. This will be helpful to avoid
unnessecary cpu checks for new boards

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
11 years agocm_t35: prevent splashimage from being set to a bad value
Nikita Kiryanov [Sun, 24 Feb 2013 06:19:23 +0000 (06:19 +0000)]
cm_t35: prevent splashimage from being set to a bad value

Define CONFIG_SPLASHIMAGE_GUARD to prevent splashimage from being
set to a value that will cause U-Boot to hang while displaying a
splash screen.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
11 years agolcd: implement a callback for splashimage
Nikita Kiryanov [Sun, 24 Feb 2013 21:28:43 +0000 (21:28 +0000)]
lcd: implement a callback for splashimage

On some architectures certain values of splashimage will lead to
a data abort exception.

Document the problem, and implement a callback for splashimage to
reject such values.

Cc: Anatolij Gustschin <agust@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
11 years agoam335x: cpsw: optimize cpsw_send to increase network performance
Mugunthan V N [Tue, 19 Feb 2013 21:34:44 +0000 (21:34 +0000)]
am335x: cpsw: optimize cpsw_send to increase network performance

Before submitting packets to cpdma, phy status is updated on every packet
which leads to delay in packet send intern reduces the Ethernet performance.
Checking mdio status for each packet will reduce timetaken to send a packet
and there by increasing the Ethernet performance. With this the performance
is increased from 208KiB/s to 375KiB/s on EVMsk

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
11 years agoomap4_common: Enable CONFIG_CMD_BOOTZ
Tom Rini [Tue, 19 Feb 2013 11:18:18 +0000 (11:18 +0000)]
omap4_common: Enable CONFIG_CMD_BOOTZ

With v3.9 and later of the Linux Kernel defaulting to multi-platform
images with omap2plus_defconfig, uImage isn't builtable anymore by
default.  Add CONFIG_CMD_BOOTZ so that we can still boot something the
kernel spits out.

Cc: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Reviewed-by: R Sricharan <r.sricharan@ti.com>
11 years agoomap3_beagle: Enable CONFIG_CMD_BOOTZ
Tom Rini [Tue, 19 Feb 2013 11:18:17 +0000 (11:18 +0000)]
omap3_beagle: Enable CONFIG_CMD_BOOTZ

With v3.9 and later of the Linux Kernel defaulting to multi-platform
images with omap2plus_defconfig, uImage isn't builtable anymore by
default.  Add CONFIG_CMD_BOOTZ so that we can still boot something the
kernel spits out.

Signed-off-by: Tom Rini <trini@ti.com>
11 years agoomap5_evm: Enable CONFIG_CMD_BOOTZ
Tom Rini [Tue, 19 Feb 2013 11:18:16 +0000 (11:18 +0000)]
omap5_evm: Enable CONFIG_CMD_BOOTZ

With v3.9 and later of the Linux Kernel defaulting to multi-platform
images with omap2plus_defconfig, uImage isn't builtable anymore by
default.  Add CONFIG_CMD_BOOTZ so that we can still boot something the
kernel spits out.

Cc: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Reviewed-by: R Sricharan <r.sricharan@ti.com>
11 years agoam335x_evm: Enable CONFIG_CMD_BOOTZ
Tom Rini [Tue, 19 Feb 2013 11:18:15 +0000 (11:18 +0000)]
am335x_evm: Enable CONFIG_CMD_BOOTZ

With v3.9 and later of the Linux Kernel defaulting to multi-platform
images with omap2plus_defconfig, uImage isn't builtable anymore by
default.  Add CONFIG_CMD_BOOTZ so that we can still boot something the
kernel spits out.

Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
11 years agoAllow AM33xx boards to setup GPMC chipselects.
Mark Jackson [Mon, 18 Feb 2013 01:26:29 +0000 (01:26 +0000)]
Allow AM33xx boards to setup GPMC chipselects.

Expose the enable_gpmc_cs_config() function so AM33xx based boards can register GPMC chip selects.

Changes in V4:
- Fix checkpatch errors (TAB -> space mangling)

Changes in V3:
- Fix line wrapping

Changes in V2:
- Indicate this is for AM33xx (not OMAP2)

Signed-off-by: Mark Jackson <mpfj@newflow.co.uk>
Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
11 years agoOMAP3: Initialize gpmc if SPL_ONENAND_SUPPORT is enabled.
Enric Balletbo i Serra [Thu, 7 Feb 2013 23:14:49 +0000 (23:14 +0000)]
OMAP3: Initialize gpmc if SPL_ONENAND_SUPPORT is enabled.

In order to use SPL boot from OneNAND we should initialize the gpmc.

Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
11 years agoSPL: ONENAND: Support SPL to boot u-boot from OneNAND.
Enric Balletbo i Serra [Thu, 7 Feb 2013 23:14:48 +0000 (23:14 +0000)]
SPL: ONENAND: Support SPL to boot u-boot from OneNAND.

This patch will allow use SPL to boot an u-boot from the OneNAND.

Tested with IGEPv2 board with a OneNAND from Numonyx

Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
[trini: Add <spl.h> hunk to fix warning]
Signed-off-by: Tom Rini <trini@ti.com>
11 years agoSPL: ONENAND: Fix onenand_spl_load_image implementation.
Enric Balletbo i Serra [Thu, 7 Feb 2013 23:14:47 +0000 (23:14 +0000)]
SPL: ONENAND: Fix onenand_spl_load_image implementation.

Tested with an IGEPv2 board seems that current onenand_spl_load_image implementation
doesn't work. This patch fixes this function changing the read loop and reading the
onenand blocks from page to page.

Tested with various IGEP based boards with a OneNAND from Numonyx.

Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
11 years agoSPL: ONENAND: Fix some ONENAND related defines.
Enric Balletbo i Serra [Thu, 7 Feb 2013 23:14:46 +0000 (23:14 +0000)]
SPL: ONENAND: Fix some ONENAND related defines.

Some ONENAND related defines use the term ONE_NAND instead of
ONENAND, as the technology name is ONENAND this patch replaces
all these defines.

Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>