Valentin Clement [Sat, 21 Nov 2020 01:17:18 +0000 (20:17 -0500)]
[flang][openacc] Add clause validity tests for the host_data directive
Add some clause validity tests for the host_data directive to avoid future regressions.
Reviewed By: kiranchandramohan
Differential Revision: https://reviews.llvm.org/D91889
Matt Arsenault [Fri, 20 Nov 2020 23:14:28 +0000 (18:14 -0500)]
Verifier: Fix assert when verifying non-pointer byval or preallocated
This would fail on a cast<PointerType> when verifying the attribute if
these attributes were incorrectly used with a non-pointer type.
Matt Arsenault [Sat, 21 Nov 2020 00:02:42 +0000 (19:02 -0500)]
OpaquePtr: Update more tests to use typed sret
Valentin Clement [Sat, 21 Nov 2020 01:04:54 +0000 (20:04 -0500)]
[flang][openacc] Add clause validity tests for the parallel directive
Add some clause validity tests for parallel directive.
Reviewed By: sameeranjoshi
Differential Revision: https://reviews.llvm.org/D91871
Aart Bik [Thu, 19 Nov 2020 20:56:30 +0000 (12:56 -0800)]
[mlir][sparse] refine optimization, add few more test cases
Adds tests for full sum reduction (tensors summed up into scalars)
and the well-known sampled-dense-dense-matrix-product. Refines
the optimizations rules slightly to handle the summation better.
Reviewed By: penpornk
Differential Revision: https://reviews.llvm.org/D91818
Evgenii Stepanov [Thu, 19 Nov 2020 22:34:56 +0000 (14:34 -0800)]
[hwasan] Implement error report callback.
Similar to __asan_set_error_report_callback, pass the entire report to a
user provided callback function.
Differential Revision: https://reviews.llvm.org/D91825
wlei [Sat, 21 Nov 2020 00:20:37 +0000 (16:20 -0800)]
[llvm-profgen][NFC]Fix build failure on different platform
see titile
Test Plan:
ninja & ninja check-llvm
Reviewed By: hoy
Differential Revision: https://reviews.llvm.org/D91897
Michael Jones [Tue, 17 Nov 2020 23:47:19 +0000 (23:47 +0000)]
[libc] Make more of the libc unit testing llvm independent
(WIP, hopefully I'll add more to this patch before submitting)
Reviewed By: sivachandra
Differential Revision: https://reviews.llvm.org/D91665
Michael Jones [Fri, 13 Nov 2020 00:26:57 +0000 (00:26 +0000)]
[libc] Switch functions to using global headers
This switches all of the files in src/string, src/math, and
test/src/math from using relative paths (e.g. `#include “include/string.h”`)
to global paths (e.g. `#include <string.h>`) to make bringing up those
functions on other platforms, such as fuchsia, easier.
Reviewed By: sivachandra
Differential Revision: https://reviews.llvm.org/D91394
Samuel Giddins [Fri, 20 Nov 2020 23:11:34 +0000 (15:11 -0800)]
Don’t break before nested block param when prior param is not a block
Add ScopedTrace to verify methods in FormatTestObjC
Add tests from D17700
Reviewed By: keith, kastiglione
Differential Revision: https://reviews.llvm.org/D91669
Matt Arsenault [Fri, 20 Nov 2020 19:07:11 +0000 (14:07 -0500)]
OpaquePtr: Bulk update tests to use typed sret
wlei [Mon, 19 Oct 2020 17:19:08 +0000 (10:19 -0700)]
[CSSPGO][llvm-profgen] Instruction symbolization
This stack of changes introduces `llvm-profgen` utility which generates a profile data file from given perf script data files for sample-based PGO. It’s part of(not only) the CSSPGO work. Specifically to support context-sensitive with/without pseudo probe profile, it implements a series of functionalities including perf trace parsing, instruction symbolization, LBR stack/call frame stack unwinding, pseudo probe decoding, etc. Also high throughput is achieved by multiple levels of sample aggregation and compatible format with one stop is generated at the end. Please refer to: https://groups.google.com/g/llvm-dev/c/1p1rdYbL93s for the CSSPGO RFC.
This change adds the support of instruction symbolization. Given the RVA on an instruction pointer, a full calling context can be printed side-by-side with the disassembly code.
E.g.
```
Disassembly of section .text [0x0, 0x4a]:
<funcA>:
0: mov eax, edi funcA:0
2: mov ecx, dword ptr [rip] funcLeaf:2 @ funcA:1
8: lea edx, [rcx + 3] fib:2 @ funcLeaf:2 @ funcA:1
b: cmp ecx, 3 fib:2 @ funcLeaf:2 @ funcA:1
e: cmovl edx, ecx fib:2 @ funcLeaf:2 @ funcA:1
11: sub eax, edx funcLeaf:2 @ funcA:1
13: ret funcA:2
14: nop word ptr cs:[rax + rax]
1e: nop
<funcLeaf>:
20: mov eax, edi funcLeaf:1
22: mov ecx, dword ptr [rip] funcLeaf:2
28: lea edx, [rcx + 3] fib:2 @ funcLeaf:2
2b: cmp ecx, 3 fib:2 @ funcLeaf:2
2e: cmovl edx, ecx fib:2 @ funcLeaf:2
31: sub eax, edx funcLeaf:2
33: ret funcLeaf:3
34: nop word ptr cs:[rax + rax]
3e: nop
<fib>:
40: lea eax, [rdi + 3] fib:2
43: cmp edi, 3 fib:2
46: cmovl eax, edi fib:2
49: ret fib:8
```
Test Plan:
ninja check-llvm
Reviewed By: wenlei, wmi
Differential Revision: https://reviews.llvm.org/D89715
wlei [Mon, 19 Oct 2020 17:02:05 +0000 (10:02 -0700)]
[CSSPGO][llvm-profgen] Disassemble text sections
This stack of changes introduces `llvm-profgen` utility which generates a profile data file from given perf script data files for sample-based PGO. It’s part of(not only) the CSSPGO work. Specifically to support context-sensitive with/without pseudo probe profile, it implements a series of functionalities including perf trace parsing, instruction symbolization, LBR stack/call frame stack unwinding, pseudo probe decoding, etc. Also high throughput is achieved by multiple levels of sample aggregation and compatible format with one stop is generated at the end. Please refer to: https://groups.google.com/g/llvm-dev/c/1p1rdYbL93s for the CSSPGO RFC.
This change enables disassembling the text sections to build various address maps that are potentially used by the virtual unwinder. A switch `--show-disassembly` is being added to print the disassembly code.
Like the llvm-objdump tool, this change leverages existing LLVM components to parse and disassemble ELF binary files. So far X86 is supported.
Test Plan:
ninja check-llvm
Reviewed By: wmi, wenlei
Differential Revision: https://reviews.llvm.org/D89712
wlei [Mon, 19 Oct 2020 04:36:54 +0000 (21:36 -0700)]
[CSSPGO][llvm-profgen] Parse mmap events from perf script
This stack of changes introduces `llvm-profgen` utility which generates a profile data file from given perf script data files for sample-based PGO. It’s part of(not only) the CSSPGO work. Specifically to support context-sensitive with/without pseudo probe profile, it implements a series of functionalities including perf trace parsing, instruction symbolization, LBR stack/call frame stack unwinding, pseudo probe decoding, etc. Also high throughput is achieved by multiple levels of sample aggregation and compatible format with one stop is generated at the end. Please refer to: https://groups.google.com/g/llvm-dev/c/1p1rdYbL93s for the CSSPGO RFC.
As a starter, this change sets up an entry point by introducing PerfReader to load profiled binaries and perf traces(including perf events and perf samples). For the event, here it parses the mmap2 events from perf script to build the loader snaps, which is used to retrieve the image load address in the subsequent perf tracing parsing.
As described in llvm-profgen.rst, the tool being built aims to support multiple input perf data (preprocessed by perf script) as well as multiple input binary images. It should also support dynamic reload/unload shared objects by leveraging the loader snaps being built by this change
Reviewed By: wenlei, wmi
Differential Revision: https://reviews.llvm.org/D89707
Amara Emerson [Fri, 20 Nov 2020 21:36:49 +0000 (13:36 -0800)]
[AArch64][GlobalISel] Make G_EXTRACT_VECTOR_ELT of <2 x p0> legal.
Also fix a selection issue for this which was using LLT::isScalar() when it
should have been using !isVector(), add test for that too.
Richard Smith [Fri, 23 Oct 2020 02:29:36 +0000 (19:29 -0700)]
Demangling support for class type non-type template parameter extensions.
The extensions in question are described in:
https://github.com/itanium-cxx-abi/cxx-abi/issues/47
https://github.com/itanium-cxx-abi/cxx-abi/issues/63
Differential Revision: https://reviews.llvm.org/D90003
Alexey Bataev [Fri, 20 Nov 2020 21:03:53 +0000 (13:03 -0800)]
[SLP][NFC]Fix assert condition in newTreeEntry, NFC.
Vitaly Buka [Fri, 20 Nov 2020 11:51:13 +0000 (03:51 -0800)]
[msan] unpoison_file from fclose and fflash
Also unpoison IO_write_base/_IO_write_end buffer
memcpy from fclose and fflash can copy internal bytes without metadata into user memory.
Reviewed By: eugenis
Differential Revision: https://reviews.llvm.org/D91858
Nathan Lanza [Fri, 20 Nov 2020 20:36:29 +0000 (15:36 -0500)]
Revert "[lldb] add a missing dependency on intrinsics_gen"
This reverts commit
137ff7331705179c83533a074d800c481b7df1ac.
This belongs in Apple's Swift fork since this is a direct fix for
unified Swift + llvm + lldb builds.
Zbigniew Sarbinowski [Fri, 20 Nov 2020 19:46:21 +0000 (14:46 -0500)]
Guard init_priority attribute within libc++
Not all platforms support priority attribute. I'm moving conditional definition of this attribute to `include/__config`.
Reviewed By: #libc, aaron.ballman
Differential Revision: https://reviews.llvm.org/D91565
Craig Topper [Fri, 20 Nov 2020 20:08:16 +0000 (12:08 -0800)]
[RISCV] Put RV32 before RV64 in the ValueTypeByHwMode and RegInfoByHwMode lists in RISCVRegisterInfo.td
Addresses post-commit feedback from
77e25b5bc8860e23395f617dcca4940489f6355c
Thomas Raoux [Mon, 16 Nov 2020 18:52:10 +0000 (10:52 -0800)]
[mlir][vector] Add transfer_op LoadToStore forwarding and deadStore optimizations
Add transformation to be able to forward transfer_write into transfer_read
operation and to be able to remove dead transfer_write when a transfer_write is
overwritten before being read.
Differential Revision: https://reviews.llvm.org/D91321
Sam McCall [Fri, 20 Nov 2020 19:51:58 +0000 (20:51 +0100)]
[clangd] semanticTokens: fields are 'property', not 'member'
This isn't obvious, but vscode maps member as 'entity.name.function.member',
so it's really for member functions.
Fixes https://github.com/clangd/vscode-clangd/issues/105
Alexey Bataev [Thu, 19 Nov 2020 17:16:25 +0000 (09:16 -0800)]
[OPENMP]Use the real pointer value as base, not indexed value.
After fix for PR48174 the base pointer for pointer-based
array-sections/array-subscripts will be emitted as `&ptr[idx]`, but
actually it should be just `ptr`, i.e. the address stored in the ponter
to point correctly to the beginning of the array. Currently it may lead
to a crash in the runtime.
Differential Revision: https://reviews.llvm.org/D91805
Craig Topper [Fri, 20 Nov 2020 18:42:51 +0000 (10:42 -0800)]
[RISCV] Remove RV32 HwMode. Use DefaultMode for RV32
Prior to this the DefaultMode was never selected, but RISCVGenDAGISel.inc, RISCVGenRegisterInfo.inc, RISCVGenGlobalISel.inc all ended up with extra table entries for that mode.
This patch removes the RV32 and uses DefaultMode for RV32. This impressively reduces the size of my release+asserts llc binary by about 270K. About 15K from RISCVGenDAGISel.inc, 1-2K from RISCVGenRegisterInfo.inc, but the vast majority from RISCVGenGlobalISel.inc.
Differential Revision: https://reviews.llvm.org/D90973
Alexey Bataev [Tue, 17 Nov 2020 17:30:33 +0000 (09:30 -0800)]
[OPENMP]Honor constantness of captured variables.
Fixes bug reported via Stackoverflow:
https://stackoverflow.com/questions/
64179168/clang-overload-resolution-failure-with-templates-and-openmp-collapse
Need to honor constantness of private/target variables to make the code
compilable.
Differential Revision: https://reviews.llvm.org/D91644
Matt Arsenault [Fri, 20 Nov 2020 15:52:27 +0000 (10:52 -0500)]
OpaquePtr: Bulk update tests to use typed byval
Upgrade of the IR text tests should be the only thing blocking making
typed byval mandatory. Partially done through regex and partially
manual.
Hongtao Yu [Thu, 10 Sep 2020 18:21:19 +0000 (11:21 -0700)]
[CSSPGO] MIR target-independent pseudo instruction for pseudo-probe intrinsic
This change introduces a MIR target-independent pseudo instruction corresponding to the IR intrinsic llvm.pseudoprobe for pseudo-probe block instrumentation. Please refer to https://reviews.llvm.org/D86193 for the whole story.
An `llvm.pseudoprobe` intrinsic call will be lowered into a target-independent operation named `PSEUDO_PROBE`. Given the following instrumented IR,
```
define internal void @foo2(i32 %x, void (i32)* %f) !dbg !4 {
bb0:
%cmp = icmp eq i32 %x, 0
call void @llvm.pseudoprobe(i64
837061429793323041, i64 1)
br i1 %cmp, label %bb1, label %bb2
bb1:
call void @llvm.pseudoprobe(i64
837061429793323041, i64 2)
br label %bb3
bb2:
call void @llvm.pseudoprobe(i64
837061429793323041, i64 3)
br label %bb3
bb3:
call void @llvm.pseudoprobe(i64
837061429793323041, i64 4)
ret void
}
```
the corresponding MIR is shown below. Note that block `bb3` is duplicated into `bb1` and `bb2` where its probe is duplicated too. This allows for an accurate execution count to be collected for `bb3`, which is basically the sum of the counts of `bb1` and `bb2`.
```
bb.0.bb0:
frame-setup PUSH64r undef $rax, implicit-def $rsp, implicit $rsp
TEST32rr killed renamable $edi, renamable $edi, implicit-def $eflags
PSEUDO_PROBE
837061429793323041, 1, 0
$edi = MOV32ri 1, debug-location !13; test.c:0
JCC_1 %bb.1, 4, implicit $eflags
bb.2.bb2:
PSEUDO_PROBE
837061429793323041, 3, 0
PSEUDO_PROBE
837061429793323041, 4, 0
$rax = frame-destroy POP64r implicit-def $rsp, implicit $rsp
RETQ
bb.1.bb1:
PSEUDO_PROBE
837061429793323041, 2, 0
PSEUDO_PROBE
837061429793323041, 4, 0
$rax = frame-destroy POP64r implicit-def $rsp, implicit $rsp
RETQ
```
The target op PSEUDO_PROBE will be converted into a piece of binary data by the object emitter with no machine instructions generated. This is done in a different patch.
Reviewed By: wmi
Differential Revision: https://reviews.llvm.org/D86495
Craig Topper [Fri, 20 Nov 2020 18:29:01 +0000 (10:29 -0800)]
[RISCV] Custom type legalize i32 bswap/bitreverse to GREVIW on RV64 with Zbp extension
Previously we required a sra to pattern match these properly in isel. If the consumer didn't need the result sign extended we'll have an srl instead of sra and fail to match.
This patch switches to custom legalizing to GREVIW using portions of D91259.
Differential Revision: https://reviews.llvm.org/D91457
Hongtao Yu [Wed, 18 Nov 2020 20:42:51 +0000 (12:42 -0800)]
[CSSPGO] IR intrinsic for pseudo-probe block instrumentation
This change introduces a new IR intrinsic named `llvm.pseudoprobe` for pseudo-probe block instrumentation. Please refer to https://reviews.llvm.org/D86193 for the whole story.
A pseudo probe is used to collect the execution count of the block where the probe is instrumented. This requires a pseudo probe to be persisting. The LLVM PGO instrumentation also instruments in similar places by placing a counter in the form of atomic read/write operations or runtime helper calls. While these operations are very persisting or optimization-resilient, in theory we can borrow the atomic read/write implementation from PGO counters and cut it off at the end of compilation with all the atomics converted into binary data. This was our initial design and we’ve seen promising sample correlation quality with it. However, the atomics approach has a couple issues:
1. IR Optimizations are blocked unexpectedly. Those atomic instructions are not going to be physically present in the binary code, but since they are on the IR till very end of compilation, they can still prevent certain IR optimizations and result in lower code quality.
2. The counter atomics may not be fully cleaned up from the code stream eventually.
3. Extra work is needed for re-targeting.
We choose to implement pseudo probes based on a special LLVM intrinsic, which is expected to have most of the semantics that comes with an atomic operation but does not block desired optimizations as much as possible. More specifically the semantics associated with the new intrinsic enforces a pseudo probe to be virtually executed exactly the same number of times before and after an IR optimization. The intrinsic also comes with certain flags that are carefully chosen so that the places they are probing are not going to be messed up by the optimizer while most of the IR optimizations still work. The core flags given to the special intrinsic is `IntrInaccessibleMemOnly`, which means the intrinsic accesses memory and does have a side effect so that it is not removable, but is does not access memory locations that are accessible by any original instructions. This way the intrinsic does not alias with any original instruction and thus it does not block optimizations as much as an atomic operation does. We also assign a function GUID and a block index to an intrinsic so that they are uniquely identified and not merged in order to achieve good correlation quality.
Let's now look at an example. Given the following LLVM IR:
```
define internal void @foo2(i32 %x, void (i32)* %f) !dbg !4 {
bb0:
%cmp = icmp eq i32 %x, 0
br i1 %cmp, label %bb1, label %bb2
bb1:
br label %bb3
bb2:
br label %bb3
bb3:
ret void
}
```
The instrumented IR will look like below. Note that each `llvm.pseudoprobe` intrinsic call represents a pseudo probe at a block, of which the first parameter is the GUID of the probe’s owner function and the second parameter is the probe’s ID.
```
define internal void @foo2(i32 %x, void (i32)* %f) !dbg !4 {
bb0:
%cmp = icmp eq i32 %x, 0
call void @llvm.pseudoprobe(i64
837061429793323041, i64 1)
br i1 %cmp, label %bb1, label %bb2
bb1:
call void @llvm.pseudoprobe(i64
837061429793323041, i64 2)
br label %bb3
bb2:
call void @llvm.pseudoprobe(i64
837061429793323041, i64 3)
br label %bb3
bb3:
call void @llvm.pseudoprobe(i64
837061429793323041, i64 4)
ret void
}
```
Reviewed By: wmi
Differential Revision: https://reviews.llvm.org/D86490
Pete Steinfeld [Fri, 20 Nov 2020 18:33:21 +0000 (10:33 -0800)]
Update OptionComparison.md
Craig Topper [Fri, 20 Nov 2020 18:11:34 +0000 (10:11 -0800)]
[RISCV] Add RISCVISD::ROLW/RORW use those for custom legalizing i32 rotl/rotr on RV64IZbb.
This should result in better utilization of RORIW since we
don't need to look for a SIGN_EXTEND_INREG that may not exist.
Also remove rotl/rotr isel matching to GREVI and just prefer RORI.
This is to keep consistency so we don't have to match ROLW/RORW
to GREVIW as well. I imagine RORI/RORIW performance will be the
same or better than GREVI.
Differential Revision: https://reviews.llvm.org/D91449
Simon Pilgrim [Fri, 20 Nov 2020 18:07:33 +0000 (18:07 +0000)]
[X86][AVX] LowerADDSAT_SUBSAT - avoid X86ISD::BLENDV in UADDSAT/USUBSAT v8i32/v4i64 lowering
Use the OR(CMP,ADD) / AND(CMP,SUB) patterns like we do on SSE targets.
Enable custom lowering for v8i32/v4i64 and generalize the 128-bit lowering code for any vector size - this also lets us use the slightly cheaper codegen for icmp_ugt instead of umin/umax.
William S. Moses [Fri, 20 Nov 2020 18:05:09 +0000 (19:05 +0100)]
[MLIR] Correct block merge bug
Block merging in MLIR will incorrectly merge blocks with operations whose values are used outside of that block. This change forbids this behavior and provides a test where it is illegal to perform such a merge.
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D91745
Yitzhak Mandelbaum [Fri, 20 Nov 2020 16:27:22 +0000 (16:27 +0000)]
[libTooling] Update Transformer's `node` combinator to include the trailing semicolon for decls.
Currently, `node` only includes the semicolon for (some) statements. However,
declarations have the same issue of (potentially) trailing semicolons, so `node`
should behave the same for them.
Differential Revision: https://reviews.llvm.org/D91872
Craig Topper [Fri, 20 Nov 2020 17:41:06 +0000 (09:41 -0800)]
[SelectionDAG][X86][PowerPC][Mips] Replace the default implementation of LowerOperationWrapper with the X86 and PowerPC version.
The default version only works if the returned node has a single
result. The X86 and PowerPC versions support multiple results
and allow a single result to be returned from a node with
multiple outputs. And allow a single result that is not result 0
of the node.
Also replace the Mips version since the new version should work
for it. The original version handled multiple results, but only
if the new node and original node had the same number of results.
Differential Revision: https://reviews.llvm.org/D91846
Alex Zinenko [Fri, 20 Nov 2020 17:50:52 +0000 (18:50 +0100)]
[mlir] add canonicalization patterns for trivial SCF 'for' and 'if'
Add canoncalization patterns to remove zero-iteration 'for' loops, replace
single-iteration 'for' loops with their bodies; remove known-false conditionals
with no 'else' branch and replace conditionals with known value by the
respective region. Although similar transformations are performed at the CFG
level, not all flows reach that level, e.g., the GPU flow may want to remove
single-iteration loops before deciding on loop mapping to thread dimensions.
Reviewed By: herhut
Differential Revision: https://reviews.llvm.org/D91865
Dave Lee [Wed, 18 Nov 2020 21:55:47 +0000 (13:55 -0800)]
[lldb] Add examples and reword source-map help string
Update the help string for `target.source-map` to remove the use of the word
"duple" and to add examples. Additionally I rewrote parts with the goal of
making the description more concrete.
rdar://
68736012
Differential Revision: https://reviews.llvm.org/D91742
Arthur Eubanks [Thu, 19 Nov 2020 23:52:21 +0000 (15:52 -0800)]
[Hexagon][NewPM] Port -hexagon-loop-idiom and add to pipeline
Fixes pmpy-mod.ll under NPM
Reviewed By: kparzysz
Differential Revision: https://reviews.llvm.org/D91829
Stella Stamenova [Fri, 20 Nov 2020 17:26:58 +0000 (09:26 -0800)]
[mlir] Expose parseDimAndSymbolList from affineops.h
This was removed from ops.h, but it is used by onnx-mlir
Reviewed By: mehdi_amini
Differential Revision: https://reviews.llvm.org/D91830
Andrew Wei [Fri, 20 Nov 2020 16:35:53 +0000 (00:35 +0800)]
[DeadMachineInstrctionElim] Post order visit all blocks and Iteratively run DeadMachineInstructionElim pass until nothing dead
Patched by: guopeilin
Reviewed By: hliao,rampitec
Differential Revision: https://reviews.llvm.org/D91513
Simon Pilgrim [Fri, 20 Nov 2020 16:52:15 +0000 (16:52 +0000)]
[X86][SSE] LowerADDSAT_SUBSAT - avoid X86ISD::BLENDV in UADDSAT/USUBSAT custom lowering
Use the OR(CMP,ADD) / AND(CMP,SUB) patterns like we do on pre-SSE4 targets.
We're still using X86ISD::BLENDV on some AVX targets as we don't do custom lowering for >= 256-bit vectors.
Really this (and combineVSelectWithAllOnesOrZeros) needs moving to DAGCombiner, but pre-SSE42 we see the vXi64 comparison type as a 2 x 32-bits result so we can't just rely on ComputeNumSignBits to give us the 'all bits' result we need.
Andrzej Warzynski [Fri, 20 Nov 2020 16:41:55 +0000 (16:41 +0000)]
[flang][driver] Remove unnecessary CMake dependencies (nfc)
Remove clangFrontend from the list of dependencies. These should have
been removed in:
8d51d37e0628bde3eb5a3200507ba7135dfc2751. See also
https://reviews.llvm.org/D87774.
Sanjay Patel [Fri, 20 Nov 2020 16:13:37 +0000 (11:13 -0500)]
[CostModel] mostly remove cost-kind predicate for intrinsics in basic TTI implementation
This is re-applying a combination of
f7eac51b9b3f and
8ec7ea3ddce7 as one patch
to avoid regressions now that we have better testing in place.
Those were reverted with
32dd5870ee31 because of crashing in experimental intrinsics.
That bug should be fixed with
7ae346434.
Paraphrased original commit messages:
This is the last step in removing cost-kind as a consideration in the
basic class model for intrinsics.
See D89461 for the start of that.
Subsequent commits dealt with each of the special-case intrinsics that
had customization here in the basic class. This should remove a barrier
to retrying D87188 (canonicalization to the abs intrinsic).
The ARM and x86 cost diffs seen here may be wrong because the
target-specific overrides have their own bugs, but we hope this is
less wrong - if something has a significant throughput cost, then it
should have a significant size / blended cost too by default.
The only behavioral diff in current regression tests is shown in the
x86 scatter-gather test (which is misplaced or broken because it runs
the entire -O3 pipeline) - we unrolled less, and we assume that is
a improvement.
Exception: in general, we want the *size* cost for a scalar call to be
cheap even if the other costs are expensive - we expect it to just be
a branch with some optional stack manipulation.
It is likely that we will want to carve out some
exceptions/overrides to this rule as follow-up patches for
calls that have some general and/or target-specific difference
to the expected lowering.
This was noticed as a regression in unrolling, so we have a test
for that now along with a couple of direct cost model tests.
If the assumed scalarization costs for the oversized vector
calls are not realistic, that would be another follow-up
refinement of the cost models.
Differential Revision: https://reviews.llvm.org/D90554
Simon Pilgrim [Fri, 20 Nov 2020 16:00:08 +0000 (16:00 +0000)]
[X86] Add SSE42 sat-add test coverage
Check SSE42 targets which have PCMPGTQ
Alex Richardson [Wed, 22 Jul 2020 13:41:06 +0000 (14:41 +0100)]
[AMDGPU] Set the default globals address space to 1
This will ensure that passes that add new global variables will create them
in address space 1 once the passes have been updated to no longer default
to the implicit address space zero.
This also changes AutoUpgrade.cpp to add -G1 to the DataLayout if it wasn't
already to present to ensure bitcode backwards compatibility.
Reviewed by: arsenm
Differential Revision: https://reviews.llvm.org/D84345
Alex Richardson [Fri, 20 Nov 2020 15:17:52 +0000 (15:17 +0000)]
Add a default address space for globals to DataLayout
This is similar to the existing alloca and program address spaces (D37052)
and should be used when creating/accessing global variables.
We need this in our CHERI fork of LLVM to place all globals in address space 200.
This ensures that values are accessed using CHERI load/store instructions
instead of the normal MIPS/RISC-V ones.
The problem this is trying to fix is that most of the time the type of
globals is created using a simple PointerType::getUnqual() (or ::get() with
the default address-space value of 0). This does not work for us and we get
assertion/compilation/instruction selection failures whenever a new call
is added that uses the default value of zero.
In our fork we have removed the default parameter value of zero for most
address space arguments and use DL.getProgramAddressSpace() or
DL.getGlobalsAddressSpace() whenever possible. If this change is accepted,
I will upstream follow-up patches to use DL.getGlobalsAddressSpace() instead
of relying on the default value of 0 for PointerType::get(), etc.
This patch and the follow-up changes will not have any functional changes
for existing backends with the default globals address space of zero.
A follow-up commit will change the default globals address space for
AMDGPU to 1.
Reviewed By: dylanmckay
Differential Revision: https://reviews.llvm.org/D70947
Siva Chandra Reddy [Thu, 19 Nov 2020 20:51:04 +0000 (12:51 -0800)]
[libc] Combine all math differential fuzzers into one target.
Also added diffing of a few more math functions. Combining the diff check
for all of these functions helps us meet the OSS fuzz bar of a minimum of
100 program edges.
Reviewed By: lntue
Differential Revision: https://reviews.llvm.org/D91817
Anton Afanasyev [Fri, 20 Nov 2020 14:49:09 +0000 (17:49 +0300)]
[SLP][Test] Update pr47269.ll test. NFC
Expand test for PR47269 to better demonstrate changes introduced by D90445.
Jamie Schmeiser [Fri, 20 Nov 2020 15:26:33 +0000 (10:26 -0500)]
Reland: Expand existing loopsink testing to also test loopsinking using new pass manager and fix LICM bug.
Summary:
Expand existing loopsink testing to also test loopsinking using new pass
manager. Enable memoryssa for loopsink with new pass manager. This
combination exposed a bug that was previously fixed for loopsink
without memoryssa. When sinking an instruction into a loop, the source
block may not be part of the loop but still needs to be checked for
pointer invalidation. This is the fix for bugzilla #39695 (PR 54659)
expanded to also work with memoryssa.
Respond to review comments. Enable Memory SSA in legacy Loop Sink pass
under EnableMSSALoopDependency option control. Update tests accordingly.
Respond to review comments. Add options controlling whether memoryssa is
used for loop sink, defaulting to off. Expand testing based on these
options.
Respond to review comments. Properly indicated preserved analyses.
This relanding addresses a compile-time performance problem by moving
test for profile data earlier to avoid unnecessary computations.
Author: Jamie Schmeiser <schmeise@ca.ibm.com>
Reviewed By: asbirlea (Alina Sbirlea)
Differential Revision: https://reviews.llvm.org/D90249
Sanjay Patel [Fri, 20 Nov 2020 15:14:44 +0000 (10:14 -0500)]
[CostModel] avoid crashing while finding scalarization overhead
The constrained intrinsics have metadata arguments, so the
tests here were crashing as noted in D90554 (and that was
reverted even though this bug exists independently of that
change).
Chris Kennelly [Sat, 7 Nov 2020 19:14:08 +0000 (14:14 -0500)]
[clang-tidy] Include std::basic_string_view in readability-redundant-string-init.
std::string_view("") produces a string_view instance that compares
equal to std::string_view(), but requires more complex initialization
(storing the address of the string literal, rather than zeroing).
Reviewed By: aaron.ballman
Differential Revision: https://reviews.llvm.org/D91009
Jamie Schmeiser [Fri, 20 Nov 2020 14:43:06 +0000 (09:43 -0500)]
[NFC intended] Refactor the code for printChanged for reuse and to facilitate subsequent reporters of changes to the IR in the new pass manager.
Summary:
[NFC intended] Refactor the code for printChanged for reuse and to facilitate
subsequent reporters of changes to the IR in the new pass manager.
Create abstract template base classes for common functionality and give
classes more appropriate names. The base classes handle all of the
determination of when a function or pass is "interesting" and should be
reported or filtered out. They have pure virtual functions which are called
when a change by a pass has been recognized so the derived class need only
provide the overrides to present the information about the changing IR.
There are at least 2 more change reporters to come (which were presented
in my tutorial at the 2020 llvm developer's meeting) that derive from
these classes.
Respond to review comments: move function out of line, remove inline keyword,
remove unneeded qualifiers, simplify comparison.
Author: Jamie Schmeiser <schmeise@ca.ibm.com>
Reviewed By: aeubanks (Arthur Eubanks), madhur13490 (Madhur Amilkanthwar)
Differential Revision: https://reviews.llvm.org/D87000
Adam Czachorowski [Tue, 17 Nov 2020 13:24:00 +0000 (14:24 +0100)]
[clang] Do not crash on pointer wchar_t pointer assignment.
wchar_t can be signed (thus hasSignedIntegerRepresentation() returns
true), but it doesn't have an unsigned type, which would lead to a crash
when trying to get it.
With this fix, we special-case WideChar types in the pointer assignment
code.
Differential Revision: https://reviews.llvm.org/D91625
Sjoerd Meijer [Fri, 20 Nov 2020 14:04:26 +0000 (14:04 +0000)]
[AArch64] Enable post RA scheduler for Cortex-R82
Just something I forgot when I added the R82. Need to have a look
at crypto and fusing, but will do that as a follow up.
Differential Revision: https://reviews.llvm.org/D91848
Yafei Liu [Fri, 20 Nov 2020 13:50:39 +0000 (08:50 -0500)]
Add a call super attribute plugin example
If a virtual method is marked as call_super, the
override method must call it, simpler feature like @CallSuper
in Android Java.
Stephen Kelly [Tue, 17 Nov 2020 16:50:53 +0000 (16:50 +0000)]
Add documentation illustrating use of IgnoreUnlessSpelledInSource
Differential Revision: https://reviews.llvm.org/D91639
David Green [Fri, 20 Nov 2020 13:30:44 +0000 (13:30 +0000)]
[ARM] Disable WLSTP loops
This checks to see if the loop will likely become a tail predicated loop
and disables wls loop generation if so, as the likelihood for reverting
is currently too high. These should be fairly rare situations anyway due
to the way iterations and element counts are used during lowering. Just
not trying can alter how SCEV's are materialized however, leading to
different codegen.
It also adds a option to disable all while low overhead loops, for
debugging.
Differential Revision: https://reviews.llvm.org/D91663
Pavel Iliin [Thu, 19 Nov 2020 19:52:46 +0000 (19:52 +0000)]
[AArch64] Out-of-line atomics (-moutline-atomics) implementation.
This patch implements out of line atomics for LSE deployment
mechanism. Details how it works can be found in llvm/docs/Atomics.rst
Options -moutline-atomics and -mno-outline-atomics to enable and disable it
were added to clang driver. This is clang and llvm part of out-of-line atomics
interface, library part is already supported by libgcc. Compiler-rt
support is provided in separate patch.
Differential Revision: https://reviews.llvm.org/D91157
Sanjay Patel [Fri, 13 Nov 2020 23:01:39 +0000 (18:01 -0500)]
[CostModel] add tests for math library calls; NFC
This is a partial un-revert of
32dd5870ee31 (originally
df09f82599 ).
I'm adding back the baseline tests first, so we don't have
to back-track as much in case there are still problems.
Sanjay Patel [Fri, 20 Nov 2020 13:03:33 +0000 (08:03 -0500)]
[LoopUnroll] add test for full unroll that is sensitive to cost-model; NFC
See discussion in D90554.
This is a partial un-revert of
32dd5870ee31. I'm adding
back the baseline tests first, so we don't have to
back-track as much in case there are still problems.
Rainer Orth [Fri, 20 Nov 2020 13:06:25 +0000 (14:06 +0100)]
[sanitizers][test] Test sanitizer_common and ubsan_minimal on Solaris
During the initial Solaris sanitizer port, I missed to enable the
`sanitizer_common` and `ubsan_minimal` testsuites. This patch fixes this,
correcting a few unportabilities:
- `Posix/getpass.cpp` failed to link since Solaris lacks `libutil`.
Omitting the library lets the test `PASS`, but I thought adding `%libutil`
along the lines of `%librt` to be overkill.
- One subtest of `Posix/getpw_getgr.cpp` is disabled because Solaris
`getpwent_r` has a different signature than expected.
- `/dev/null` is a symlink on Solaris.
- XPG7 specifies that `uname` returns a non-negative value on success.
Tested on `amd64-pc-solaris2.11` and `sparcv9-sun-solaris2.11`.
Differential Revision: https://reviews.llvm.org/D91606
Stephan Herhut [Fri, 20 Nov 2020 10:21:27 +0000 (11:21 +0100)]
[mlir][std] Canonicalize a dim(memref_reshape) into a load from the shape operand
This canonicalization helps propagate shape information through the program.
Differential Revision: https://reviews.llvm.org/D91854
Sanjay Patel [Fri, 20 Nov 2020 11:40:28 +0000 (06:40 -0500)]
[InstCombine] add test comments for negative tests; NFC
Stephan Herhut [Fri, 20 Nov 2020 10:32:42 +0000 (11:32 +0100)]
[mlir][std] Fold load(tensor_to_memref) into extract_element
This canonicalization is useful to resolve loads into scalar values when
doing partial bufferization.
Differential Revision: https://reviews.llvm.org/D91855
Raphael Isemann [Fri, 20 Nov 2020 12:01:01 +0000 (13:01 +0100)]
Partially revert '[MachO] Update embedded part of ObjectFileMachO for Mangled API change'
Commit
f3aa9e36d91b7b0f4f24f7a3b13cf80c11356e5e fixed the embedded OS
build by removing all passed args for `GetName`/`GetDemangledName`. The motivation
for this was that these arguments were apparently removed in
commit
22b044877d239c40c9a932d1ea47d489c507000f. However, only `GetName`'s language
argument was removed but the mangling preference argument was *not* removed
(and unfortunately had a default argument). So when that commit removed all
the args it didn't just fix the build but it also changed all the mangling
preferences to 'demangled' for all `GetName` calls.
Also some `GetName` calls were outside the TARGET_OS_EMBEDDED ifdef, so
this change ended up breaking the following tests on macOS:
lldb-api :: lang/objc/objc-static-method-stripped/TestObjCStaticMethodStripped.py
lldb-api :: lang/objc/objc-super/TestObjCSuper.py
From what I can see
f3aa9e36d91b7 removed 12 ePreferMangled args and this patch
re-adds 12 args with roughly the same line numbers, so this *should* restore the
old behaviour and also keep the embedded build working. On the other hand,
ObjectFileMachO::ParseSymtab is a very successful attempt at writing
the longest possible function within LLVM, so this fix is partly based
on the engineering principle known as "hoping for the best".
Kazushi (Jam) Marukawa [Thu, 19 Nov 2020 12:31:21 +0000 (21:31 +0900)]
[VE] Change threshold for jump table generation
Implement getMinimumJumpTableEntries() to specify threshold for jump
table genaration. We use 8 for the case of PIC mode to relieve the
impact of PIC calculation required to implement PIC mode jump table.
Update jump table regression test also.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D91785
Stephan Herhut [Fri, 20 Nov 2020 10:46:22 +0000 (11:46 +0100)]
[mlir][std] Fold comparisons when the operands are equal
For equal operands, comparisons can be decided statically.
Differential Revision: https://reviews.llvm.org/D91856
Mikhail Goncharov [Fri, 20 Nov 2020 12:09:28 +0000 (13:09 +0100)]
Revert "[mlir][Linalg] Fuse sequence of Linalg operation (on buffers)"
This reverts commit
f8284d21a8e294d58a0acd4b8b2e906d7a9f110c.
Revert "[mlir][Linalg] NFC: Expose some utility functions used for promotion."
This reverts commit
0c59f51592ef5c014352994369f5216c6376fae1.
Revert "Remove unused isZero function"
This reverts commit
0f9f0a4046e11c2b4c130640f343e3b2b5db08c1.
Change
f8284d21 led to multiple failures in IREE compilation.
Simon Pilgrim [Fri, 20 Nov 2020 12:02:57 +0000 (12:02 +0000)]
[clang][CodeGen] Move WebAssembly specific tests to WebAssembly subtarget folder
Minor cleanup to move more target specific tests out of the root codegen test folder
Simon Pilgrim [Fri, 20 Nov 2020 11:47:27 +0000 (11:47 +0000)]
[clang][CodeGen] Move riscv specific tests to RISCV subtarget folder
Minor cleanup to move more target specific tests out of the root codegen test folder
Rainer Orth [Fri, 20 Nov 2020 12:02:15 +0000 (13:02 +0100)]
[sanitizer_common][test] Disable CombinedAllocator32Compact etc. on Solaris/sparcv9
As reported in PR 48202, two allocator tests `FAIL` on Solaris/sparcv9,
presumably because Solaris uses the full 64-bit address space and the
allocator cannot deal with that:
SanitizerCommon-Unit :: ./Sanitizer-sparcv9-Test/SanitizerCommon.CombinedAllocator32Compact
SanitizerCommon-Unit :: ./Sanitizer-sparcv9-Test/SanitizerCommon.SizeClassAllocator32Iteration
This patch disables the tests.
Tested on `sparcv9-sun-solaris2.11`.
Differential Revision: https://reviews.llvm.org/D91622
Rainer Orth [Fri, 20 Nov 2020 11:52:18 +0000 (12:52 +0100)]
[sanitizer_common][test] Disable FastUnwindTest.* on SPARC
Many of the `FastUnwindTest.*` tests `FAIL` on SPARC, both Solaris and
Linux. The issue is that the fake stacks used in those tests don't match
the requirements of the SPARC unwinder in `sanitizer_stacktrace_sparc.cpp`
which has to look at the register window save area.
I'm disabling the failing tests.
Tested on `sparcv9-sun-solaris2.11`.
Differential Revision: https://reviews.llvm.org/D91618
Simon Pilgrim [Fri, 20 Nov 2020 11:40:59 +0000 (11:40 +0000)]
Fix MSVC "not all control paths return a value" warnings. NFCI.
David Spickett [Mon, 17 Aug 2020 14:02:04 +0000 (15:02 +0100)]
[lldb][AArch64/Linux] Show memory tagged memory regions
This extends the "memory region" command to
show tagged regions on AArch64 Linux when the MTE
extension is enabled.
(lldb) memory region the_page
[0x0000fffff7ff8000-0x0000fffff7ff9000) rw-
memory tagging: enabled
This is done by adding an optional "flags" field to
the qMemoryRegion packet. The only supported flag is
"mt" but this can be extended.
This "mt" flag is read from /proc/{pid}/smaps on Linux,
other platforms will leave out the "flags" field.
Where this "mt" flag is received "memory region" will
show that it is enabled. If it is not or the target
doesn't support memory tagging, the line is not shown.
(since majority of the time tagging will not be enabled)
Testing is added for the existing /proc/{pid}/maps
parsing and the new smaps parsing.
Minidump parsing has been updated where needed,
though it only uses maps not smaps.
Target specific tests can be run with QEMU and I have
added MTE flags to the existing helper scripts.
Reviewed By: labath
Differential Revision: https://reviews.llvm.org/D87442
Eugene Zhulenev [Fri, 20 Nov 2020 10:42:28 +0000 (02:42 -0800)]
[mlir] Automatic reference counting for Async values + runtime support for ref counted objects
Depends On D89963
**Automatic reference counting algorithm outline:**
1. `ReturnLike` operations forward the reference counted values without
modifying the reference count.
2. Use liveness analysis to find blocks in the CFG where the lifetime of
reference counted values ends, and insert `drop_ref` operations after
the last use of the value.
3. Insert `add_ref` before the `async.execute` operation capturing the
value, and pairing `drop_ref` before the async body region terminator,
to release the captured reference counted value when execution
completes.
4. If the reference counted value is passed only to some of the block
successors, insert `drop_ref` operations in the beginning of the blocks
that do not have reference coutned value uses.
Reviewed By: silvas
Differential Revision: https://reviews.llvm.org/D90716
Sebastian Neubauer [Thu, 15 Oct 2020 11:26:44 +0000 (13:26 +0200)]
[AMDGPU] Implement flat scratch init for pal
Extract the scratch offset from the scratch buffer descriptor that is
stored in the global table.
Differential Revision: https://reviews.llvm.org/D91701
QingShan Zhang [Fri, 20 Nov 2020 09:56:53 +0000 (09:56 +0000)]
[NFC][Test] Update test for IEEE Long Double
Max Kazantsev [Fri, 20 Nov 2020 09:52:50 +0000 (16:52 +0700)]
[Test] Auto-update checks in a test
Georgii Rymar [Thu, 19 Nov 2020 15:23:27 +0000 (18:23 +0300)]
[llvm-readelf/obj] - Improve error reporting when dumping group sections.
Our code that dumps groups has 3 noticeable issues:
1) It uses `unwrapOrError` in many places.
2) It doesn't allow reporting unique warnings, because the `getGroups` helper is not
a member of `DumpStyle<ELFT>`.
3) It might just crash. See the comment for `StrTableOrErr->data() + Sym.st_name` line.
In this patch I am starting addressing these points.
For start I've converted one of `unwrapOrError` calls to a unique warning.
Differential revision: https://reviews.llvm.org/D91798
Kirill Bobyrev [Fri, 20 Nov 2020 09:38:41 +0000 (10:38 +0100)]
[clangd] NFC: Reorder headers in tests accordig to Clang-Tidy
Georgii Rymar [Thu, 12 Nov 2020 09:46:59 +0000 (12:46 +0300)]
[llvm-readobj] - Introduce `forEachRelocationDo` helper.
Our `printStackSize` implementation currently uses
API like `RelocationRef`, `object::symbol_iterator`.
It is not ideal as it doesn't allow
to handle possible error conditions properly.
Some time ago I started rewriting it and this NFC patch is
a one more step toward to it. Here I am introducing the
`forEachRelocationDo` helper. With it it is possible to iterate
over all kinds of relocations, what is helpful for improving
the code in `printStackSize` and around.
Differential revision: https://reviews.llvm.org/D91530
AndreyChurbanov [Fri, 20 Nov 2020 09:15:00 +0000 (12:15 +0300)]
Revert "[OpenMP] Add support for Intel's umonitor/umwait"
This reverts commit
9cfad5f9c5bfd985f1bc8b0954f58013c5236e58.
Max Kazantsev [Fri, 20 Nov 2020 08:57:44 +0000 (15:57 +0700)]
[Test] Add tests demonstrating a bug in SCEV, PR48225
Slightly simplified version of original test reported by Congzhe Cao.
Michał Górny [Fri, 20 Nov 2020 08:43:08 +0000 (09:43 +0100)]
[lldb] [test/Register] XFAIL x86-fp-write on Darwin
Michał Górny [Fri, 20 Nov 2020 08:42:13 +0000 (09:42 +0100)]
Revert "[LLDB] Fixing lldb/test/Shell/Register/x86-fp-write.test"
The problem is not specific to arch but to the whole Darwin platform.
Reverts:
0fd04337a17138174adf9e6d408cf9c885dea086
Liu, Chen3 [Fri, 30 Oct 2020 03:11:35 +0000 (11:11 +0800)]
[X86] Add support for vex, vex2, vex3, and evex for MASM
For MASM syntax, the prefixes are not enclosed in braces.
The assembly code should like:
"evex vcvtps2pd xmm0, xmm1"
Differential Revision: https://reviews.llvm.org/D90441
Georgii Rymar [Thu, 12 Nov 2020 12:16:57 +0000 (15:16 +0300)]
[lib/Object] - Generalize the RelocationResolver API.
This allows to reuse the RelocationResolver from the code
that doesn't want to deal with `RelocationRef` class.
I am going to use it in llvm-readobj. See the description
of D91530 for more details.
Differential revision: https://reviews.llvm.org/D91533
Qiu Chaofan [Fri, 20 Nov 2020 07:04:57 +0000 (15:04 +0800)]
[NFC] Pre-commit test for flt_rounds on PowerPC
Arthur Eubanks [Thu, 19 Nov 2020 22:40:33 +0000 (14:40 -0800)]
[PGO] Make -disable-preinline work with NPM
Fixes cspgo_profile_summary.ll under NPM.
Reviewed By: xur
Differential Revision: https://reviews.llvm.org/D91826
Eric Christopher [Fri, 20 Nov 2020 05:59:16 +0000 (21:59 -0800)]
Temporarily Revert "[CostModel] remove cost-kind predicate for intrinsics in basic TTI implementation"
as it's causing crashes in the optimizer. A reduced testcase has been posted as a follow-up.
This reverts commit
f7eac51b9b3f780c96ca41913293851c5acb465b.
Temporarily Revert "[CostModel] make default size cost for libcalls small (again)" as it depends upon the primary revert.
This reverts commit
8ec7ea3ddce7379e13e8dfb4a5260a6d2004aa1c.
Temporarily Revert "[CostModel] add tests for math library calls; NFC" as it depends upon the primary revert.
This reverts commit
df09f825995b10da03f148133c119f52c94fd6e4.
Temporarily Revert "[LoopUnroll] add test for full unroll that is sensitive to cost-model; NFC" as it depends upon the primary revert.
This reverts commit
618d555e8d926a83161774df2035519c387269db.
Kazu Hirata [Fri, 20 Nov 2020 06:07:55 +0000 (22:07 -0800)]
[CodeGen] Use llvm::is_contained (NFC)
Haruki Imai [Fri, 20 Nov 2020 05:07:31 +0000 (05:07 +0000)]
[mlir] Support big-endian systems in DenseElementsAttr (multiple word)
D78076 supports big endian in DenseElementsAttr, but does not work when
APInt has multiple words(the number of bits > 64). This patch updates
D78076 to support it.
This patch removed the fix in D78076 and re-implemented to support multiple words.
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D80272
Geoffrey Martin-Noble [Fri, 20 Nov 2020 03:35:13 +0000 (19:35 -0800)]
Remove unused isZero function
Unused since https://reviews.llvm.org/D91503 and triggering
-Wunused-function
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D91838
MaheshRavishankar [Fri, 20 Nov 2020 03:04:57 +0000 (19:04 -0800)]
[mlir][Linalg] NFC: Expose some utility functions used for promotion.
Exposing some utility functions from Linalg to allow for promotion of
fused views outside of the core tile+fuse logic.
This is an alternative to patch D91322 which adds the promotion logic
to the tileAndFuse method. Downside with that approach is that it is
not easily customizable based on needs.
Differential Revision: https://reviews.llvm.org/D91503
MaheshRavishankar [Fri, 20 Nov 2020 03:02:31 +0000 (19:02 -0800)]
[mlir][Linalg] Fuse sequence of Linalg operation (on buffers)
Enhance the tile+fuse logic to allow fusing a sequence of operations.
Differential Revision: https://reviews.llvm.org/D90991
MaheshRavishankar [Fri, 20 Nov 2020 02:59:48 +0000 (18:59 -0800)]
[mlir][Linalg] Add utility function that return static loop bounds of Linalg ops
Differential Revision: https://reviews.llvm.org/D91749
Bill Wendling [Wed, 18 Nov 2020 12:06:09 +0000 (04:06 -0800)]
[PowerPC] Allow a '%' prefix for registers in CFI directives
Clang generates a '%' prefix for some registers in CFI directives. E.g.
".cfi_register lr, r12" becomes ".cfi_register lr, %r12" after
processing.
Differential Revision: https://reviews.llvm.org/D91735
Arthur Eubanks [Fri, 20 Nov 2020 02:13:22 +0000 (18:13 -0800)]
[test] Fix multiply-minimal.ll
Duncan P. N. Exon Smith [Thu, 19 Nov 2020 02:57:50 +0000 (18:57 -0800)]
ADT: Split out isSafeToReferenceAfterResize helper to use early returns, NFC
The assertion logic in SmallVector::assertSafeToReferenceAfterResize is
hard to follow; split out SmallVector::isSafeToReferenceAfterResize and
add early returns and comments. No functionality change here.