Andy Shevchenko [Sat, 11 Sep 2021 18:27:42 +0000 (21:27 +0300)]
x86: tangier: acpi: Add GPIO card detection to SDHCI #2
On Intel Tangier the SDHCI #2 provides SD card connection.
Add GPIO card detection for it.
Fixes:
39665beed6f7 ("x86: tangier: Enable ACPI support for Intel Tangier")
BugLink: https://github.com/edison-fw/meta-intel-edison/issues/135
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
Andy Shevchenko [Fri, 10 Sep 2021 07:59:27 +0000 (10:59 +0300)]
x86: edison: Mark eMMC non-removable
eMMC is non-removable on Intel Edison board. Fix the DTS accordingly.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Patrick Delaunay [Tue, 14 Sep 2021 12:14:52 +0000 (14:14 +0200)]
arm: dts: stm32mp1: use ssbl partition name for U-Boot
Continue to use the "ssbl" name for GPT partition of secondary boot
stage = U-Boot for basic boot with SPL to avoid to disturb existing user.
The "fip" partition name is only used for TFA_BOOT with FIP, it is a TF-A
BL2 requirement; it the default configuration for STMicroelectronics
boards.
Fixes:
b73e8bf453f8 ("arm: stm32mp: add defconfig for trusted boot with FIP")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Tom Rini [Mon, 20 Sep 2021 12:45:26 +0000 (08:45 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- wdt: dw: Fix passing NULL pointer to reset functions (Sean)
Sean Anderson [Sat, 11 Sep 2021 19:11:30 +0000 (15:11 -0400)]
wdt: dw: Fix passing NULL pointer to reset functions
reset_*_bulk expects a real pointer.
Fixes:
4f7abafe1c ("driver: watchdog: reset watchdog in designware_wdt_stop() function")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tom Rini [Sun, 19 Sep 2021 14:38:20 +0000 (10:38 -0400)]
Merge tag 'dm-pull-18sep21' of https://source.denx.de/u-boot/custodians/u-boot-dm
Revert the public-key-embedded-in-executable patches so this does not form
part of an official release before it is agreed.
Simon Glass [Mon, 2 Aug 2021 14:44:31 +0000 (08:44 -0600)]
Revert "efi_capsule: Move signature from DTB to .rodata"
This was unfortunately applied despite much discussion about it beiong
the wrong way to implement this feature.
Revert it before too many other things are built on top of it.
This reverts commit
ddf67daac39de76d2697d587148f4c2cb768f492.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 2 Aug 2021 14:44:30 +0000 (08:44 -0600)]
Revert "mkeficapsule: Remove dtb related options"
This reverts commit
f86caab058ff062ce72b24cd1ab9ec1253cc1352.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 2 Aug 2021 14:44:29 +0000 (08:44 -0600)]
Revert "doc: Update CapsuleUpdate READMEs"
This reverts commit
316ab801c0d91c02b21b8be1e3db7e69555364e9.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tom Rini [Fri, 17 Sep 2021 22:51:57 +0000 (18:51 -0400)]
Merge branch '2021-09-17-TI-platform-updates'
- Assorted bugfixes for TI platforms
Nishanth Menon [Tue, 31 Aug 2021 18:20:48 +0000 (13:20 -0500)]
arm: mach-k3: common: Make sure firmware sections are loaded prior to armv8 startup
With Device Manager firmware in an elf file form, we cannot load the FIT
image to the exact same address as any of the executable sections of the
elf file itself is located.
However, the device tree descriptions for the ARMV8 bootloader/OS
includes DDR regions only the final sections in DDR where the Device
Manager firmware is actually executing out of.
As the R5 uC is usually operating at a slower rate than an ARMv8 MPU,
by starting the Armv8 ahead of parsing the elf and copying the correct
sections to the required memories creates a race condition where the
ARMv8 could overwrite the elf image loaded from the FIT image prior to
the R5 completing parsing and putting the correct sections of elf in
the required memory locations. OR create rather obscure debug conditions
where data in the section is being modified by ARMV8 OS while the elf
copy is in progress.
To prevent all these conditions, lets make sure that the elf parse and
copy operations are completed ahead of ARMv8 being released to execute.
We will pay a penalty of elf copy time, but that is a valid tradeoff in
comparison to debug of alternate scenarios.
Signed-off-by: Nishanth Menon <nm@ti.com>
Roger Quadros [Wed, 8 Sep 2021 20:28:59 +0000 (15:28 -0500)]
arm: mach-k3: am6_init: Prioritize MSMC traffic over DDR in NAVSS Northbridge
NB0 is bridge to SRAM and NB1 is bridge to DDR.
To ensure that SRAM transfers are not stalled due to delays during DDR
refreshes, SRAM traffic should be higher priority (threadmap=2) than
DDR traffic (threadmap=0).
This fixup is critical to provide deterministic access latency to
MSMC from ICSSG, it applies to all AM65 silicon revisions and is due
to incorrect reset values (has no erratum id) and statically setting
things up should be done independent of usecases and board.
This specific style of Northbridge configuration is specific only to
AM65x devices, follow-on K3 devices have different data prioritization
schemes (ASEL and the like) and hence the fixup applies purely to
AM65x.
Without this fix, ICSSG TX lock-ups due to delays in MSMC transfers in
case of SR1 devices, on SR2 devices, lockups were not observed so far
but high retry rates of ICSSG Ethernet (icssg-eth) and, thus, lower
throughput.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Andrew F. Davis <afd@ti.com>
Acked-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Benoit Parrot <bparrot@ti.com>
[Jan: rebased, dropped used define, extended commit log]
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
[Nishanth: Provide relevant context in the commit message]
Signed-off-by: Nishanth Menon<nm@ti.com>
Suman Anna [Tue, 7 Sep 2021 22:16:58 +0000 (17:16 -0500)]
clk: ti: k3: Update driver to account for divider flags
The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in
turn serve as inputs to other HSDIV output clocks. These clocks use
the actual value to compute the divider clock rate, and need to be
registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk
driver and data lacks the infrastructure to pass in divider flags.
Update the driver and data to account for these divider flags.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Dave Gerlach [Tue, 7 Sep 2021 22:16:57 +0000 (17:16 -0500)]
clk: ti: k3-pll: Change DIV_CTRL programming to read-modify-write
There are three different divider values in the DIV_CTRL register
controlled by the k3-pll driver. Currently the ti_pll_clk_set_rate
function writes the entire register when programming plld, even though
plld only resides in the lower 6 bits.
Change the plld programming to read-modify-write to only affect the
relevant bits for plld and to preserve the other two divider values
present in the upper 16 bits, otherwise they will always get set to zero
when programming plld.
Fixes:
0aa2930ca192 ("clk: add support for TI K3 SoC PLL")
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Dave Gerlach [Tue, 7 Sep 2021 22:16:56 +0000 (17:16 -0500)]
arm: mach-k3: Add note to auto-generated files
Add a note to the automatically generated clk-data and dev-data files
for j721e and j7200 to indicate that they are in fact auto-generated and
should not be hand edited.
Also adjust TI URL to use https instead of http and also add an empty
line before first header inclusion.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Suman Anna [Tue, 7 Sep 2021 22:16:55 +0000 (17:16 -0500)]
arm: mach-k3: j7200: Fix clk-data parenting for postdiv PLL clocks
The TI K3 Fractional PLLs use two programmable POSTDIV1 and POSTDIV2
divisors to generate the final FOUTPOSTDIV clock. These are in sequence
with POSTDIV2 following the POSTDIV1 clock. The current J7200 clock data
has the POSTDIV2 clock as the parent for the POSTDIV1 clock, which is
opposite of the actual implementation. Fix the data by simply adjusting
the register bit-shifts.
The Main PLL1 POSTDIV clocks were also defined incorrectly using Main PLL0
register values, fix these as well.
Fixes:
277729eaf373 ("arm: mach-k3: Add platform data for j721e and j7200")
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Suman Anna [Tue, 7 Sep 2021 22:16:54 +0000 (17:16 -0500)]
arm: mach-k3: j721e: Fix clk-data parenting for postdiv PLL clocks
The TI K3 Fractional PLLs use two programmable POSTDIV1 and POSTDIV2
divisors to generate the final FOUTPOSTDIV clock. These are in sequence
with POSTDIV2 following the POSTDIV1 clock. The current J721E clock data
has the POSTDIV2 clock as the parent for the POSTDIV1 clock, which is
opposite of the actual implementation. Fix the data by simply adjusting
the register bit-shifts.
The Main PLL1 POSTDIV clocks were also defined incorrectly using Main PLL0
register values, fix these as well.
Fixes:
277729eaf373 ("arm: mach-k3: Add platform data for j721e and j7200")
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Suman Anna [Tue, 27 Jul 2021 23:24:40 +0000 (18:24 -0500)]
arm: mach-k3: common: Add a release_resources_for_core_shutdown() stub
Add a weak release_resources_for_core_shutdown() stub implementation
that can be overridden by actual implementation if a SoC supports that
function.
Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Suman Anna [Tue, 27 Jul 2021 23:24:39 +0000 (18:24 -0500)]
firmware: ti_sci: Include linux/err.h in ti_sci_protocol.h
The common TI SCI header file uses some macros from err.h and these
get exercised when CONFIG_TI_SCI_PROTOCOL is not defined. Include
the linux/err.h header file in this header file directly rather
than relying on source files to include it to eliminate any
potential build errors.
While at this, reorder the existing header file include to the
beginning of the file.
Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Christophe Leroy [Wed, 13 May 2020 05:30:03 +0000 (05:30 +0000)]
MAINTAINERS: POWERPC MPC8XX: Update email address
Our email addresses have changed from @c-s.fr to @csgroup.eu
Update entry in MAINTAINERS
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Tom Rini [Wed, 15 Sep 2021 19:22:46 +0000 (15:22 -0400)]
Merge branch 'rpi-next' of https://source.denx.de/u-boot/custodians/u-boot-raspberrypi
Ivan's patch fixes a kernel warning when booting RPi2, as the firmware
already
provides a frambebuffer node.
Marek's patch fixes random crashes on 32 bit RPi4 with newer firmware.
My SMBIOS patchesfixes an issue that show up with
e4f8e543f1 ("smbios: Drop the unused Kconfig options").
Basically the SMBIOS table broke and wasn't readable anymore.
Ivan T. Ivanov [Tue, 10 Aug 2021 14:31:14 +0000 (16:31 +0200)]
rpi: Conditionally add simple-framebuffer node
It appears that RPi firmware has already added framebuffer
node under /chosen, at least on RPi 2 versions. So check
for this and don't add duplicate node.
Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Marek Szyprowski [Thu, 17 Jun 2021 09:22:03 +0000 (11:22 +0200)]
ARM: bcm283x: change the virtual address of the XHCI PCI device base
Move the XHCI PCI device base up in the virtual address space. This fixes
initialization failure observed with newer Raspberry Pi firmware, later
than
63b1922311 ("firmware: arm_loader: Update armstubs with those from
PR 117). It looks that chosing 0xff800000 as the XHCI PCI device base
conflicts with the updated ARM/VideoCore firmware.
This also requires to reduce the size of the mapped PCI device region
from 8MiB to 4MiB to fit into 32bit address space. This is still enough
for the XHCI PCI device.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Nicolas Saenz Julienne <nsaenz@kernel.org>
Tested-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Matthias Brugger [Mon, 12 Apr 2021 13:38:52 +0000 (15:38 +0200)]
configs: rpi: Enable SMBIOS sysinfo driver
Enable this driver to allow U-Boot to get SMBIOS table information from
a device tree node.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Acked-by: Fabian Vogt <fvogt@suse.com>
Matthias Brugger [Mon, 12 Apr 2021 13:38:51 +0000 (15:38 +0200)]
arm: dts: bcm283x: Add minimal smbios information
At present SMBIOS tables are empty, which breaks some use-cases that
rely on that. Add some minimal information to fulfill this.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Tom Rini [Tue, 14 Sep 2021 22:58:10 +0000 (18:58 -0400)]
Prepare v2021.10-rc4
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Tue, 14 Sep 2021 22:48:05 +0000 (18:48 -0400)]
configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py
Signed-off-by: Tom Rini <trini@konsulko.com>
Alexandru Gagniuc [Tue, 14 Sep 2021 20:53:33 +0000 (15:53 -0500)]
image: Avoid erroneous double byte-swap in CRC value
The hash algorithm selection was streamlined in commit
92055e138f28
("image: Drop if/elseif hash selection in calculate_hash()"). Said
commit kept the call to cpu_to_uimage() to convert the CRC to big
endian format.
This would have been correct when calling crc32_wd(). However, the
->hash_func_ws member of crc32 points to crc32_wd_buf(), which already
converts the CRC to big endian. On a little endian host, doing both
conversions results in a little-endian CRC. This is incorrect.
To remedy this, simply drop the call to cpu_to_uimage(), thus only
doing the byte-order conversion once.
Fixes:
92055e138f28 ("image: Drop if/elseif hash selection in
calculate_hash()")
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tom Rini [Tue, 14 Sep 2021 19:47:07 +0000 (15:47 -0400)]
Merge branch '2021-09-14-assorted-fixes'
- Assorted bugfixes
Alexandru Gagniuc [Wed, 18 Aug 2021 22:49:02 +0000 (17:49 -0500)]
image: rsa: Move padding_algos to linker lists
We are not guaranteed to have the padding_pkcs_15_verify symbol since
commit
92c960bc1d ("lib: rsa: Remove #ifdefs from rsa.h"), and
commit
61416fe9df ("Kconfig: FIT_SIGNATURE should not select RSA_VERIFY")
The padding_algos only make sense with RSA verification, which can now
be disabled in lieu of ECDSA. In fact this will lead to build failures
because of the missing symbol mentioned earlier.
To resolve this, move the padding_algos to a linker list, with
declarations moved to rsa_verify.c. This is consistent with commit
6909edb4ce ("image: rsa: Move verification algorithm to a linker list")
One could argue that the added #ifdef USE_HOSTCC is ugly, and should
be hidden within the U_BOOT_PADDING_ALGO() macro. However, this would
be inconsistent with the "cryptos" list. This logic for was not
previously explored:
Without knowledge of the U_BOOT_PADDING_ALGO() macro, its use is
similar to something being declared. However, should #ifndef
USE_HOSTCC be part of the macro, it would not be obvious that it
behaves differently on host code and target code. Having the #ifndef
outside the macro makes this obvious.
Also, the #ifdef is not always necessary. For example ecda-verify
makes use of U_BOOT_CRYPTO_ALGO() without any accompanying #ifdefs.
The fundamental issue is a lack of separation of host and target code
in rsa_verify. Therefore, the declaration of a padding algo with the
external #ifdef is more readable and consistent.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Yuan Fang [Wed, 8 Sep 2021 11:06:48 +0000 (19:06 +0800)]
pinctrl: fix typo
fix typo in pinctrl Kconfig file to avoid git commit failure on
some commit hooks check.
Signed-off-by: Yuan Fang <fangyuanseu@gmail.com>
Oleksandr Suvorov [Wed, 1 Sep 2021 13:05:08 +0000 (16:05 +0300)]
lib: fix typos in Kconfig
There are trivial typos in the Kconfig file. Fixed them.
Also, fixed grammar in the descriptions with typos.
Fixes:
d56b4b1974 ("configs: Migrate RBTREE, LZO, CMD_MTDPARTS, CMD_UBI and CMD_UBIFS")
Fixes:
7264f2928b ("spl: fit: Eanble GZIP support for image decompression")
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Heinrich Schuchardt [Sat, 28 Aug 2021 10:13:05 +0000 (12:13 +0200)]
lib/rsa: don't use NULL as key_id
If keydir is not provided but name is we want to use name as key_id.
But with the current coding name is only used on its own if it is NULL
and keydir is provided which never occurs.
Fixes:
824ee745fbca ("lib/rsa: Use the 'keyfile' argument from mkimage")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Tue, 14 Sep 2021 01:03:36 +0000 (21:03 -0400)]
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
- a fix for U-Boot 2021.10 to bring back MMC boot on older boards.
Andre Przywara [Fri, 3 Sep 2021 15:49:16 +0000 (16:49 +0100)]
sunxi: mmc: A20: Fix MMC optimisation
Some SoCs (as seen on A20) seem to misreport the MMC FIFO level if the
FIFO is completely full: the level size reads as zero, but the FIFO_FULL
bit is set. We won't do a single iteration of the read loop in this
case, so will be stuck forever.
Check for this situation and use a safe minimal FIFO size instead when
we hit this case.
This fixes MMC boot on A20 devices after the MMC FIFO optimisation
(
9faae5457f52).
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Tom Rini [Mon, 13 Sep 2021 22:23:24 +0000 (18:23 -0400)]
Merge branch '2021-09-09-finish-pre-DM_PCI-removal'
- Finish removing the non-DM_PCI legacy code.
Simon Glass [Mon, 2 Aug 2021 00:54:44 +0000 (18:54 -0600)]
pci: Drop DM_PCI
This option has not effect now. Drop it, using PCI instead where needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 2 Aug 2021 00:54:43 +0000 (18:54 -0600)]
pci: Drop PCI_INDIRECT_BRIDGE
This does not work with driver model so can be removed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 2 Aug 2021 00:54:34 +0000 (18:54 -0600)]
net: Drop DM_PCI check from designware driver
We don't need this check anymore since when PCI is enabled, driver model
is always used.
Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 2 Aug 2021 00:54:25 +0000 (18:54 -0600)]
pci: acpi: Drop DM_PCI check from ahci
We don't need these checks anymore since when PCI is enabled, driver model
is always used.
Drop them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 2 Aug 2021 00:54:18 +0000 (18:54 -0600)]
pci: Drop DM_PCI check from fdtdec
We don't need this check anymore since when PCI is enabled, driver model
is always used.
Sadly this doesn't work with nds32 for some reason to do with the
toolchain. Add a work-around for that.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 2 Aug 2021 00:54:16 +0000 (18:54 -0600)]
pci: Drop old code from header file
We don't need this code anymore since when PCI is enabled, driver model is
always used.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 2 Aug 2021 00:54:15 +0000 (18:54 -0600)]
ppc: Remove UCP1020 board
This board has not been converted to CONFIG_DM_PCI by the deadline.
Remove it.
Note that we have to add CONFIG_SPIFLASH to scripts/config_whitelist.txt
because it's not really migrated at this point.
Acked-by: Michael Durrant <mdurrant@arcturusnetworks.com>
Acked-by: Oleksandr Zhadan <oleks@arcturusnetworks.com>
Acked-by: Oleksandr Zhadan and Michael Durrant <arcsupport@arcturusnetworks.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Handle CONFIG_SPIFLASH differently and delete Kconfig file]
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 13 Sep 2021 12:31:41 +0000 (08:31 -0400)]
Merge tag 'mmc-2021-9-13' of https://source.denx.de/u-boot/custodians/u-boot-mmc
Support using mmc command for enumerating mmc card in a given mode
Fix device_remove in mmc
Fix switch issue with send_status disabled
Drop 1ms delay in fsl_esdhc command sending
Revert "mmc: sdhci: set to INT_DATA_END when there are data"
Michael Walle [Fri, 10 Sep 2021 09:20:52 +0000 (11:20 +0200)]
mmc: fsl_esdhc: remove 1ms sleep in esdhc_send_cmd_common()
Since the beginning of this driver which was initially for the MPC8379
and MPC8536 SoCs, there is this spurious 1ms delay. According to the
comment it should actually be only 8 clock cycles. Esp. during EFI block
transfers, this 1ms add up to a significant delay and slows down EFI
boot.
I couldn't find any mention in the MPC8536 that there should be a delay
of 8 clock cycles between commands. The SD card specification mentions that
the clock has to be left enabled for 8 cycles after a command or
response. But I don't see how this delay will help with this.
Go ahead and just remove it. If there will ever be any regression we can
introduce a compile time flag, but for now I'd like to keep it simple.
In the split off imx driver this delay was also removed in commit
9098682200e6 ("mmc: fsl_esdhc_imx: remove the 1ms delay before sending
command").
Signed-off-by: Michael Walle <michael@walle.cc>
Tom Rini [Mon, 13 Sep 2021 00:33:21 +0000 (20:33 -0400)]
Merge tag 'efi-2021-10-rc4-2' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request for efi-2021-10-rc4-2
Documentation:
* improve documentation of U-Boot for /config DT node
* integrate bloblist documentation
UEFI:
* correct usage of EFI_CALL()
* code tidy up
Tom Rini [Sat, 11 Sep 2021 12:15:56 +0000 (08:15 -0400)]
Merge branch '2021-09-10-assorted-TI-updates'
- A number of TI platform bugfixes
Heinrich Schuchardt [Thu, 9 Sep 2021 05:47:05 +0000 (07:47 +0200)]
efi_loader: simplify efi_watchdog_timer_notify()
We can call do_reset() directly without invoking the UEFI API.
This decreases the code size.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Thu, 9 Sep 2021 05:39:40 +0000 (07:39 +0200)]
efi_loader: eliminate EFI_CALL() in nvedit_efi.c
Reduce the code size by avoiding using the external UEFI API and using our
internal functions instead.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Ilias Apalodimas [Wed, 8 Sep 2021 21:30:49 +0000 (00:30 +0300)]
efi_loader: Remove incorrect calls of EFI_CALL in TCG2
There is two unneeded EFI_CALL references in tcg2_measure_pe_image().
The first one in efi_search_protocol() and the second on in the device path
calculation. The second isn't even a function we should be calling, but a
pointer assignment, which happens to work with the existing macro.
While at it switch the malloc call to a calloc, remove the unnecessary cast
and get rid of an unneeded if statement before copying the device path
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Tue, 7 Sep 2021 06:56:47 +0000 (08:56 +0200)]
efi_loader: require CONFIG_BLK
The move to driver model should by now be completed. To be able to remove
pre-driver model code from our block IO code require CONFIG_BLK=y for UEFI
support.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Masahisa Kojima [Mon, 6 Sep 2021 03:04:12 +0000 (12:04 +0900)]
efi_loader: boot_service_capability_min should be capitalized
boot_service_capability_min is constant, it should be capitalized.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Simon Glass [Thu, 9 Sep 2021 20:10:32 +0000 (14:10 -0600)]
doc: Complete the list of available runtime-config options
The current list is missing a few items. Add them.
Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Simon Glass [Thu, 9 Sep 2021 20:10:31 +0000 (14:10 -0600)]
doc: Tidy up the bindings for the config/ node
Sort these and add a type so it is clear how to set the value. Add a note
about usage to the top. Correct the 'no-keyboard' binding which is missing
a prefix.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Simon Glass [Wed, 8 Sep 2021 13:33:52 +0000 (07:33 -0600)]
bloblist: Move to rST format
Move this documentation to the new format.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Oleksandr Suvorov [Thu, 9 Sep 2021 19:12:09 +0000 (22:12 +0300)]
doc: board: toradex: fix file names
Fix the documentation file names: s/apalix/apalis/.
Fixes:
e98ea49a0e ("toradex: MAINTAINERS: entries for new reST docs")
Fixes:
3730106cf0 ("doc: board: apalis-imx8x: add documentation")
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Acked-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Aswath Govindraju [Thu, 26 Aug 2021 15:58:59 +0000 (21:28 +0530)]
configs: j72*_evm: Define the buffer sizes for dfu
On J721e R5 SPL, dfu buffer for loading sysfw.itb image gets allocated
before DRAM gets initialized. So, the buffer gets allocated in MCU L3
RAM. The current buffer size to be allocated is 256KB and the available
total heap memory is 0x70000 (448KB). This leads to NOMEM errors during
allocation.
In other cases when constraints such as above are not present fix the size
of buffers to the sector size in OSPI for proper functioning.
Also, if CONFIG_SYS_DFU_DATA_BUF_SIZE is defined and
CONFIG_SYS_DFU_MAX_FILE_SIZE is not defined then the max file size for dfu
transfer is defined as CONFIG_SYS_DFU_DATA_BUF_SIZE.
Fix these by setting appropriate buffer sizes in their respective defconfig
files and defining the max file size as 8 MB which is the default dfu
buffer size.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Aswath Govindraju [Thu, 26 Aug 2021 15:58:58 +0000 (21:28 +0530)]
environment: ti: k3_dfu: Increase the size allocated for bootloader images in dfu_alt_info_ram
The size of u-boot.img is above 1MB and that of tispl.bin is close to 1MB,
in case of j721e. Therefore, increase the sizes allocated for tispl.bin and
u-boot.img to 2 MB and 4 MB respectively, in dfu_alt_info_ram environment
variable.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Aswath Govindraju [Thu, 26 Aug 2021 15:58:57 +0000 (21:28 +0530)]
arm: dts: k3-j721e-r5-*.dts: Fix clock-names property in the usb0 instance
In the cdns3 usb driver, the clock name looked for is ref. Therefore, fix
the clock-names property in usb0 instance for proper initialization of
cdns3 usb gadget driver.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Roger Quadros [Tue, 24 Aug 2021 11:07:27 +0000 (14:07 +0300)]
ARM: dts: Fix node status to "okay" on TI boards
As per Device Tree Specification [1], the status parameter of nodes can
be "okay", "disabled", etc. "ok" is not a valid parameter.
U-boot Driver Model does not recognize status="ok" either and treats
the node as disabled.
[1] https://github.com/devicetree-org/devicetree-specification/releases/tag/v0.3
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
Suman Anna [Sat, 14 Aug 2021 06:49:01 +0000 (01:49 -0500)]
tools: k3_fit_atf: Fix DM binary FIT load addresses
The DM binary runs on the MCU R5F Core0 after R5 SPL on J721E and J7200
SoCs. The binary is built alongside the TFA, OPTEE and A72 SPL binaries
and included in the tispl.bin FIT image. The R5 SPL loads the DM binary
at 0xA0000000 address, based on the value used in the FIT image build
script. The DM binary though is an ELF image and not a regular binary
file, and so is processed further to load the actual program segments
using the U-Boot's standard ELF loader library.
The DM binary does leverage a certain portion of DDR for its program
segments, and typically reserves 16 MB of DDR at 0xA0000000 with the
1st MB used for IPC between Linux and the remote processor, and
remaining memory for firmware segments. This can cause an incomplete
loading of the program segments if the DM binary is larger than 1 MB,
due to overlap of the initial loaded binary and the actual program
segments.
Fix this by using the address 0x89000000, which matches the current
"addr_mcur5f0_0load" env variable used by R5 SPL before the DM firmware
inclusion into the tispl.bin.
Fixes:
df5363a67f35 ("tools: k3_fit_atf: add DM binary to the FIT image")
Signed-off-by: Suman Anna <s-anna@ti.com>
Aswath Govindraju [Mon, 9 Aug 2021 17:02:23 +0000 (22:32 +0530)]
arm: dts: k3-am642-evm-u-boot: Add u-boot, dm-spl tag in the pinmux node of mmc1
Add u-boot,dm-spl tag in the pinmux device tree node, required for MMCSD1
subsystem.
Fixes:
b6059ddc45b9 ("arm: dts: k3-am642: Add r5 specific dt support")
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Matwey V. Kornilov [Sat, 7 Aug 2021 11:17:38 +0000 (14:17 +0300)]
am33xx: Fix USB for am335x boards
USB nodes were mistakenly disabled in
commit
942853dd96df ("arm: dts: Resync BeagleBone device trees")
This commit is to fix the following issue:
starting USB...
No working controllers found
USB is stopped. Please issue 'usb start' first.
starting USB...
No working controllers found
Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=
0782e8572ce43f521ed6ff15e4a7ab9aa5acdc85
Fixes:
942853dd96df ("arm: dts: Resync BeagleBone device trees")
Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Paul Barker <paul.barker@sancloud.com>
Aswath Govindraju [Wed, 4 Aug 2021 13:12:46 +0000 (18:42 +0530)]
include: configs: am64x_evm: Add env variables for booting to kernel using USB MSC device
Add env variables for booting to kernel from USB MSC device. The second
partition in the USB MSC device needs to formatted as ext4 file system with
kernel and dtb images, present in the /boot folder.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Aswath Govindraju [Wed, 4 Aug 2021 13:12:45 +0000 (18:42 +0530)]
environment: ti: mmc.h: Make the finduuid generic for usage across different device types
Make finduuid generic by making it dependent on the boot variable. For
example, this can now be used for finding the uuid of partitions in usb
device too.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Aswath Govindraju [Wed, 4 Aug 2021 13:12:44 +0000 (18:42 +0530)]
board: ti: am64x: Add support for fixing dr_mode while booting from USB
Fix the dr_mode in the U-Boot device tree blob, by reading the mode field
from the USB Boot Configuration fields. The dr_mode will only be fixed when
booting from USB.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Derald D. Woods [Mon, 2 Aug 2021 03:46:19 +0000 (03:46 +0000)]
ARM: omap3: evm: Enable booting 'fitImage' with DEFAULT_FIT_TI_ARGS
This commit uses the existing DEFAULT_MMC_TI_ARGS and
DEFAULT_FIT_TI_ARGS defintions to replace the 'mmc*' environment
variables in the configuration. The check for the 'boot_fit' is handled
like the 'am335x_*' boards with 'CONFIG_BOOTCOMMAND'.
Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
Tom Rini [Sat, 31 Jul 2021 23:21:58 +0000 (19:21 -0400)]
arm: am335x: Enable SPL_OF_CONTROL on some configs
Both am335x_boneblack_vboot and am335x_evm_spiboot require
SPL_OF_CONTROL to function but are currently missing this option. Add
it.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Fri, 10 Sep 2021 12:24:19 +0000 (08:24 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- mvebu: dts: Armada8k enable mdio (Sven)
- a37xx: pci: Fix / enhance error handling (Pali)
- mvebu: espressobin/turris_: Enable GPT partition support (Pali)
- mvebu: sata_mv: Probe all ports (Tony)
- a37xx: pci: Don't spam about PIO Response Status (Marek)
Ye Li [Tue, 17 Aug 2021 09:20:34 +0000 (17:20 +0800)]
mmc: fix device_remove when HS400_ES is enabled
HS400_ES is missed when down grade to HS mode during
device_remove the mmc device
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Ye Li [Tue, 17 Aug 2021 09:20:33 +0000 (17:20 +0800)]
mmc: fix switch issue with send_status disabled
When send_status is false or wait_dat0 is not supported, the switch
function should not send CMD13 but directly return.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Aswath Govindraju [Fri, 13 Aug 2021 17:34:42 +0000 (23:04 +0530)]
doc: usage: mmc: Document usage of speed mode in "mmc dev" and "mmc rescan"
Add documentation on the usage of "mmc dev" and "mmc rescan" commands to
set user defined speed modes.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Aswath Govindraju [Fri, 13 Aug 2021 17:34:41 +0000 (23:04 +0530)]
mmc: Add support for enumerating MMC card in a given mode using mmc command
Add support for enumerating MMC card in a given mode using mmc rescan and
mmc dev commands. The speed mode is provided as the last argument in these
commands and is indicated using the index from enum bus_mode in
include/mmc.h. A speed mode can be set only if it has already been enabled
in the device tree.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
Yuezhang.Mo@sony.com [Wed, 17 Mar 2021 06:44:37 +0000 (06:44 +0000)]
Revert "mmc: sdhci: set to INT_DATA_END when there are data"
This reverts commit
17ea3c862865c0d704646f67dbf8412f9ff54f59.
In eMMC specification, for the response-with-busy(R1b, R5b)
command, the DAT0 will driven to LOW as BUSY status, and in
sdhci specification, the transfer complete bit should be wait
for BUSY status de-assert.
All response-with-busy commands don't contain data, the data
judgement is no need.
Signed-off-by: Yuezhang.Mo <Yuezhang.Mo@sony.com>
Reviewed-by: Andy Wu <Andy.Wu@sony.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Marek Behún [Tue, 7 Sep 2021 15:27:08 +0000 (17:27 +0200)]
arm: a37xx: pci: Don't spam about PIO Response Status
Use dev_dbg() instead of dev_err() in pcie_advk_check_pio_status().
For example CRS is not an error status, it just says that the request
should be retried.
Without this, U-Boot spams the terminal with
pcie_advk pcie@
d0070000: Non-posted PIO Response Status: UR, 0xc80 @ 0x100000
pcie_advk pcie@
d0070000: Non-posted PIO Response Status: UR, 0xc80 @ 0x108000
pcie_advk pcie@
d0070000: Non-posted PIO Response Status: UR, 0xc80 @ 0x110000
pcie_advk pcie@
d0070000: Non-posted PIO Response Status: UR, 0xc80 @ 0x120000
pcie_advk pcie@
d0070000: Non-posted PIO Response Status: UR, 0xc80 @ 0x128000
pcie_advk pcie@
d0070000: Non-posted PIO Response Status: UR, 0xc80 @ 0x130000
...
when a device is not connected to a PCIe switch (Unsupported Request
from the switch).
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tony Dinh [Mon, 6 Sep 2021 23:28:35 +0000 (16:28 -0700)]
arm: marvell: Dreamplug: fix typo in eth1 name
Ethernet 1 should be ethernet-controller@76000.
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tony Dinh [Sun, 5 Sep 2021 21:48:25 +0000 (14:48 -0700)]
arm: mvebu : sata_mv should probe all ports
While a board could have multiple SATA ports, some of the ports might
not have a disk attached to them. So while probing for disks,
sata_mv_probe() should continue probing all ports, and skip one with
no disk attached.
Tests with:
- Seagate Goflex Net (Marvell Kirkwood 88F6281) out-of-tree u-boot.
- Zyxel NSA325 (Marvell Kirkwood 88F6282 out-of-tree u-boot.
Observation:
If a board has 2 or more SATA ports, and there is only one disk
attached to one of the ports, sata_mv_probe() does not return
a successful probe status. And if only one disk is attached to the
2nd port (i.e. port 1), it is not probed at all.
Patch Description:
Let sata_mv_probe() continues probing all ports, even if there
is error in probing a given port, and then return a successful
status if there is at least one port was probed successfully.
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Thu, 2 Sep 2021 10:00:51 +0000 (12:00 +0200)]
arm: mvebu: a38x: Fix 5200000 baudrate
Fix baudrate value 5150000 which was added in commit
ead4864fa6cc ("arm:
mvebu: a38x: Define supported UART baudrates").
Exact value for divisor 3 with 250 MHz TCLK is 5208333 baudrate. In above
commit I incorrectly rounded it to 5150000 value due to testing with
USB-UART hw which incorrectly reported exact value and divisor configured
on other other end of UART link.
Fix this value to 520000 baudrate which is more close to the exact hardware
value and also has less fraction parts.
Signed-off-by: Pali Rohár <pali@kernel.org>
Fixes:
ead4864fa6cc ("arm: mvebu: a38x: Define supported UART baudrates")
Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Thu, 2 Sep 2021 08:46:37 +0000 (10:46 +0200)]
arm: mvebu: espressobin: Enable GPT partition support
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Thu, 2 Sep 2021 08:34:00 +0000 (10:34 +0200)]
arm: mvebu: turris_{omnia, mox}: GPT partition support
This allows U-Boot to access filesystems on GPT partitioned disks.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Fri, 27 Aug 2021 12:14:44 +0000 (14:14 +0200)]
arm: a37xx: pci: Implement re-issuing config requests on CRS response
According to PCIe base specification, if CRS Software Visibility is not
enabled, the Root Complex must re-issue the Configuration Request as a new
Request.
Normally this part of Root Complex is implemented in hardware but aardvark
is somehow special and does not implement it in hardware and expect that
handling of config requests are fully implemented in software.
This re-issuing functionality is required also because U-Boot does not
support CRS Software Visibility feature and therefore expects that Root
Complex re-issues requests as is specified in PCIe base specification.
Retry / re-issue config request up to the PIO_MAX_RETRIES, to prevent
infinite loop. After retry count exceed PIO_MAX_RETRIES, returns failure.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Fri, 27 Aug 2021 12:14:43 +0000 (14:14 +0200)]
arm: a37xx: pci: Disable returning CRS response
There was mistake in commit
4cd61c43fd51 ("arm: a37xx: pci: Fix handling
PIO config error responses"). U-Boot does not support handling of CRS
return value for PCI_VENDOR_ID config read request and also does not set
CRSSVE bit.
Therefore disable returning CRS response for now.
Signed-off-by: Pali Rohár <pali@kernel.org>
Fixes:
4cd61c43fd51 ("arm: a37xx: pci: Fix handling PIO config error responses")
Reviewed-by: Stefan Roese <sr@denx.de>
Sven Auhagen [Tue, 24 Aug 2021 08:14:25 +0000 (10:14 +0200)]
arm: mvebu: dts: Armada8k enable mdio
Since mvpp2 is using the new mdio driver and the cp110 has been
synced with the linux upstream, the mdio has to enabled in the
device tree file.
This is missing for some device tree files and therefore the
network cards do not come online.
Signed-off-by: Sven Auhagen <sven.auhagen@voleatech.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Tony Dinh [Thu, 12 Aug 2021 21:33:34 +0000 (14:33 -0700)]
arm: kirkwood: Sheevaplug: Update board maintainer
Change maintainer to me. Prafulla is no longer active in U-Boot community.
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Lokesh Vutla [Fri, 3 Sep 2021 07:15:37 +0000 (12:45 +0530)]
MAINTAINERS: Update ARM TI entry
Move TI maintainership to Tom.
Updated with the following commands:
find ./ -name MAINTAINERS | xargs sed -i s/"Lokesh Vutla <lokeshvutla@ti.com>"/"Tom Rini <trini@konsulko.com>"/g
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Acked-by: Tom Rini <trini@konsulko.com>
Tom Rini [Thu, 9 Sep 2021 14:57:34 +0000 (10:57 -0400)]
Kconfig: Drop duplicate 'select SHA512' instances
When dropping SHA512_ALGO in general, we didn't catch some cases where
an option was selecting both SHA512 and SHA512_ALGO and caused them to
select SHA512 twice. Kconfig doesn't complain, but this is still wrong
and should be corrected.
Fixes:
e60e44993120 ("lib: Drop SHA512_ALGO in lieu of SHA512")
Reported-by: Andreas Schwab <schwab@suse.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Thu, 9 Sep 2021 01:23:55 +0000 (21:23 -0400)]
Merge branch '2021-09-08-fix-FIT-hash-algos-in-SPL'
- Merge some fixes to how we enable hash algorithms for FIT images in
SPL. This fixes a few cases where we should have had some options
enabled, but did not. This also removes otherwise unused options in a
few other cases.
Alexandru Gagniuc [Fri, 3 Sep 2021 00:54:22 +0000 (19:54 -0500)]
image: Drop IMAGE_ENABLE_{MD5, CRC32} #defines
These are no longer used, so drop them.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Alexandru Gagniuc [Fri, 3 Sep 2021 00:54:21 +0000 (19:54 -0500)]
image: Drop if/elseif hash selection in calculate_hash()
calculate_hash() would try to select the appropriate hashing function
by a if/elseif contruct. But that is exactly why hash_lookup_algo()
exists, so use it instead.
This does mean that we now have to 'select HASH' to make sure we get
the hash_lookup_algo() symbol. However, the change makes sense because
even basic FITs will have to deal with "hash" nodes.
My only concern is that the 'select SPL_HASH' might cause some
platform to grow above its SPL size allowance
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
[trini: Make FSL_CAAM be implied only on ARM && SPL]
Signed-off-by: Tom Rini <trini@konsulko.com>
Alexandru Gagniuc [Fri, 3 Sep 2021 00:54:20 +0000 (19:54 -0500)]
common: Move MD5 hash to hash_algo[] array.
MD5 is being called directly in some places, but it is not available
via hash_lookup_algo("md5"). This is inconsistent with other hasing
routines. To resolve this, add an "md5" entry to hash_algos[].
The #ifdef clause looks funnier than those for other entries. This is
because both MD5 and SPL_MD5 configs exist, whereas the other hashes
do not have "SPL_" entries. The long term plan is to get rid of the
ifdefs, so those should not be expected to survive much longer.
The md5 entry does not have .hash_init/update/finish members. That's
okay because hash_progressive_lookup_algo() will catch that, and
return -EPROTONOSUPPORT, while hash_lookup_algo() will return the
correct pointer.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
[trini: Use CONFIG_IS_ENABLED not IS_ENABLED for MD5 check]
Signed-off-by: Tom Rini <trini@konsulko.com>
Alexandru Gagniuc [Fri, 3 Sep 2021 00:54:19 +0000 (19:54 -0500)]
common/spl: Drop [ST]PL_HASH_SUPPORT in favor of [ST]PL_HASH
All of these configs exist. Stick to using CONFIG_[ST]PL_HASH, and drop all
references to CONFIG_[ST]PL_HASH_SUPPORT. This means we need for
CHAIN_OF_TRUST to select SPL_HASH now.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
[trini: Add TPL case, fix CHAIN_OF_TRUST, other tweaks]
Signed-off-by: Tom Rini <trini@konsulko.com>
Alexandru Gagniuc [Fri, 3 Sep 2021 00:54:18 +0000 (19:54 -0500)]
lib: Drop SHA512_ALGO in lieu of SHA512
SHA512_ALGO was used as a "either SHA512 or SHA384", although the
implementations of these two algorithms share a majority of code.
From a Kconfig interface perspective, it makes sense to present two
distinct options. This requires #ifdefing out the SHA512
implementation from sha512.c. The latter doesn't make any sense.
It's reasonable to say in Kconfig that SHA384 depends on SHA512, and
seems to be the more polite way to handle the selection.
Thus, automatically select SHA512 when SHA384 is enabled.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Alexandru Gagniuc [Fri, 3 Sep 2021 00:54:17 +0000 (19:54 -0500)]
common: Remove unused CONFIG_FIT_SHAxxx selectors
Originally CONFIG_FIT_SHAxxx enabled specific SHA algos for and only
for hash_calculate() in common/image-fit.c. However, since commit
14f061dcb1 ("image: Drop IMAGE_ENABLE_SHAxxx"),
the correct selector was changed to CONFIG_SHAxxx.
The extra "_FIT_" variants are neither used, nor needed. Remove them.
One defconfig disables FIT_SHA256, which is now changed to 'SHA256'.
CMD_MVEBU_BUBT needs to select select SHA256 to avoid undefined
references to "sha256_*()". bubt.c needs sha256, so this selection is
correct. It is not clear why this problem did not manifest before.
Note that SHA selection in SPL is broken for this exact reason. There
is no corresponding SPL_SHAxxx. Fixing this is is beyond the scope of
this change.
Also note that we make CONFIG_FIT now imply SHA256, to make up for
FIT_SHA256 previously being a default y option.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
[trini: Add imply SHA256 to FIT]
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Tue, 7 Sep 2021 11:58:56 +0000 (07:58 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-riscv
Zong Li [Wed, 1 Sep 2021 07:01:43 +0000 (15:01 +0800)]
riscv: lib: modify the indent
We usually use a space in function declaration, rather than a tab.
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Zong Li [Wed, 1 Sep 2021 07:01:42 +0000 (15:01 +0800)]
board: sifive: use ccache driver instead of helper function
Invokes the common cache_init function to initialize ccache.
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Zong Li [Wed, 1 Sep 2021 07:01:41 +0000 (15:01 +0800)]
riscv: lib: implement enable_caches for sifive cache
The enable_caches is a generic hook for architecture-implemented, we
define this function to enable composable cache of sifive platforms.
In sifive_cache, it invokes the generic cache_enable interface of cache
uclass to execute the relative implementation in SiFive ccache driver.
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Zong Li [Wed, 1 Sep 2021 07:01:40 +0000 (15:01 +0800)]
common: board_r: support enable_caches for RISC-V
The enable_caches is a generic hook for architecture-implemented, we
leverage this function to enable caches for RISC-V
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Zong Li [Wed, 1 Sep 2021 07:01:39 +0000 (15:01 +0800)]
cache: add sifive composable cache driver
This driver is currently responsible for enabling all ccache ways.
Composable cache could be configure as RAM or cache, we will use it as
RAM at the beginning to put the u-boot SPL there. In u-boot proper
phrase, we will use the composable cache as cache, and try to enable the
cache ways.
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Thomas Skibo [Sun, 15 Aug 2021 23:04:03 +0000 (16:04 -0700)]
riscv: Add missing sentinel in ocores_i2c.c
The ocores_i2c.c driver is missing a sentinel at the end of
the compatible strings list. This causes the "dm compat" command
to spew garbage.
Signed-off-by: Thomas Skibo <thomas-git@skibo.net>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>