Michael Strauss [Thu, 17 Nov 2022 15:40:46 +0000 (10:40 -0500)]
drm/amd/display: Fix DCN2.1 default DSC clocks
[WHY]
Low dscclk in high vlevels blocks some DSC modes.
[HOW]
Update dscclk to 1/3 of dispclk.
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
David Galiffi [Fri, 18 Nov 2022 22:35:22 +0000 (17:35 -0500)]
drm/amd/display: Enable dp_hdmi21_pcon support
[Why]
It is not enabled for DCN3.0.1, 3.0.2, 3.0.3.
[How]
Add `dc->caps.dp_hdmi21_pcon_support = true` to these DCN versions.
Reviewed-by: Martin Leung <Martin.Leung@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: David Galiffi <David.Galiffi@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dmytro Laktyushkin [Mon, 21 Nov 2022 20:29:35 +0000 (15:29 -0500)]
drm/amd/display: prevent seamless boot on displays that don't have the preferred dig
Seamless boot requires VBIOS to select dig matching to link order wise. A significant
amount of dal logic makes assumption we are using preferred dig for eDP and if this
isn't the case then seamless boot is not supported.
Reviewed-by: Martin Leung <Martin.Leung@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aurabindo Pillai [Mon, 21 Nov 2022 20:48:23 +0000 (15:48 -0500)]
drm/amd/display: trigger timing sync only if TG is running
[Why&How]
If the timing generator isnt running, it does not make sense to trigger
a sync on the corresponding OTG. Check this condition before starting.
Otherwise, this will cause error like:
*ERROR* GSL: Timeout on reset trigger!
Fixes:
dc55b106ad477c ("drm/amd/display: Disable phantom OTG after enable for plane disable")
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chris Park [Thu, 5 May 2022 05:55:52 +0000 (01:55 -0400)]
drm/amd/display: Remove DTB DTO on CLK update
[Why]
DTB DTO is programmed more correctly during
link enable. Programming them on CLK update
which may arrive frequently and sporadically
per flip throws off DTB DTO.
[How]
Remove DTB DTO programming on clock update.
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Chris Park <Chris.Park@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 1 Dec 2022 21:41:53 +0000 (16:41 -0500)]
drm/amdgpu: expand on GPUVM documentation
Expand the GPUVM documentation to better describe the
hardware functionality and use cases it serves.
v2: Fixed a couple of spelling mistakes.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Link: https://lore.kernel.org/r/20221201214153.8453-2-alexander.deucher@amd.com
Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Alex Deucher [Thu, 1 Dec 2022 21:41:52 +0000 (16:41 -0500)]
drm/amdgpu: add GART, GPUVM, and GTT to glossary
Add definitions to clarify GPU virtual memory.
v2: clarify the terms a bit more
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Suggested-by: Peter Maucher <bellosilicio@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Link: https://lore.kernel.org/r/20221201214153.8453-1-alexander.deucher@amd.com
Prike Liang [Thu, 1 Dec 2022 03:17:31 +0000 (11:17 +0800)]
drm/amdgpu/sdma_v4_0: turn off SDMA ring buffer in the s2idle suspend
In the SDMA s0ix save process requires to turn off SDMA ring buffer for
avoiding the SDMA in-flight request, otherwise will suffer from SDMA page
fault which causes by page request from in-flight SDMA ring accessing at
SDMA restore phase.
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2248
Cc: stable@vger.kernel.org # 6.0,5.15+
Fixes:
f8f4e2a51834 ("drm/amdgpu: skipping SDMA hw_init and hw_fini for S0ix.")
Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Tested-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jiadong.Zhu [Wed, 7 Sep 2022 02:24:37 +0000 (10:24 +0800)]
drm/amdgpu: MCBP based on DRM scheduler (v9)
Trigger Mid-Command Buffer Preemption according to the priority of the software
rings and the hw fence signalling condition.
The muxer saves the locations of the indirect buffer frames from the software
ring together with the fence sequence number in its fifo queue, and pops out
those records when the fences are signalled. The locations are used to resubmit
packages in preemption scenarios by coping the chunks from the software ring.
v2: Update comment style.
v3: Fix conflict caused by previous modifications.
v4: Remove unnecessary prints.
v5: Fix corner cases for resubmission cases.
v6: Refactor functions for resubmission, calling fence_process in irq handler.
v7: Solve conflict for removing amdgpu_sw_ring.c.
v8: Add time threshold to judge if preemption request is needed.
v9: Correct comment spelling. Set fence emit timestamp before rsu assignment.
Cc: Christian Koenig <Christian.Koenig@amd.com>
Cc: Luben Tuikov <Luben.Tuikov@amd.com>
Cc: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Cc: Michel Dänzer <michel@daenzer.net>
Signed-off-by: Jiadong.Zhu <Jiadong.Zhu@amd.com>
Acked-by: Luben Tuikov <luben.tuikov@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jiadong.Zhu [Wed, 13 Jul 2022 09:30:25 +0000 (17:30 +0800)]
drm/amdgpu: Modify unmap_queue format for gfx9 (v6)
1. Modify the unmap_queue package on gfx9. Add trailing fence to track the
preemption done.
2. Modify emit_ce_meta emit_de_meta functions for the resumed ibs.
v2: Restyle code not to use ternary operator.
v3: Modify code format.
v4: Enable Mid-Command Buffer Preemption for gfx9 by default.
v5: Optimize the flag bit set for emit_fence.
v6: Modify log message for preemption timeout.
Cc: Christian Koenig <Christian.Koenig@amd.com>
Cc: Michel Dänzer <michel@daenzer.net>
Cc: Luben Tuikov <Luben.Tuikov@amd.com>
Signed-off-by: Jiadong.Zhu <Jiadong.Zhu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jiadong.Zhu [Wed, 7 Sep 2022 02:03:10 +0000 (10:03 +0800)]
drm/amdgpu: Add software ring callbacks for gfx9 (v8)
Set ring functions with software ring callbacks on gfx9.
The software ring could be tested by debugfs_test_ib case.
v2: Set sw_ring 2 to enable software ring by default.
v3: Remove the parameter for software ring enablement.
v4: Use amdgpu_ring_init/fini for software rings.
v5: Update for code format. Fix conflict.
v6: Remove unnecessary checks and enable software ring on gfx9 by default.
v7: Use static array for software ring names and priorities.
v8: Stop creating software rings if no gfx ring existed.
Cc: Christian Koenig <Christian.Koenig@amd.com>
Cc: Luben Tuikov <Luben.Tuikov@amd.com>
Cc: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Cc: Michel Dänzer <michel@daenzer.net>
Cc: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Jiadong.Zhu <Jiadong.Zhu@amd.com>
Acked-by: Luben Tuikov <luben.tuikov@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jiadong.Zhu [Wed, 7 Sep 2022 01:40:47 +0000 (09:40 +0800)]
drm/amdgpu: Introduce gfx software ring (v9)
The software ring is created to support priority context while there is only
one hardware queue for gfx.
Every software ring has its fence driver and could be used as an ordinary ring
for the GPU scheduler.
Multiple software rings are bound to a real ring with the ring muxer. The
packages committed on the software ring are copied to the real ring.
v2: Use array to store software ring entry.
v3: Remove unnecessary prints.
v4: Remove amdgpu_ring_sw_init/fini functions,
using gtt for sw ring buffer for later dma copy
optimization.
v5: Allocate ring entry dynamically in the muxer.
v6: Update comments for the ring muxer.
v7: Modify for function naming.
v8: Combine software ring functions into amdgpu_ring_mux.c
v9: Use kernel-doc comment on the get_rptr function.
Cc: Christian Koenig <Christian.Koenig@amd.com>
Cc: Luben Tuikov <Luben.Tuikov@amd.com>
Cc: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Cc: Michel Dänzer <michel@daenzer.net>
Signed-off-by: Jiadong.Zhu <Jiadong.Zhu@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Acked-by: Luben Tuikov <luben.tuikov@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hamza Mahfooz [Tue, 15 Nov 2022 16:58:45 +0000 (11:58 -0500)]
drm/amd/display: add FB_DAMAGE_CLIPS support
Currently, userspace doesn't have a way to communicate selective updates
to displays. So, enable support for FB_DAMAGE_CLIPS for DCN ASICs newer
than DCN301, convert DRM damage clips to dc dirty rectangles and fill
them into dirty_rects in fill_dc_dirty_rects().
Reviewed-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Peter Maucher [Thu, 1 Dec 2022 15:38:24 +0000 (16:38 +0100)]
drm/amdgpu: mention RDNA support in docu
The amdgpu kernel module has supported RDNA for a while,
mention that in the module description.
v2: Add CDNA as well (Alex)
Signed-off-by: Peter Maucher <bellosilicio@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Peter Maucher [Thu, 1 Dec 2022 15:38:20 +0000 (16:38 +0100)]
drm/amdgpu: improve GART and GTT documentation
Document difference between amdgpu.gartsize and amdgpu.gttsize
module parameters, as initially explained by Alex Deucher here:
https://lists.freedesktop.org/archives/dri-devel/2022-October/375358.html
v2: minor cleanups (Alex)
Signed-off-by: Peter Maucher <bellosilicio@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
ye xingchen [Thu, 1 Dec 2022 02:24:21 +0000 (10:24 +0800)]
drm/amdgpu: use sysfs_emit() to instead of scnprintf()
Replace the open-code with sysfs_emit() to simplify the code.
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 28 Nov 2022 15:38:53 +0000 (10:38 -0500)]
drm/amd/display: use the proper fb offset for DM
This fixes DMCU initialization in APU GPU passthrough. The
DMCU needs the GPU physical address, not the CPU physical
address. This ends up working out on bare metal because
we always use the physical address, but doesn't work in
passthrough because the addresses are different.
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
YuBiao Wang [Wed, 30 Nov 2022 09:14:56 +0000 (17:14 +0800)]
drm/amdgpu: Add nv mailbox irq in soc21
Under virtualization guest needs to receive notification from host to
perform reset in some cases. Add nv mailbox irq in soc21.
Signed-off-by: YuBiao Wang <YuBiao.Wang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo Liu [Tue, 29 Nov 2022 23:53:18 +0000 (18:53 -0500)]
drm/amdgpu: enable Vangogh VCN indirect sram mode
So that uses PSP to initialize HW.
Fixes:
0c2c02b66c672e ("drm/amdgpu/vcn: add firmware support for dimgrey_cavefish")
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Tue, 29 Nov 2022 03:52:19 +0000 (11:52 +0800)]
drm/amdgpu: enable VCN RAS poison for VCN v4.0
Configure related registers.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Tue, 29 Nov 2022 03:12:32 +0000 (11:12 +0800)]
drm/amdgpu/mes11: enable reg active poll
Enable reg active poll in mes11.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Tested-and-acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Xiao [Tue, 29 Nov 2022 03:12:08 +0000 (11:12 +0800)]
drm/amd/amdgpu: update mes11 api def
Update the api def of mes11.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Tested-and-acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Konstantin Meskhidze [Tue, 29 Nov 2022 07:10:32 +0000 (15:10 +0800)]
drm/amdgpu: Fix logic error
This commit fixes logic error in function 'amdgpu_hw_ip_info':
- value 'uvd' might be 'vcn'.
Signed-off-by: Konstantin Meskhidze <konstantin.meskhidze@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Konstantin Meskhidze [Tue, 29 Nov 2022 04:02:54 +0000 (23:02 -0500)]
drm/amdkfd: Fix memory leakage
This patch fixes potential memory leakage and seg fault
in _gpuvm_import_dmabuf() function
Fixes:
d4ec4bdc0bd5 ("drm/amdkfd: Allow access for mmapping KFD BOs")
Signed-off-by: Konstantin Meskhidze <konstantin.meskhidze@huawei.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Randy Dunlap [Fri, 25 Nov 2022 21:00:55 +0000 (13:00 -0800)]
drm/amdgpu: update docum. filename following rename
Fix documentation build errors for amdgpu: correct the filename.
Error: Cannot open file ../drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
Error: Cannot open file ../drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
Error: Cannot open file ../drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
WARNING: kernel-doc '../scripts/kernel-doc -rst -enable-lineno -sphinx-version 5.3.0 -function MMU Notifier ../drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c' failed with return code 1
WARNING: kernel-doc '../scripts/kernel-doc -rst -enable-lineno -sphinx-version 5.3.0 -internal ../drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c' failed with return code 2
Fixes:
d9483ecd327b ("drm/amdgpu: rename the files for HMM handling")
Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Cc: Christian König <christian.koenig@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Felix Kuehling <Felix.Kuehling@amd.com>
Cc: David Airlie <airlied@gmail.com>
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: amd-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiongfeng Wang [Tue, 22 Nov 2022 11:30:43 +0000 (19:30 +0800)]
drm/amdgpu: Fix PCI device refcount leak in amdgpu_atrm_get_bios()
As comment of pci_get_class() says, it returns a pci_device with its
refcount increased and decreased the refcount for the input parameter
@from if it is not NULL.
If we break the loop in amdgpu_atrm_get_bios() with 'pdev' not NULL, we
need to call pci_dev_put() to decrease the refcount. Add the missing
pci_dev_put() to avoid refcount leak.
Fixes:
d38ceaf99ed0 ("drm/amdgpu: add core driver (v4)")
Signed-off-by: Xiongfeng Wang <wangxiongfeng2@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Guchun Chen [Thu, 24 Nov 2022 05:23:09 +0000 (13:23 +0800)]
drm/amdgpu: use dev_dbg to print messages in runtime cycle
Runtime PM can happen pretty frequently, as these printings
may be annoyed, switch to dev_dbg.
Suggested-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alvin Lee [Sat, 19 Nov 2022 16:42:41 +0000 (11:42 -0500)]
drm/amd/display: Fix DTBCLK disable requests and SRC_SEL programming
[Description]
- When transitioning FRL / DP2 is not required, we will always request
DTBCLK = 0Mhz, but PMFW returns the min freq
- This causes us to make DTBCLK requests every time we call optimize
after transitioning from FRL to non-FRL
- If DTBCLK is not required, request the min instead (then we only need
to make 1 extra request at boot time)
- Also when programming PIPE_DTO_SRC_SEL, don't programming for DP
first, just programming once for the required selection (programming
DP on an HDMI connection then switching back causes corruption)
Reviewed-by: Dillon Varone <Dillon.Varone@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Stylon Wang [Tue, 15 Nov 2022 12:10:05 +0000 (20:10 +0800)]
drm/amd/display: Create debugfs to tell if connector is DPIA link
[Why]
Tests need to tell if display is connected via USB4 DPIA link.
Currently this is only possible via analyzing dmesg logs.
[How]
Create a per-connector debugfs entry to report if the link is
tunneled via USB4 DPIA.
Reviewed-by: Wayne Lin <Wayne.Lin@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dillon Varone [Fri, 18 Nov 2022 01:04:46 +0000 (20:04 -0500)]
drm/amd/display: program output tf when required
[Description]
Output transfer function must be programmed per pipe as part of a front end
update when the plane changes, or output transfer function changes for a
given plane.
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dillon Varone [Thu, 17 Nov 2022 00:32:16 +0000 (19:32 -0500)]
drm/amd/display: Use DCC meta pitch for MALL allocation requirements
[Description]
Calculations for determining DCC meta size should be pitch*height*bpp/256.
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dillon Varone [Thu, 17 Nov 2022 18:57:31 +0000 (13:57 -0500)]
drm/amd/display: Fix arithmetic error in MALL size calculations for subvp
[Description]
Need to subtract unused section of the viewport when calculating required space
in MALL for subvp instead of adding, to prevent over allocation.
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alvin Lee [Thu, 17 Nov 2022 16:55:52 +0000 (11:55 -0500)]
drm/amd/display: Retain phantom pipes when min transition into subvp (#7358)
[Description]
- When entering into a SubVP config that requires a minimal
transition we need to retain phantom pipes and also restore
the mall config
- This is because the min transition will remove phantom pipes
from the context (shallow copy) and not restore it's original
state
- This is just a workaround, and needs a proper fix
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alvin Lee [Fri, 18 Nov 2022 18:49:11 +0000 (13:49 -0500)]
drm/amd/display: Don't overwrite subvp pipe info in fast updates
[Description]
- This is a workaround to avoid concurrency issues -- a fast update
creates a shallow copy of the dc current_state, and removes all
subvp/phantom related flags.
- We want to prevent the fast update thread from removing those
flags in case there's another thread running that requires
the info for proper programming
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dmytro Laktyushkin [Tue, 22 Nov 2022 15:06:19 +0000 (10:06 -0500)]
drm/amd/display: set per pipe dppclk to 0 when dpp is off
The 'commit
52e4fdf09ebc ("drm/amd/display: use low clocks for no plane
configs")' introduced a change that set low clock values for DCN31 and
DCN32. As a result of these changes, DC started to spam the log with the
following warning:
------------[ cut here ]------------
WARNING: CPU: 8 PID: 1486 at
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dccg.c:58
dccg2_update_dpp_dto+0x3f/0xf0 [amdgpu]
[..]
CPU: 8 PID: 1486 Comm: kms_atomic Tainted: G W 5.18.0+ #1
RIP: 0010:dccg2_update_dpp_dto+0x3f/0xf0 [amdgpu]
RSP: 0018:
ffffbbd8025334d0 EFLAGS:
00010206
RAX:
00000000000001ee RBX:
ffffa02c87dd3de0 RCX:
00000000000a7f80
RDX:
000000000007dec3 RSI:
0000000000000000 RDI:
ffffa02c87dd3de0
RBP:
ffffbbd8025334e8 R08:
0000000000000001 R09:
0000000000000005
R10:
00000000000331a0 R11:
ffffffffc0b03d80 R12:
ffffa02ca576d000
R13:
ffffa02cd02c0000 R14:
00000000001453bc R15:
ffffa02cdc280000
[..]
dcn20_update_clocks_update_dpp_dto+0x4e/0xa0 [amdgpu]
dcn32_update_clocks+0x5d9/0x650 [amdgpu]
dcn20_prepare_bandwidth+0x49/0x100 [amdgpu]
dcn30_prepare_bandwidth+0x63/0x80 [amdgpu]
dc_commit_state_no_check+0x39d/0x13e0 [amdgpu]
dc_commit_streams+0x1f9/0x3b0 [amdgpu]
dc_commit_state+0x37/0x120 [amdgpu]
amdgpu_dm_atomic_commit_tail+0x5e5/0x2520 [amdgpu]
? _raw_spin_unlock_irqrestore+0x1f/0x40
? down_trylock+0x2c/0x40
? vprintk_emit+0x186/0x2c0
? vprintk_default+0x1d/0x20
? vprintk+0x4e/0x60
We can easily trigger this issue by using a 4k@120 or a 2k@165 and
running some of the kms_atomic tests. This warning is triggered because
the per-pipe clock update is not happening; this commit fixes this issue
by ensuring that DPPCLK is updated when calculating the watermark and
dlg is invoked.
Fixes:
2641c7b78081 ("drm/amd/display: use low clocks for no plane configs")
Reported-by: Mark Broadworth <mark.broadworth@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Stylon Wang [Thu, 10 Nov 2022 13:53:01 +0000 (21:53 +0800)]
drm/amd/display: Fix race condition in DPIA AUX transfer
[Why]
This fix was intended for improving on coding style but in the process
uncovers a race condition, which explains why we are getting incorrect
length in DPIA AUX replies. Due to the call path of DPIA AUX going from
DC back to DM layer then again into DC and the added complexities on top
of current DC AUX implementation, a proper fix to rely on current dc_lock
to address the race condition is difficult without a major overhual
on how DPIA AUX is implemented.
[How]
- Add a mutex dpia_aux_lock to protect DPIA AUX transfers
- Remove DMUB_ASYNC_TO_SYNC_ACCESS_* codes and rely solely on
aux_return_code_type for error reporting and handling
- Separate SET_CONFIG from DPIA AUX transfer because they have quiet
different processing logic
- Remove unnecessary type casting to and from void * type
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dillon Varone [Wed, 16 Nov 2022 15:03:23 +0000 (10:03 -0500)]
drm/amd/display: MALL SS calculations should iterate over all pipes for cursor
[Description]
MALL SS allocation calculations should iterate over all pipes to determine the
the allocation size required for HW cursor.
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aric Cyr [Mon, 21 Nov 2022 05:12:38 +0000 (00:12 -0500)]
drm/amd/display: 3.2.214
This version brings along following fixes:
-Program output transfer function when required
-Fix arthmetic errror in MALL size caluclations for subvp
-DCC Meta pitch used for MALL allocation
-Debugfs entry to tell if connector is DPIA link
-Use largest vready_offset in pipe group
-Fixes race condition in DPIA Aux transfer
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Aric Cyr <Aric.Cyr@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wesley Chalmers [Wed, 9 Nov 2022 22:43:13 +0000 (17:43 -0500)]
drm/amd/display: Use the largest vready_offset in pipe group
[WHY]
Corruption can occur in LB if vready_offset is not large enough.
DML calculates vready_offset for each pipe, but we currently select the
top pipe's vready_offset, which is not necessarily enough for all pipes
in the group.
[HOW]
Wherever program_global_sync is currently called, iterate through the
entire pipe group and find the highest vready_offset.
Reviewed-by: Dillon Varone <Dillon.Varone@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiongfeng Wang [Tue, 22 Nov 2022 11:30:42 +0000 (19:30 +0800)]
drm/radeon: Fix PCI device refcount leak in radeon_atrm_get_bios()
As comment of pci_get_class() says, it returns a pci_device with its
refcount increased and decreased the refcount for the input parameter
@from if it is not NULL.
If we break the loop in radeon_atrm_get_bios() with 'pdev' not NULL, we
need to call pci_dev_put() to decrease the refcount. Add the missing
pci_dev_put() to avoid refcount leak.
Fixes:
d8ade3526b2a ("drm/radeon: handle non-VGA class pci devices with ATRM")
Fixes:
c61e2775873f ("drm/radeon: split ATRM support out from the ATPX handler (v3)")
Signed-off-by: Xiongfeng Wang <wangxiongfeng2@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dan Carpenter [Fri, 25 Nov 2022 07:39:49 +0000 (10:39 +0300)]
drm/amdkfd: Remove unnecessary condition in kfd_topology_add_device()
We re-arranged this code recently so "ret" is always zero at this point.
Signed-off-by: Dan Carpenter <error27@gmail.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yu Songping [Thu, 24 Nov 2022 01:52:37 +0000 (09:52 +0800)]
swsmu/amdgpu_smu: Fix the wrong if-condition
The logical operator '&&' will make
smu->ppt_funcs->set_gfx_power_up_by_imu segment fault when
smu->ppt_funcs is NULL.
Signed-off-by: Yu Songping <yusongping@huawei.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yushan Zhou [Wed, 23 Nov 2022 07:44:37 +0000 (15:44 +0800)]
drm/amdgpu: remove redundant NULL check
release_firmware() checks whether firmware pointer is NULL.
Remove the redundant NULL check in psp_sw_fini().
Signed-off-by: Yushan Zhou <katrinzhou@tencent.com>
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Veerabadhran Gopalakrishnan [Wed, 23 Nov 2022 14:40:32 +0000 (20:10 +0530)]
amdgpu/nv.c: Corrected typo in the video capabilities resolution
Corrected the typo in the 4K resolution parameters.
Fixes:
b3a24461f9fb15 ("amdgpu/nv.c - Added codec query for Beige Goby")
Fixes:
9075096b09e590 ("amdgpu/nv.c - Optimize code for video codec support structure")
Fixes:
9ac0edaa0f8323 ("drm/amdgpu: add vcn_4_0_0 video codec query")
Signed-off-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com>
Acked-by: Luben Tuikov <luben.tuikov@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Liang He [Tue, 22 Nov 2022 04:28:49 +0000 (12:28 +0800)]
drm/amdgpu: Fix potential double free and null pointer dereference
In amdgpu_get_xgmi_hive(), we should not call kfree() after
kobject_put() as the PUT will call kfree().
In amdgpu_device_ip_init(), we need to check the returned *hive*
which can be NULL before we dereference it.
Signed-off-by: Liang He <windhl@126.com>
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tim Huang [Mon, 21 Nov 2022 02:24:14 +0000 (10:24 +0800)]
drm/amdgpu: enable PSP IP v13.0.11 support
Enable PSP FW loading for PSP IP v13.0.11
Signed-off-by: Tim Huang <tim.huang@amd.com>
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Saleemkhan Jamadar [Tue, 8 Nov 2022 05:54:48 +0000 (11:24 +0530)]
drm/amdgpu: Enable pg/cg flags on GC11_0_4 for VCN
This enable VCN PG, CG and JPEG PG, CG
Signed-off-by: Saleemkhan Jamadar <saleemkhan.jamadar@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yifan Zhang [Tue, 25 Oct 2022 08:59:44 +0000 (16:59 +0800)]
drm/amdgpu/discovery: enable nbio support for NBIO v7.7.1
this patch is to enable nbio support for NBIO v7.7.1.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tim Huang [Mon, 24 Oct 2022 03:05:59 +0000 (11:05 +0800)]
drm/amdgpu/pm: use the specific mailbox registers only for SMU IP v13.0.4
The SMU IP v13.0.4 ppt interface is shared by IP v13.0.11, they use
the different mailbox register offset. So use the specific mailbox
registers offset for v13.0.4.
Signed-off-by: Tim Huang <tim.huang@amd.com>
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tim Huang [Mon, 24 Oct 2022 02:32:05 +0000 (10:32 +0800)]
drm/amdgpu/soc21: add mode2 asic reset for SMU IP v13.0.11
Set the default reset method to mode2 for SMU IP v13.0.11
Signed-off-by: Tim Huang <tim.huang@amd.com>
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yifan Zhang [Wed, 12 Oct 2022 05:17:40 +0000 (13:17 +0800)]
drm/amdgpu/pm: add GFXOFF control IP version check for SMU IP v13.0.11
Enable the SMU IP v13.0.11 GFXOFF control
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yifan Zhang [Wed, 12 Oct 2022 05:16:25 +0000 (13:16 +0800)]
drm/amdgpu: add smu 13 support for smu 13.0.11
this patch to add smu 13 support for smu 13.0.11.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yifan Zhang [Wed, 12 Oct 2022 05:08:30 +0000 (13:08 +0800)]
drm/amdgpu/pm: enable swsmu for SMU IP v13.0.11
Add the entry to set the ppt functions for SMU IP v13.0.11.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yifan Zhang [Wed, 12 Oct 2022 05:01:22 +0000 (13:01 +0800)]
drm/amdkfd: add GC 11.0.4 KFD support
Add initial support for GC 11.0.4 in KFD compute driver.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yifan Zhang [Wed, 12 Oct 2022 04:56:01 +0000 (12:56 +0800)]
drm/amdgpu: add gmc v11 support for GC 11.0.4
Add gmc v11 support for GC 11.0.4.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yifan Zhang [Wed, 12 Oct 2022 04:54:52 +0000 (12:54 +0800)]
drm/amdgpu: add soc21 common ip block support for GC 11.0.4
Add common soc21 ip block support for GC 11.0.4.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yifan Zhang [Wed, 12 Oct 2022 04:49:06 +0000 (12:49 +0800)]
drm/amdgpu: add gfx support for GC 11.0.4
this patch to add GC 11.0.4 gfx support to gfx11 implementation.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yifan Zhang [Wed, 12 Oct 2022 03:16:29 +0000 (11:16 +0800)]
drm/amdgpu/discovery: set the APU flag for GC 11.0.4
Set the APU flag appropriately for GC 11.0.4.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yifan Zhang [Wed, 12 Oct 2022 03:15:24 +0000 (11:15 +0800)]
drm/amdgpu: set GC 11.0.4 family
this patch is to set GC 11.0.4 family.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tim Huang [Mon, 21 Nov 2022 08:19:44 +0000 (16:19 +0800)]
drm/amdgpu/discovery: add PSP IP v13.0.11 support
Add PSP IP v13.0.11 ip discovery support.
Signed-off-by: Tim Huang <tim.huang@amd.com>
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yifan Zhang [Wed, 12 Oct 2022 03:11:57 +0000 (11:11 +0800)]
drm/amdgpu/discovery: enable mes support for GC v11.0.4
this patch is to enable mes for GC 11.0.4.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yifan Zhang [Wed, 12 Oct 2022 03:11:09 +0000 (11:11 +0800)]
drm/amdgpu/discovery: enable gfx v11 for GC 11.0.4
Enable gfx v11 for GC 11.0.4.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yifan Zhang [Wed, 12 Oct 2022 03:09:50 +0000 (11:09 +0800)]
drm/amdgpu/discovery: enable gmc v11 for GC 11.0.4
Enable gmc (graphic memory controller) v11 for GC 11.0.4.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yifan Zhang [Wed, 12 Oct 2022 03:08:49 +0000 (11:08 +0800)]
drm/amdgpu/discovery: enable soc21 common for GC 11.0.4
Enable soc21 common for GC 11.0.4.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Wed, 23 Nov 2022 09:49:28 +0000 (17:49 +0800)]
drm/amdgpu: skip vram reserve on firmware_v2_2 for bare-metal
vram_usagebyfirmware v2_2 is only used in SRIOV case, skip the related
settings in bare-metal case currently.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Guchun Chen [Wed, 23 Nov 2022 01:39:40 +0000 (09:39 +0800)]
drm/amdgpu: add printing to indicate rpm completeness
Add an explicit printing to tell when finishing rpm execution
in amdgpu.
Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Guchun Chen [Tue, 22 Nov 2022 09:47:04 +0000 (17:47 +0800)]
drm/amd/pm/smu11: poll BACO status after RPM BACO exits
After executing BACO exit, driver needs to poll the status
to ensure FW has completed BACO exit sequence to prevent
timing issue.
v2: use usleep_range to replace msleep to fix checkpatch.pl warnings
Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Guchun Chen [Tue, 22 Nov 2022 09:33:24 +0000 (17:33 +0800)]
drm/amd/pm/smu11: BACO is supported when it's in BACO state
Return true early if ASIC is in BACO state already, no need
to talk to SMU. It can fix the issue that driver was not
calling BACO exit at all in runtime pm resume, and a timing
issue leading to a PCI AER error happened eventually.
Fixes:
8795e182b02d ("PCI/portdrv: Don't disable AER reporting in get_port_device_capability()")
Suggested-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tong Liu01 [Thu, 17 Nov 2022 10:18:58 +0000 (18:18 +0800)]
drm/amdgpu: add drv_vram_usage_va for virt data exchange
For vram_usagebyfirmware_v2_2, fw_vram_reserve is not used. So
fw_vram_usage_va is NULL, and cannot do virt data exchange
anymore. Should add drv_vram_usage_va to do virt data exchange
in vram_usagebyfirmware_v2_2 case. And refine some code style
checks in pre add vram reservation logic patch
Signed-off-by: Tong Liu01 <Tong.Liu01@amd.com>
Acked-by: Luben Tuikov <luben.tuikov@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
James Zhu [Thu, 17 Nov 2022 20:57:52 +0000 (15:57 -0500)]
drm/amdgpu: fix stall on CPU when allocate large system memory
-v2: 1. rename variable to redue confuse
2. optimize the code
-v3: move new define out of the middle of the code
-v4: squash in minmax error fix (Luben)
When applications try to allocate large system (more than > 128GB),
"stall cpu" is reported.
for such large system memory, walk_page_range takes more than 20s usually.
The warning message can be removed when splitting hmm range into smaller
ones which is not more 64GB for each walk_page_range.
[ 164.437617] amdgpu:amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu:1753: amdgpu: create BO VA 0x7f63c7a00000 size 0x2f16000000 domain CPU
[ 164.488847] amdgpu:amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu:1785: amdgpu: creating userptr BO for user_addr =
7f63c7a00000
[ 185.439116] rcu: INFO: rcu_sched self-detected stall on CPU
[ 185.439125] rcu: 8-....: (20999 ticks this GP) idle=e22/1/0x4000000000000000 softirq=2242/2242 fqs=5249
[ 185.439137] (t=21000 jiffies g=6325 q=1215)
[ 185.439141] NMI backtrace for cpu 8
[ 185.439143] CPU: 8 PID: 3470 Comm: kfdtest Kdump: loaded Tainted: G O 5.12.0-0_fbk5_zion_rc1_5697_g2c723fb88626 #1
[ 185.439147] Hardware name: HPE ProLiant XL675d Gen10 Plus/ProLiant XL675d Gen10 Plus, BIOS A47 11/06/2020
[ 185.439150] Call Trace:
[ 185.439153] <IRQ>
[ 185.439157] dump_stack+0x64/0x7c
[ 185.439163] nmi_cpu_backtrace.cold.7+0x30/0x65
[ 185.439165] ? lapic_can_unplug_cpu+0x70/0x70
[ 185.439170] nmi_trigger_cpumask_backtrace+0xf9/0x100
[ 185.439174] rcu_dump_cpu_stacks+0xc5/0xf5
[ 185.439178] rcu_sched_clock_irq.cold.97+0x112/0x38c
[ 185.439182] ? tick_sched_handle.isra.21+0x50/0x50
[ 185.439185] update_process_times+0x8c/0xc0
[ 185.439189] tick_sched_timer+0x63/0x70
[ 185.439192] __hrtimer_run_queues+0xff/0x250
[ 185.439195] hrtimer_interrupt+0xf4/0x200
[ 185.439199] __sysvec_apic_timer_interrupt+0x51/0xd0
[ 185.439201] sysvec_apic_timer_interrupt+0x69/0x90
[ 185.439206] </IRQ>
[ 185.439207] asm_sysvec_apic_timer_interrupt+0x12/0x20
[ 185.439211] RIP: 0010:clear_page_rep+0x7/0x10
[ 185.439214] Code: e8 fe 7c 51 00 44 89 e2 48 89 ee 48 89 df e8 60 ff ff ff c6 03 00 5b 5d 41 5c c3 cc cc cc cc cc cc cc cc b9 00 02 00 00 31 c0 <f3> 48 ab c3 0f 1f 44 00 00 31 c0 b9 40 00 00 00 66 0f 1f 84 00 00
[ 185.439218] RSP: 0018:
ffffc9000f58f818 EFLAGS:
00000246
[ 185.439220] RAX:
0000000000000000 RBX:
0000000000000881 RCX:
000000000000005c
[ 185.439223] RDX:
0000000000100dca RSI:
0000000000000000 RDI:
ffff88a59e0e5d20
[ 185.439225] RBP:
ffffea0096783940 R08:
ffff888118c35280 R09:
ffffea0096783940
[ 185.439227] R10:
ffff888000000000 R11:
0000160000000000 R12:
ffffea0096783980
[ 185.439228] R13:
ffffea0096783940 R14:
ffff88b07fdfdd00 R15:
0000000000000000
[ 185.439232] prep_new_page+0x81/0xc0
[ 185.439236] get_page_from_freelist+0x13be/0x16f0
[ 185.439240] ? release_pages+0x16a/0x4a0
[ 185.439244] __alloc_pages_nodemask+0x1ae/0x340
[ 185.439247] alloc_pages_vma+0x74/0x1e0
[ 185.439251] __handle_mm_fault+0xafe/0x1360
[ 185.439255] handle_mm_fault+0xc3/0x280
[ 185.439257] hmm_vma_fault.isra.22+0x49/0x90
[ 185.439261] __walk_page_range+0x692/0x9b0
[ 185.439265] walk_page_range+0x9b/0x120
[ 185.439269] hmm_range_fault+0x4f/0x90
[ 185.439274] amdgpu_hmm_range_get_pages+0x24f/0x260 [amdgpu]
[ 185.439463] amdgpu_ttm_tt_get_user_pages+0xc2/0x190 [amdgpu]
[ 185.439603] amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu+0x49f/0x7a0 [amdgpu]
[ 185.439774] kfd_ioctl_alloc_memory_of_gpu+0xfb/0x410 [amdgpu]
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 21 Nov 2022 17:34:14 +0000 (12:34 -0500)]
drm/amdgpu: Partially revert "drm/amdgpu: update drm_display_info correctly when the edid is read"
This partially reverts
20543be93ca45968f344261c1a997177e51bd7e1.
Calling drm_connector_update_edid_property() in
amdgpu_connector_free_edid() causes a noticeable pause in
the system every 10 seconds on polled outputs so revert this
part of the change.
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2257
Cc: Claudio Suarez <cssk@net-c.es>
Acked-by: Luben Tuikov <luben.tuikov@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 21 Nov 2022 17:17:33 +0000 (12:17 -0500)]
drm/amdgpu: add missing license to some files
The driver is MIT, so add the licenses.
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2265
Acked-by: Luben Tuikov <luben.tuikov@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Thu, 27 Oct 2022 09:12:05 +0000 (17:12 +0800)]
drm/amdgpu: enable RAS poison for VCN 2.6
Configure related settings to enable it.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Felix Kuehling [Wed, 16 Nov 2022 20:38:44 +0000 (15:38 -0500)]
drm/amdkfd: Release the topology_lock in error case
Move the topology-locked part of kfd_topology_add_device into a separate
function to simlpify error handling and release the topology lock
consistently.
Reported-by: Dan Carpenter <error27@gmail.com>
Signed-off-by: Felix Kuehling <felix.kuehling@gmail.com>
Signed-off-by: Ma Jun <Jun.Ma2@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Thu, 27 Oct 2022 09:50:56 +0000 (17:50 +0800)]
drm/amdgpu: add register definition for VCN RAS initialization
Prepare for enableing VCN RAS poison.
v2: move SHIFT and MASK definitions to related sh_mask.h file.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Shikang Fan [Fri, 18 Nov 2022 09:35:33 +0000 (17:35 +0800)]
drm/amdgpu: fix for suspend/resume kiq fence fallback under sriov
- in device_resume, sriov configure interrupt should be in full access,
so release_full_gpu should be done after kfd_resume.
- remove the previous workaround solution for sriov.
Fixes:
ec4927d463cb ("drm/amdgpu: fix for suspend/resume sequence under sriov")
Signed-off-by: Shikang Fan <shikang.fan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aurabindo Pillai [Mon, 21 Nov 2022 20:48:23 +0000 (15:48 -0500)]
drm/amd/display: trigger timing sync only if TG is running
[Why&How]
If the timing generator isnt running, it does not make sense to trigger
a sync on the corresponding OTG. Check this condition before starting.
Otherwise, this will cause error like:
*ERROR* GSL: Timeout on reset trigger!
Fixes:
dc55b106ad47 ("drm/amd/display: Disable phantom OTG after enable for plane disable")
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Paulo Miguel Almeida [Mon, 21 Nov 2022 07:25:58 +0000 (20:25 +1300)]
drm/amdgpu: Replace remaining 1-element array with flex-array
One-element arrays are deprecated, and we are replacing them with
flexible array members instead. So, replace one-element array with
flexible-array member in struct GOP_VBIOS_CONTENT and refactor the
rest of the code accordingly.
Important to mention is that doing a build before/after this patch
results in no functional binary output differences.
This helps with the ongoing efforts to tighten the FORTIFY_SOURCE
routines on memcpy() and help us make progress towards globally
enabling -fstrict-flex-arrays=3 [1].
Link: https://github.com/KSPP/linux/issues/79
Link: https://github.com/KSPP/linux/issues/238
Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101836
Signed-off-by: Paulo Miguel Almeida <paulo.miguel.almeida.rodenas@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 17 Nov 2022 14:37:16 +0000 (09:37 -0500)]
Revert "drm/amd/display: fix dpms_off issue when disabling bios mode"
This reverts commit
5aa663752ff6f844c6bfc97d89231e98884ae769.
This causes a blank screen on boot on an Asus G513QY / 6800M laptop.
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2259
Cc: Aric Cyr <Aric.Cyr@amd.com>
Cc: Tom Chung <chiahsuan.chung@amd.com>
Cc: Zhongwei Zhang <Zhongwei.Zhang@amd.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Tested-by: Mike Lothian <mike@fireburn.co.uk>
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Ren Zhijie [Mon, 21 Nov 2022 13:04:18 +0000 (13:04 +0000)]
drm/amdgpu: fix unused-function error
If CONFIG_DRM_AMDGPU=y and CONFIG_DRM_AMD_DC is not set,
gcc complained about unused-function :
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c:1705:13: error: ‘amdgpu_discovery_set_sriov_display’ defined but not used [-Werror=unused-function]
static void amdgpu_discovery_set_sriov_display(struct amdgpu_device *adev)
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
To fix this error, use CONFIG_DRM_AMD_DC to wrap
the definition of amdgpu_discovery_set_sriov_display().
Fixes:
25263da37693 ("drm/amdgpu: rework SR-IOV virtual display handling")
Signed-off-by: Ren Zhijie <renzhijie2@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Luben Tuikov [Mon, 21 Nov 2022 17:18:36 +0000 (12:18 -0500)]
drm/amdgpu: Fix minmax warning
Fix minmax warning by using min_t() macro and explicitly specifying
the assignment type.
Cc: Alex Deucher <Alexander.Deucher@amd.com>
Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
Reviewed-by: Alex Deucher <Alexander.Deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Stanley.Yang [Wed, 16 Nov 2022 09:08:22 +0000 (17:08 +0800)]
drm/amdgpu: fix use-after-free during gpu recovery
[Why]
[ 754.862560] refcount_t: underflow; use-after-free.
[ 754.862898] Call Trace:
[ 754.862903] <TASK>
[ 754.862913] amdgpu_job_free_cb+0xc2/0xe1 [amdgpu]
[ 754.863543] drm_sched_main.cold+0x34/0x39 [amd_sched]
[How]
The fw_fence may be not init, check whether dma_fence_init
is performed before job free
Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
ZhenGuo Yin [Fri, 18 Nov 2022 08:24:07 +0000 (16:24 +0800)]
drm/amdgpu: update documentation of parameter amdgpu_gtt_size
Fixes:
f7ba887f606b ("drm/amdgpu: Adjust logic around GTT size (v3)")
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: ZhenGuo Yin <zhenguo.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jane Jian [Wed, 16 Nov 2022 10:22:52 +0000 (18:22 +0800)]
drm/amdgpu/vcn: re-use original vcn0 doorbell value
root cause that S2A need to use deduct offset flag.
after setting this flag, vcn0 doorbell value works.
so return it as before
Signed-off-by: Jane Jian <Jane.Jian@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
lyndonli [Mon, 21 Nov 2022 01:10:20 +0000 (09:10 +0800)]
drm/amdgpu: add the fan abnormal detection feature
Update the SW CTF limit from existing register
when there's a fan failure detected via SMU interrupt.
Signed-off-by: lyndonli <Lyndon.Li@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
lyndonli [Mon, 21 Nov 2022 01:08:42 +0000 (09:08 +0800)]
drm/amd/pm: update driver if header for smu_13_0_7
update driver if header for smu_13_0_7
Signed-off-by: lyndonli <Lyndon.Li@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Candice Li [Thu, 17 Nov 2022 12:34:15 +0000 (20:34 +0800)]
drm/amd/pm: Enable bad memory page/channel recording support for smu v13_0_0
Send message to SMU to update bad memory page and bad channel info.
Signed-off-by: Candice Li <candice.li@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aric Cyr [Mon, 14 Nov 2022 02:35:51 +0000 (21:35 -0500)]
drm/amd/display: 3.2.213
This version brings along following fixes:
-Add configuration 2 for ABM 2.3/2.4.
-Add margin for HUBP for SubVp + DRR.
-Fix no display after resume from WB/CB.
-Limit HW cursor size to be less than 64 x 64 bytes when the stream is >= 4K.
-Lower watermarks for enter/enter+exit latency.
-Update support types for DCN314 to include z8 only and z8_z10 only state.
-Add new value for soc bounding box and dummy pstate.
-Override fclk chang latency when calculating prefetch schedule for subvp with low uclk.
-Add check for DET fetch latency for dcn32.
-Add check if PSR enabled when entering MALL.
-Use base MALL allocation size calculations off vewport height.
-Add YCBCR2020 to CSC matrix.
-Implement DP-Tx portion to interact with DPIA.
-Add debug option for increasing phantom lines.
-Fix phantom plane/stream retain after fail validation.
-Fix display corruption with VSR enable.
-Set valid divider value for virtual and FRL/DP2.
-Add new num clk levels struct for max mclk index.
-Fix check for phantom BPP.
-Fix rotated cursor offset calculation.
Signed-off-by: Aric Cyr <Aric.Cyr@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
David Galiffi [Thu, 10 Nov 2022 19:40:20 +0000 (14:40 -0500)]
drm/amd/display: Fix rotated cursor offset calculation
[Why]
Underflow is observed when cursor is still enabled when the cursor
rectangle is outside the bounds of it's surface viewport.
[How]
Update parameters used to determine when cursor should be disabled.
Reviewed-by: Martin Leung <Martin.Leung@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: David Galiffi <David.Galiffi@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alvin Lee [Fri, 11 Nov 2022 21:21:54 +0000 (16:21 -0500)]
drm/amd/display: Revert check for phantom BPP
[Description]
Revert change since enabling SubVP on 8K60 single cable
results in corruption
Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
Reviewed-by: Martin Leung <Martin.Leung@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dillon Varone [Fri, 11 Nov 2022 19:06:58 +0000 (14:06 -0500)]
drm/amd/display: Use new num clk levels struct for max mclk index
[WHY?]
When calculating watermark and dlg values, the max mclk level index and
associated speed are needed to find the correlated dummy latency value.
Currently the incorrect index is given due to a clock manager refactor.
[HOW?]
Use num_memclk_level from num_entries_per_clk struct for getting the correct max
mem speed.
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Taimur Hassan [Fri, 11 Nov 2022 19:11:00 +0000 (14:11 -0500)]
drm/amd/display: Avoid setting pixel rate divider to N/A
[Why]
Pixel rate divider values should never be set to N/A (0xF) as the K1/K2
field is only 1/2 bits wide.
[How]
Set valid divider values for virtual and FRL/DP2 cases.
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Ilya Bakoulin [Fri, 11 Nov 2022 17:03:54 +0000 (12:03 -0500)]
drm/amd/display: Fix display corruption w/ VSR enable
[Why]
Brief corruption is observed on hotplug/unplug with certain display
configurations when VSR is enabled.
[How]
Work around the issue by avoiding 2to1 ODM when stream plane_count is 0.
Reviewed-by: Dillon Varone <Dillon.Varone@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alvin Lee [Fri, 11 Nov 2022 17:14:37 +0000 (12:14 -0500)]
drm/amd/display: Retain phantom plane/stream if validation fails
[Description]
- If we fail validation, we should retain the phantom
stream/planes
- Full updates assume that phantom pipes will be fully
removed, but if validation fails we keep the phantom
pipes
- Therefore we have to retain the plane/stream if validation
fails (since the refcount is decremented before validation,
and the expectation is that it's fully freed when the old
dc_state is released)
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alvin Lee [Fri, 11 Nov 2022 17:14:34 +0000 (12:14 -0500)]
drm/amd/display: Add debug options for increasing phantom lines
[Description]
- Add debug option for increasing number of phantom lines
Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mustapha Ghaddar [Wed, 2 Nov 2022 14:14:16 +0000 (10:14 -0400)]
drm/amd/display: Phase 1 Add Bw Allocation source and header files
[WHY]
To implement BW Allocation as per USB4 spec chapter 10.7
[HOW]
Implement the DP-Tx portion of the logic to interact with DPIA
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Mustapha Ghaddar <mghaddar@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rodrigo Siqueira [Thu, 3 Nov 2022 13:38:14 +0000 (09:38 -0400)]
drm/amd/display: Add YCBCR2020 coefficients to CSC matrix
When some of the IGT tests are executed in DCN31, it is possible to see
multiple occurrences of this warning:
WARNING: CPU: 9 PID: 3482 at
drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dcn30/dcn30_dpp.c:154
dpp3_program_post_csc+0x196/0x220 [amdgpu]
[..]
PU: 9 PID: 3482 Comm: amd_hdr Tainted: G W 5.18.0+ #3
IP: 0010:dpp3_program_post_csc+0x196/0x220 [amdgpu]
[..]
all Trace:
<TASK>
dpp3_cnv_setup+0x5d9/0x5f0 [amdgpu]
? dcn20_blank_pixel_data+0x30a/0x330 [amdgpu]
dcn20_program_pipe+0x259/0xb40 [amdgpu]
? offset_to_id+0x1b0/0x1c0 [amdgpu]
dcn20_program_front_end_for_ctx+0x36a/0x450 [amdgpu]
commit_planes_for_stream+0x8eb/0x13e0 [amdgpu]
This commit fix the above issue by adding YCBCR2020 coefficients to the
DPP Color Space Converter (CSC) matrix.
Reviewed-by: Nawwar Ali <nawwar.ali@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dillon Varone [Thu, 10 Nov 2022 17:13:47 +0000 (12:13 -0500)]
drm/amd/display: Use viewport height for subvp mall allocation size
[WHY?]
MALL allocation size depends on the viewport height, not the addressable
vertical lines, which will not match when scaling.
[HOW?]
Base MALL allocation size calculations off viewport height.
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Reviewed-by: Martin Leung <Martin.Leung@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alvin Lee [Tue, 8 Nov 2022 23:46:52 +0000 (18:46 -0500)]
drm/amd/display: Check if PSR enabled when entering MALL
[Description]
- When attempting to enter MALL SS when a PSR panel
is connected, we have to check that the PSR panel
has already entered PSR because the vsync interrupt
call is per display index (can be called for the
non-PSR panel first)
- Also don't override link settings when programming
phantom stream (main and phantom pipe share the same link)
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dillon Varone [Tue, 8 Nov 2022 23:45:33 +0000 (18:45 -0500)]
drm/amd/display: Add check for DET fetch latency hiding for dcn32
[WHY?]
Some configurations are constructed with very marginal DET buffers relative to
the worst possible time required to fetch a swath.
[HOW?]
Add a check to see that the DET buffer allocated for each pipe can hide the
latency for all pipes to fetch at least one swath.
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>