Zachary Turner [Mon, 29 Aug 2016 19:58:14 +0000 (19:58 +0000)]
Convert GetNameColonValue to return StringRefs.
StringExtractor::GetNameColonValue() looks for a substring of the
form "<name>:<value>" and returns <name> and <value> to the caller.
This results in two unnecessary string copies, since the name and
value are not translated in any way and simply returned as-is.
By converting this to return StringRefs we can get rid of hundreds
of string copies.
llvm-svn: 280000
Eric Fiselier [Mon, 29 Aug 2016 19:50:49 +0000 (19:50 +0000)]
Turn On -DLIBCXX_ENABLE_BENCHMARKS by default.
This patch enables the `cxx-benchmarks` target by default. Note that the target
still has to be manually invoked since it isn't included in the default 'make'
rule.
This patch also gets the benchmarks building w/ GCC. The build previously
required the '-stdlib=libc++' flag but upstream patches to Google Benchmark
now allow the library to build w/ libc++ and GCC.
These changes should make the benchmarks easier to build and test.
llvm-svn: 279999
Krzysztof Parzyszek [Mon, 29 Aug 2016 19:50:15 +0000 (19:50 +0000)]
Propagate TBAA info in SelectionDAG::getIndexedLoad
Patch by Pranav Bhandarkar.
llvm-svn: 279998
Zachary Turner [Mon, 29 Aug 2016 19:45:59 +0000 (19:45 +0000)]
Copy StringExtractor to StdStringExtractor.
I have some improvements to make to StringExtractor that require
using LLVM. debugserver can't take a dependency on LLVM but uses
this file, so I'm forking it off into StdStringExtractor and
StringExtractor, so that StringExtractor can take advantage of
some performance improvements and readability improvements that
LLVM can provide.
llvm-svn: 279997
Douglas Katzman [Mon, 29 Aug 2016 19:42:57 +0000 (19:42 +0000)]
[Myriad]: add missing 'mcpu' values
Should have been done with r276646.
llvm-svn: 279996
Tom Stellard [Mon, 29 Aug 2016 19:42:52 +0000 (19:42 +0000)]
AMDGPU/SI: Implement a custom MachineSchedStrategy
Summary:
GCNSchedStrategy re-uses most of GenericScheduler, it's just uses
a different method to compute the excess and critical register
pressure limits.
It's not enabled by default, to enable it you need to pass -misched=gcn
to llc.
Shader DB stats:
32464 shaders in 17874 tests
Totals:
SGPRS: 1542846 -> 1643125 (6.50 %)
VGPRS: 1005595 -> 904653 (-10.04 %)
Spilled SGPRs: 29929 -> 27745 (-7.30 %)
Spilled VGPRs: 334 -> 352 (5.39 %)
Scratch VGPRs: 1612 -> 1624 (0.74 %) dwords per thread
Code Size:
36688188 ->
37034900 (0.95 %) bytes
LDS: 1913 -> 1913 (0.00 %) blocks
Max Waves: 254101 -> 265125 (4.34 %)
Wait states: 0 -> 0 (0.00 %)
Totals from affected shaders:
SGPRS: 1338220 -> 1438499 (7.49 %)
VGPRS: 886221 -> 785279 (-11.39 %)
Spilled SGPRs: 29869 -> 27685 (-7.31 %)
Spilled VGPRs: 334 -> 352 (5.39 %)
Scratch VGPRs: 1612 -> 1624 (0.74 %) dwords per thread
Code Size:
34315716 ->
34662428 (1.01 %) bytes
LDS: 1551 -> 1551 (0.00 %) blocks
Max Waves: 188127 -> 199151 (5.86 %)
Wait states: 0 -> 0 (0.00 %)
Reviewers: arsenm, mareko, nhaehnle, MatzeB, atrick
Subscribers: arsenm, kzhuravl, llvm-commits
Differential Revision: https://reviews.llvm.org/D23688
llvm-svn: 279995
Zachary Turner [Mon, 29 Aug 2016 19:30:26 +0000 (19:30 +0000)]
Remove std::atomic from lldb::Address.
std::atomic<uint64_t> requires 64-bit alignment in order to
guarantee atomicity. Normally the compiler is pretty good about
aligning types, but an exception to this is when the type is
passed by value as a function parameter. In this case, if your
stack is 4-byte aligned, most modern compilers (including clang
as of LLVM 4.0) fail to align the type, rendering the atomicity
ineffective.
A deeper investigation of the class's implementation suggests
that the use of atomic was in vain anyway, because if the class
were to be shared amongst multiple threads, there were already
other data races present, and that the proper way to ensure
thread-safe access to this data would be to use a mutex from a
higher level.
Since the std::atomic was not serving its intended purpose anyway,
and since the presence of it generates compiler errors on some
platforms that cannot be workaround, we remove std::atomic from
Address here. Although unlikely, if data races do resurface
the proper fix should involve a mutex from a higher level, or an
attempt to limit the Address's access to a single thread.
llvm-svn: 279994
Vitaly Buka [Mon, 29 Aug 2016 19:28:34 +0000 (19:28 +0000)]
[asan] Enable new stack poisoning with store instruction by default
Reviewers: eugenis
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D23968
llvm-svn: 279993
Tim Northover [Mon, 29 Aug 2016 19:27:20 +0000 (19:27 +0000)]
GlobalISel: switch to SmallVector for pending legalizations.
std::queue was doing far to many heap allocations to be healthy.
llvm-svn: 279992
Tom Stellard [Mon, 29 Aug 2016 19:15:22 +0000 (19:15 +0000)]
AMDGPU/SI: Improve SILoadStoreOptimizer and run it before the scheduler
Summary:
The SILoadStoreOptimizer can now look ahead more then one instruction when
looking for instructions to merge, which greatly improves the number of
loads/stores that we are able to merge.
Moving the pass before scheduling avoids increasing register pressure after
the scheduler, so that the scheduler's register pressure estimates will be
more accurate. It also gives more consistent results, since it is no longer
affected by minor scheduling changes.
Reviewers: arsenm
Subscribers: arsenm, kzhuravl, llvm-commits
Differential Revision: https://reviews.llvm.org/D23814
llvm-svn: 279991
Tim Northover [Mon, 29 Aug 2016 19:12:20 +0000 (19:12 +0000)]
ASan: remove variable only used in assertions build
llvm-svn: 279990
Eric Fiselier [Mon, 29 Aug 2016 19:12:01 +0000 (19:12 +0000)]
Update Google Benchmark library.
llvm-svn: 279989
Tim Northover [Mon, 29 Aug 2016 19:07:16 +0000 (19:07 +0000)]
GlobalISel: legalize frem to a libcall on AArch64.
llvm-svn: 279988
Tim Northover [Mon, 29 Aug 2016 19:07:08 +0000 (19:07 +0000)]
GlobalISel: rework CallLowering so that it can be used for libcalls too.
There should be no functional change here, I'm just making the implementation
of "frem" (to libcall) legalization easier for a followup.
llvm-svn: 279987
Matt Arsenault [Mon, 29 Aug 2016 19:01:48 +0000 (19:01 +0000)]
AMDGPU/R600: Fix fixups used for constant arrays
Fixes bug 29289
llvm-svn: 279986
Kyle Butt [Mon, 29 Aug 2016 18:27:12 +0000 (18:27 +0000)]
IfConversion: Fix branch predication bug.
This bug shows up with diamonds that share unpredicable, unanalyzable branches.
There's an included test case from Hexagon. What was happening was that we were
attempting to predicate the branch instruction despite the fact that it was
checked to be the same. Now for unanalyzable branches we skip over the branch
instructions when predicating the block.
Differential Revision: https://reviews.llvm.org/D23939
llvm-svn: 279985
Vitaly Buka [Mon, 29 Aug 2016 18:17:21 +0000 (18:17 +0000)]
Use store operation to poison allocas for lifetime analysis.
Summary:
Calling __asan_poison_stack_memory and __asan_unpoison_stack_memory for small
variables is too expensive.
Code is disabled by default and can be enabled by -asan-experimental-poisoning.
PR27453
Reviewers: eugenis
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D23947
llvm-svn: 279984
Kostya Serebryany [Mon, 29 Aug 2016 17:45:43 +0000 (17:45 +0000)]
[scudo] use 32 bits of ASLR entropy instead of just 24 when shuffling allocated chunks
llvm-svn: 279983
Vitaly Buka [Mon, 29 Aug 2016 17:41:29 +0000 (17:41 +0000)]
[asan] Separate calculation of ShadowBytes from calculating ASanStackFrameLayout
Summary: No functional changes, just refactoring to make D23947 simpler.
Reviewers: eugenis
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D23954
llvm-svn: 279982
Vitaly Buka [Mon, 29 Aug 2016 17:16:59 +0000 (17:16 +0000)]
[asan] Remove runtime flag detect_stack_use_after_scope
Summary:
We are going to use store instructions to poison some allocas.
Runtime flag will require branching in instrumented code on every lifetime
intrinsic. We'd like to avoid that.
Reviewers: eugenis
Subscribers: llvm-commits, kubabrecka
Differential Revision: https://reviews.llvm.org/D23967
llvm-svn: 279981
David Majnemer [Mon, 29 Aug 2016 17:14:08 +0000 (17:14 +0000)]
[SimplifyCFG] Hoisting invalidates metadata
We forgot to remove optimization metadata when performing hosting during
FoldTwoEntryPHINode.
This fixes PR29163.
llvm-svn: 279980
Reid Kleckner [Mon, 29 Aug 2016 16:35:43 +0000 (16:35 +0000)]
Make vec_fabs.ll pass with MSVC 2013
We should revert this change once we drop support for MSVC 2013.
llvm-svn: 279979
Reid Kleckner [Mon, 29 Aug 2016 16:24:57 +0000 (16:24 +0000)]
Try to fix clang-offload-bunder.c test once more
llvm-svn: 279978
Teresa Johnson [Mon, 29 Aug 2016 16:22:23 +0000 (16:22 +0000)]
[gold] Fix test accidentally regressed for newer gold
With r279911 I accidentally regressed the gold/X86/start-lib-common.ll
test for newer golds (v1.12+) that honor the --start-lib/--end-lib.
Remove the alignment which should not be there to make this work with
both old and new gold linkers.
Additionally, now that we have a subdirectory for v1.12+ gold tests,
copy this test there and check specifically for the v1.12+ behavior.
llvm-svn: 279977
Evandro Menezes [Mon, 29 Aug 2016 16:04:37 +0000 (16:04 +0000)]
[AArch64] Adjust the scheduling model for Exynos M1.
Further refine the model for loads.
llvm-svn: 279976
Anna Thomas [Mon, 29 Aug 2016 15:41:59 +0000 (15:41 +0000)]
[StatepointsForGC] Rematerialize in the presence of PHIs
Summary:
While walking the use chain for identifying rematerializable values in RS4GC,
add the case where the current value and base value are the same PHI nodes.
This will aid rematerialization of geps and casts instead of relocating.
Reviewers: sanjoy, reames, igor
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D23920
llvm-svn: 279975
Teresa Johnson [Mon, 29 Aug 2016 15:33:01 +0000 (15:33 +0000)]
[LTO] Remove extraneous output
Remove some debugging output to stderr that snuck in with r279576.
llvm-svn: 279974
Sanjay Patel [Mon, 29 Aug 2016 15:27:17 +0000 (15:27 +0000)]
[Constant] remove fdiv and frem from canTrap()
Assuming the default FP env, we should not treat fdiv and frem any differently in terms of
trapping behavior than any other FP op. Ie, FP ops do not trap with the default FP env.
This matches how we treat the fdiv/frem in IR with isSafeToSpeculativelyExecute() and in
the backend after:
https://reviews.llvm.org/rL279970
llvm-svn: 279973
Sanjay Patel [Mon, 29 Aug 2016 14:57:53 +0000 (14:57 +0000)]
[SimplifyCFG] rename test file, regenerate checks, and add test
The fdiv test shows a problem similar to:
https://reviews.llvm.org/rL279970
llvm-svn: 279972
Gor Nishanov [Mon, 29 Aug 2016 14:34:12 +0000 (14:34 +0000)]
[Coroutines] Part 9: Add cleanup subfunction.
Summary:
[Coroutines] Part 9: Add cleanup subfunction.
This patch completes coroutine heap allocation elision. Now, the heap elision example from docs\Coroutines.rst compiles and produces expected result (see test/Transform/Coroutines/ex3.ll)
Intrinsic Changes:
* coro.free gets a token parameter tying it to coro.id to allow reliably discovering all coro.frees associated with a particular coroutine.
* coro.id gets an extra parameter that points back to a coroutine function. This allows to check whether a coro.id describes the enclosing function or it belongs to a different function that was later inlined.
CoroSplit now creates three subfunctions:
# f$resume - resume logic
# f$destroy - cleanup logic, followed by a deallocation code
# f$cleanup - just the cleanup code
CoroElide pass during devirtualization replaces coro.destroy with either f$destroy or f$cleanup depending whether heap elision is performed or not.
Other fixes, improvements:
* Fixed buglet in Shape::buildFrame that was not creating coro.save properly if coroutine has more than one suspend point.
* Switched to using variable width suspend index field (no longer limited to 32 bit index field can be as little as i1 or as large as i<whatever-size_t-is>)
Reviewers: majnemer
Subscribers: llvm-commits, mehdi_amini
Differential Revision: https://reviews.llvm.org/D23844
llvm-svn: 279971
Sanjay Patel [Mon, 29 Aug 2016 13:32:41 +0000 (13:32 +0000)]
[TargetLowering] remove fdiv and frem from canOpTrap() (PR29114)
Assuming the default FP env, we should not treat fdiv and frem any differently in terms of
trapping behavior than any other FP op. Ie, FP ops do not trap with the default FP env.
This matches how we treat these ops in IR with isSafeToSpeculativelyExecute(). There's a
similar bug in Constant::canTrap().
This bug manifests in PR29114:
https://llvm.org/bugs/show_bug.cgi?id=29114
...as a sequence of scalar divisions instead of a vector division on x86 for a <3 x float>
type.
Differential Revision: https://reviews.llvm.org/D23974
llvm-svn: 279970
Krzysztof Parzyszek [Mon, 29 Aug 2016 13:15:35 +0000 (13:15 +0000)]
Do not use MRI::getMaxLaneMaskForVReg as a mask covering whole register
MRI::getMaxLaneMaskForVReg does not always cover the whole register.
For example, on X86 the upper 16 bits of EAX cannot be accessed via
any subregister. Consequently, there is no lane mask that only covers
that part of EAX. The getMaxLaneMaskForVReg will return the union of
the lane masks for all subregisters, and in case of EAX, that union
will not cover the upper 16 bits.
This fixes https://llvm.org/bugs/show_bug.cgi?id=29132
llvm-svn: 279969
Tom Stellard [Mon, 29 Aug 2016 13:06:10 +0000 (13:06 +0000)]
AMDGPU/SI: Improve register allocation hints for sopk instructions
Summary:
For shrinking SOPK instructions, we were creating a hint to tell the
register allocator to use the register allocated for src0 for the dst
operand as well. However, this seems to not work sometimes depending
on the order virtual registers are assigned physical registers.
To fix this, I've added a second allocation hint which does the reverse,
asks that the register allocated for dst is used for src0.
Reviewers: arsenm
Subscribers: arsenm, llvm-commits, kzhuravl
Differential Revision: https://reviews.llvm.org/D23862
llvm-svn: 279968
Rafael Espindola [Mon, 29 Aug 2016 12:47:22 +0000 (12:47 +0000)]
Use the correct ctor/dtor section for dynamic-no-pic.
llvm-svn: 279967
Benjamin Kramer [Mon, 29 Aug 2016 12:41:32 +0000 (12:41 +0000)]
Mark test as XFAIL instead of disabling it everywhere.
There is no lit feature 'X86' so this test is just disabled completely.
Make it XFAIL until a solution is found.
llvm-svn: 279966
Rafael Espindola [Mon, 29 Aug 2016 12:33:42 +0000 (12:33 +0000)]
Move code only used by codegen out of MC. NFC.
MC itself never needs to know about these sections.
llvm-svn: 279965
Haojian Wu [Mon, 29 Aug 2016 12:26:33 +0000 (12:26 +0000)]
Fix -Wunused-but-set-variable warning.
Summary: A follow-up fix on r279958.
Reviewers: bkramer
Subscribers: cfe-commits
Differential Revision: https://reviews.llvm.org/D23989
llvm-svn: 279964
Tom Stellard [Mon, 29 Aug 2016 12:05:32 +0000 (12:05 +0000)]
AMDGPU/SI: Query AA, if available, in areMemAccessesTriviallyDisjoint()
Summary:
The SILoadStoreOptimizer will need to use AliasAnalysis here in order to
move it before scheduling.
Reviewers: arsenm
Subscribers: arsenm, llvm-commits, kzhuravl
Differential Revision: https://reviews.llvm.org/D23813
llvm-svn: 279963
Igor Kudrin [Mon, 29 Aug 2016 11:48:50 +0000 (11:48 +0000)]
[Coverage] Prevent creating a redundant counter if a nested body ends with a macro.
If there were several nested statements arranged in a way that all of them
end up with the same macro, then the expansion of this macro was assigned
with all the corresponding counters of these statements.
As a result, the wrong counter value was shown for the macro in llvm-cov.
This patch fixes the issue by preventing adding a counter for an expanded
source range if it already has an assigned counter, which is expected
to come from the most specific statement.
Differential Revision: https://reviews.llvm.org/D23160
llvm-svn: 279962
Igor Breger [Mon, 29 Aug 2016 09:12:31 +0000 (09:12 +0000)]
Fixed a bug in type legalizer for masked gather.
The problem occurs when the Node doesn't updated in place , UpdateNodeOperation() return the node that already exist.
In this case assert fail in PromoteIntegerOperand() , N have 2 results ( val + chain).
Differential Revision: http://reviews.llvm.org/D23756
llvm-svn: 279961
Igor Breger [Mon, 29 Aug 2016 08:52:52 +0000 (08:52 +0000)]
[AVX512] In some cases KORTEST instruction may be used instead of ZEXT + TEST sequence.
Differential Revision: http://reviews.llvm.org/D23490
llvm-svn: 279960
Haojian Wu [Mon, 29 Aug 2016 08:48:15 +0000 (08:48 +0000)]
[InstructionSelect] NumBlocks isn't defined in DEBUG build.
Summary: A follow-up fixing on http://llvm.org/viewvc/llvm-project?view=revision&revision=279905.
Reviewers: bkramer
Subscribers: cfe-commits
Differential Revision: https://reviews.llvm.org/D23985
llvm-svn: 279959
Craig Topper [Mon, 29 Aug 2016 04:49:31 +0000 (04:49 +0000)]
[X86] Don't lower FABS/FNEG masking directly to a ConstantPool load. Just create a ConstantFPSDNode and let that be lowered.
This allows broadcast loads to used when available.
llvm-svn: 279958
Craig Topper [Mon, 29 Aug 2016 04:49:27 +0000 (04:49 +0000)]
[AVX-512] Always use v8i64 when converting 512-bit FAND/FOR/FXOR/FANDN to integer operations when DQI isn't supported. This is consistent with the recent changes to promote logical operations to i64 vectors.
llvm-svn: 279957
Craig Topper [Mon, 29 Aug 2016 04:49:24 +0000 (04:49 +0000)]
[AVX-512] Add 512-bit fabs tests with and without AVX512DQ.
llvm-svn: 279956
Eric Fiselier [Mon, 29 Aug 2016 01:43:41 +0000 (01:43 +0000)]
Fix pair::operator=(TupleLike&&).
This assignment operator was previously broken since the SFINAE always resulted
in substitution failure. This caused assignments to turn into
copy construction + assignment.
This patch was originally committed as r279953 but was reverted due to warnings
in the test-suite. This new patch corrects those warnings.
llvm-svn: 279955
Eric Fiselier [Mon, 29 Aug 2016 01:39:54 +0000 (01:39 +0000)]
Revert r279953 - Fix pair::operator=(TupleLike&&)
The test emits warnings causing the test-suite to fail. Since I want this
patch merged into 3.9 I'll recommit it with a clean test.
llvm-svn: 279954
Eric Fiselier [Mon, 29 Aug 2016 01:09:47 +0000 (01:09 +0000)]
Fix pair::operator=(TupleLike&&).
This assignment operator was previously broken since the SFINAE always resulted
in substitution failure. This caused assignments to turn into
copy construction + assignment.
llvm-svn: 279953
Lang Hames [Mon, 29 Aug 2016 00:54:29 +0000 (00:54 +0000)]
[Orc] Simplify LogicalDylib and move it back inside CompileOnDemandLayer. Also
switch to using one indirect stub manager per logical dylib rather than one per
input module.
LogicalDylib is a helper class used by the CompileOnDemandLayer to manage
symbol resolution between modules during lazy compilation. In particular, it
ensures that internal symbols resolve correctly even in the case where multiple
input modules contain the same internal symbol name (which must to be promoted
to external hidden linkage so that functions in any given module can be split
out by lazy compilation). LogicalDylib's resolution scheme (before this commit)
required one stub-manager per input module. This made recompilation of functions
(by adding a module containing a new definition) difficult, as the stub manager
for any given symbol was bound to the module that supplied the original
definition. By using one stubs manager for the whole logical dylib symbols can
be more easily replaced, although support for doing this is not included in this
patch (it will be implemented in a follow up).
llvm-svn: 279952
Craig Topper [Sun, 28 Aug 2016 22:20:51 +0000 (22:20 +0000)]
[AVX-512] Add support for selecting 512-bit VPABSB/VPABSW when BWI is available.
llvm-svn: 279951
Craig Topper [Sun, 28 Aug 2016 22:20:48 +0000 (22:20 +0000)]
[AVX-512] Add patterns for selecting 128/256-bit EVEX VPABS instructions.
llvm-svn: 279950
Craig Topper [Sun, 28 Aug 2016 22:20:45 +0000 (22:20 +0000)]
[AVX-512] Add testcases showing that we don't emit 512-bit vpabsb/vpabsw. Will be fixed in a future commit.
llvm-svn: 279949
Eric Fiselier [Sun, 28 Aug 2016 22:14:37 +0000 (22:14 +0000)]
Implement C++17 std::sample.
This patch implements the std::sample function added to C++17 from LFTS. It
also removes the std::experimental::sample implementation which now forwards
to std::sample.
llvm-svn: 279948
Eric Fiselier [Sun, 28 Aug 2016 21:55:00 +0000 (21:55 +0000)]
Mark LWG 2716 as complete - shuffle and sample disallows lvalue URNGs.
Libc++'s implementation of shuffle and sample already support lvalue and rvalue
RNG's. This patch adds tests for both categories and marks the issue as complete.
This patch also contains drive-by change for std::experimental::sample which
improves the diagnostics produced when the correct iterator categories are
not supplied.
llvm-svn: 279947
Saleem Abdulrasool [Sun, 28 Aug 2016 21:33:30 +0000 (21:33 +0000)]
AST: improve layout of SimpleTypoCorrector
Add the "explicit" specifier to the single-argument constructor of
SimpleTypoCorrector. Reorder the fields to remove excessive padding (8 bytes).
Patch by Alexander Shaposhnikov!
llvm-svn: 279946
Eric Fiselier [Sun, 28 Aug 2016 21:26:01 +0000 (21:26 +0000)]
Implement LWG 2711. Constrain path members.
llvm-svn: 279945
Sylvestre Ledru [Sun, 28 Aug 2016 20:33:42 +0000 (20:33 +0000)]
Fix some typos in the doc
llvm-svn: 279944
Sylvestre Ledru [Sun, 28 Aug 2016 20:29:18 +0000 (20:29 +0000)]
Fix some typos in the doc
llvm-svn: 279943
Sylvestre Ledru [Sun, 28 Aug 2016 20:22:34 +0000 (20:22 +0000)]
Fix a typo in the doc: overriden -> overridden
llvm-svn: 279942
Saleem Abdulrasool [Sun, 28 Aug 2016 20:10:33 +0000 (20:10 +0000)]
EHABI: fail on WMMX vops without WMMX support
When the unwinder is built without WMMX support, if we encounter a WMMX register
virtual operation, early rather than attempting to continue as we would not have
saved the register set anyways. This should never come down this path, but,
just in case, help it abort more explicitly.
llvm-svn: 279941
Eric Fiselier [Sun, 28 Aug 2016 18:33:08 +0000 (18:33 +0000)]
[Docs] Update libc++ target names after r279675.
llvm-svn: 279940
Sanjay Patel [Sun, 28 Aug 2016 18:31:32 +0000 (18:31 +0000)]
[x86] add tests for <3 x N> vector types (PR29114)
llvm-svn: 279939
Eric Fiselier [Sun, 28 Aug 2016 18:28:51 +0000 (18:28 +0000)]
[CMake] Be more consistent about naming targets and components in libc++abi
This patch (and commit summary) mirror r279675 by Chris B which was applied
to libc++ but not libc++abi.
Summary:
The point of this patch is to have a consistent convention for naming build,
check and install targets so that the targets can be constructed from the
project name.
This change renames a bunch of CMake components and targets from libcxxabi to
cxxabi. For each renamed target I've added a convenience target that matches
the old target name and depends on the new target. This will preserve function
of the old targets so that the change doesn't break the world. We can evaluate
if it is worth removing the extra targets later.
llvm-svn: 279938
Sanjay Patel [Sun, 28 Aug 2016 18:18:00 +0000 (18:18 +0000)]
[InstCombine] use m_APInt to allow icmp (and X, Y), C folds for splat constant vectors
llvm-svn: 279937
Eric Fiselier [Sun, 28 Aug 2016 18:16:18 +0000 (18:16 +0000)]
[CMake] Apply r279151 cleanup to libc++abi.
This patch applies changes similar to those in r279515 to libc++abi.
Summary of changes in this patch:
* Renamed variable LLVM_CONFIG -> LLVM_CONFIG_PATH
* Renamed variable LIBCXXABI_BUILT_STANDALONE -> LIBCXXABI_STANDALONE_BUILD
* Add an include of AddLLVM in the tests subdirectory for add_lit_testsuite.
llvm-svn: 279936
Saleem Abdulrasool [Sun, 28 Aug 2016 18:16:00 +0000 (18:16 +0000)]
test: fix test under ASAN and MSAN
When we're running tests under ASAN or MSAN, they're compiled with -O1, which
enables tail call elimination. This causes backtrace_test to fail: the compiler
performs tail call elimination for call3_nothrow, but it can't for call3_throw,
leading to a mismatched frame count. Disable tail call elimination (and
inlining, just to be explicit) to avoid this.
Patch by Shoaib Meenai!
llvm-svn: 279935
Simon Pilgrim [Sun, 28 Aug 2016 17:27:14 +0000 (17:27 +0000)]
[X86][AVX512] Only combine EVEX targets shuffles to shuffles of the same number of vector elements
Over eager combing prevents the correct folding of writemasks.
At the moment this occurs for ALL EVEX shuffles, in the future we need to check that the user of the root shuffle is a VSELECT that can fold to a writemask.
llvm-svn: 279934
Hal Finkel [Sun, 28 Aug 2016 16:17:58 +0000 (16:17 +0000)]
[PowerPC] Implement lowering for atomicrmw min/max/umin/umax
Implement lowering for atomicrmw min/max/umin/umax. Fixes PR28818.
llvm-svn: 279933
Filipe Cabecinhas [Sun, 28 Aug 2016 10:42:21 +0000 (10:42 +0000)]
Revert "Start reifying error descriptions. Second try: Try to appease Visual Studio."
This reverts r279931. Will try it with the same Visual Studio version
before committing again.
llvm-svn: 279932
Filipe Cabecinhas [Sun, 28 Aug 2016 10:32:44 +0000 (10:32 +0000)]
Start reifying error descriptions. Second try: Try to appease Visual Studio.
Summary:
This commit sets up the infrastructure to use reified error
descriptions, and moves ReportStackOverflow to the new system.
After we convert all the errors, we'll be able to simplify ScopedInErrorReport
and remove the older debugging mechanism which had some errors partly reified
in some way. We'll be able to maintain the external API.
ScopedInErrorReport will be able to track one of the reified errors at a time.
The purpose of this is so we have its destructor actually print the error and
possibly interface with the debugger (will depend on the platform, of course).
Reviewers: kcc, samsonov, timurrrr
Subscribers: kubabrecka, llvm-commits
Differential Revision: https://reviews.llvm.org/D23672
llvm-svn: 279931
Elena Demikhovsky [Sun, 28 Aug 2016 08:53:53 +0000 (08:53 +0000)]
[Loop Vectorizer] Fixed memory confilict checks.
Fixed a bug in run-time checks for possible memory conflicts inside loop.
The bug is in Low <-> High boundaries calculation. The High boundary should be calculated as "last memory access pointer + element size".
Differential revision: https://reviews.llvm.org/D23176
llvm-svn: 279930
Craig Topper [Sun, 28 Aug 2016 06:06:28 +0000 (06:06 +0000)]
[AVX-512] Promote AND/OR/XOR to v2i64/v4i64/v8i64 even when we have AVX512F/AVX512VL.
Previously we weren't creating masked logical operations if bitcasts appeared between the logic operation and the select. The IR optimizers can move bitcasts across logic operations and create these cases. To minimize the number of cases we need to handle, this change promotes all logic ops to an i64 vector type just like when only SSE or AVX is available.
Unfortunately, this also has the consequence of making it difficult to select unmasked VPANDD/VPORD/VPXORD in all the cases it was previously used. This is the cause of most of the test change. This shouldn't result in any functional change though.
llvm-svn: 279929
Craig Topper [Sun, 28 Aug 2016 06:06:24 +0000 (06:06 +0000)]
[AVX-512] Add tests to show that we don't select masked logic ops if there are bitcasts between the logic op and the select.
This is taken from optimized IR of clang test cases for masked logic ops.
llvm-svn: 279928
Craig Topper [Sun, 28 Aug 2016 06:06:21 +0000 (06:06 +0000)]
[X86] Rename PABSB/D/W instructions to be consistent with SSE/AVX instructions instead of ending 128/256. NFC
llvm-svn: 279927
Dimitry Andric [Sat, 27 Aug 2016 19:32:03 +0000 (19:32 +0000)]
Avoid embedded preprocessor directives in __tree
Similar to rL242623, move C++ version checks outside of _NOEXCEPT_()
macro invocation argument lists, to avoid "embedding a directive within
macro arguments has undefined behavior" warnings.
Differential Revision: https://reviews.llvm.org/D23961
llvm-svn: 279926
Jan Vesely [Sat, 27 Aug 2016 19:09:43 +0000 (19:09 +0000)]
AMDGPU/R600: Enable Load combine
Fix and improve tests
Differential Revision: https://reviews.llvm.org/D23899
llvm-svn: 279925
Craig Topper [Sat, 27 Aug 2016 17:13:43 +0000 (17:13 +0000)]
[X86] Rename predicate function that detects if requires one of the REX.B, REX.X or REX.R bits. It's old name conflicted with a function in X8II namespace that doesnt' quite do the same thing. NFC
llvm-svn: 279924
Craig Topper [Sat, 27 Aug 2016 17:13:41 +0000 (17:13 +0000)]
[X86] Keep looping over operands looking for byte registers even if we already found a register that requires a REX prefix. Otherwise we don't error if a high byte register is used after SPL/BPL/DIL/SIL.
llvm-svn: 279923
Craig Topper [Sat, 27 Aug 2016 17:13:37 +0000 (17:13 +0000)]
[X86] Include XMM/YMM/ZMM16-23 in X86II::isX86_64ExtendedReg. This feels more consistent with its name and simplifies assembler code.
llvm-svn: 279922
Craig Topper [Sat, 27 Aug 2016 17:13:34 +0000 (17:13 +0000)]
[X86] Don't allow DR8-DR15 to be assembled in 32-bit mode. Add missing test for CR8-CR15.
llvm-svn: 279921
Zachary Turner [Sat, 27 Aug 2016 16:38:11 +0000 (16:38 +0000)]
Fix some build bot breakages.
There was some code that was ifdef'ed out that I didn't catch
in my earlier patch.
llvm-svn: 279920
Zachary Turner [Sat, 27 Aug 2016 16:35:15 +0000 (16:35 +0000)]
Add some unit tests for StringExtractor::GetNameColonValue.
These are helpful on their own, but will be even more useful
once the GetNameColonValue is updated to return StringRefs
instead of std::strings.
llvm-svn: 279919
Akira Hatanaka [Sat, 27 Aug 2016 16:06:36 +0000 (16:06 +0000)]
[asan] Disable tests more selectively.
Add "target-arch+host-os" to the feature list to enable disabling the
tests I committed in r279614 and r279880 more selectively.
llvm-svn: 279918
Zachary Turner [Sat, 27 Aug 2016 15:52:29 +0000 (15:52 +0000)]
Convert some functions to use StringRef instead of c_str, len
This started as an effort to change StringExtractor to store a
StringRef internally instead of a std::string. I got that working
locally with just 1 test failure which I was unable to figure out the
cause of. But it was also a massive changelist due to a trickle
down effect of changes.
So I'm starting over, using what I learned from the first time to
tackle smaller, more isolated changes hopefully leading up to
a full conversion by the end.
At first the changes (such as in this CL) will seem mostly
a matter of preference and pointless otherwise. However, there
are some places in my larger CL where using StringRef turned 20+
lines of code into 2, drastically simplifying logic. Hopefully
once these go in they will illustrate some of the benefits of
thinking in terms of StringRef.
llvm-svn: 279917
Akira Hatanaka [Sat, 27 Aug 2016 05:57:50 +0000 (05:57 +0000)]
[asan] Use "REQUIRES: x86_64-target-arch" to disable the test on i386.
My attempt to disable this test on i386 by adding "UNSUPPORTED: i386-apple"
in r279880 wasn't succesful, so I'm using REQUIRES instead.
llvm-svn: 279916
Craig Topper [Sat, 27 Aug 2016 05:26:54 +0000 (05:26 +0000)]
[X86] Remove stale comment about FixupBWInsts pass being off by default. NFC
llvm-svn: 279915
Craig Topper [Sat, 27 Aug 2016 05:22:15 +0000 (05:22 +0000)]
[AVX-512] Allow EVEX encoding unordered/ordered/equal/notequal VCMPPS/PD/SS/SD to be commuted just like the SSE and AVX counterparts.
llvm-svn: 279914
Craig Topper [Sat, 27 Aug 2016 05:22:12 +0000 (05:22 +0000)]
[X86] Enable FR32/FR64 cmpeq/cmpne/cmpunord/cmpord to be commuted.
llvm-svn: 279913
Craig Topper [Sat, 27 Aug 2016 05:22:08 +0000 (05:22 +0000)]
[AVX-512] Add load folding for EVEX vcmpps/pd/ss/sd.
llvm-svn: 279912
Teresa Johnson [Sat, 27 Aug 2016 04:41:22 +0000 (04:41 +0000)]
[LTO] Don't create a new common unless merged has different size
Summary:
This addresses a regression in common handling from the new LTO
API in r278338. Only create a new common if the size is different.
The type comparison against an array type fails when the size is
different but not an array. GlobalMerge does not handle the
array types as well and we lose some global merging opportunities.
Reviewers: mehdi_amini
Subscribers: junbuml, llvm-commits, mehdi_amini
Differential Revision: https://reviews.llvm.org/D23955
llvm-svn: 279911
Matt Arsenault [Sat, 27 Aug 2016 03:39:27 +0000 (03:39 +0000)]
AMDGPU: Mark sched model complete
Fixes bug 26800
llvm-svn: 279910
Matt Arsenault [Sat, 27 Aug 2016 03:00:51 +0000 (03:00 +0000)]
AMDGPU: Remove unneeded implicit exec uses/defs
SI_BREAK, SI_IF_BREAK, and SI_ELSE_BREAK do not def exec.
SI_IF_BREAK and SI_ELSE_BREAK do not read it either.
llvm-svn: 279909
Lang Hames [Sat, 27 Aug 2016 02:59:24 +0000 (02:59 +0000)]
[Orc] Explicitly specify type for assignment.
This should fix the MSVC errors in
http://lab.llvm.org:8011/builders/clang-x64-ninja-win7/builds/15120
llvm-svn: 279908
Sebastian Pop [Sat, 27 Aug 2016 02:48:41 +0000 (02:48 +0000)]
GVN-hoist: invalidate MD cache (PR29144)
Without invalidating the entries in the MD cache we would try to access instructions
that were removed in previous iterations of hoisting.
Differential Revision: https://reviews.llvm.org/D23927
llvm-svn: 279907
Quentin Colombet [Sat, 27 Aug 2016 02:38:27 +0000 (02:38 +0000)]
[RegBankSelect] Do not abort when the target wants to fall back.
llvm-svn: 279906
Quentin Colombet [Sat, 27 Aug 2016 02:38:24 +0000 (02:38 +0000)]
[InstructionSelect] Do not abort when the target wants to fall back.
llvm-svn: 279905
Quentin Colombet [Sat, 27 Aug 2016 02:38:21 +0000 (02:38 +0000)]
[MachineLegalize] Do not abort when the target wants to fall back.
llvm-svn: 279904
Aditya Kumar [Sat, 27 Aug 2016 02:26:42 +0000 (02:26 +0000)]
Add attribute noreturn to functions that throw
Reviewers: mclow.lists, EricWF, howard.hinnant, sebpop
Subscribers: cfe-commits
Differential Revision: https://reviews.llvm.org/D21232
llvm-svn: 279903
Matt Arsenault [Sat, 27 Aug 2016 01:32:27 +0000 (01:32 +0000)]
AMDGPU: Select mulhi 24-bit instructions
llvm-svn: 279902
Matt Arsenault [Sat, 27 Aug 2016 01:00:37 +0000 (01:00 +0000)]
AMDGPU: Move cndmask pseudo to be isel pseudo
There's only one use of this for the convenience
of a pattern. I think v_mov_b64_pseudo should also be
moved, but SIFoldOperands does currently make use of it.
llvm-svn: 279901