platform/kernel/u-boot.git
8 years agodriver: net: fsl-mc: flib changes for MC FW 9.0.0
Prabhakar Kushwaha [Thu, 24 Dec 2015 10:02:49 +0000 (15:32 +0530)]
driver: net: fsl-mc: flib changes for MC FW 9.0.0

MC firmware version 9.0.0 contains
 - Support of new APIs
 - Update in existing APIs
 - Change in Major and minor version of DPAA2 objects

This patch contains modifications in FLIB files to support new
MC firmware version.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agodriver: net: fsl-mc: Add version check for MC objects
Prabhakar Kushwaha [Thu, 24 Dec 2015 10:02:37 +0000 (15:32 +0530)]
driver: net: fsl-mc: Add version check for MC objects

Check and compare version of management  complex's object with
the version supported by Freescale ldpaa2 ethernet driver.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agosecure_boot: change error handler for esbc_validate
Aneesh Bansal [Fri, 22 Jan 2016 11:07:28 +0000 (16:37 +0530)]
secure_boot: change error handler for esbc_validate

In case of error while executing esbc_validate command, SNVS
transition and issue of reset is required only for secure-boot.
If boot mode is non-secure, this is not required.

Similarly, esbc_halt command which puts the core in Spin Loop
is applicable only for Secure Boot.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agosecure_boot: enable chain of trust for PowerPC platforms
Aneesh Bansal [Fri, 22 Jan 2016 11:07:27 +0000 (16:37 +0530)]
secure_boot: enable chain of trust for PowerPC platforms

Chain of Trust is enabled for PowerPC platforms for Secure Boot.
CONFIG_BOARD_LATE_INIT is defined.
In board_late_init(), fsl_setenv_chain_of_trust() is called which
will perform the following:
- If boot mode is non-secure, return (No Change)
- If boot mode is secure, set the following environmet variables:
   bootdelay = 0 (To disable Boot Prompt)
   bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agosecure_boot: enable chain of trust for ARM platforms
Aneesh Bansal [Fri, 22 Jan 2016 11:07:26 +0000 (16:37 +0530)]
secure_boot: enable chain of trust for ARM platforms

Chain of Trust is enabled for ARM platforms (LS1021 and LS1043).
In board_late_init(), fsl_setenv_chain_of_trust() is called which
will perform the following:
- If boot mode is non-secure, return (No Change)
- If boot mode is secure, set the following environmet variables:
   bootdelay = 0 (To disable Boot Prompt)
   bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agosecure_boot: create function to determine boot mode
Aneesh Bansal [Fri, 22 Jan 2016 11:07:25 +0000 (16:37 +0530)]
secure_boot: create function to determine boot mode

A function is created to detrmine if the boot mode is secure
or non-secure for differnt SoC's.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agosecure_boot: split the secure boot functionality in two parts
Aneesh Bansal [Fri, 22 Jan 2016 11:07:24 +0000 (16:37 +0530)]
secure_boot: split the secure boot functionality in two parts

There are two phases in Secure Boot
1. ISBC: In BootROM, validate the BootLoader (U-Boot).
2. ESBC: In U-Boot, continuing the Chain of Trust by
         validating and booting LINUX.

For ESBC phase, there is no difference in SoC's based on ARM or
PowerPC cores.

But the exit conditions after ISBC phase i.e. entry conditions for
U-Boot are different for ARM and PowerPC.
PowerPC:

If Secure Boot is executed, a separate U-Boot target is required
which must be compiled with a diffrent Text Base as compared to
Non-Secure Boot. There are some LAW and TLB settings which are
required specifically for Secure Boot scenario.

ARM:
ARM based SoC's have a fixed memory map and exit conditions from
BootROM are same irrespective of boot mode (Secure or Non-Secure).

Thus the current Secure Boot functionlity has been split into
two parts:
CONFIG_CHAIN_OF_TRUST
This will have the following functionality as part of U-Boot:
1. Enable commands like esbc_validate, esbc_halt
2. Change the environment settings based on bootmode, determined
   at run time:
     - If bootmode is non-secure, no change
     - If bootmode is secure, set the following:
         - bootdelay = 0 (Don't give boot prompt)
         - bootcmd = Validate and execute the bootscript.

CONFIG_SECURE_BOOT
This is defined only for creating a different compile time target
for secure boot.

Traditionally, both these functionalities were defined under
CONFIG_SECURE_BOOT. This patch is aimed at removing the requirement
for a separate Secure Boot target for ARM based SoC's.
CONFIG_CHAIN_OF_TRUST will be defined and boot mode will be
determine at run time.

Another Security Requirement for running CHAIN_OF_TRUST is that
U-Boot environemnt must not be picked from flash/external memory.
This cannot be done based on bootmode at run time in current U-Boot
architecture. Once this dependency is resolved, no separate
SECURE_BOOT target will be required for ARM based SoC's.

Currently, the only code under CONFIG_SECURE_BOOT for ARM SoC's is
defining CONFIG_ENV_IS_NOWHERE

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agosecure_boot: include/configs: move definition of CONFIG_CMD_BLOB
Aneesh Bansal [Fri, 22 Jan 2016 11:07:23 +0000 (16:37 +0530)]
secure_boot: include/configs: move definition of CONFIG_CMD_BLOB

CONFIG_CMD_BLOB must be defined in case of Secure Boot. It was
earlier defined in all config files. The definition has been
moved to a common file which is included by all configs.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agosecure_boot: include/configs: make secure boot header file uniform
Aneesh Bansal [Fri, 22 Jan 2016 11:07:22 +0000 (16:37 +0530)]
secure_boot: include/configs: make secure boot header file uniform

The file fsl_secure_boot.h must be included in config file for
Secure Boot. This is not required to be protected by any macro.
CONFIG_FSL_CAAM must be defined and CONFIG_CMD_HASH should be
turned on.

The above was missing in some config files and all files have been
made uniform in this respect.

Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agodrivers: net: fsl_mc: Compare pointer value qbman_swp_mc_start
Pratiyush Mohan Srivastava [Tue, 22 Dec 2015 11:20:19 +0000 (16:50 +0530)]
drivers: net: fsl_mc: Compare pointer value qbman_swp_mc_start

Current code compares the return pointer of function
qbman_cena_write_start with NULL. Instead the value of the return
pointer should be compared.

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Acked-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: ls2080a: Increase MC's DDR size to 512 MB
Pratiyush Mohan Srivastava [Tue, 22 Dec 2015 11:19:34 +0000 (16:49 +0530)]
armv8: ls2080a: Increase MC's DDR size to 512 MB

Freescale's management complex (MC) uses System DDR for internal usage.
Increase used System DDR size from 256MB to 512 MB.

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Acked-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: ls2040a: Add support of LS2040A SoC
Pratiyush Mohan Srivastava [Tue, 22 Dec 2015 11:18:43 +0000 (16:48 +0530)]
armv8: ls2040a: Add support of LS2040A SoC

Freescale's LS2040A is a another personality of LS2080A SoC
without AIOP support consisting of 4 armv8 cores.

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Acked-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: Enable all 8 DPMAC ports in LS2080A Personality
Pratiyush Mohan Srivastava [Tue, 22 Dec 2015 11:17:35 +0000 (16:47 +0530)]
armv8: Enable all 8 DPMAC ports in LS2080A Personality

LS2080A has support for 8 DPMAC ports out of which
only 5 ports can be used at a time.
Enabling all 8 DPMAC ports of LS2080A personality.

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Acked-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoSECURE BOOT: support for validation of dynamic image
Aneesh Bansal [Tue, 8 Dec 2015 08:44:15 +0000 (14:14 +0530)]
SECURE BOOT: support for validation of dynamic image

Some images to be validated are relocated to a dynamic
address at run time. So, these addresses cannot be known
befor hand while signing the images and creating the header
offline.
So, support is required to pass the image address to the
validate function as an argument.
If an address is provided to the function, the address
field in Header is not read and is treated as a reserved
field.

Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoSECURE BOOT: separate function created for signature
Aneesh Bansal [Tue, 8 Dec 2015 08:44:14 +0000 (14:14 +0530)]
SECURE BOOT: separate function created for signature

The code for image hash calculation, hash calculation from
RSA signature and comparison of hashes has been mobed to a
separate function.

Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoSECURE BOOT: separate functions for reading keys
Aneesh Bansal [Tue, 8 Dec 2015 08:44:13 +0000 (14:14 +0530)]
SECURE BOOT: separate functions for reading keys

Separate functions are created for reading and checking the
sanity of Public keys:
- read_validate_single_key
- read_validate_ie_tbl
- read_validate_srk_table

Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoSECURE BOOT: change prototype of fsl_secboot_validate function
Aneesh Bansal [Tue, 8 Dec 2015 08:44:12 +0000 (14:14 +0530)]
SECURE BOOT: change prototype of fsl_secboot_validate function

The prototype and defination of function fsl_secboot_validate
has been changed to support calling this function from another
function within u-boot.
Only two aruments needed:
1) header address - Mandatory
2) SHA256 string - optional

Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agodrivers/ddr/fsl: fsl_ddr_sdram_size remove unused controllers
Ed Swarthout [Thu, 14 Jan 2016 18:28:04 +0000 (12:28 -0600)]
drivers/ddr/fsl: fsl_ddr_sdram_size remove unused controllers

Following commit 61bd2f75, exclude unused DDR controller from
calculating RAM size for SPL boot.

Signed-off-by: Ed Swarthout <Ed.Swarthout@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: fsl-layerscape: fixes lsch2 serdes registers define
Shaohui Xie [Mon, 14 Dec 2015 10:05:35 +0000 (18:05 +0800)]
armv8: fsl-layerscape: fixes lsch2 serdes registers define

Fixes lsch2 SerDes registers define according to LS1043A RM Rev D.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarm: ls1021a: Adjust sata register default values
Tang Yuantian [Wed, 16 Dec 2015 05:50:57 +0000 (13:50 +0800)]
arm: ls1021a: Adjust sata register default values

Updated the default sata register values to enhance the
performance and stability.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agodriver/ddr/fsl: Add workaround for A009663
Shengzhou Liu [Wed, 16 Dec 2015 08:45:41 +0000 (16:45 +0800)]
driver/ddr/fsl: Add workaround for A009663

Erratum A-009663 workaround requires to set DDR_INTERVAL[BSTOPRE] to 0
before setting DDR_SDRAM_CFG[MEM_EN] and set DDR_INTERVAL[BSTOPRE]
to the desired value after DDR initialization has completed.

When DDR controller is configured to operate in auto-precharge
mode(DDR_INTERVAL[BSTOPRE]=0), this workaround is not needed.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8: fsl-lsch3: fixup SYSCLK frequency in device tree
Prabhakar Kushwaha [Thu, 24 Dec 2015 11:55:06 +0000 (17:25 +0530)]
armv8: fsl-lsch3: fixup SYSCLK frequency in device tree

SYSCLK frequency is dependent on on-board switch settings. It may
vary as per requirement. boot-loader is aware of board switch
configurations.

So Fixup Linux device tree from boot-loader.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
CC: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8/ls1043aqds: enable qixis_reset command to boot from NAND/SD
Gong Qianyu [Thu, 31 Dec 2015 10:29:04 +0000 (18:29 +0800)]
armv8/ls1043aqds: enable qixis_reset command to boot from NAND/SD

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8/ls1043aqds: fix qixis_reset command issue
Gong Qianyu [Thu, 31 Dec 2015 10:29:03 +0000 (18:29 +0800)]
armv8/ls1043aqds: fix qixis_reset command issue

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agofreescale/qixis: Add support for booting from SD/QSPI
Gong Qianyu [Thu, 31 Dec 2015 10:29:02 +0000 (18:29 +0800)]
freescale/qixis: Add support for booting from SD/QSPI

1.Use "qixis_reset sd" to boot from SD
2.Use "qixis_reset sd_qspi" to boot from SD with QSPI support
3.Use "qixis_reset qspi" to boot from QSPI flash

On some SoCs such as LS1021A and LS1043A, IFC and QSPI could be
pin-multiplexed. So the switches are different between SD boot with
IFC support and SD boot with QSPI support. The default booting from
SD is with IFC support.

Once QSPI is enabled(IFC disabled), only use I2C to access QIXIS.

Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoarmv8/ls1043aqds: Add support for >2GB memory
Shaohui Xie [Mon, 4 Jan 2016 03:03:44 +0000 (11:03 +0800)]
armv8/ls1043aqds: Add support for >2GB memory

This patch also exposes the complete DDR region(s) to Linux.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agofsl/ddr: Add workaround for ERRATUM_A009942
Shengzhou Liu [Wed, 6 Jan 2016 03:26:51 +0000 (11:26 +0800)]
fsl/ddr: Add workaround for ERRATUM_A009942

During the receive data training, the DDRC may complete on a
non-optimal setting that could lead to data corruption or
initialization failure.

Workaround: before setting MEM_EN, set DEBUG_29 register with
specific value for different data rates.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
8 years agoMerge git://git.denx.de/u-boot-fdt
Tom Rini [Fri, 22 Jan 2016 22:01:22 +0000 (17:01 -0500)]
Merge git://git.denx.de/u-boot-fdt

8 years agodevicetree: use wildcard to clean arch subdir
Thomas Chou [Wed, 6 Jan 2016 01:49:24 +0000 (09:49 +0800)]
devicetree: use wildcard to clean arch subdir

Use wildcard to clean arch subdirectories, as it is cleaner than
listing all the arch which builds dtb.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
8 years agorockchip: Update the README
Simon Glass [Fri, 22 Jan 2016 02:45:25 +0000 (19:45 -0700)]
rockchip: Update the README

GPIO, I2C, LCD and HDMI are now implemented. We have more than one PMIC.
There is an implementation to run the CPU at full speed although it does
not seem to make much difference.

Update the README to cover recent developments.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: Add support for Raxda Rock 2
Simon Glass [Fri, 22 Jan 2016 02:45:24 +0000 (19:45 -0700)]
rockchip: Add support for Raxda Rock 2

This board includes an RK3288 SoC on a SOM. It can be mounted on a
base-board which provides a wide range of peripherals.

So far this is verified to boot to a prompt from a microSD card. The serial
console works as well as HDMI.

Thanks to Tom Cubie for sending me a board.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: rock2: dts: Make changes for U-Boot
Simon Glass [Fri, 22 Jan 2016 02:45:23 +0000 (19:45 -0700)]
rockchip: rock2: dts: Make changes for U-Boot

Add the required pre-relocation tags and SDRAM init information for U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: rock2: Bring in device tree files from Linux
Simon Glass [Fri, 22 Jan 2016 02:45:22 +0000 (19:45 -0700)]
rockchip: rock2: Bring in device tree files from Linux

Bring in the current device tree files for rock2 from linux/next commit
719d6c1. Hopefully this is the latest one.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: dts: Sync up SPDIF node with Linux
Simon Glass [Fri, 22 Jan 2016 02:45:21 +0000 (19:45 -0700)]
rockchip: dts: Sync up SPDIF node with Linux

This has been added and we have references to it in the rock2 board. Add
this node.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: firefly-rk3288: Enable HDMI output
Simon Glass [Fri, 22 Jan 2016 02:45:20 +0000 (19:45 -0700)]
rockchip: firefly-rk3288: Enable HDMI output

Enable HDMI output and a console on firefly.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: jerry: Enable EDP and HDMI video output
Simon Glass [Fri, 22 Jan 2016 02:45:19 +0000 (19:45 -0700)]
rockchip: jerry: Enable EDP and HDMI video output

Enable these devices using the VOPL video output device. We explicitly
disable VOPB in the device tree to avoid it taking over. Since this device
has an LCD display this comes up by default. If the display fails for some
reason then it will attempt to use HDMI. It is possible to force it to fail
(and thus fall back to HDMI) by puting 'return -EPERM' at the top of
rk_edp_probe(). For now there is no easy way to select between the two.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: jerry: Add support for timing SPI flash speed
Simon Glass [Fri, 22 Jan 2016 02:45:18 +0000 (19:45 -0700)]
rockchip: jerry: Add support for timing SPI flash speed

Add the 'time' and 'sf test' commands so that we can test SPI flash
performance.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: spl: Support full-speed CPU in SPL
Simon Glass [Fri, 22 Jan 2016 02:45:17 +0000 (19:45 -0700)]
rockchip: spl: Support full-speed CPU in SPL

Add a feature which speeds up the CPU to full speed in SPL to minimise
boot time. This is only supported for certain boards (at present only
jerry).

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: rk3288: pinctrl: Fix HDMI pinctrl
Simon Glass [Fri, 22 Jan 2016 02:45:16 +0000 (19:45 -0700)]
rockchip: rk3288: pinctrl: Fix HDMI pinctrl

Since the device tree does not specify the EDID pinctrl option for HDMI we
must set it manually. Fix the driver to handle this.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: rk3288: clock: Fix various minor errors
Simon Glass [Fri, 22 Jan 2016 02:45:15 +0000 (19:45 -0700)]
rockchip: rk3288: clock: Fix various minor errors

Fix a number of small errors which were found in reviewing the clock code.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: jerry: Fix the SDRAM timing
Simon Glass [Fri, 22 Jan 2016 02:45:14 +0000 (19:45 -0700)]
rockchip: jerry: Fix the SDRAM timing

There is a minor error in the SDRAM timing. It does not seem to affect
anything so far. Fix it just in case.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: spl: Drop MMC support code when not needed
Simon Glass [Fri, 22 Jan 2016 02:45:13 +0000 (19:45 -0700)]
rockchip: spl: Drop MMC support code when not needed

When the board does not use MMC SPL this code is a waste of space. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: Tidy up the register-access macros
Simon Glass [Fri, 22 Jan 2016 02:45:12 +0000 (19:45 -0700)]
rockchip: Tidy up the register-access macros

These work reasonable well, but there are a few errors:

- Brackets should be used to avoid unexpected side-effects
- When setting bits, the corresponding upper 16 bits should be set also

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: sdram: Use syscon_get_first_range() where possible
Simon Glass [Fri, 22 Jan 2016 02:45:11 +0000 (19:45 -0700)]
rockchip: sdram: Use syscon_get_first_range() where possible

This is a shortcut to obtaining a register address. Use it where possible, to
simplify the code.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: sdram: Tidy up a few comments
Simon Glass [Fri, 22 Jan 2016 02:45:10 +0000 (19:45 -0700)]
rockchip: sdram: Tidy up a few comments

Fix spaces in two comments in this file.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: config: Enable the 'gpio' command
Simon Glass [Fri, 22 Jan 2016 02:45:09 +0000 (19:45 -0700)]
rockchip: config: Enable the 'gpio' command

Now that we have a pretty good GPIO driver, enable the 'gpio' command on all
rockchip boards.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: Add a script to parse datasheets
Simon Glass [Fri, 22 Jan 2016 02:45:08 +0000 (19:45 -0700)]
rockchip: Add a script to parse datasheets

This script has proved useful for parsing datasheets and creating register
shift/mask values for use in header files. Include it in case it is useful
for others.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: Add a simple 'clock' command
Simon Glass [Fri, 22 Jan 2016 02:45:07 +0000 (19:45 -0700)]
rockchip: Add a simple 'clock' command

Add a command that displays the PLLs and their current rate.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: Don't skip low-level init
Simon Glass [Fri, 22 Jan 2016 02:45:06 +0000 (19:45 -0700)]
rockchip: Don't skip low-level init

At present the low-level init is skipped on rockchip. Among other things
this means that the instruction cache is left disabled. Fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: video: Add a video-output driver
Simon Glass [Fri, 22 Jan 2016 02:45:05 +0000 (19:45 -0700)]
rockchip: video: Add a video-output driver

Some rockchip SoCs include video output (VOP). Add a driver to support this.
It can output via a display driver (UCLASS_DISPLAY) and currently HDMI and
eDP are supported.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: video: Add a display driver for rockchip eDP
Simon Glass [Fri, 22 Jan 2016 02:45:04 +0000 (19:45 -0700)]
rockchip: video: Add a display driver for rockchip eDP

Some Rockchip SoCs support embedded DisplayPort output. Add a display driver
for this so that these displays can be used on supported boards.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: video: Add a display driver for rockchip HDMI
Simon Glass [Fri, 22 Jan 2016 02:45:03 +0000 (19:45 -0700)]
rockchip: video: Add a display driver for rockchip HDMI

Some Rockchip SoCs support HDMI output. Add a display driver for this so
that these displays can be used on supported boards.

Unfortunately this driver is not fully functional. It cannot reliably read
EDID information over HDMI. This seems to be due to the clocks being
incorrect - the I2C bus speed appears to be up to 100x slower than the
clock settings indicate. The root cause may be in the clock logic.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: clk: Add support for clocks needed by the displays
Simon Glass [Fri, 22 Jan 2016 02:45:02 +0000 (19:45 -0700)]
rockchip: clk: Add support for clocks needed by the displays

The displays need to use NPLL and also select some new peripheral clocks.
Add support for these to the clock driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: Rename the CRU_MODE_CON fields
Simon Glass [Fri, 22 Jan 2016 02:45:01 +0000 (19:45 -0700)]
rockchip: Rename the CRU_MODE_CON fields

These should match the datasheet naming. Adjust them.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agodm: video: Repurpose the 'displayport' uclass to 'display'
Simon Glass [Fri, 22 Jan 2016 02:45:00 +0000 (19:45 -0700)]
dm: video: Repurpose the 'displayport' uclass to 'display'

The current DisplayPort uclass is too specific. The operations it provides
are shared with other types of output devices, such as HDMI and LVDS LCD
displays.

Generalise the uclass so that it can be used with these devices as well.
Adjust the uclass to handle the EDID reading and conversion to
display_timing internally.

Also update nyan-big which is affected by this.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agovideo: panel: Add a simple panel driver
Simon Glass [Fri, 22 Jan 2016 02:44:59 +0000 (19:44 -0700)]
video: panel: Add a simple panel driver

Most panels are very simple - they just have a power supply and a backlight.
Add a driver which supports this and implements the enable_backlight()
method.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agodm: panel: Add a panel uclass
Simon Glass [Fri, 22 Jan 2016 02:44:58 +0000 (19:44 -0700)]
dm: panel: Add a panel uclass

LCD panels can usefully be modelled as their own uclass. They can be probed
(which powers them up ready for use). If they have a backlight, this can be
enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agodm: backlight: Add a driver for a PWM backlight
Simon Glass [Fri, 22 Jan 2016 02:44:57 +0000 (19:44 -0700)]
dm: backlight: Add a driver for a PWM backlight

Many backlights need to use a PWM to control the brightness. Add a driver
for this. It understands the standard device tree binding.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agodm: backlight: Add a backlight uclass
Simon Glass [Fri, 22 Jan 2016 02:44:56 +0000 (19:44 -0700)]
dm: backlight: Add a backlight uclass

LCD panels normally have a backlight which can be controlled to illuminate
the LCD contents. Add a uclass to support this. Initially it only has a
method to enable the backlight.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agopwm: rockchip: Add a PWM driver for Rockchip SoCs
Simon Glass [Fri, 22 Jan 2016 02:44:55 +0000 (19:44 -0700)]
pwm: rockchip: Add a PWM driver for Rockchip SoCs

Add a simple driver which implements the standard PWM uclass interface.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agodm: pwm: Add a PWM uclass
Simon Glass [Fri, 22 Jan 2016 02:44:54 +0000 (19:44 -0700)]
dm: pwm: Add a PWM uclass

Add a uclass that supports Pulse Width Modulation (PWM) devices. It
provides methods to enable/disable and configure the device.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agovideo: bridge: Allow GPIOs to be optional
Simon Glass [Fri, 22 Jan 2016 02:44:53 +0000 (19:44 -0700)]
video: bridge: Allow GPIOs to be optional

Some video bridges will not have GPIOs to control reset, etc. Allow these
to be optional.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agovideo: Add a function to control cache flushing
Simon Glass [Fri, 22 Jan 2016 02:44:52 +0000 (19:44 -0700)]
video: Add a function to control cache flushing

Allow the cache-flushing function of a video device to be controlled.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agovideo: Name consoles by their number
Simon Glass [Fri, 22 Jan 2016 02:44:51 +0000 (19:44 -0700)]
video: Name consoles by their number

We must use the console name in the 'stdout' variable to select the one
we want. At present the name is formed from the driver name with a suffix
indicating the rotation value.

It seems better to name them sequentially since this can be controlled by
driver order. So adjust the code to use 'vidconsole' for the first,
'vidconsole1' for the second, etc.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agogpio: Warn about invalid GPIOs used with the 'gpio' command
Simon Glass [Fri, 22 Jan 2016 02:44:50 +0000 (19:44 -0700)]
gpio: Warn about invalid GPIOs used with the 'gpio' command

At present there is no indication that an invalid GPIO is used except that
the GPIO status is not displayed. Make the error more explicit to avoid
confusion.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agostdio: Correct a build error with driver model
Simon Glass [Fri, 22 Jan 2016 02:44:49 +0000 (19:44 -0700)]
stdio: Correct a build error with driver model

When driver model is used for video but not for the keyboard, a compiler
warnings is produced. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: jerry: Enable the Chrome OS EC
Simon Glass [Fri, 22 Jan 2016 02:44:13 +0000 (19:44 -0700)]
rockchip: jerry: Enable the Chrome OS EC

Turn on the EC and enable the keyboard.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: spi: Remove the explicit pinctrl setting
Simon Glass [Fri, 22 Jan 2016 02:44:12 +0000 (19:44 -0700)]
rockchip: spi: Remove the explicit pinctrl setting

The correct pinctrl is handled automatically so we don't need to do it in
the driver. The exception is when we want to use a different chip select
(other than 0). But this isn't used at present.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: spi: Correct chip-enable code
Simon Glass [Fri, 22 Jan 2016 02:44:11 +0000 (19:44 -0700)]
rockchip: spi: Correct chip-enable code

At present there is an incorrect call to rkspi_enable_chip(). It should
be disabling the chip, not enabling it. Correct this and ensure that the
chip is disabled when releasing the bus.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: spi: Implement the delays
Simon Glass [Fri, 22 Jan 2016 02:44:10 +0000 (19:44 -0700)]
rockchip: spi: Implement the delays

Some devices need delays before and after activiation. Implement these
features in the SPI driver so that we will be able to enable the Chrome
OS EC.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: gpio: Implement the get_function() method
Simon Glass [Fri, 22 Jan 2016 02:44:09 +0000 (19:44 -0700)]
rockchip: gpio: Implement the get_function() method

Provide this method so that 'gpio status' works fully. It now shows
whether a pin is used for input, output or some other function.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: gpio: Read the GPIO value correctly
Simon Glass [Fri, 22 Jan 2016 02:44:08 +0000 (19:44 -0700)]
rockchip: gpio: Read the GPIO value correctly

This function should return 0 or 1, not a mask. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: pinctrl: Implement the get_gpio_mux() method
Simon Glass [Fri, 22 Jan 2016 02:44:07 +0000 (19:44 -0700)]
rockchip: pinctrl: Implement the get_gpio_mux() method

Implement this so that the GPIO command will be able to report whether a
GPIO is used for input or output.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: pinctrl: Reduce the size for SPL
Simon Glass [Fri, 22 Jan 2016 02:44:06 +0000 (19:44 -0700)]
rockchip: pinctrl: Reduce the size for SPL

This file has many features that are not needed by SPL. Use #ifdef to
remove the unused features and reduce the code size.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: clk: Make rkclk_get_clk() SoC-specific
Simon Glass [Fri, 22 Jan 2016 02:44:05 +0000 (19:44 -0700)]
rockchip: clk: Make rkclk_get_clk() SoC-specific

The current method assumes that clocks are numbered from 0 and we can
determine a clock by its number. It is safer to use an ID in the clock's
platform data to avoid the situation where another clock is bound before
the one we expect.

Move the existing code into rk3036 since it still works there. Add a new
implementation for rk3288.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: spi: Correct the bus init code
Simon Glass [Fri, 22 Jan 2016 02:44:04 +0000 (19:44 -0700)]
rockchip: spi: Correct the bus init code

Two of the init values are created locally so cannot be out of range.
The masking is unnecessary and in one case is incorrect. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: spi: Remember the last speed to avoid re-setting it
Simon Glass [Fri, 22 Jan 2016 02:44:03 +0000 (19:44 -0700)]
rockchip: spi: Remember the last speed to avoid re-setting it

Rather than changing the clock to the same value on every transaction,
remember the last value and don't adjust the clock unless it is necessary.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: reset: Use the rk_clr/setreg() interface
Simon Glass [Fri, 22 Jan 2016 02:44:02 +0000 (19:44 -0700)]
rockchip: reset: Use the rk_clr/setreg() interface

Use this function in preference to the macro.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: sdram: Use the rk_clr/setreg() interface
Simon Glass [Fri, 22 Jan 2016 02:44:01 +0000 (19:44 -0700)]
rockchip: sdram: Use the rk_clr/setreg() interface

Use this function in preference to the macro.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agodm: clk: Add a simple version of clk_get_by_index()
Simon Glass [Fri, 22 Jan 2016 02:44:00 +0000 (19:44 -0700)]
dm: clk: Add a simple version of clk_get_by_index()

This function adds quite a bit of code to SPL and we probably don't need
all the features in SPL. Add a simple version (for SPL only) to save space.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agodm: power: Allow regulators to not implement all operations
Simon Glass [Fri, 22 Jan 2016 02:43:59 +0000 (19:43 -0700)]
dm: power: Allow regulators to not implement all operations

Some regulators will not implement any operations (e.g. fixed regulators).
This is not an error, so allow the autoset process to continue when one
of these regulators is found.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agodm: power: Tidy up debugging output and return values
Simon Glass [Fri, 22 Jan 2016 02:43:58 +0000 (19:43 -0700)]
dm: power: Tidy up debugging output and return values

The currect PMIC debugging is a little confusing. Adjust it so that it is
clear whether the operation succeeded or failed. Also, avoid creating a new
error return value when a perfectly good one is already available.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agodm: core: Export uclass_find_device_by_of_offset()
Simon Glass [Fri, 22 Jan 2016 02:43:57 +0000 (19:43 -0700)]
dm: core: Export uclass_find_device_by_of_offset()

It is sometimes useful to be able to find a device before probing it,
perhaps to set up some platform data for it. Allow finding by of_offset
also.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agodm: pinctrl: Add a way for a GPIO driver to obtain a pin function
Simon Glass [Fri, 22 Jan 2016 02:43:56 +0000 (19:43 -0700)]
dm: pinctrl: Add a way for a GPIO driver to obtain a pin function

GPIO drivers want to be able to show if a pin is enabled for input, output,
or is being used by another function. Some drivers can easily find this
and the code is included in the driver. For some SoCs this is more complex.
Conceptually this should be handled by pinctrl rather than GPIO. Most
pinctrl drivers will have this feature anyway.

Add a method by which a GPIO driver can obtain the pin mux value given a
GPIO reference. This avoids repeating the code in two places.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agodm: power: Allow regulators to be omitted from SPL
Simon Glass [Fri, 22 Jan 2016 02:43:55 +0000 (19:43 -0700)]
dm: power: Allow regulators to be omitted from SPL

For some boards the pmic interface is useful but the regulator interface
(which comes with it) is too large. Allow them to be separated such that
SPL can decide which it needs.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agospi: Correct device tree usage in spi_flash_decode_fdt()
Simon Glass [Fri, 22 Jan 2016 02:43:54 +0000 (19:43 -0700)]
spi: Correct device tree usage in spi_flash_decode_fdt()

This function currently searches the entire device tree for a node that
it thinks is relevant. But the node is known and is passed in. Correct the
code and enable it only with driver model, since only driver-model boards
will use it.

This avoids bringing in a large number of strings from fdtdec.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agodm: i2c: Allow muxes to be enabled for SPL separately
Simon Glass [Fri, 22 Jan 2016 02:43:53 +0000 (19:43 -0700)]
dm: i2c: Allow muxes to be enabled for SPL separately

Since I2C muxes are seldom needed in SPL, and the code for this increases
the size somewhat, add a separate option to enable I2C muxes for SPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agocros_ec: Disable the Chrome OS EC in SPL
Simon Glass [Fri, 22 Jan 2016 02:43:52 +0000 (19:43 -0700)]
cros_ec: Disable the Chrome OS EC in SPL

This is not used in SPL so don't allow it to be built there, even if I2C
is enabled in SPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agogpio: Allow 's' as an abbreviation for 'status'
Simon Glass [Fri, 22 Jan 2016 02:43:51 +0000 (19:43 -0700)]
gpio: Allow 's' as an abbreviation for 'status'

The 'gpio' command allows abbreviations for most subcommands. Allow them
for 'status' also.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: jerry: Drop unused options
Simon Glass [Fri, 22 Jan 2016 02:43:50 +0000 (19:43 -0700)]
rockchip: jerry: Drop unused options

To reduce the SPL image size, drop the LED features. Jerry does not have
an LED and we can leave out GPIO support also.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: Disable simple-bus in SPL for firefly-rk3288, jerry
Simon Glass [Fri, 22 Jan 2016 02:43:49 +0000 (19:43 -0700)]
rockchip: Disable simple-bus in SPL for firefly-rk3288, jerry

This is not needed for booting, so drop it from SPL to save about 300 bytes.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: jerry: Enable the RK808 PMIC and regulator
Simon Glass [Fri, 22 Jan 2016 02:43:48 +0000 (19:43 -0700)]
rockchip: jerry: Enable the RK808 PMIC and regulator

Enable this PMIC and regulator, which is used on jerry.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: Move firefly and jerry to use the full pinctrl
Simon Glass [Fri, 22 Jan 2016 02:43:47 +0000 (19:43 -0700)]
rockchip: Move firefly and jerry to use the full pinctrl

Use the full pinctrl driver in U-Boot proper.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: pinctrl: Add a full pinctrl driver
Simon Glass [Fri, 22 Jan 2016 02:43:46 +0000 (19:43 -0700)]
rockchip: pinctrl: Add a full pinctrl driver

We can make use of the device tree to configure pinctrl settings. Add this
support for the driver so we can use it in U-Boot proper.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: mmc: Update the driver to use the new clock ID
Simon Glass [Fri, 22 Jan 2016 02:43:45 +0000 (19:43 -0700)]
rockchip: mmc: Update the driver to use the new clock ID

We can use the new clk_get_by_index() function to get the correct clock.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: spi: Avoid setting the pinctrl twice
Simon Glass [Fri, 22 Jan 2016 02:43:44 +0000 (19:43 -0700)]
rockchip: spi: Avoid setting the pinctrl twice

If full pinctrl is enabled we don't need to manually set the pinctrl in the
driver. It will happen automatically. Adjust the code to suit - we will
still use manual mode in SPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: spi: Update the driver to use the new clock ID
Simon Glass [Fri, 22 Jan 2016 02:43:43 +0000 (19:43 -0700)]
rockchip: spi: Update the driver to use the new clock ID

We can use the new clk_get_by_index() function to get the correct clock.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: i2c: Update the driver to use the new clock ID
Simon Glass [Fri, 22 Jan 2016 02:43:42 +0000 (19:43 -0700)]
rockchip: i2c: Update the driver to use the new clock ID

We can use the new clk_get_by_index() function to get the correct clock.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: clock: Add a function to find a clock by ID
Simon Glass [Fri, 22 Jan 2016 02:43:41 +0000 (19:43 -0700)]
rockchip: clock: Add a function to find a clock by ID

The current approach of using uclass_get_device() is error-prone. Another
clock (for example a fixed-clock) may cause it to break. Add a function that
does a proper search.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agorockchip: clk: Add a function to get a peripheral clock rate
Simon Glass [Fri, 22 Jan 2016 02:43:40 +0000 (19:43 -0700)]
rockchip: clk: Add a function to get a peripheral clock rate

It is useful to be able to read the rate of a peripheral clock. Add a
handler for that.

Signed-off-by: Simon Glass <sjg@chromium.org>