radv/amdgpu: Use STACK_ARRAY for IB array to reduce stack usage.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22668>

radv/amdgpu: Pass preambles to get_bo_list.

Instead of allocating an array for them.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22668>

radv/amdgpu: Split radv_amdgpu_get_bo_list to smaller functions.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22668>

radv/amdgpu: Remove unused extra BO array.

Not needed anymore.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22668>

zink: do not open-code memcpy

There's a lot of optimized memcpy implementations out there, let's use
them instead of manually copying.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23027>

zink: clean up tcs_vertices_out_word handling

At this point, we already have the index of the declaration itself in
the tcs_vertices_out_word variable, so we only need to add the offset
from the start of the exec_modes buffer.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23027>

zink: fix bad indent

This was indented too much

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23027>

nir/inline_uniforms: Handle num_components > 1

Vulkan UBO loads can have a buffer_index source with more than one component.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23016>

gallium/nir: Handle unified atomics in nir_to_tgsi_info

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23016>

radv: Use common GetPhysicalDeviceFeatures2

This is a big delete-the-code win. Tested by diff'ing vulkaninfo output
before/after the patch and confirming no changes (other than the driverInfo git
sha and the pipelineCacheUUID).

Note: removes handling for VkDeviceMemoryOverallocationCreateInfoAMD. This was
surely added as a mistake.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22999>

radv: Constify radv_device_supports_etc

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22999>

pvr: fixup stack overflow in {start,end}_sub_cmd

Signed-off-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22955>

zink: add some ci flakes

roundup from recent ci jobs

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23021>

amd/drm-shim: add navi10

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22989>

amd/drm-shim: add vega10

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22989>

amd/drm-shim: add polaris10

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22989>

amd/drm-shim: move device list to external file

This is already pretty large.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22989>

zink: don't create invalid inputs in `zink_create_quads_emulation_gs`

The helper was creating input locations for some builtin bariables.

This caused validation errors in zink because those builtins can't be
used as input.

Fixes: e2220ee55e4 ("zink: filled quad emulation gs generation function")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22871>

nir: make var arrays large enough in `nir_create_passthrough_gs`

Because each location has 4 possible different values for location_frac
the arrays need to br 4x the size.

Fixes: d0342e28 ("nir: Add helper to create passthrough GS shader")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22871>

zink: handle interface blocks in `copy_vars`

Fixes: edaf49160e5 ("zink: fix array copying in pv lowering")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22871>

nir: handle interface blocks in `copy_vars`

Fixes: 99121c9b779 ("nir/gs: fix array type copying for passthrough gs")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22871>

zink: don't replace non generated gs

Zink replaced the gs emulation shader when the primitive type changes,
however it didn't check whether the gs being replaced was generated.

Fixes: eedbf9046e7 ("zink: handle switching between primitives")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22871>

nir: don't create invalid inputs in `nir_create_passthrough_gs`

The helper was creating input locations for some builtin bariables.

This caused validation errors in zink because those builtins can't be
used as input.

Fixes: d0342e28b32 ("nir: Add helper to create passthrough GS shader")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22871>

nir: use `nir_variable_clone` in `nir_create_passthrough_gs`

Some stream out properties where not being copied causing problems in
zink.

Use the appropiate helper instead of copying fields by hand.

Fixes: d0342e28b32 ("nir: Add helper to create passthrough GS shader")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22871>

pvr: Remove unneeded assert in pvr_get_hw_clear_color()

Fixes: dEQP-VK.synchronization.op.single_queue.fence
  .write_draw_read_image_compute.image_128x128_r8_unorm

Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reported-by: James Glanville <james.glanville@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22868>

pvr: Fix off-by-one in pvr_cmd_buffer_upload_desc_set_table() assert

Fixes: dEQP-VK.pipeline.monolithic.dynamic_offset.compute.multiset
  .uniform_buffer.numcmdbuffers_1.sameorder.numdescriptorsetbindings_1
  .numdynamicbindings_2.numnondynamicbindings_1

Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reported-by: James Glanville <james.glanville@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22868>

pvr: Correctly compile graphics pipelines without a fragment shader

Fixes: dEQP-VK.pipeline.monolithic.stencil.nocolor.format.s8_uint
  .states.fail_keep.pass_keep.dfail_repl.comp_greater_or_equal

Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reported-by: James Glanville <james.glanville@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22868>

pvr: Initialize aspect_mask when creating buffer views

Fixes random aborts in CSB handling.

Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reported-by: James Glanville <james.glanville@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22868>

pvr: Actually check for depth load when setting up load op constants

Fixes: Assorted tests in dEQP-VK.draw.renderpass.*

Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reported-by: James Glanville <james.glanville@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22868>

radv: stop using the pipeline for determining the null export workaround

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22981>

radv: remove unused pipeline param in radv_generate_ps_epilog_key()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22981>

radv: reset the emitted PS epilog when a new fragment shader is bound

When a new fragment shader is bound, the PS epilog needs to be
re-emitted, and this allows us to avoid tracking if the pipeline is
dirty.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22981>

panvk: drop path from panvk_physical_device struct

Unnecessary. Only produces warning:
```
../src/panfrost/vulkan/panvk_device.c:437:4: warning: 'strncpy' specified bound 20 equals destination size [-Wstringop-truncation]
  437 |    strncpy(device->path, path, ARRAY_SIZE(device->path));
      |    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
```

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22880>

radv/ci: Test ray tracing pipelines

Since we expose them for a few games by default now, it would make sense
to have test coverage for them.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21638>

radv: advertise VK_EXT_tooling_info

This small extension just returns active tools running like RGP.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22954>

broadcom/compiler: use unified atomics

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22939>

radv: stop compiling a noop FS when the application doesn't provide a FS

This is unnecessary because the hardware doesn't execute a FS when it
has no effect and it's possible to execute pre-rasterization stages
without a FS.

This might improve depth-only pass performance very slightly because
the number of packets emitted is reduced a bit.

No fossils-db changes.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22848>

radv: allow to determine NGG settings with a NULL fragment shader

This shouldn't change anything because a noop FS doesn't read any
inputs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22848>

radv: rework the checks for implicit exports with GPL

No logical changes but this allows us to distinguish between noop FS
and unknown FS with GPL.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22848>

radv: handle NULL fragment shaders when creating graphics pipelines

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22848>

radv: handle NULL fragment shaders when recording cmdbuf

This will be useful for shader objects and also because creating and
emitting a noop FS is useless, the hardware doesn't execute it.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22848>

radv: implement dynamic sample locations enable

VK_EXT_sample_locations is only supported on < GFX10 due to some weird
issues on recent GPUs. extendedDynamicState3SampleLocationsEnable is
only enabled on GFX6-GFX9 for the same reason.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22947>

glx: fix build with APPLEGL

fixes: 1eab7e69e2ba84244f551f6901f4307a687a9504

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8885
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22621>

radeonsi: be able to use aco compiler for mono ps

Need to set AMD_DEBUG=useaco environment variable.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>

radeonsi: fixup sampler desc for tg4 in nir

For ACO which won't do this for us. But we still can't
remove the same code in llvm because non-uniform sampler
is keept as index in nir.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>

ac/llvm,radeonsi: enable lower_array_layer_round_even

ACO need this to be done in nir. Remove the llvm round code
because both radv and radeonsi do this in nir for both aco
and llvm.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>

radeonsi: clamp shadow texture reference in nir for aco

This is ported from the LLVM ac_shader_abi->clamp_shadow_reference
code.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>

radeonsi: pass use_aco to ac_nir_lower_ps

For dual source blend code emition in aco.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>

radeonsi: adjust ps args for aco

aco need explicite args including PS arg compaction and
scratch_offset.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>

radeonsi: resolve aco scratch addr symbols

Used for scratch buffer operation and reg spill when aco.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>

radeonsi: add symbols to si_shader_binary

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>

radeonsi: add initial aco compile code

Only for monolithic PS.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>

radeonsi: lower non uniform texture access when aco

aco need all resource have been lowered to descriptor.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>

radeonsi: add has_non_uniform_tex_access shader info

Can be used to skip nir_lower_non_uniform_access pass.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>

radeonsi: lower vector const to scalar at last for aco

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>

radeonsi: lower some 64bit ops aco does not support

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>

ac/llvm,radeonsi: lower nir_fpow for aco and llvm

aco does not implement fpow, need nir to lower it
first. llvm will do by itself in the same way, so
we always lower fpow in nir now.

Remove the llvm fpow implementation that has special
handling for the muliplication. It's not used any
more and does not match GLSL spec as fpow(0,0)=NaN
but here we get 0.

There's some pixel changes for gl-radeonsi-stoney:
  ror-default 2 (no tolerance), 0 (1% tol.)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>

ac/llvm,radeonsi: lower some pack/unpack ops not supported by aco

aco only support the split vertion of these instructions.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>

ac/llvm,radeonsi: lower ineg in nir

aco does not implement it.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>

ac/llvm,radeonsi: lower txf offset in nir

aco will complain if txf has offset. Not if other
texture ops.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>

ac/llvm,radeonsi: lower fsin/fcos in nir

ACO only support nir_fsin/cos_amd.

There's some pixel changes for gl-radeonsi-stoney trace.
Different pixels:
  furmark  61 (no tolerance), 0 (1% tol.)
  gimark   93867 (no tolerance), 888 (1% tol.)
  tessmark 39 (no tolerance), 0 (1% tol.)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>

ac/llvm,radeonsi: lower idiv in nir

aco does not implement these idiv ops.

nir_lower_idiv is for idiv ops <= 32bit and ported from
llvm amdgpu, so llvm do the same.

nir_lower_divmod64 is for 64bit idiv ops.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>

tgsi_to_nir: call nir_lower_int64 when required

Use case: radeonsi will generate internal tgsi shader
with 64bit udiv instruction, and we want all 64bit udiv
to be lowered in nir by lower_int64_options.

For GLSL shaders, this is done in glsl to nir, so we do
the same for tgsi here.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>

radeonsi: remove ps vgpr index save when args init

They will be set by ac_get_fs_input_vgpr_cnt() later anyway.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>

radeonsi: support print raw shader binary

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>

radeonsi: support raw shader binary upload

Only monolithic shader.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>

ac/binary: pack prefech align code to a function

To be used by radeonsi raw shader binary.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>

radeonsi: add a raw shader binary type

It's the output of ACO compiler. To share the si_shader_binary
struct with ELF type:
  * add a type field to indicate RAW or ELF
  * rename elf_buffer/size to code_buffer/size

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>

radeonsi: init spi ps input shader config when aco

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>

radeonsi: pack spi ps input fixup to a function

To be shared with ACO spi ps input construction.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>

radeonsi: add shader info uses_sampleid

Used by ACO to set spi_ps_intput.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>

radeonsi: add shader info for frag coord and sample pos read

To construct spi_ps_input when ACO compilation.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>

radeonsi: add use_aco field for struct si_shader

We are going to use aco for monolithic ps first.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>

radeonsi: add aco debug option

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>

meson: build radeonsi with aco

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22573>

ci/skqp: handle all warnings printed with clang >= 14

Useful for the https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21977

Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22808>

radv: Stop running constant folding during ray query lowering

Now that committed is an intrinsic index, there is no need for constant
folding.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22963>

nir: Make rq_load committed src an index

committed has to be a constant so there is no need to have a src and
depend on constant folding to remove the i2b.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22963>

gtest: Update to 1.13.0

Fix msan issue found with recent GCC on Debian 12.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8915

Acked-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22814>

util/tests: adjust for new gtest

GTest deprecated the GTEST_ARRAY_SIZE_ macro.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22814>

nv50: Fix return type of nv50_blit_is_array

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22997>

nvc0: Free blitter->vp

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22997>

nv50,nvc0: Free nir from blitter fp shader

Fixes: d11145e837 ("nv50,nvc0: Use nir in nv50_blitter_make_fp")
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22997>

dxil: Use unified atomics

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22993>

microsoft/compiler: Back-propagate type requirement information

For ALU ops where input types are known, we can store that info on
the input sources. This can be used to produce the correct overloads
of load instructions that don't immediately need to be followed by
bitcasts, or similarly to produce a constant value which can be directly
consumed by the relevant instruction without needing a bitcast.

Similarly for values that will be stored in an output, we know type
information. And using that info, we can use more-correct information
for phis instead of forcing all phi sources to be bitcast to int just
to be bitcast back to float on the other side for an alu or an output
store.

One missing piece is SSBO stores, where we can support int or float.
If the input is coming from a phi, we don't influence the phi's type,
so it'll be int, even though the incoming sources might've been float.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22972>

microsoft/compiler: Duplicate some SSA values to simplify SSA typing

For each phi src, ensure that it's only used as a phi src.
This lets us give each phi their own unique types without worrying
about them stomping on each other. Also scalarize phis.

For each constant, ensure that it's only used once. The DXIL backend
will already dedupe these consts within the module, but this lets a
single load_const have multiple types depending on how it's used.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22972>

microsoft/compiler: Remove alu type info from store_dest()

We pass in a *typed* value, we don't need to pass in additional
type info. That's just more opportunities to get it wrong.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22972>

ac/llvm: rewrite and unify how GLC, DLC, SLC are set

Use ACCESS_* flags in call sites instead of GLC/DLC/SLC.

ACCESS_* flags are extended to describe other aspects of memory instructions
like load/store/atomic/smem.

Then add a function that converts the access flags to GLC, DLC, SLC.

The new functions are also usable by ACO.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22770>

ac/llvm: don't treat ACCESS_NON_READABLE as ACCESS_COHERENT

... and expect it to behave like ACCESS_NON_TEMPORAL.
Handling ACCESS_NON_TEMPORAL is sufficient.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22770>

aco: don't treat ACCESS_NON_READABLE as ACCESS_COHERENT

... and expect it to behave like ACCESS_NON_TEMPORAL.
Handling ACCESS_NON_TEMPORAL is sufficient.

This was copied from ac_nir_to_llvm.c.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22770>

intel: Secondary CB print primary CB's renderpass

Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22723>

intel: batch consecutive dispatches into implicit renderpasses

Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22723>

intel: refactor INTEL_MEASURE pointer dumping

Refactor framebuffer to renderpass to mirror previous INTEL_MEASURE
changes.

We dump hashes/pointers for shaders and framebuffer/renderpass.
Reduce from 64bit to 32bit pointers. We don't benefit from the
extra precision and reduced output size is convenient.

Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22723>

anv: re-enable RT data in INTEL_MEASURE

Per-RenderTarget analysis was removed from anv's INTEL_MEASURE
previously, probably after switching to dynamic rendering model.
Restore capability by tracking count of beginRenderPass calls.

Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22723>

anv: fix INTEL_MEASURE on MTL

Ensure counter buffer is coherent. Required for MTL which changes
coherence policy.

Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22723>

nir/validate: Handle unified atomics

nir_validate checks that the format of an atomic (if specified) is compatible
with the atomic operation. For example, we can't fadd R64_UINT texels. The logic
can't be extended as-is to unified atomics because it's split across different
switch cases for different atomic-op intrinsics. So we add our own validation
case, porting over the logic from the separate existing cases below.

(The redundant logic will be deleted once we delete legacy atomics.)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>

nir/opt_uniform_atomics: Handle unified atomics

This is the one place where using nir_atomic_op instead of nir_op directly is a
little annoying, since we need to translate between the two enums, but it's not
a big deal.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>

nir/lower_ssbo: Handle unified atomics

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>

nir/lower_io: Handle unified atomics

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>

nir/lower_task_shader: Handle unified atomics

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22914>