turnip: Use the common WSI wrappers

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>

radv: Use the common WSI wrappers

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>

anv: Use the common WSI wrappers

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>

vulkan/wsi: Add common wrappers for most entrypoints

For a long time, our Vulkan WSI code has acted as something of a layer.
The WSI code calls into various Vulkan entrypoints inside the driver to
create images, allocate memory, etc.  It then implements the API-facing
interface almost entirely.  The only thing the driver has to provide is
little wrappers that wrap around the WSI calls to expose them through
the API.

However, now that we have a common dispatch framework, we can implement
entrypoints directly in the WSI code.  As long as the driver uses
vk_instance, vk_physical_device, and vk_device, we can provide common
wrappers for the vast majority of entrypoints.  The only exceptions are
vkAcquireNextImage, vkQueuePresent, vkRegisterDeviceEventEXT, and
vkRegisterDisplayEventEXT because those may have to manually poke at
synchronization primitives.  We provide wrappers for vkAcquireNextImage
and vkQueuePresent because some drivers can use the default versions.

For now, we're intentionally avoiding any link-time dependencies between
WSI and the common code.  We only use VK_FROM_HANDLE and associated
inline helpers and vk_physical_device has a pointer to a wsi_device.
Eventually, we may tie the two together closer, but this lets us get 95%
of the way there without reworking the universe.

Acked-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>

vulkan/wsi: Add a dispatch table for WSI entrypoints

Acked-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>

meson: Add and use an idep for Vulkan WSI

Acked-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13234>

v3dv: enable VK_KHR_surface_protected_capabilities

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13298>

egl: implement EGL_EXT_present_opaque on wayland

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: James Jones <jajones@nvidia.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12373>

egl: sync eglext.h & egl.xml from Khronos

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12373>

ci/freedreno: Disable the minetest trace due to flaky shader code.

Fixes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4595
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13316>

iris: Tile cache flush for depth before fast clear

Instead of doing a tile cache flush after slow clears or when the clear
value changes, do it before every fast clear of a HIZ_CCS_WT surface.
This agrees with the Bspec.

Fixes: c85ea824bca ("iris: reduce redundant tile cache flushes")
Reviewed-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11539>

anv: Tile cache flush for depth before fast clear

Instead of doing a tile cache flush after slow clears, resolves, and
ambiguates, do it before fast clears of HIZ_CCS_WT surfaces. This agrees
with the Bspec.

Reviewed-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11539>

anv: Allow HIZ_CCS_WT with subpass self-dependencies

This unblocks later commits that aim to align the driver with the tile
cache flushing requirements in the Bspec.

Reviewed-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11539>

ir3/freedreno: handle non-uniform a1en instructions

Fixes vkd3d test "test_bindless_samplers_sm51"

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13311>

ir3/freedreno: handle non-uniform resinfo

We forgot to handle non-uniform resinfo case.

Fixes vkd3d test "test_bindless_bufinfo_sm51"

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13311>

aco/optimizer: Skip SDWA on v_lshlrev when unnecessary in apply_extract.

In the following cases:
- lower 16 bits are extracted and the shift amount is 16 or more
- lower 8 bits are extracted and the shift amount is 24 or more
the undesireable upper bits are already shifted out, and therefore
there is no need to add SDWA to the v_lshlrev instruction.

Fossil DB stats on Sienna Cichlid with NGGC on:

Totals from 58239 (45.27% of 128647) affected shaders:
CodeSize: 153498624 -> 153265616 (-0.15%); split: -0.15%, +0.00%
Instrs: 29636304 -> 29578064 (-0.20%); split: -0.20%, +0.00%
Latency: 136931496 -> 136876379 (-0.04%); split: -0.04%, +0.00%
InvThroughput: 21134367 -> 21078861 (-0.26%); split: -0.26%, +0.00%
Copies: 2777550 -> 2777548 (-0.00%); split: -0.00%, +0.00%

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13121>

ac/nir/nggc: Write undef to variables in non-repacked ES threads.

This helps the compiler generate a little bit more efficient code.

Fossil DB stats on Sienna Cichlid with NGGC on:

Totals from 4659 (3.62% of 128647) affected shaders:
CodeSize: 7468320 -> 7404484 (-0.85%); split: -0.88%, +0.03%
Instrs: 1423425 -> 1407454 (-1.12%); split: -1.16%, +0.03%
Latency: 5250593 -> 5226163 (-0.47%); split: -0.47%, +0.00%
InvThroughput: 739848 -> 733373 (-0.88%); split: -0.90%, +0.02%
Copies: 200139 -> 190307 (-4.91%); split: -5.13%, +0.22%
Branches: 87925 -> 85998 (-2.19%)

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13121>

ac/nir/cull: Accept NaN and +/- Inf in face culling.

When the determinant that we use for calculating triangle area
is NaN, it's not possible to decide the facing of the triangle.

This can happen when a coordinate of one of the triangle's vertices
is INFINITY. It's better to just accept these triangles in the shader
and let the PA deal with them.

Let's do the same for +/- Infinity too.
Though we haven't seen this yet, it may be troublesome as well.

Fixes: 651a3da1b59446a6e392321d1dbbc1891a0544a8
Closes: #5470
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13299>

amd/common: Add fallback for misreported clocks for RGP.

Traces with clock = 0 are totally useless due to RGP getting very
confused.

Cc: mesa-stable
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13301>

ir3: Fold ldc src immediates

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>

ir3: Fix handling cat6 immediates

We were treating them the same as regular cat2/cat3/cat4 immediates, but
that's not right because cat6 sources are only 8 bits.

Our bindless code was handling this before for bindless resources, and
it was disabled for most other things, so this was mostly harmless, but
fixing it will be necessary for handling ldc offsets.

In addition enable tests for this that were just commented out, and add
a custom test making sure that the immediate source is treated as
unsigned.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>

ir3: Fix check for immediate range

This would incorrectly allow both e.g. 0x2000 and 0xffffe000 to be
encoded as 0x2000.

Fixes: f0a1f3de278 ("freedreno/ir3: cp small negative integers too")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>

ir3/legalize: handle WAR for special regs

In particular many cat5/cat6 instructions read a1.x, and we need to add
a (ss) before any mova1 instruction afterwards, as the blob does.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>

ir3: Handle special regs in regmask

Use the same hack as post-RA scheduling.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>

ir3: Remove separate regmask.h

Inline it into its one user. There's no point in keeping it separate,
and in order to handle special registers it will have to become a bit
more intertwined with core ir3.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>

ir3: Always create barycentrics in the input block

Otherwise, when there are uses in multiple blocks the collect may not
dominate some of the uses.

This is a bugfix, but before it would've mattered only in weird
scenarios with interpolateAt*. When we start moving prefetch textures
into the block before the preamble it will start to matter more, because
it will need to read the barycentrics from a different block than the
bary.f instructions.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>

ir3: Make ir3_create_collect() take a block

There's no reason to make this any different from the other builders,
since it just creates a collect instruction, and in the next commit
we'll need to create a collect in the first block for prefetch textures.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>

ir3: Fix printing branch type

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>

nir/lower_ubo_vec4: Fix align_mul=8 special case

In order for the load to never straddle the load can't extend past 8
bytes, not 16. For example a vec2 load with align_mul = 8 and
align_offset = 4 can straddle.

Fixes assertion failures when we stop pushing UBOs in the preamble on
a6xx.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>

ir3/cp: Fix inlining 32->16 const into meta instructions

We shouldn't return early here, because we still need to actually do the
conversion. Fixes an infinite loop.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>

ir3/cp: Add missing const promotion check

We need to check the source type for moves when the destination type is
u16, just like the f16 check above.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13142>

radv: Do early and late tests for fast clears

We don't know some information regarding DCC image stores and therefore fast clears until we know the surface info.

We should work towards eliminating this, but the cases where this will hit on GFX10_3 is basically 0.

Finally fixes a perf regression in Doom Eternal.

Signed-off-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13283>

radv: implement VK_KHR_format_feature_flags2

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13194>

radv: switch to VK_FORMAT_FEATURE_2_XXX/VkFormatProperties3KHR

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13194>

radv: remove duplicated code about NGG passthrough determination

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13243>

radv: do not initialize is_ngg_passthrough for geometry shaders

Geometry shaders can't be NGG passthrough at all.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13243>

aco: cleanup setup_vs_output_info()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13243>

radv: stop gathering output GS info for vertex shaders

This has no effect.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13243>

radv: rename needs_multiview_view_index to uses_view_index

To avoid confusion with radv_pipeline_key::has_multiview_view_index.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13243>

radv: remove no-op about the view index in the shader info pass

The view index is always lowered to map the layer ID for fragment
shaders. This was never reached.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13243>

radv,aco: remove nir_intrinsic_load_layer_id

This was never used because the layer ID isn't a system value.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13243>

radv: Handle copying zero queries.

Looks like this is allowed.

Fixes: 8475a14302e ("radv: Implement pipeline statistics queries.")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12907>

docs/panfrost: Fix link to use rst syntax

Currently the link uses markdown syntax to direct users to IRC, switch
to IRC to render this correctly.

Fixes: e39929663bb ("docs/panfrost: Add web chat link")

Signed-Off by: Esme Xuan Lim <esmethedev@gmail.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13296>

freedreno: Add valgrind dependency.

Fix a build error.

In file included from ../src/util/u_queue.h:38,
                 from ../src/freedreno/drm/freedreno_ringbuffer.h:33,
                 from ../src/freedreno/ds/fd_pps_driver.h:13,
                 from ../src/freedreno/ds/fd_pps_driver.cc:7:
../src/util/simple_mtx.h:35:12: fatal error: valgrind.h: No such file or directory
   35 | #  include <valgrind.h>
      |            ^~~~~~~~~~~~

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13280>

vulkan: Generate defines for aliases of promoted enums

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13264>

vulkan: fix handling of aliases in enum members

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13264>

ir3/ra: Use killed sources in register eviction

Let's assume we have a vec2 collect instruction with killed sources that
are non-contiguous and the entire rest of the register file is blocked,
which can happen when our register target is very tight. It's impossible
to just insert move instructions to resolve this, but we can make space
by swapping one of the killed sources with the value next to the other,
assuming it's also scalar.

This commit implements that idea, preventing us from falling back to the
terrible shuffle-everything approach in this case.

total instructions in shared programs: 1566648 -> 1565117 (-0.10%)
instructions in affected programs: 13332 -> 11801 (-11.48%)
helped: 30
HURT: 5
helped stats (abs) min: 6 max: 535 x̄: 51.77 x̃: 25
helped stats (rel) min: 2.67% max: 33.63% x̄: 12.28% x̃: 9.58%
HURT stats (abs)   min: 1 max: 6 x̄: 4.40 x̃: 6
HURT stats (rel)   min: 0.18% max: 5.13% x̄: 2.41% x̃: 2.13%
95% mean confidence interval for instructions value: -75.05 -12.43
95% mean confidence interval for instructions %-change: -13.18% -7.18%
Instructions are helped.

total mov in shared programs: 77336 -> 76683 (-0.84%)
mov in affected programs: 2135 -> 1482 (-30.59%)
helped: 29
HURT: 5
helped stats (abs) min: 2 max: 227 x̄: 23.31 x̃: 10
helped stats (rel) min: 6.06% max: 72.73% x̄: 31.83% x̃: 30.00%
HURT stats (abs)   min: 2 max: 9 x̄: 4.60 x̃: 4
HURT stats (rel)   min: 14.29% max: 69.23% x̄: 34.00% x̃: 27.78%
95% mean confidence interval for mov value: -33.21 -5.20
95% mean confidence interval for mov %-change: -32.94% -11.35%
Mov are helped.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13143>

ir3/ra: Don't reset round-robin start for each block

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13143>

ir3: Initialize local size earlier

We need the local size in RA for occupancy calculations. Not
initializing these had the unfortunate consequence of
ir3_get_reg_independent_max_waves() returning 0 for compute shaders with
shared variables, disabling the register limiting logic.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13143>

anv: implement VK_KHR_format_feature_flags2

v2: fix SAMPLED_IMAGE_DEPTH_COMPARISON_BIT_KHR (Ivan)

v3: Fixup VK_FORMAT_FEATURE_2_STORAGE_IMAGE_BIT_KHR setting (Ivan)
    Add missing drm-modifiers/android bits (Lionel)

v4: Avoid duplicating get_ahw_buffer_format_properties() (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13198>

anv: start computing KHR_format_features2 flags for storage images

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13198>

anv: Flip around the way we reason about storage image lowering

There are roughly two cases when it comes to storage images.  In the
easy case, we have full hardware support and we can just emit a typed
read/write message in the shader and we're done.  In the more complex
cases, we may need to fall back to a typed read with a different format
or even to a raw (SSBO) read.

The hardware has always had basically full support for typed writes all
the way back to Ivy Bridge but typed reads have been harder to come by.
Starting with Skylake, we finally have enough that we at least have a
format of the right bit size but not necessarily the right format so we
can use a typed read but may still have to do an int->unorm or similar
cast in the shader.

Previously, in ANV, we treated lowered images as the default and write-
only as a special case that we can optimize.  This flips everything
around and treats the cases where we don't need to do any lowering as
the default "vanilla" case and treats the lowered case as special.
Importantly, this means that read-write access to surfaces where the
native format handles typed writes now use the same surface state as
write-only access and the only thing that uses the lowered surface state
is access read-write access with a format that doesn't support typed
reads.  This has the added benefit that now, if someone does a read
without specifying a format, we can default to the vanilla surface and
it will work as long as it's a format that supports typed reads.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13198>

intel/nir: allow unknown format in lowering of storage images

We're about to allow unknown format for specific formats in Anv.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13198>

anv: switch to use VkFormatFeatureFlags2KHR internally

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13198>

anv: Use the common wrapper for GetPhysicalDeviceFormatProperties

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13198>

vulkan: Generate #defines with every bit in a given bitfield

This is useful when trying to restrict from VkFoo2 to VkFoo.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13198>

vulkan: Generate flag #defines based on bitwidth

Instead of basing it on a fixed list, just generate #defines for every
bitfield that's 64-bit.  As part of this refactor, we rework things a
bit to record all bitfields and just not do anything with them if
they're not 64-bit.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13198>

radv: store the post-processed shader binary config to the cache

This will allow us to reduce the size of radv_shader_info which is
stored in the cache entry.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12992>

radv: move ac_shader_config to radv_shader_binary instead of legacy

This will allow us to avoid postprocessing binaries when they are
loaded from the shaders cache.

LLVM binaries already contain the shader config as part of the ELF,
so it's duplicated and increase the cache entry by 48 bytes. Though,
I don't think that should matter for LLVM.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12992>

ac/surface: Expose modifiers capable of DCC image stores first

These also have a higher compressed block size.

Signed-off-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13056>

radv: Respect max extent for modifiers

Some of our modifiers only support upto a certain range, expose this in ImageFormatProperties.

Signed-off-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13056>

radeonsi: Check if modifier supports the image extent

DCN only supports an extent < 4K on !64B && 128B.

Signed-off-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13056>

ac/surface: Add ac_modifier_max_extent

Currently, we aren't checking if the modifier supports the extent of the image.

DCN only works with !64B && 128B on extents < 4K.

Signed-off-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13056>

tu: Expose VK_KHR_shader_subgroup_extended_types

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13271>

ir3: Skip src size validation for cat1

They are already handled below, like cat6. The default rules won't work
for the READ_* macros once they have 16-bit sources.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13271>

ir3/lower_subgroups: Support 16-bit READ_* sources

With VK_EXT_shader_subgroup_extended_types these will have 16-bit
sources that need to be expanded to 32-bit (and then narrowed again).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13271>

anv: fix potential integer overflow

Description by Coverity:
"Unintentional integer overflow (OVERFLOW_BEFORE_WIDEN)
overflow_before_widen: Potentially overflowing expression 1 << b with type int
(32 bits, signed) is evaluated using 32-bit arithmetic, and then used in
a context that expects an expression of type VkAccessFlags2KHR (64 bits,
unsigned)"

CID: 1492745
CID: 1492748

Fixes: b996fa8efaa ("anv: implement VK_KHR_synchronization2")
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13284>

radv: use nir_ssa_undef() for unused image components in meta shaders

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12561>

radv: use get_global_ids() to compute coordinates in meta shaders

This was duplicated everywhere.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12561>

radv: remove few useless nir_channels() in meta shaders

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12561>

radv: remove useless coordinate computation in the compute clear path

Global Z is always 0.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12561>

radv: use nir_image_deref_{load,store} in the DCC retile compute path

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12561>

radv: advertise VK_KHR_maintenance4

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13193>

radv: implement vkGetDeviceImageSparseMemoryRequirementsKHR()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13193>

radv: implement vkGetDeviceImageMemoryRequirementsKHR()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13193>

radv: implement vkGetDeviceBufferMemoryRequirementsKHR()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13193>

radv: remove radv_pipeline::layout

From the VK_KHR_maintenance4 spec:
    "Allow the application to destroy their VkPipelineLayout object
     immediately after it was used to create another object. It is no
     longer necessary to keep its handle valid while the created object
     is in use."

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13193>

radeonsi: remove GS fast launch

It regresses the first snx test because it adds CPU overhead, and there is
no way to work around it. The average effect on viewperf is 0, meaning that
a few cases improve, while a few others regress.

Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13279>

crocus/gen5: add dirty flags for urb fences.

Fixes hang with some gtk4 apps.

Fixes: f3630548f1da ("crocus: initial gallium driver for Intel gfx 4-7")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13282>

crocus/gen5: reemit shaders on gen5 after new program cache bo.

This fixes gtk4 programs.

Fixes: f3630548f1da ("crocus: initial gallium driver for Intel gfx 4-7")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13281>

radeonsi: add back a workaround for DCC MSAA on gfx9 due to conformance issues

Fixes: 8b95f51ef1 - radeonsi: fix and enable full DCC with MSAA 2x on gfx9

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13256>

swrast: Fix another warning from gcc 11

This is similar change as commit f535ab59e26.

[2/4] Compiling C object src/mesa/libmesa_classic.a.p/swrast_s_texfilter.c.o
../src/mesa/swrast/s_texfilter.c: In function ‘sample_2d_footprint’:
../src/mesa/swrast/s_texfilter.c:1817:7: warning: ‘sample_2d_linear’ reading 16 bytes from a region of size 8 [-Wstringop-overread]
 1817 |       sample_2d_linear(ctx, samp, img, newCoord, rgba);
      |       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../src/mesa/swrast/s_texfilter.c:1817:7: note: referencing argument 4 of type ‘const GLfloat *’ {aka ‘const float *’}
../src/mesa/swrast/s_texfilter.c:1150:1: note: in a call to function ‘sample_2d_linear’
 1150 | sample_2d_linear(struct gl_context *ctx,
      | ^~~~~~~~~~~~~~~~

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13245>

venus: update to latest venus-protocol to include tracing

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13255>

venus: add atrace support

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13255>

android_stub: update platform headers to include atrace

1. Add tracing headers
2. Update to reflect relocated headers
3. Remove redundant apex/window.h

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13255>

radv/anv android: rename buffer usage camera mask

AHARDWAREBUFFER_USAGE_CAMERA_MASK enum is defined later and gets
included in the stub headers.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13255>

nir/lower_discard_or_demote: Fix metadata

Passes generally shouldn't use nir_metadata_all unless they don't change
the program in any significant way.  Some of these passes insert new
instructions so they should definitely not be preserving most of it.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13261>

zink: move glx@glx-multi-window-single-context to flakes

I got too excited when this passed on all the runners I guess

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13277>

isl: Use software programmable render compression format encoding

Instead of relying on hardcoded (legacy) encoding format, use software
programmable encoding for render compression format.

v2: (Nanley)
- Fix param mismatch
- Set RenderCompressionFormat unconditionally
- Fix commit message

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12686>

isl: Add helper to return render compression format encoding

v2:
- Fix typo (Marcin)
- Fix comment (Nanley)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12686>

intel/genxml: Add new bit fields Render Compression Format

Add RenderCompressionFormat bit field in 3DSTATE_DEPTH/STENCIL_BUFFER
and RENDER_SURFACE_STATE packet to use compression format encoding for
Unified Losless Compression.

v2: (Nanley)
- Drop default value.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12686>

microsoft/spirv_to_dxil: use dxil_nir_lower_bool_input pass

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13262>

gallium/d3d12: move d3d12_lower_bool_input to microsoft/compiler

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13262>

intel/isl: FXT1 support was removed on Gfx12.5

v2: cleanup (Jordan Justen)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13241>

tu: Implement VK_KHR_imageless_framebuffer

This is mostly a matter of auditing uses of
cmd->state.framebuffer and replacing every use of fb->attachments with
cmd->state.attachments. We already weren't using the attachments
anywhere outside of the render pass, so this is pretty straightforward.
We also don't have any use for anything in
VkFramebufferAttachmentImageInfo so we can just ignore it.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13228>

tu/clear_blit: Constify some image views

I wanted cmd->state.attachments to contain const pointers, since we
can't change the image view, but a few places were still not yet
constified.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13228>

radv: Enable NGG culling by default on GFX10.3, add nonggc debug flag.

This commit enables NGG culling on all GFX10.3 GPUs by default.

A new debug flag environment variable RADV_DEBUG=nonggc is added to
disable this feature on GPUs where it is enabled by default.

The previous perf test flag RADV_PERFTEST=nggc will not be needed on
GFX10.3 anymore but it can still be used to enable the feature on
GPUs where it isn't on by default.

Totals from 58239 (45.27% of 128647) affected shaders:
VGPRs: 1989752 -> 2049408 (+3.00%); split: -3.21%, +6.21%
SpillSGPRs: 675 -> 883 (+30.81%); split: -78.07%, +108.89%
CodeSize: 72205968 -> 153572764 (+112.69%)
LDS: 0 -> 227125248 (+inf%)
MaxWaves: 1614598 -> 1646934 (+2.00%); split: +3.08%, -1.08%
Instrs: 14202239 -> 29654042 (+108.80%)
Latency: 87986508 -> 136960419 (+55.66%); split: -0.23%, +55.89%
InvThroughput: 14444832 -> 21141875 (+46.36%); split: -0.01%, +46.37%
VClause: 340794 -> 493067 (+44.68%); split: -1.33%, +46.01%
SClause: 520983 -> 738636 (+41.78%); split: -0.25%, +42.03%
Copies: 775639 -> 2787382 (+259.37%)
Branches: 296911 -> 1225431 (+312.73%)
PreSGPRs: 1316896 -> 2057270 (+56.22%); split: -0.14%, +56.36%
PreVGPRs: 1473558 -> 1658432 (+12.55%); split: -1.44%, +13.99%

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13086>

vulkan/device-select: select correct default device for xcb apiVersion 1.0

In function fill_drm_device_info(), struct ext_pci_properties is filled only
if has_vulkan11 is true. But the data received from ext_pci_properties is used
without checking for has_vulkan11. Fixing this by setting
drm_device->has_bus_info also if has_vulkan11 is true.

This fix will help in case of nonidentical gpu being used and xcb_surface
extension enabled.

Signed-off-by: Yogesh Mohanmarimuthu <yogesh.mohanmarimuthu@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12816>

aco: constify radv_shader_{info,args}

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13192>

radv,aco: remap PS inputs when declaring shader arguments

LLVM seems to require all inputs for PS.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13192>