Daniel Schwierzeck [Wed, 21 Apr 2021 19:13:13 +0000 (21:13 +0200)]
MIPS: remove deprecated qemu_mips board
Remove qemu_mips boards because DM migration doesn't make sense.
The board support for qemu_mips is already marked as deprecated
in Qemu in favour of the Malta board. Also qemu_mips support
has been removed from Linux a long time ago.
The official replacement is the Malta board. The same Malta U-Boot
image can be used with Qemu and on physical hardware.
All combinations of Big Endian and Little Endian as well as 32 bit
and 64 bit are supported.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Stefan Roese [Mon, 26 Apr 2021 14:43:18 +0000 (16:43 +0200)]
mips: octeon: octeon_ebb7304_defconfig: Fix CFI flash setup
This patch makes the necessary adjustments in the defconfig to fully
support the CFI flash on the Octeon EBB7304.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Tom Rini [Tue, 25 May 2021 00:53:13 +0000 (20:53 -0400)]
Prepare v2021.07-rc3
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 24 May 2021 20:12:31 +0000 (16:12 -0400)]
Merge branch '2021-05-24-add-lto-support'
- Add LTO (link time optimization) support to the build system and
enable it on a few boards. This is an alternative to using
-ffunction-sections/-fdata-sections and --gc-sections at link time to
remove unused code. This can result in notable savings, but needs
testing on each platform before use as it can expose problems by
optimizing away various functionally necessary calls.
Tom Rini [Mon, 24 May 2021 18:19:05 +0000 (14:19 -0400)]
stackprot: Make our test a bit more complex
With better compiler optimizations available, a compiler may see we do
nothing with our buffer after calling memset and omit the call, thus
causing us to not smash the stack. Add a comment to explain why we now
also have a printf call, so that the test will pass as the memset will
not be omitted.
Reported-by: Marek Behún <marek.behun@nic.cz>
Signed-off-by: Tom Rini <trini@konsulko.com>
Marek Behún [Thu, 20 May 2021 11:24:25 +0000 (13:24 +0200)]
ARM: enable LTO for some boards
Enable LTO for some boards that were tested by people on U-Boot Mailing
List.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Adam Ford <aford173@gmail.com>
Tested-by: Pali Rohár <pali@kernel.org>
Tested-by: Tim Harvey <tharvey@gateworks.com>
Marek Behún [Thu, 20 May 2021 11:24:24 +0000 (13:24 +0200)]
ARM: don't use --gc-sections with LTO when using private libgcc
When using LTO, we can throw away the --gc-sections flag, but only if
using private libgcc.
When using system's libgcc, --gc-sections is still needed, otherwise
linking will fail due to undefined references to libc's symbols.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Behún [Thu, 20 May 2021 11:24:23 +0000 (13:24 +0200)]
ARM: don't use -ffunction-sections/-fdata-sections with LTO build
When building with LTO, using -ffunction-sections/-fdata-sections is not
useful anymore.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Behún [Thu, 20 May 2021 11:24:22 +0000 (13:24 +0200)]
ARM: make LTO available
Make LTO available for ARM architecture.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Behún [Thu, 20 May 2021 11:24:21 +0000 (13:24 +0200)]
ata: ahci: fix ahci_link_up() type mismatch for LTO
When building highbank_defconfig with LTO, the compiler complains about
type mismatch of function ahci_link_up().
The third parameter of this function is of type u8 in
drivers/ata/ahci.c, but of type int in board/highbank/ahci.c.
There is no reason in using u8, and the code using this function
actually passes an int variable into the function (so it is implicitly
converted to u8).
Change the type of this parameter to int in drivers/ata/ahci.c.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Marek Behún [Thu, 20 May 2021 11:24:20 +0000 (13:24 +0200)]
armv8: SPL: discard relocation information
For some reason when building SPL for ARMv8 with LTO, the relocation
information is not discarded.
Discard it explicitly in the linker script.
This fixes LTO build for imx8mm_venice_defconfig.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Behún [Thu, 20 May 2021 11:24:19 +0000 (13:24 +0200)]
ARM: omap3: fix LTO for DM3730 (and possibly other omap3 boards)
Adam Ford says that DM3730 needs board.c compiled without LTO flags.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Adam Ford <aford173@gmail.com>
Marek Behún [Thu, 20 May 2021 11:24:18 +0000 (13:24 +0200)]
ARM: fix LTO for rockchip and samsung
When building with LTO, the compiler complains about type mismatch of
function usb_gadget_handle_interrupts(). This function is defined
without parameters in files
arch/arm/mach-rockchip/board.c
board/samsung/common/exynos5-dt.c
but it should have one parameter, int index.
Fix this.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Marek Behún [Thu, 20 May 2021 11:24:17 +0000 (13:24 +0200)]
ARM: fix LTO for seaboard
When seaboard_defconfig is compiled with LTO, the compiler complains
about some instructions not being supported in ARM mode.
This is caused by arch/arm/mach-tegra/tegra20/warmboot_avp.c having
different CFLAGS declared in Makefile. This file needs to be compiled
without LTO.
Fix this by removing -flto for this file.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Behún [Thu, 20 May 2021 11:24:16 +0000 (13:24 +0200)]
ARM: imx8m: fix imx_eqos_txclk_set_rate() type mismatch for LTO
When building imx8mp_evk_defconfig with LTO, the compiler complains
about type mismatch of function imx_eqos_txclk_set_rate() in file
drivers/net/dwc_eth_qos.c:845:12
which contains a weak definition of this function, vs file
arch/arm/mach-imx/imx8m/clock_imx8mm.c
which contains an implementation.
Change the type of this function in the implementation to fix this.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Marek Behún [Thu, 20 May 2021 11:24:15 +0000 (13:24 +0200)]
ARM: kona: fix clk_bsc_enable() type mismatch for LTO
When building with LTO, the compiler complains about type mismatch of
function clk_bsc_enable() in file:
arch/arm/cpu/armv7/kona-common/clk-stubs.c
vs other files that define or use this function:
warning: type of ‘clk_bsc_enable’ does not match original declaration.
Change the type of this function to that of the other usages.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Marek Behún [Thu, 20 May 2021 11:24:14 +0000 (13:24 +0200)]
ARM: fix LTO for keystone
When building keystone with LTO the compiler complains:
Error: selected processor does not support `smc #0' in Thumb mode
Fix this by removing -flto for the file implementing these SMC calls.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Marek Behún [Thu, 20 May 2021 11:24:13 +0000 (13:24 +0200)]
ARM: fix LTO for apf27
When apf27_defconfig is built with LTO, linking complains about
undefined reference to `nand_boot`. This is because it is referenced
from inline assembly. Make it visible.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Marek Behún [Thu, 20 May 2021 11:24:12 +0000 (13:24 +0200)]
ARM: fix LTO for imx28_xea
When imx28_xea_defconfig is built with LTO, the compiler complains about
the two different declarations of _start:
include/asm-generic/sections.h as extern void _start(void);
arch/arm/cpu/arm926ejs/mxs/mxs.c as extern uint32_t _start;
Fix this.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Marek Behún [Thu, 20 May 2021 11:24:11 +0000 (13:24 +0200)]
ARM: fix LTO build for some thumb-interwork cases
Fix LTO build for some thumb-interwork usecases (such as for
da850evm_defconfig), where inline assmebly such as
mrc p15,0,r2,c1,c0,0
causes the compiler to fail during LTO linking with
Error: selected processor does not support `mrc p15,0,r2,c1,c0,0'
in Thumb mode
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Behún [Thu, 20 May 2021 11:24:10 +0000 (13:24 +0200)]
ARM: make gd a function call for LTO and set via set_gd()
On ARM, the gd pointer is stored in registers r9 / x18. For this the
-ffixed-r9 / -ffixed-x18 flag is used when compiling, but using global
register variables causes errors when building with LTO, and these
errors are very difficult to overcome.
Richard Biener says [1]:
Note that global register vars shouldn't be used with LTO and if they
are restricted to just a few compilation units the recommended fix is
to build those CUs without -flto.
We cannot do this for U-Boot since all CUs use -ffixed-reg flag.
It seems that with LTO we could in fact store the gd pointer differently
and gain performance or size benefit by allowing the compiler to use
r9 / x18. But this would need more work.
So for now, when building with LTO, go the clang way, and instead of
declaring gd a global register variable, we make it a function call via
macro.
[1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68384
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Behún [Thu, 20 May 2021 11:24:09 +0000 (13:24 +0200)]
ARM: global_data: make set_gd() work for armv5 and armv6
The Thumb instruction `ldr` is able to move high registers only from
armv7. For armv5 and armv6 we have to use `mov`.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Behún [Thu, 20 May 2021 11:24:08 +0000 (13:24 +0200)]
sandbox: enable LTO by default
Build sandbox targets with LTO by default.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Marek Behún [Thu, 20 May 2021 11:24:07 +0000 (13:24 +0200)]
sandbox: make LTO available
Make LTO available for sandbox architecture.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Marek Behún [Thu, 20 May 2021 11:24:06 +0000 (13:24 +0200)]
sandbox: use sections instead of symbols for getopt array boundaries
In style of linked lists, instead of declaring symbols for boundaries
of getopt options array in the linker script, declare corresponding
sections and retrieve the boundaries via static inline functions.
Without this clang's LTO produces binary without any getopt options,
because for some reason it thinks that array is empty (start and end
symbols are at the same address).
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Behún [Thu, 20 May 2021 11:24:05 +0000 (13:24 +0200)]
sandbox: errno: avoid conflict with libc's errno
When building with LTO, the system libc's `errno` variable used in
arch/sandbox/cpu/os.c conflicts with U-Boot's `errno` (defined in
lib/errno.c) with the following error:
.../ld: errno@@GLIBC_PRIVATE: TLS definition in /lib64/libc.so.6
section .tbss mismatches non-TLS reference in
/tmp/u-boot.EQlEXz.ltrans0.ltrans.o
To avoid this conflict use different asm label for this variable when
CONFIG_SANDBOX is enabled.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Behún [Thu, 20 May 2021 11:24:04 +0000 (13:24 +0200)]
build: link with --build-id=none
Some toolchains are compiled so that they pass a --build-id=something
parameter to the linker implicitly.
This causes U-Boot LTO linking to fail with something like:
ld: section .note.gnu.build-id LMA ... overlaps section .text LMA ...
because U-Boot's link scripts do not currently handle .note.gnu.build-id
section.
Fix this by explicitly disabling build-id.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Behún [Thu, 20 May 2021 11:24:03 +0000 (13:24 +0200)]
build: support building with Link Time Optimizations
Add plumbing for building U-Boot with Link Time Optimizations.
When building with LTO, $(PLATFORM_LIBS) has to be in --whole-archive /
--no-whole-archive group, otherwise some functions declared in assembly
may not be resolved and linking may fail.
Note: clang may throw away linker list symbols it thinks are unused when
compiling with LTO. To force these symbols to be included, we refer to
them via the __ADDRESSABLE macro in a C file generated from compiled
built-in.o files before linking.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Behún [Thu, 20 May 2021 11:24:02 +0000 (13:24 +0200)]
build: use thin archives instead of incremental linking
Currently we use incremental linking (ld -r) to link several object
files from one directory into one built-in.o object file containing the
linked code from that directory (and its subdirectories).
Linux has, some time ago, moved to thin archives instead.
Thin archives are archives (.a) that do not really contain the object
files, only references to them.
Using thin archives instead of incremental linking
- saves disk space
- apparently works better with dead code elimination
- makes things easier for LTO
The third point is the important one for us. With incremental linking
there are several options how to do LTO, and that would unnecessarily
complicate things.
We have to use the --whole-archive/--no-whole-archive linking option
instead of --start-group/--end-group, otherwise linking may fail because
of unresolved symbols, or the resulting binary will be unusable.
We also need to use the P flag for ar, otherwise final linking may fail.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Behún [Thu, 20 May 2021 11:24:01 +0000 (13:24 +0200)]
Makefile, Makefile.spl: cosmetic change
Indent the linking commands so that they look cosmetically better.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Marek Behún [Thu, 20 May 2021 11:24:00 +0000 (13:24 +0200)]
lib: crc32: put the crc_table variable into efi_runtime_rodata section
When compiling with LTO, the compiler fails with an error saying that
`crc_table` causes a section type conflict with `efi_var_buf`.
This is because both are declared to be in the same section (via macro
`__efi_runtime_data`), but one is const while the other is not.
Put this variable into the section .rodata.efi_runtime, instead of
.data.efi_runtime, via macro __efi_runtime_rodata.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Heinrich Schuchardt <xypron.gpk@gmx.de>
Marek Behún [Thu, 20 May 2021 11:23:59 +0000 (13:23 +0200)]
efi_selftest: compiler flags for efi_selftest_miniapp_exception.o
Add $(CFLAGS_EFI) and remove $(CFLAGS_NON_EFI) for
efi_selftest_miniapp_exception.o.
The removal is needed when compiling with LTO - this object file needs
to be compiled without -flto.
The adding is for consistency with other miniapps.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Marek Behún [Thu, 20 May 2021 11:23:58 +0000 (13:23 +0200)]
efi_loader: add macro for const EFI runtime data
Add macro __efi_runtime_rodata, for const variables with similar purpose
as those using __efi_runtime_data.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Marek Behún [Thu, 20 May 2021 11:23:57 +0000 (13:23 +0200)]
efi_loader: add Sphinx doc for __efi_runtime and __efi_runtime_data
Document the macros __efi_runtime and __efi_runtime_data in Sphinx
style.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Marek Behún [Thu, 20 May 2021 11:23:56 +0000 (13:23 +0200)]
efi_loader: fix warning when linking with LTO
When linking with LTO, the compiler complains about type mismatch of
variables `__efi_runtime_start`, `__efi_runtime_stop`,
`__efi_runtime_rel_start` and `__efi_runtime_rel_stop`:
include/efi_loader.h:218:21: warning: type of ‘__efi_runtime_start’
does not match original
declaration [-Wlto-type-mismatch]
218 | extern unsigned int __efi_runtime_start, __efi_runtime_stop;
| ^
arch/sandbox/lib/sections.c:7:6: note: ‘__efi_runtime_start’ was
previously declared here
7 | char __efi_runtime_start[0] __attribute__((section(".__efi_run
| ^
Change the type to char[] in include/efi_loader.h.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Marek Behún [Thu, 20 May 2021 11:23:55 +0000 (13:23 +0200)]
string: make memcpy(), memset(), memcmp() and memmove() visible for LTO
It seems that sometimes (happening on ARM64, for example with
turris_mox_defconfig) GCC, when linking with LTO, changes the symbol
names of some functions, for example lib/string.c's memcpy() function to
memcpy.isra.0.
This is a problem however when GCC for a code such as this:
struct some_struct *info = get_some_struct();
struct some struct tmpinfo;
tmpinfo = *info;
emits a call to memcpy() by builtin behaviour, to copy *info to tmpinfo.
This then results in the following linking error:
.../lz4.c:93: undefined reference to `memcpy'
.../uuid.c:206: more undefined references to `memcpy' follow
GCC's documentation says this about -nodefaultlibs option:
The compiler may generate calls to "memcmp", "memset", "memcpy" and
"memmove". These entries are usually resolved by entries in libc.
These entry points should be supplied through some other mechanism
when this option is specified.
Make these functions visible by using the __used macro to avoid this
error.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Behún [Thu, 20 May 2021 11:23:54 +0000 (13:23 +0200)]
test/py: improve regular expression for ut subtest symbol matcher
Improve the regular expression that matches unittest symbols in
u-boot.sym.
Currently we do not enforce no prefix in symbol string, but with the
soon to come change in linker lists declaring lists and entries with the
__ADDRESSABLE macro (because of LTO), the symbol file will contain for
every symbol of the form
_u_boot_list_2_ut_X_2_Y
also symbol
__UNIQUE_ID___addressable__u_boot_list_2_ut_X_2_YN,
(where N at the end is some number).
In order to avoid matching these additional symbols, ensure that the
character before "_u_boot_list_2_ut" is not a symbol name character.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Behún [Thu, 20 May 2021 11:23:53 +0000 (13:23 +0200)]
compiler.h: align the __ADDRESSABLE macro with Linux' version
Use UNIQUE_ID in the __ADDRESSABLE macro.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Marek Behún [Thu, 20 May 2021 11:23:52 +0000 (13:23 +0200)]
treewide: Convert macro and uses of __section(foo) to __section("foo")
This commit does the same thing as Linux commit
33def8498fdd.
Use a more generic form for __section that requires quotes to avoid
complications with clang and gcc differences.
Remove the quote operator # from compiler_attributes.h __section macro.
Convert all unquoted __section(foo) uses to quoted __section("foo").
Also convert __attribute__((section("foo"))) uses to __section("foo")
even if the __attribute__ has multiple list entry forms.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Behún [Thu, 20 May 2021 11:23:51 +0000 (13:23 +0200)]
checkpatch: require quotes around section name in the __section() macro
This is how Linux does this now, see Linux commit
339f29d91acf.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Behún [Thu, 20 May 2021 11:23:50 +0000 (13:23 +0200)]
regmap: fix a serious pointer casting bug
There is a serious bug in regmap_read() and regmap_write() functions
where an uint pointer is cast to (void *) which is then cast to (u8 *),
(u16 *), (u32 *) or (u64 *), depending on register width of the map.
For example given a regmap with 16-bit register width the code
int val = 0x12340000;
regmap_read(map, 0, &val);
only changes the lower 16 bits of val on little-endian machines.
The upper 16 bits will remain 0x1234.
Nobody noticed this probably because this bug can be triggered with
regmap_write() only on big-endian architectures (which are not used by
many people anymore), and on little endian this bug has consequences
only if register width is 8 or 16 bits and also the memory place to
which regmap_read() should store it's result has non-zero upper bits,
which it seems doesn't happen anywhere in U-Boot normally. CI managed to
trigger this bug in unit test of dm_test_devm_regmap_field when compiled
for sandbox_defconfig using LTO.
Fix this by utilizing an union { u8; u16; u32; u64; } and reading data
into this union / writing data from this union.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Pratyush Yadav <p.yadav@ti.com>
Simon Glass [Fri, 14 May 2021 01:39:23 +0000 (19:39 -0600)]
test: Avoid random numbers in dm_test_devm_regmap()
There is no good reason to use a sequence from rand() here. We may as well
invent our own sequence.
This should molify Coverity which does not use rand() being used.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Coverity (CID: 312949)
Tom Rini [Mon, 24 May 2021 15:47:01 +0000 (11:47 -0400)]
pylibfdt: Rework "avoid unused variable warning" lines
Clang has -Wself-assign enabled by default under -Wall and so when
building with -Werror we would get an error here. Inspired by Linux
kernel git commit
a21151b9d81a ("tools/build: tweak unused value
workaround") make use of the fact that both Clang and GCC support
casting to `void` as the method to note that something is intentionally
unused.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sun, 23 May 2021 14:15:15 +0000 (10:15 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-sh
- Various clk/pinctrl updates to re-sync with Linux and other fixes
Marek Vasut [Tue, 27 Apr 2021 20:03:38 +0000 (22:03 +0200)]
pinctrl: renesas: Implement unlock register masks
The V3U SoC has several unlock registers, one per register group. They
reside at offset zero in each 0x200 bytes-sized block.
To avoid adding yet another table to the PFC implementation, this
patch adds the option to specify an address mask instead of the fixed
address in sh_pfc_soc_info::unlock_reg.
This is a direct port of Linux 5.12 commit
e127ef2ed0a6
("pinctrl: renesas: Implement unlock register masks") by
Ulrich Hecht <uli+renesas@fpond.eu>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Marek Vasut [Tue, 27 Apr 2021 00:03:33 +0000 (02:03 +0200)]
pinctrl: renesas: Fix R-Car Gen2 help text
The help text for Gen2 entries had a copy paste error, still containing
the Gen3 string, while the description was correctly listing Gen2. Fix
the help text.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Marek Vasut [Tue, 27 Apr 2021 00:01:50 +0000 (02:01 +0200)]
pinctrl: renesas: Deduplicate Kconfig
The help text in the Kconfig file was always a copy of the same thing.
Move single copy into the common PFC driver entry instead. Also fix a
copy-paste error in the PFC help text, which identified PFC as clock.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Marek Vasut [Tue, 27 Apr 2021 19:17:43 +0000 (21:17 +0200)]
gpio: renesas: Pass struct udevice to rcar_gpio_set_direction()
Pass struct udevice to rcar_gpio_set_direction() in preparation of
quirk handling in rcar_gpio_set_direction(). No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Marek Vasut [Tue, 27 Apr 2021 17:36:39 +0000 (19:36 +0200)]
clk: renesas: Deduplicate gen3_clk_get_rate64() PLL handling
Most of the PLLx, MAIN, FIXED clock handlers are calling very similar
code, which determines parent rate and then applies multiplication and
division. The only difference is whether multiplication is fixed factor
or coming from CRx register. Deduplicate the code into a single function.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Hai Pham [Thu, 5 Nov 2020 15:30:37 +0000 (22:30 +0700)]
clk: renesas: Add register pointers into struct cpg_mssr_info
Base on Linux v5.10-rc2, commit
8b652aa8a1fb by Yoshihiro Shimoda
To support other register layouts in the future, add register pointers
of {control,status,reset,reset_clear}_regs into struct cpg_mssr_info
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Hai Pham [Thu, 5 Nov 2020 14:32:38 +0000 (21:32 +0700)]
clk: renesas: Introduce enum clk_reg_layout
From Linux v5.10-rc2, commit
ffbf9cf3f946 by Yoshihiro Shimoda
Introduce enum clk_reg_layout to support multiple register layout variants
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Hai Pham [Fri, 22 May 2020 03:39:04 +0000 (10:39 +0700)]
clk: renesas: Pass struct cpg_mssr_info to renesas_clk_endisable()
CPG IP in some specific Renesas SoCs (i.e. new R8A779A0 V3U SoC)
requires a different setting procedure. Make struct cpg_mssr_info
accessible to handle the clock setting in that case.
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Marek Vasut [Sun, 25 Apr 2021 19:53:05 +0000 (21:53 +0200)]
clk: renesas: Make reset controller modemr register offset configurable
The MODEMR register offset changed on R8A779A0, make the MODEMR offset
configurable. Fill the offset in on all clock drivers. No functional
change.
Based off "clk: renesas: Make CPG Reset MODEMR offset accessible from
struct cpg_mssr_info" by Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Hai Pham [Tue, 11 Aug 2020 03:25:28 +0000 (10:25 +0700)]
clk: renesas: Add support for RPCD2 clock
This supports RPCD2 clock handling. While at it, add the check point
for RPC-IF clock RPCD2 Frequency Division Ratio, since it must be odd
number
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Hai Pham [Tue, 19 May 2020 10:42:05 +0000 (17:42 +0700)]
clk: renesas: Fix Realtime Module Stop Control Register offsets
This patch fixes Realtime Module Stop Control Register (RMSTPCR) offsets
based on R-Car Gen3, H2/M2/M2N/E2/E2X hardware user's manual.
The r8a73a4 only has RMSTPCR0 - RMSTPCR5 so this calculation change
doesn't affect it.
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Hai Pham [Sat, 5 Dec 2020 02:35:40 +0000 (09:35 +0700)]
clk: renesas: Fix incorrect return RPC clk_get_rate
RPC clk_get_rate will return error code instead of expected clock rate.
Fix this.
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Marek Vasut [Sun, 25 Apr 2021 19:26:22 +0000 (21:26 +0200)]
clk: renesas: Reinstate RPC clock on R-Car D3/E3
Reinstate RPC clock on D3/E3 after Linux 5.12 synchronization.
The D3 and E3 clock drivers do not contain RPC clock entries
mainline Linux yet.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Marek Vasut [Sun, 25 Apr 2021 19:10:40 +0000 (21:10 +0200)]
clk: renesas: Synchronize R-Car Gen3 tables with Linux 5.12
Synchronize R-Car Gen3 clock tables with Linux 5.12,
commit
9f4ad9e425a1 ("Linux 5.12") .
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Marek Vasut [Sun, 25 Apr 2021 19:09:10 +0000 (21:09 +0200)]
clk: renesas: Synchronize R-Car Gen2 tables with Linux 5.12
Synchronize R-Car Gen2 clock tables with Linux 5.12,
commit
9f4ad9e425a1 ("Linux 5.12") .
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Marek Vasut [Sun, 25 Apr 2021 19:08:18 +0000 (21:08 +0200)]
clk: renesas: Synchronize RZ/G2 tables with Linux 5.12
Synchronize RZ/G2 clock tables with Linux 5.12,
commit
9f4ad9e425a1 ("Linux 5.12") .
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Tom Rini [Thu, 20 May 2021 15:06:56 +0000 (11:06 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- Sync Armada mvpp2 ethernet driver with Marvell version (misc Marvell
authors)
Tom Rini [Thu, 20 May 2021 15:06:33 +0000 (11:06 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-riscv
Stefan Roese [Tue, 27 Apr 2021 09:48:28 +0000 (11:48 +0200)]
arm: mvebu: armada-3720-uDPU.dts: Change back to phy-mode "2500base-x"
With commit
8678776df6f5 (arm: mvebu: armada-3720-uDPU: fix PHY mode
definition to sgmii-2500) the PHY mode was switch to "sgmii-2500", even
when this is functionally incorrect since "2500base-x" was not supported
in U-Boot at that time. As this mode is now supported (at least present
in the headers), this patch moves back to the orinal version.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Jakov Petrina <jakov.petrina@sartura.hr>
Cc: Vladimir Vid <vladimir.vid@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Marcin Wojtas [Mon, 3 May 2021 06:08:53 +0000 (08:08 +0200)]
net: mvpp2: add explicit sgmii-2500 support
Until now the mvpp2 driver used an extra 'phy-speed'
DT property in order to differentiate between the
SGMII and SGMII @2.5GHz. As there is a dedicated
PHY_INTERFACE_MODE_SGMII_2500 flag to mark the latter
start using it and drop the custom flag.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Tested-by: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Stefan Chulski [Mon, 3 May 2021 06:08:52 +0000 (08:08 +0200)]
net: mvpp2: allow MDIO registration for fixed links
Currently, there are 2 valid cases for interface, PHY
and mdio relation:
- If an interface has PHY handler, it'll call
mdio_mii_bus_get_from_phy(), which will register
MDIO bus.
- If we want to use fixed-link for an interface,
PHY handle is not defined in the DTS, and no
MDIO is registered.
There is a third case, for some boards (with switch),
the MDIO is used for switch configuration, but the interface
itself uses fixed link. This patch allows this option by
checking if fixed-link subnode is defined, in this case,
MDIO bus is registers, but the PHY address is set to
PHY_MAX_ADDR for this interface, so this interface will
not try to access the PHY later on.
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Ben Peled [Mon, 3 May 2021 06:08:51 +0000 (08:08 +0200)]
net: mvpp2: fix missing switch case break
Signed-off-by: Ben Peled <bpeled@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Ben Peled [Mon, 3 May 2021 06:08:50 +0000 (08:08 +0200)]
net: mvpp2: remove unused define MVPP22_SMI_PHY_ADDR_REG
Signed-off-by: Ben Peled <bpeled@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Ben Peled [Mon, 3 May 2021 06:08:49 +0000 (08:08 +0200)]
net: mvpp2: AN Bypass in 1000 and 2500 basex mode
Signed-off-by: Ben Peled <bpeled@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Stefan Chulski [Mon, 3 May 2021 06:08:48 +0000 (08:08 +0200)]
net: mvpp2: Fix 2.5G GMII_SPEED configurations
GMII_SPEED should be enabled for 2.5G speed
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Yan Markman <ymarkman@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Marcin Wojtas [Mon, 3 May 2021 06:08:47 +0000 (08:08 +0200)]
net: mvpp2: remove redundant SMI address configuration
Because the mvpp2 driver now relies on the PHYLIB and
the external MDIO driver, configuring low level
SMI bus settings is redundant.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Stefan Chulski [Mon, 3 May 2021 06:08:46 +0000 (08:08 +0200)]
net: mvpp2: add 1000BaseX and 2500BaseX ppv2 support
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Stefan Chulski [Mon, 3 May 2021 06:08:45 +0000 (08:08 +0200)]
net: mvpp2: add CP115 port1 10G/5G SFI support
1. Differ between Port1 RGMII and SFI modes in Netcomplex config.
2. Remove XPCS config from SFI mode.
Port1 doesn't XPCS domain, XPCS config should be removed.
Access to Port1 XPCS can cause stall.
3. Add Port1 MPCS configurations.
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Stefan Chulski [Mon, 3 May 2021 06:08:44 +0000 (08:08 +0200)]
phy: introduce 1000BaseX and 2500BaseX modes
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Tom Rini [Wed, 19 May 2021 15:50:25 +0000 (11:50 -0400)]
Merge tag 'xilinx-for-v2021.07-rc3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2021.07-rc3
ZynqMP:
- Syncup DT with Linux kernel
- Fix mmc mini configurations via DT
- Add pinctrl/psgtr description to DTs
- Add DTs for Kria boards
- Enable RTC and Time commands
Versal:
- Fix early BSS section location
Rick Chen [Tue, 18 May 2021 01:51:29 +0000 (09:51 +0800)]
riscv: ae350: Increase malloc size for binman spl flow
It will need larger heap size for u-boot-spl to load u-boot.itb which
be generated from binman than USE_SPL_FIT_GENERATOR.
Signed-off-by: Rick Chen <rick@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng [Mon, 10 May 2021 12:23:41 +0000 (20:23 +0800)]
riscv: Drop USE_SPL_FIT_GENERATOR
Now that we have switched to binman to generate u-boot.itb for all
RISC-V boards, USE_SPL_FIT_GENERATOR is no longer needed and can
be dropped.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 10 May 2021 12:23:40 +0000 (20:23 +0800)]
riscv: ae350: Switch to use binman to generate u-boot.itb
Use the new BINMAN_STANDALONE_FDT option for AE350 based SPL defconfigs,
so that binman is now used to generate u-boot.itb.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rick Chen <rick@andestech.com>
Bin Meng [Mon, 10 May 2021 12:23:39 +0000 (20:23 +0800)]
riscv: qemu: Switch to use binman to generate u-boot.itb
By utilizing the newly introduced BINMAN_STANDALONE_FDT option, along
with a new dedicated device tree source file for the QEMU virt target
used for binman only, we can now use binman to generate u-boot.itb.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 10 May 2021 12:23:38 +0000 (20:23 +0800)]
riscv: dts: Sort build targets in alphabetical order
Sort the RISC-V DTS build targets by their Kconfig target names in
alphabetical order.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 10 May 2021 12:23:37 +0000 (20:23 +0800)]
binman: Support packaging U-Boot for scenarios like OF_BOARD or OF_PRIOR_STAGE
For scenarios like OF_BOARD or OF_PRIOR_STAGE, no device tree blob is
provided in the U-Boot build phase hence the binman node information
is not available. In order to support such use case, a new Kconfig
option BINMAN_STANDALONE_FDT is introduced, to tell the build system
that a device tree blob containing binman node is explicitly required
when using binman to package U-Boot.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 10 May 2021 12:23:36 +0000 (20:23 +0800)]
lib: kconfig: Limit BINMAN_FDT for OF_SEPARATE or OF_EMBED
Generally speaking BINMAN_FDT makes sense for OF_SEPARATE or OF_EMBED.
For the other OF_CONTROL methods, it's quite possible binman node is
not available as binman is invoked during the build phase instead of
runtime. Let's only turn it on for OF_SEPARATE or OF_EMBED by default.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 10 May 2021 12:23:35 +0000 (20:23 +0800)]
riscv: sifive: unleashed: Switch to use binman to generate u-boot.itb
At present SiFive Unleashed board uses the Makefile to create the FIT,
using USE_SPL_FIT_GENERATOR, which is deprecated as per the Makefile
warning. Update to use binman instead.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 10 May 2021 12:23:34 +0000 (20:23 +0800)]
makefile: Pass OpenSBI blob to binman make rules
This updates the make rules to pass OpenSBI blob to binman.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 10 May 2021 12:23:33 +0000 (20:23 +0800)]
binman: Add support for RISC-V OpenSBI fw_dynamic blob
Add an entry for RISC-V OpenSBI's 'fw_dynamic' firmware payload.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Bin Meng [Mon, 10 May 2021 12:23:32 +0000 (20:23 +0800)]
binman: test: Rename 172_fit_fdt.dts to 170_fit_fdt.dts
Currently there are 2 binman test cases using the same 172 number.
It seems that 172_fit_fdt.dts was originally named as 170_, but
commit
c0f1ebe9c1b9 ("binman: Allow selecting default FIT configuration")
changed its name to 172_ for no reason. Let's change it back.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 10 May 2021 12:23:31 +0000 (20:23 +0800)]
binman: Correct the comment for ATF entry type
This is wrongly referring to Intel ME, which should be ATF.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 10 May 2021 12:23:30 +0000 (20:23 +0800)]
binman: Correct '-a' description in the doc
It needs a space around '-a'.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rick Chen <rick@andestech.com>
Bin Meng [Mon, 10 May 2021 12:23:29 +0000 (20:23 +0800)]
common: kconfig: Correct a typo in SPL_LOAD_FIT
It should be FDT, not FTD.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rick Chen <rick@andestech.com>
Michal Simek [Wed, 12 May 2021 08:03:44 +0000 (10:03 +0200)]
xilinx: zynqmp: Enable DM_RTC/emul driver/cmd date/gettime and efi settime
Right now U-Boot is not aware about date/time that's why enable it by
default also with EFI runtime service for setting time.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
T Karthik Reddy [Wed, 12 May 2021 05:39:16 +0000 (23:39 -0600)]
xilinx: versal: Enable CONFIG_POSITION_INDEPENDENT
U-Boot expects to be linked to a specific hard-coded address and to
be loaded to and run from that address. CONFIG_POSITION_INDEPENDENT
config lifts that restriction & allowing the code to be loaded to
and executed from almost any address.
As we enabled CONFIG_POSITION_INDEPENDENT, CONFIG_INIT_SP_RELATIVE
is enabled by default, where it will set the early stack pointer at
runtime by adding an offset value to &_bss_start. The offset value
is taken from SYS_INIT_SP_BSS_OFFSET.
SYS_INIT_SP_BSS_OFFSET offset should be large enough so that the
early malloc region, global data (gd), and early stack should fit.
With commit
d8fabcc424bd ("arm64: versal: Increase SYS_MALLOC_F_LEN")
SYS_MALLOC_F_LEN is increased from 32KB to 1MB, so we need to
accommodate this space with SYS_INIT_SP_BSS_OFFSET. Hence increasing
SYS_INIT_SP_BSS_OFFSET to 1.5MB.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 10 May 2021 14:02:15 +0000 (16:02 +0200)]
arm64: zynqmp: Add description for SOM/Kria boards
The patch contains several DT files for SOM platform.
Carrier card is sck-kv (KV260) revA/B. SMK-K26 is description for starter
kit which doesn't have EMMC populated. And SM-K26 is full som with EMMC.
Files are divided in this way to make sure that SOM can be plugged to
different carrier card and all peripherals on SOM (or defined by a spec) can
be used by U-Boot. Full DT for SOM+CC can be merged together as overlays.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 10 May 2021 12:55:34 +0000 (14:55 +0200)]
arm64: zynqmp: Add psgtr DT descriptions
Mainline kernel has psgtr driver that's why it is good to add description
to DT files. Some boards are just missing description for USB3 and sata.
zc1751-dc1 and p-a2197 are also missing clock descriptions for input
clocks.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 10 May 2021 11:14:02 +0000 (13:14 +0200)]
arm64: zynqmp: Add pinctrl description
ZynqMP pinctrl Linux driver has been merged to 5.13-rc1 kernel. Based on it
DT files can be extended by pinctrl configurations.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
T Karthik Reddy [Thu, 29 Apr 2021 14:02:29 +0000 (08:02 -0600)]
arm64: zynqmp: Add zynqmp firmware specific DT nodes
Probe zynqmp firmware driver by adding zynqmp firmware, power &
ipi mailbox device tree nodes for mini emmc.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Michal Simek [Thu, 21 Jan 2021 10:26:55 +0000 (11:26 +0100)]
arm64: zynqmp: Add missing mio-bank properties to sdhci
Add missing xlnx,mio-bank property to sdhci node. Also add properties with
0 value to have it listed in case that files are copied to different
projects where default case doesn't need to be handled in the same way.
That's why explicitly list them too.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 11 Mar 2021 12:34:02 +0000 (13:34 +0100)]
arm64: zynqmp: Remove comment about clock chips
These comments weren't push to mainline that's why remove them.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Raviteja Narayanam [Thu, 1 Apr 2021 13:14:10 +0000 (07:14 -0600)]
arm64: zynqmp: Add 'i2c-mux-idle-disconnect' property
I2C muxes that have the slave devices with same address are
falling into the below problem.
VCK190 system controller (SC) - zynqmp-e-a2197-00-revA.dts
I2C1 (0xff030000) -> Mux1 (@0x74) -> Channel 3 -> 0x50
I2C1 (0xff030000) -> Mux2 (@0x75) -> Channel 0 -> 0x50
1. SC accesses I2C1 - Mux1 (0x74) - Channel 3 and then
2. SC accesses I2C1 - Mux2 (0x75) - Channel 0.
Now it results in 2 slave devices with same address (0x50)
on the I2C bus, making the communication un-reliable.
When ' i2c-mux-idle-disconnect' is in DT, after '1', the Mux
channel output is disconnected, making none of the channels
available to the I2C1. So, there is no question of having the
same addressed slave (0x50) present on the bus when we are doing '2'.
Same pattern is seen in below two boards also.
ZCU208 - zynqmp-zcu208-revA.dts
ZCU216 - zynqmp-zcu216-revA.dts
Signed-off-by: Raviteja Narayanam <raviteja.narayanam@xilinx.com>
Saeed Nowshadi [Tue, 13 Apr 2021 23:01:42 +0000 (16:01 -0700)]
arm64: zynqmp: Add label to all GPIO lines for VCK190 SC
Add label to GPIO lines so the user-level applications can find any line
without knowing its physical path on System Controller on VCK190/VMK180.
These labels are describing EMIO gpio connection which depends on PL which
we normally don't describe but that's only way to go for now. Lately this
should be done out of this source code.
Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Saeed Nowshadi [Mon, 22 Mar 2021 18:58:38 +0000 (11:58 -0700)]
arm64: zynqmp: Add 'silabs,skip-recall' to DDR DIMM si570 clk node
The 'silabs,skip-recall' property prevents interruption in operation of
the clock while the driver is being probed. Without this property, the
DDR DIMM clk can cause a failure during Versal's boot.
Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com>
Michal Simek [Tue, 9 Mar 2021 11:43:42 +0000 (12:43 +0100)]
arm64: zynqmp: Add missing silabs,skip-recall for si570 ref clk nodes
All si570 which are used for ps reference clock generation should contain
silabs,skip-recall property not to cause break on ps clock.
On Versal boards this will cause hang on Versal cpu when it is booted at
the same time with SC.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>