Joseph Huber [Mon, 27 Jun 2022 16:23:50 +0000 (12:23 -0400)]
[OpenMP] Add loop tripcount argument to kernel launch and remove push function
Previously we added the `push_target_tripcount` function to send the
loop tripcount to the device runtime so we knew how to configure the
teams / threads for execute the loop for a teams distribute construct.
This was implemented as a separate function mostly to avoid changing the
interface for backwards compatbility. Now that we've changed it anyway
and the new interface can take an arbitrary number of arguments via the
struct without changing the ABI, we can move this to the new interface.
This will simplify the runtime by removing unnecessary state between
calls.
Depends on D128550
Reviewed By: jdoerfert
Differential Revision: https://reviews.llvm.org/D128816
Joseph Huber [Fri, 24 Jun 2022 13:13:53 +0000 (09:13 -0400)]
[OpenMP] Change OpenMP code generation for target region entries
This patch changes the code we generate to enter a target region on the
device. This is in-line with the new definition in the runtime that was
added previously. Additionally we implement this in the OpenMPIRBuilder
so that this code can be shared with Flang in the future.
Reviewed By: ABataev
Differential Revision: https://reviews.llvm.org/D128550
Joseph Huber [Thu, 23 Jun 2022 18:57:59 +0000 (14:57 -0400)]
[Libomptarget] Implement a unified kernel entry function
This patch implements a unified kernel entry function that will be
targeted from both teams and non-teams clauses. We introduce a new
interface and make the old functions call in using the new one. A
following patch will include the necessary changes to Clang to call
these new functions instead.
Reviewed By: jdoerfert
Differential Revision: https://reviews.llvm.org/D128549
LLVM GN Syncbot [Fri, 8 Jul 2022 18:34:42 +0000 (18:34 +0000)]
[gn build] Port
23c7328bad92
Jacques Pienaar [Fri, 8 Jul 2022 18:31:12 +0000 (11:31 -0700)]
[mlir] Add method to populate default attributes
Previously default attributes were only usable by way of the ODS generated
accessors, but this was undesirable as
1. The ODS getters could construct Attribute each get request;
2. For non-C++ uses this would require either duplicating some of tee default
attribute generating or generating additional bindings to generate methods;
3. Accessing op.getAttr("foo") and op.getFoo() would return different results;
Generate method to populate default attributes that can be used to address
these.
This merely adds this facility but does not employ by default on any path.
Differential Revision: https://reviews.llvm.org/D128962
Joseph Huber [Fri, 8 Jul 2022 18:29:04 +0000 (14:29 -0400)]
[Clang][Docs] Update the clang-linker-wrapper documentation.
Joseph Huber [Fri, 8 Jul 2022 18:15:18 +0000 (14:15 -0400)]
[llvm-objdump] Fix alignment issues when dumping offloading sections
Summary:
The `.llvm.offloading` section should always be aligned by `8`. However,
we may want to show the offloading data stored in a static library. In
this case, even though the section's alignment is correct, the offset
inside the archive will result in the memory buffer being misaligned. TO
combat this we simply check if the buffer does not have the proper
alignment and copies it to a new buffer if not. This copy should have
the proper alignment.
zoecarver [Fri, 8 Jul 2022 17:42:29 +0000 (10:42 -0700)]
[objcxx] Fix `std::addressof` for `id`.
Differential Revision: https://reviews.llvm.org/D129384
Konstantin Varlamov [Fri, 8 Jul 2022 03:35:51 +0000 (20:35 -0700)]
[libc++][ranges] Implement `ranges::nth_element`.
Differential Revision: https://reviews.llvm.org/D128149
Cole Kissane [Fri, 8 Jul 2022 18:24:45 +0000 (11:24 -0700)]
[llvm] Remove unused and redundant crc32 funcction from llvm::compression::zlib namespace
* Remove crc32 from zlib compression namespace, people should use the `llvm::crc32` instead.
Reviewed By: MaskRay, leonardchan
Differential Revision: https://reviews.llvm.org/D128754
Daniil Fukalov [Fri, 8 Jul 2022 18:19:10 +0000 (21:19 +0300)]
[NFC] Fix cvt_f32_ubyte.ll test.
Remove (unintended) infinite loop in the test.
Reviewed By: vangthao
Differential Revision: https://reviews.llvm.org/D129328
Cole Kissane [Fri, 8 Jul 2022 18:19:05 +0000 (11:19 -0700)]
[NFC] Refactor llvm::zlib namespace
* Refactor compression namespaces across the project, making way for a possible
introduction of alternatives to zlib compression.
Changes are as follows:
* Relocate the `llvm::zlib` namespace to `llvm::compression::zlib`.
Reviewed By: MaskRay, leonardchan, phosek
Differential Revision: https://reviews.llvm.org/D128953
tlattner [Fri, 1 Jul 2022 21:07:48 +0000 (14:07 -0700)]
Update references to Discourse instead of the mailing lists.
Update the references to the old Mailman mailing lists to point to Discourse forums.
Reviewed By: aaron.ballman
Differential Revision: https://reviews.llvm.org/D128766
Nicolai Hähnle [Mon, 4 Jul 2022 11:35:26 +0000 (13:35 +0200)]
Fix test: LLVMGetBitcodeModule takes ownership of memory buffer
Clarify this behavior in the C interface header file and fix a related
bug in a test.
Differential Revision: https://reviews.llvm.org/D129113
Iain Sandoe [Mon, 13 Jun 2022 09:15:50 +0000 (10:15 +0100)]
[C++20][Modules] Allow for redeclarations in partitions.
The existing provision is not sufficient, it did not allow for the cases
where an implementation partition includes the primary module interface,
or for the case that an exported interface partition is contains a decl
that is then implemented in a regular implementation unit.
It is somewhat unfortunate that we have to compare top level module names
to achieve this, since built modules are not necessarily available.
TODO: It might be useful to cache a hash of the primary module name if
this test proves to be a significant load.
Differential Revision: https://reviews.llvm.org/D127624
Ryan Thomas Lynch (@emosy) [Fri, 8 Jul 2022 17:58:20 +0000 (10:58 -0700)]
[vscode-mlir] add tablegen <> bracket colorization
Add support for colorizing angle brackets "<>" in TableGen files.
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D128229
Jacques Pienaar [Fri, 8 Jul 2022 17:57:04 +0000 (10:57 -0700)]
[mlir][tosa] Enable decomposing Conv2D also where 1 input dim is dynamic
Restricted to just 1 dynamic input dim as that worked all the way through to
codegen.
Differential Revision: https://reviews.llvm.org/D129334
Philip Reames [Fri, 8 Jul 2022 17:19:49 +0000 (10:19 -0700)]
[RISCV] Switch to using get.active.lane.mask when tail folding
The motivation here is to a) bring us closer into alignment with AArch64 under the assumption that codepath is better tested, and b) simplify pattern matching in an upcoming change.
The immediate impact is a significant IR reduction but a fairly minimal change in the generated assembly. Due to a difference in expansion behavior we get a saturating add vs an unsaturating one for the old code, but that's about it. This difference comes down to different handling of overflow, which doesn't seem to be possible here anyways, so the assembly codegen is arguably a minor regression. I don't expect that to matter in practice.
Differential Revision: https://reviews.llvm.org/D129221
Craig Topper [Fri, 8 Jul 2022 17:14:27 +0000 (10:14 -0700)]
[RISCV] Mark fminnum_vl and fmaxnum_vl as commutable.
Craig Topper [Fri, 8 Jul 2022 17:11:44 +0000 (10:11 -0700)]
[RISCV] Add commuted fixed vector vfmax.vf and vfmin.vf tests. NFC
The ISD opcodes aren't marked commutable so we don't match these
properly.
Philip Reames [Fri, 8 Jul 2022 17:09:49 +0000 (10:09 -0700)]
[RISCV] Mark vsadd(u)_vl as commutable
This allows fixed length vectors involving splats on the LHS to commute into the _vx form of the instruction. Oddly, the generic canonicalization rules appear to catch the scalable vector cases. I haven't fully dug in to understand why, but I suspect it's because of a difference in how we represent splats (splat_vector vs build_vector).
Differential Revision: https://reviews.llvm.org/D129302
Alexander Yermolovich [Thu, 7 Jul 2022 18:41:51 +0000 (11:41 -0700)]
[DWARF] Add linkagename to hash
Originally encountered with RUST, but also there are cases with distributed LTO
where debug info dwo units contain structurally the same debug information, with
difference in DW_AT_linkage_name. This causes collision on DWO ID.
Differential Revision: https://reviews.llvm.org/D129317
Nandor Licker [Fri, 8 Jul 2022 05:57:37 +0000 (08:57 +0300)]
[mlir] Fixed double-free bug in SymbolUserMap
`SymbolUserMap` relied on `try_emplace` and `std::move` to relocate an entry to another key. However, if this triggered the resizing of the `DenseMap`, the value was destroyed before it could be moved to the new storage location, leading to a dangling `users` reference to be inserted into the map. On destruction, since a new entry was created from one that was already freed, a double-free error occurred.
Fixed issue by re-fetching the iterator after the mutation of the container.
Differential Revision: https://reviews.llvm.org/D129345
Craig Topper [Fri, 8 Jul 2022 16:54:48 +0000 (09:54 -0700)]
[RISCV] Mark (s/u)min_vl and (s/u)max_vl as commutable.
Craig Topper [Fri, 8 Jul 2022 16:47:43 +0000 (09:47 -0700)]
[RISCV] Add fixed vector vmin(u).vx and vmax(u).vx tests. NFC
Simon Pilgrim [Fri, 8 Jul 2022 16:59:10 +0000 (17:59 +0100)]
[X86] Regenerate vec_shift6.ll to remove superfluous whitespace. NFC
Arthur Eubanks [Fri, 8 Jul 2022 16:48:41 +0000 (09:48 -0700)]
[gn build] Manually port
d2ead9e3
Slava Zakharin [Fri, 1 Jul 2022 21:22:29 +0000 (14:22 -0700)]
[flang] Changed lowering for allocatable assignment to make array-value-copy correct.
Array-value-copy fails to generate a temporary array for case like this:
subroutine bug(b)
real, allocatable :: b(:)
b = b(2:1:-1)
end subroutine
Since LHS may need to be reallocated, lowering produces the following FIR:
%rhs_load = fir.array_load %b %slice
%lhs_mem = fir.if %b_is_allocated_with_right_shape {
fir.result %b
} else {
%new_storage = fir.allocmem %rhs_shape
fir.result %new_storage
}
%lhs = fir.array_load %lhs_mem
%loop = fir.do_loop {
....
}
fir.array_merge_store %lhs, %loop to %lhs_mem
// deallocate old storage if reallocation occured,
// and update b descriptor if needed.
Since %b in array_load and %lhs_mem in array_merge_store are not the same SSA
values, array-value-copy does not detect the conflict and does not produce
a temporary array. This causes incorrect result in runtime.
The suggested change in lowering is to generate this:
%rhs_load = fir.array_load %b %slice
%lhs_mem = fir.if %b_is_allocated_with_right_shape {
%lhs = fir.array_load %b
%loop = fir.do_loop {
....
}
fir.array_merge_store %lhs, %loop to %b
fir.result %b
} else {
%new_storage = fir.allocmem %rhs_shape
%lhs = fir.array_load %new_storage
%loop = fir.do_loop {
....
}
fir.array_merge_store %lhs, %loop to %new_storage
fir.result %new_storage
}
// deallocate old storage if reallocation occured,
// and update b descriptor if needed.
Note that there are actually 3 branches in FIR, so the assignment loops
are currently produced in three copies, which is a code-size issue.
It is possible to generate just two branches with two copies of the loops,
but it is not addressed in this change-set.
Differential Revision: https://reviews.llvm.org/D129314
Florian Hahn [Fri, 8 Jul 2022 16:33:17 +0000 (09:33 -0700)]
[VPlan] Move VPWidenSelectRecipe::execute to VPlanRecipes.cpp (NFC).
Depends on D127968.
Reviewed By: Ayal
Differential Revision: https://reviews.llvm.org/D127970
Nikolas Klauser [Fri, 8 Jul 2022 16:17:26 +0000 (18:17 +0200)]
[libc++] Make parameter names consistent and enforce the naming style using readability-identifier-naming
Ensure that parameter names have the style `__lower_case`
Reviewed By: ldionne, #libc
Spies: aheejin, sstefan1, libcxx-commits, miyuki
Differential Revision: https://reviews.llvm.org/D129051
Matt Arsenault [Tue, 12 Apr 2022 16:41:16 +0000 (12:41 -0400)]
AArch64/GlobalISel: Stop using legal s1 values
As far as I can tell treating s1 values as legal makes no sense. There
are no allocatable 1-bit registers. SelectionDAG legalizes the usual
set of boolean operations to 32-bits, and this should do the
same. This avoids some special case handling in the selector of s1
values, and some extra code to look through truncates.
This makes some code worse at -O0, since nothing cleans up the and 1
the artifact combiner inserts. We could probably add some
non-essential combines or teach the artifact combiner to elide
intermediates betweeen boolean uses and defs.
Matt Arsenault [Tue, 12 Apr 2022 13:27:33 +0000 (09:27 -0400)]
GlobalISel: Add buildBoolExtInReg helper
Matt Arsenault [Sat, 9 Apr 2022 18:22:31 +0000 (14:22 -0400)]
GlobalISel: Allow forming atomic/volatile G_SEXTLOAD
Mirror the change to G_ZEXTLOAD.
Matt Arsenault [Sat, 9 Apr 2022 18:06:04 +0000 (14:06 -0400)]
GlobalISel: Allow forming atomic/volatile G_ZEXTLOAD
SelectionDAG has a target hook, getExtendForAtomicOps, which it uses
in the computeKnownBits implementation for ATOMIC_LOAD. This is pretty
ugly (as is having a separate load opcode for atomics), so instead
allow making use of atomic zextload. Enable this for AArch64 since the
DAG path defaults in to the zext behavior.
The tablegen changes are pretty ugly, but partially helps migrate
SelectionDAG from using ISD::ATOMIC_LOAD to regular ISD::LOAD with
atomic memory operands. For now the DAG emitter will emit matchers for
patterns which the DAG will not produce.
I'm still a bit confused by the intent of the isLoad/isStore/isAtomic
bits. The DAG implementation rejects trying to use any of these in
combination. For now I've opted to make the isLoad checks also check
isAtomic, although I think having isLoad and isAtomic set on these
makes most sense.
Joseph Huber [Fri, 8 Jul 2022 15:50:41 +0000 (11:50 -0400)]
[Clang] Fix test failing due to renamed arg
Nikita Popov [Fri, 8 Jul 2022 15:43:55 +0000 (17:43 +0200)]
[ConstantFolding] Guard against unfolded FP binop
Check that the operation actually folded before trying to flush
denormals. A minor variation of the pr33453 test exposed this
with the FP binops marked as undesirable.
Joseph Huber [Fri, 8 Jul 2022 15:37:15 +0000 (11:37 -0400)]
[LinkerWrapper] Fix save-temps and argument name
Summary:
The previous path reworked some handling of temporary files which
exposed some bugs related to capturing local state by reference in the
callback labmda. Squashing this by copying in everything instead. There
was also a problem where the argument name was changed for
`--bitcode-library=` but clang still used `--target-library=`.
Nikita Popov [Fri, 8 Jul 2022 15:19:04 +0000 (17:19 +0200)]
[InstCombine] Avoid ConstantExpr::get() in vector binop fold (NFCI)
Use the ConstantFoldBinaryOpOperands() API instead. This case
would bail out on a non-folded result anyway.
Joseph Huber [Fri, 8 Jul 2022 15:00:14 +0000 (11:00 -0400)]
[LinkerWrapper][NFC] Move error handling to a common function
Summary:
This patch merges all the error handling functions to a single function
call so we don't define the same lambda many times.
Joseph Huber [Thu, 7 Jul 2022 02:58:52 +0000 (22:58 -0400)]
[LinkerWrapper][NFC] Rework command line argument handling in the linker wrapper
Summary:
This patch reworks the command line argument handling in the linker
wrapper from using the LLVM `cl` interface to using the `Option`
interface with TableGen. This has several benefits compared to the old
method.
We use arguments from the linker arguments in the linker
wrapper, such as the libraries and input files, this allows us to
properly parse these. Additionally we can now easily set up aliases to
the linker wrapper arguments and pass them in the linker input directly.
That is, pass an option like `cuda-path=` as `--offload-arg=cuda-path=`
in the linker's inputs. This will allow us to handle offloading
compilation in the linker itself some day. Finally, this is also a much
cleaner interface for passing arguments to the individual device linking
jobs.
Nikita Popov [Fri, 8 Jul 2022 15:11:08 +0000 (17:11 +0200)]
[InstCombine] Avoid ConstantExpr::get() call
Avoid calling ConstantExpr::get() for associative/commutative
binops, call ConstantFoldBinaryOpOperands() instead. We only
want to perform the reassociation of the constants actually fold.
Simon Pilgrim [Fri, 8 Jul 2022 15:08:22 +0000 (16:08 +0100)]
[DAG] SimplifyDemandedBits - fold AND(INSERT_SUBVECTOR(C,X,I),M) -> INSERT_SUBVECTOR(AND(C,M),X,I)
If all the demanded bits of the AND mask covering the inserted subvector 'X' are known to be one, then the mask isn't affecting the subvector at all.
In which case, if the base vector 'C' is undef/constant, then move the AND mask up to just (constant) fold it directly.
Addresses some of the regressions from D129150, particularly the cases where we're attempting to zero the upper elements of a widened vector.
Differential Revision: https://reviews.llvm.org/D129290
Ye Luo [Fri, 8 Jul 2022 13:52:08 +0000 (08:52 -0500)]
[libomptarget] compile DeviceRTL bc files with -O3
bc files of DeviceRTL are compiled with -O3, the same as the static library.
Differential Revision: https://reviews.llvm.org/D129344
Nikita Popov [Fri, 8 Jul 2022 14:37:34 +0000 (16:37 +0200)]
[ConstantExpr] Don't create float binop expressions
Mark the fadd, fsub, fmul, fdiv, and frem expressions as
undesirable, so they are not created automatically. This is in
preparation for their removal.
Nikita Popov [Fri, 8 Jul 2022 14:04:21 +0000 (16:04 +0200)]
[InstCombine] Avoid creating float binop ConstantExprs
Replace ConstantExpr:getFAdd etc with call to
ConstantFoldBinaryOpOperands(). I'm using the constant folding API
rather than IRBuilder here to ensure that this does actually
constant fold. These transforms don't use m_ImmConstant(), so this
would not otherwise be guaranteed (and apparently, they can't use
m_ImmConstant because they want to handle scalable vector splats).
There is an opportunity here to further migrate these to the
ConstantFoldFPInstOperands() API, which would respect the denormal
mode. I've held off on doing so here, because some of this code
explicitly checks for denormal results, and I don't want to touch
it in a mostly NFC change.
Sanjay Patel [Fri, 8 Jul 2022 13:52:57 +0000 (09:52 -0400)]
[InstCombine] enhance fold for subtract-from-constant -> xor
A low-bit mask is not required:
https://alive2.llvm.org/ce/z/yPShss
This matches the SDAG implementation that was updated at:
8b756713140f
Sanjay Patel [Fri, 8 Jul 2022 12:35:36 +0000 (08:35 -0400)]
[InstCombine] add tests for masked sub; NFC
Valentin Clement [Fri, 8 Jul 2022 14:01:34 +0000 (16:01 +0200)]
[flang][openacc][NFC] Extract device_type parser to its own
Move the device_type parser to a separate parser AccDeviceTypeExprList. Preparatory work for D106968.
Reviewed By: kiranchandramohan
Differential Revision: https://reviews.llvm.org/D106967
Valentin Clement [Fri, 8 Jul 2022 13:44:48 +0000 (15:44 +0200)]
[flang][openacc][NFC] Make self clause value optional in ACC.td and extract the parser
Set the isOptional flag for the self clause. Move the optional and parenthesis part of the parser. Update the rest of the code to deal with the optional value.
Preparatory work for D106968.
Reviewed By: kiranchandramohan
Differential Revision: https://reviews.llvm.org/D106965
Cullen Rhodes [Fri, 8 Jul 2022 12:55:52 +0000 (12:55 +0000)]
[AArch64] Use Neoverse N2 sched model as default for:
- Cortex-A710
- Cortex-X2
- Neoverse-V1
- Neoverse-512tvb
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D129203
Daniil Fukalov [Fri, 8 Jul 2022 13:06:45 +0000 (16:06 +0300)]
[LiveIntervals] Fix incorrect range (re)construction from subranges.
After D82916 `updateAllRanges()` started to fix holes in main range with
subranges but it fails on instructions with two subregs def which are parts of
one reg. The main range constructed with //all// subranges of subregs just after
processing the first operand. So the main range gets intervals from subranges
those are not updated yet.
The patch takes into account lane mask to update the main range.
Reviewed By: rampitec, arsenm
Differential Revision: https://reviews.llvm.org/D128553
LLVM GN Syncbot [Fri, 8 Jul 2022 12:39:02 +0000 (12:39 +0000)]
[gn build] Port
1cdec6c96e85
Louis Dionne [Thu, 7 Jul 2022 18:07:37 +0000 (14:07 -0400)]
[libc++] Re-apply the use of ABI tags to provide per-TU insulation
This commit re-applies
9ee97ce3b830, which was reverted by
61d417ce
because it broke the LLDB data formatter tests. It also re-applies
6148c79a (the manual GN change associated to it).
Differential Revision: https://reviews.llvm.org/D127444
Phoebe Wang [Fri, 8 Jul 2022 11:11:33 +0000 (19:11 +0800)]
[X86][FP16] Add constrained FP support for scalar emulation
This is a follow up patch to support constrained FP in FP16 emulation.
Reviewed By: skan
Differential Revision: https://reviews.llvm.org/D128114
Hui Xie [Sun, 26 Jun 2022 15:13:43 +0000 (16:13 +0100)]
[libcxx][ranges] implement `std::ranges::set_difference`
implement `std::ranges::set_difference`
reused classic std::set_difference
added unit tests
Differential Revision: https://reviews.llvm.org/D128983
Sanjay Patel [Fri, 8 Jul 2022 12:13:14 +0000 (08:13 -0400)]
[SDAG] try to replace subtract-from-constant with xor
This is almost the same as the abandoned D48529, but it
allows splat vector constants too.
This replaces the x86-specific code that was added with
the alternate patch D48557 with the original generic
combine.
This transform is a less restricted form of an existing
InstCombine and the proposed SDAG equivalent for that
in D128080:
https://alive2.llvm.org/ce/z/OUm6N_
Differential Revision: https://reviews.llvm.org/D128123
Aaron Ballman [Fri, 8 Jul 2022 11:34:18 +0000 (07:34 -0400)]
Disable clang-format entirely for test directories
See discussion here:
https://github.com/llvm/llvm-project/issues/55982
And the RFC here:
https://discourse.llvm.org/t/rfc-disable-clang-format-in-the-clang-test-tree/63498/2
We don't generally expect test files to be formatted according to the
style guide. Indeed, some tests may require specific formatting for the
purposes of the test.
When tests intentionally do not conform to the "correct" formatting,
this causes errors in the CI, which can drown out real errors and causes
people to stop trusting the CI over time.
From the history of the clang/test/.clang-format file, it looks as if
there have been attempts to make clang-format do a subset of formatting
that would be useful for tests. However, it looks as if it's hard to
make clang-format do exactly the right thing -- see the back-and-forth
between
13316a7
and
7b5bddf.
These changes disable the .clang-format file for clang/test, llvm/test,
and clang-tools-extra/test.
Fixes #55982
Differential Revision: https://reviews.llvm.org/D128706
Aaron Ballman [Fri, 8 Jul 2022 11:23:40 +0000 (07:23 -0400)]
Fix the Clang sphinx bot
This should resolve the issues with:
https://lab.llvm.org/buildbot/#/builders/92/builds/29439
OCHyams [Fri, 8 Jul 2022 08:33:41 +0000 (09:33 +0100)]
[NFC][SelectionDAG] Fix debug prints in salvageUnresolvedDbgValue
The prints are printing pointer values - fix by dereferencing the pointers.
Nikita Popov [Fri, 8 Jul 2022 11:04:00 +0000 (13:04 +0200)]
[PhaseOrdering] Add test for IndVars + SROA interaction (NFC)
Jay Foad [Fri, 8 Jul 2022 10:44:23 +0000 (11:44 +0100)]
[AMDGPU] Add GFX11 test coverage sharing checks with GFX10
David Green [Fri, 8 Jul 2022 10:38:00 +0000 (11:38 +0100)]
[AArch64] Remove incorrect use of DemandElts
This call to computeKnownBits was passing in a 0xff mask, looking like
it was expecting it to be used as a DemandBits, not a DemandElts mask.
serge-sans-paille [Fri, 8 Jul 2022 10:13:28 +0000 (12:13 +0200)]
[lldb/test] Disable TestStringLiteralExpr.test on Windows
This test, introduced by
b042d15d2e39eea528c51a30fe637b9ea84250d3, fails on
https://lab.llvm.org/buildbot/#/builders/83/builds/20933/steps/7/logs/stdio
but succeeds on other targets, see for instance
https://lab.llvm.org/buildbot/#/builders/68/builds/35462/steps/6/logs/stdio
This test is not be arch specific, just disabling it on Windows.
Kito Cheng [Fri, 8 Jul 2022 09:01:44 +0000 (17:01 +0800)]
[RISCV] Fix wrong register rename for store value during make-compressible optimization
Current implementation will rename both register in store instructions if
we store base address into memory with same base register, it's OK if
the offset is 0, however that is wrong transform if offset isn't 0, give
a smalle example here:
sd a0, 808(a0)
We should not transform into:
addi a2, a0, 768
sd a2, 40(a2)
That should just rename base address like this:
addi a2, a0, 768
sd a0, 40(a2)
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D128876
Jay Foad [Fri, 8 Jul 2022 09:55:21 +0000 (10:55 +0100)]
[AMDGPU] More GFX11 coverage for tests with generated checks
Cullen Rhodes [Fri, 8 Jul 2022 09:16:30 +0000 (09:16 +0000)]
[AArch64] Initial sched model for Neoverse N2
The optimization guide can be found here:
https://developer.arm.com/documentation/PJDOC-
466751330-18256/latest/
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D128631
Andrew Ng [Thu, 30 Jun 2022 17:55:53 +0000 (18:55 +0100)]
[Support] Fix Windows dump file hang with multi-threaded crashes
Prevents deadlock between MiniDumpWriteDump and
CryptAcquireContextW (called via fs::createTemporaryFile) in
WriteWindowsDumpFile.
However, there's no guarantee that deadlock can't still occur between
MiniDumpWriteDump and some other Win32 API call. But that would appear
to be the "accepted" risk of using MiniDumpWriteDump in this manner.
Differential Revision: https://reviews.llvm.org/D129004
Weining Lu [Fri, 8 Jul 2022 08:59:25 +0000 (16:59 +0800)]
[LoongArch] Add codegen support for multiplication operations
Reference:
https://llvm.org/docs/LangRef.html#mul-instruction
Differential Revision: https://reviews.llvm.org/D128194
zhongyunde [Fri, 8 Jul 2022 09:03:17 +0000 (17:03 +0800)]
[IndVars] Eliminate redundant type cast between integer and float
Recompute the range: match for fptosi of sitofp, and then query the range of the input to the sitofp
according the comment on D129140.
Fixes https://github.com/llvm/llvm-project/issues/55505.
Reviewed By: nikic
Differential Revision: https://reviews.llvm.org/D129191
Kito Cheng [Fri, 8 Jul 2022 09:00:53 +0000 (17:00 +0800)]
[RISCV] Precommit testcase to show wrong result of make-compressible optimization
Use following example to demo what happened now:
li a1, 1
sd a1, 800(a0)
sd a0, 808(a0) # Store base address into base + offset
li a1, 2
sd a1, 816(a0)
Current will optimizate into:
li a1, 1
addi a2, a0, 768
sd a1, 32(a2)
sd a2, 40(a2) # Wrong replacement for the source register.
li a1, 2
sd a1, 48(a2)
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D128875
Jay Foad [Fri, 8 Jul 2022 08:39:02 +0000 (09:39 +0100)]
[AMDGPU] Add GFX11 coverage to shared sdag/gisel tests
Petar Avramovic [Wed, 6 Jul 2022 12:49:07 +0000 (14:49 +0200)]
[AArch64][GlobalISel] Fix call lowering for <3 x i32> vector arguments
Differential Revision: https://reviews.llvm.org/D129194
Sergei Barannikov [Fri, 8 Jul 2022 08:18:43 +0000 (09:18 +0100)]
[SelectionDAG] computeKnownBits / ComputeNumSignBits for the remaining overflow-aware nodes
Some overflow-aware nodes were missing from the switches in
computeKnownBits and ComputeNumSignBits.
Jay Foad [Wed, 6 Jul 2022 11:14:57 +0000 (12:14 +0100)]
[AMDGPU] Add GFX11 test coverage
Add GFX11 test coverage to a bunch of tests where it was easy to do so,
mostly because the checks are autogenerated and/or GFX11 can share the
same checks as GFX10.
Differential Revision: https://reviews.llvm.org/D129295
Jesus Checa Hidalgo [Fri, 8 Jul 2022 08:00:13 +0000 (10:00 +0200)]
[lldb/test] Add Shell/Expr/TestStringLiteralExpr.test
This test should exercise the usage of expressions containing
string literals and ensure that lldb doesn't crash.
Differential Revision: https://reviews.llvm.org/D129261
Nicolas Vasilache [Fri, 8 Jul 2022 06:40:17 +0000 (23:40 -0700)]
[mlir][Transform] Fix isDefiniteFailure helper
This newly added helper was returning definiteFailure even in the case of silenceableFailure.
Differential Revision: https://reviews.llvm.org/D129347
ChenYang Li [Fri, 8 Jul 2022 07:29:17 +0000 (09:29 +0200)]
[JumpThreading] Avoid threadThroughTwoBasicBlocks when PredPred BB ends with indirectbranch
Since we can't change the destination of indirectbr, so when
encounter indirectbr as PredPredBB terminator, we should pass it.
Differential Revision: https://reviews.llvm.org/D129193
Nikita Popov [Fri, 8 Jul 2022 07:24:11 +0000 (09:24 +0200)]
[CallSiteSplitting] Regenerate test checks (NFC)
This test requires --function-signature to work with unmodified UTC.
Nikita Popov [Thu, 7 Jul 2022 07:32:36 +0000 (09:32 +0200)]
[BasicBlockUtils] Allow critical edge splitting with callbr terminators
After D129205, we support SplitBlockPredecessors() for predecessors
with callbr terminators. This means that it is now also safe to
invoke critical edge splitting for an edge coming from a callbr
terminator. Remove checks in various passes that were protecting
against that.
Differential Revision: https://reviews.llvm.org/D129256
Nikita Popov [Thu, 7 Jul 2022 07:54:09 +0000 (09:54 +0200)]
[UpdateTestChecks] Remove outdated help text
Manually modifying the result of update_test_checks.py is discouraged,
we prefer unmodified check lines where possible. The output is also
considered authoritative nowadays, at least for tests targeting core
middle-end components, where not using it is an automatic review
rejection.
Differential Revision: https://reviews.llvm.org/D129259
Martin Storsjö [Thu, 7 Jul 2022 06:49:25 +0000 (09:49 +0300)]
[libcxx] Make LIBCXX_HERMETIC_STATIC_LIBRARY apply to libc++experimental too
This avoids dllexports in that library.
Differential Revision: https://reviews.llvm.org/D129271
Chuanqi Xu [Fri, 8 Jul 2022 06:32:33 +0000 (14:32 +0800)]
[NFC] Move isSameDefaultTemplateArgument into ASTContext
Move isSameDefaultTemplateArgument into ASTContext to keep consistent
with other ASTContext:isSame* methods.
Craig Topper [Fri, 8 Jul 2022 06:25:21 +0000 (23:25 -0700)]
[SLP] Add missing space to optimization remark.
Reviewed By: vporpo
Differential Revision: https://reviews.llvm.org/D129330
Lian Wang [Wed, 29 Jun 2022 01:38:25 +0000 (01:38 +0000)]
[RISCV] Change VECTOR_SPLICE mask operation from expand to promote
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D128717
Johannes Doerfert [Fri, 8 Jul 2022 05:53:38 +0000 (00:53 -0500)]
Revert "[Attributor] Replace AAValueSimplify with AAPotentialValues"
This reverts commit
f17639ea0cd30f52ac853ba2eb25518426cc3bb8 as three
AMDGPU tests haven't been updated. Will need to verify the changes are
not regressions we should avoid.
Johannes Doerfert [Tue, 21 Jun 2022 15:30:10 +0000 (10:30 -0500)]
[Attributor] Replace AAValueSimplify with AAPotentialValues
For the longest time we used `AAValueSimplify` and
`genericValueTraversal` to determine "potential values". This was
problematic for many reasons:
- We recomputed the result a lot as there was no caching for the 9
locations calling `genericValueTraversal`.
- We added the idea of "intra" vs. "inter" procedural simplification
only as an afterthought. `genericValueTraversal` did offer an option
but `AAValueSimplify` did not. Thus, we might end up with "too much"
simplification in certain situations and then gave up on it.
- Because `genericValueTraversal` was not a real `AA` we ended up with
problems like the infinite recursion bug (#54981) as well as code
duplication.
This patch introduces `AAPotentialValues` and replaces the
`AAValueSimplify` uses with it. `genericValueTraversal` is folded into
`AAPotentialValues` as are the instruction simplifications performed in
`AAValueSimplify` before. We further distinguish "intra" and "inter"
procedural simplification now.
`AAValueSimplify` was not deleted as we haven't ported the
re-materialization of instructions yet. There are other differences over
the former handling, e.g., we may not fold trivially foldable
instructions right now, e.g., `add i32 1, 1` is not folded to `i32 2`
but if an operand would be simplified to `i32 1` we would fold it still.
We are also even more aware of function/SCC boundaries in CGSCC passes,
which is good even if some tests look like they regress.
Fixes: https://github.com/llvm/llvm-project/issues/54981
Note: A previous version was flawed and consequently reverted in
6555558a80589d1c5a1154b92cc3af9495f8f86c.
Abinav Puthan Purayil [Sun, 8 May 2022 18:09:49 +0000 (23:39 +0530)]
[AMDGPU] Use the HasNoUse predicate for no-ret atomic op selection
This change replaces the C++ predicates with the HasNoUse builtin
predicate that would enable the no-ret atomic op selection in
GlobalISel.
Differential Revision: https://reviews.llvm.org/D125213
Abinav Puthan Purayil [Sun, 8 May 2022 15:54:52 +0000 (21:24 +0530)]
[GlobalISel][SelectionDAG] Implement the HasNoUse builtin predicate
This change introduces the HasNoUse builtin predicate in PatFrags that
checks for the absence of use of the first result operand.
GlobalISelEmitter will allow source PatFrags with this predicate to be
matched with destination instructions with empty outs. This predicate is
required for selecting the no-return variant of atomic instructions in
AMDGPU.
Differential Revision: https://reviews.llvm.org/D125212
Abinav Puthan Purayil [Mon, 20 Jun 2022 09:18:14 +0000 (14:48 +0530)]
[AMDGPU] Use AddedComplexity for ret and noret atomic ops selection
This patch removes the predicate for return atomic ops and uses
AddedComplexity to distinguish its selection from its no return variant.
This will produce better matchers that doesn't unnecessarily check for
the negated predicate if the initial predicate failed. Also, it
simplifies the enabling of no return atomic ops selection in GlobalISel.
Differential Revision: https://reviews.llvm.org/D128241
Mogball [Mon, 27 Jun 2022 20:46:29 +0000 (13:46 -0700)]
[mlir] Delete ForwardDataFlowAnalysis
With SCCP and integer range analysis ported to the new framework, this old framework is redundant. Delete it.
Depends on D128866
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D128867
Chuanqi Xu [Mon, 13 Jun 2022 09:40:45 +0000 (17:40 +0800)]
[docs] Add document "Debugging C++ Coroutines"
Previously in D99179, I tried to construct debug information for
coroutine frames in the middle end to enhance the debugability for
coroutines. But I forget to add ReleaseNotes to hint people and
documents to help people to use. My bad. @probinson revealed this in
https://github.com/llvm/llvm-project/issues/55916.
So I try to add the use document now.
Reviewed By: erichkeane
Differential Revision: https://reviews.llvm.org/D127626
Mogball [Thu, 23 Jun 2022 19:03:27 +0000 (19:03 +0000)]
[mlir] Swap integer range inference to the new framework
Integer range inference has been swapped to the new framework. The integer value range lattices automatically updates the corresponding constant value on update.
Depends on D127173
Reviewed By: krzysz00, rriddle
Differential Revision: https://reviews.llvm.org/D128866
Chuanqi Xu [Fri, 8 Jul 2022 03:10:49 +0000 (11:10 +0800)]
[C++20] [Modules] Don't complain about duplicated default template argument across modules
See https://github.com/cplusplus/draft/pull/5204 for a detailed
background.
Simply, the test redundant-template-default-arg.cpp attached to this
patch should be accepted instead of being complained about the
redefinition.
Reviewed By: urnathan, rsmith, ChuanqiXu
Differential Revision: https://reviews.llvm.org/D118034
lewuathe [Fri, 8 Jul 2022 02:30:26 +0000 (04:30 +0200)]
[mlir][complex] Lower complex.angle to libm
complex.angle corresponds to arg function in libm. We can lower complex.angle to arg and argf.
Reviewed By: pifon2a
Differential Revision: https://reviews.llvm.org/D129341
Haohai Wen [Fri, 8 Jul 2022 02:27:02 +0000 (10:27 +0800)]
[X86] Fix collectLeaves for adds used by phi that forms loop
When add has additional users, we should indentify whether add's
user is phi that forms loop rather than root's.
Reviewed By: LuoYuanke
Differential Revision: https://reviews.llvm.org/D129169
Lian Wang [Fri, 8 Jul 2022 02:19:46 +0000 (02:19 +0000)]
[RISCV] Recommit test for D128717
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D128778
Phoebe Wang [Fri, 8 Jul 2022 00:13:29 +0000 (17:13 -0700)]
[X86][FP16] Fix crash when lowering copysign for f16
This is to address the assertion fail reported in https://reviews.llvm.org/D107082#3635612
Not sure if it is a problem of promoting FCOPYSIGN + libcall FP_ROUND.
The promoting will set the rounding mode to 1 https://github.com/llvm/llvm-project/blob/
a442c628882eb07fffff8c9f7c87a317af14555a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp#L4810-L4814
While libcall cannot handle the rounding mode equals to 1 https://github.com/llvm/llvm-project/blob/
a442c628882eb07fffff8c9f7c87a317af14555a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp#L4324-L4328
So changing the action to Expand to workaround the problem.
Reviewed By: clementval, MaskRay
Differential Revision: https://reviews.llvm.org/D129294
Lian Wang [Fri, 8 Jul 2022 01:56:29 +0000 (01:56 +0000)]
Revert "[RISCV] Precommit test for D128717"
This reverts commit
b3b37f3ecfd6be665c385455561603bdfc7d6c76.
Lian Wang [Wed, 29 Jun 2022 02:44:02 +0000 (02:44 +0000)]
[RISCV] Precommit test for D128717
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D128778
Eric Astor [Thu, 7 Jul 2022 15:59:41 +0000 (11:59 -0400)]
[ms] [llvm-ml] Add support for the remaining binary named operators
Finish adding support for the remaining binary named operators in expression context: XOR, SHL, and SHR.
Differential Revision: https://reviews.llvm.org/D129299