intel/compiler: Use nir_lower_tex_options::lower_offset_filter for tg4 on XeHP

Based on Rafael's:
 * "nir/lower_tex: Add option to lower offset for tg4 too."
 * "intel/compiler: Lower offsets for tg4 on gen9+."
 * "WIP: Do not lower basic offsets."
 * "WIP: intel/compiler: Enable lowering offsets restriction."

But, with these changes:
 * Fixed range checking to be signed 4 bits
 * Converted to filter
 * Apply only to gfx12.5+
 * Use nir_src_is_const / nir_src_comp_as_int (s-b Jason)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14142>

nir/lower_tex: Add filter for tex offset lowering

Rework:
 * Add callback_data (s-b Jason)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14142>

iris: Align buffer VMA to 2MiB for XeHP

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14155>

anv: Align buffer VMA to 2MiB for XeHP

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14155>

iris: Not all gfx12+ have aux_map_ctx

This code matches other similar cases in iris.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14152>

glapi: Never use dllimport/dllexport for TLS vars on Windows

Fixes: c691149f ("win32: Fixes thread local on win32 with clang/mingw")
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14162>

radv,aco: don't lower some ffma instructions

GFX10.3 has no v_mad_f32 and we can't recombine exact ffma into a
v_fma_f32 if they're split. GFX9+ only has v_fma_f16 and no generation has
a 64-bit MAD.

fossil-db (GFX10.3):
Totals from 84040 (57.46% of 146267) affected shaders:
VGPRs: 3717256 -> 3688064 (-0.79%); split: -0.87%, +0.08%
SpillSGPRs: 10419 -> 10403 (-0.15%)
CodeSize: 263064884 -> 262442820 (-0.24%); split: -0.31%, +0.07%
MaxWaves: 2036908 -> 2038374 (+0.07%); split: +0.10%, -0.03%
Instrs: 49849448 -> 49572182 (-0.56%); split: -0.60%, +0.04%
Latency: 908130602 -> 907764246 (-0.04%); split: -0.18%, +0.14%
InvThroughput: 207051300 -> 206762704 (-0.14%); split: -0.24%, +0.10%

fossil-db (GFX10):
Totals from 2 (0.00% of 146267) affected shaders:
Latency: 8123 -> 8107 (-0.20%)

fossil-db (GFX9):
Totals from 2 (0.00% of 146401) affected shaders:
(no statistics affected)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9805>

radv,aco: implement nir_op_ffma

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9805>

aco: swap multiplication operands if needed to create v_fmac_f32/etc

For v_pk_fma_f32 and v_fma_f32 from nir_op_ffma, we don't try to put
scalars in the first operand.

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9805>

aco: swap operands if necessary to create v_madak/v_fmaak

Also rewrite the check_literal logic to be more straightforward.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9805>

aco: create v_fmamk_f32/v_fmaak_f32 from nir_op_ffma

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9805>

aco: use more predictable tiebreaker when forming MADs

fossil-db (GFX10.3):
Totals from 84981 (58.10% of 146267) affected shaders:
VGPRs: 3829896 -> 3820480 (-0.25%); split: -0.33%, +0.08%
CodeSize: 270860472 -> 270850132 (-0.00%); split: -0.08%, +0.08%
MaxWaves: 2035822 -> 2042516 (+0.33%); split: +0.39%, -0.06%
Instrs: 51285526 -> 51308869 (+0.05%); split: -0.03%, +0.08%
Latency: 931503706 -> 932556231 (+0.11%); split: -0.19%, +0.30%
InvThroughput: 217084232 -> 217070849 (-0.01%); split: -0.12%, +0.11%

fossil-db (GFX10):
Totals from 85520 (58.47% of 146267) affected shaders:
VGPRs: 3729132 -> 3725344 (-0.10%); split: -0.21%, +0.10%
CodeSize: 272796500 -> 272783084 (-0.00%); split: -0.09%, +0.08%
MaxWaves: 2246410 -> 2249012 (+0.12%); split: +0.17%, -0.05%
Instrs: 51643962 -> 51664865 (+0.04%); split: -0.04%, +0.08%
Latency: 932331949 -> 933274979 (+0.10%); split: -0.19%, +0.29%
InvThroughput: 214187040 -> 214130994 (-0.03%); split: -0.13%, +0.11%

fossil-db (GFX9):
Totals from 84619 (57.80% of 146401) affected shaders:
SGPRs: 5366240 -> 5366944 (+0.01%); split: -0.09%, +0.10%
VGPRs: 3765608 -> 3764972 (-0.02%); split: -0.23%, +0.22%
CodeSize: 263634732 -> 263616320 (-0.01%); split: -0.08%, +0.08%
MaxWaves: 546617 -> 547091 (+0.09%); split: +0.18%, -0.09%
Instrs: 51426195 -> 51458334 (+0.06%); split: -0.03%, +0.10%
Latency: 1164445660 -> 1161923480 (-0.22%); split: -0.46%, +0.24%
InvThroughput: 542964697 -> 542329595 (-0.12%); split: -0.26%, +0.14%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9805>

radv: ignore dynamic inheritance if the render pass isn't NULL

From the Vulkan spec:

    "If the pNext chain of VkCommandBufferInheritanceInfo includes a
     VkCommandBufferInheritanceRenderingInfoKHR structure, then that
     structure controls parameters of dynamic render pass instances
     that the VkCommandBuffer can be executed within. If
     VkCommandBufferInheritanceInfo::renderPass is not VK_NULL_HANDLE,
     or VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT is not
     specified in VkCommandBufferBeginInfo::flags, parameters of this
     structure are ignored."

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14109>

radv: fix dynamic rendering inheritance if the subpass index isn't 0

The driver will always create only one subpass in the render pass
for inheritance but the subpass index isn't always zero.

This fixes dEQP-VK.multiview.dynamic_rendering.secondary_cmd_buffer*.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14109>

radv: enable lower_lod_zero_width

This fixes dEQP-VK.glsl.texture_functions.query.texturequerylod.*.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14147>

nir/lower_tex: add lower_lod_zero_width

On AMD, the hardware will return 0 for the raw LOD if the sum of the
absolute values of derivatives is 0 but Vulkan expects the value to
be in the [-inf, -22.0f] range.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14147>

radeonsi: use max_zplanes after the last write

Fixes: c0f723ce2b8 ("radeonsi: allow and finish TC-compatible MSAA HTILE")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14089>

radeonsi: silence a warning

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14089>

radeonsi: fix fast clear / depth decompression corruption

Insert a flush after a depth decompression pass if the texture
was fast cleared.
This fixes a corruption which seems to only affect gfx10.3 chips.

Ideally we should also clear tex->need_flush_after_depth_decompression
after a flush but there's no easy way for this so this commit will
introduce extra flushes.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14089>

nir: limit lower_clip_cull_distance_arrays input to traditional stages

Compute, task, mesh & raytracing stages don't support
ClipDistance/CullDistance as input.

This change is not needed for correctness. Just something I stumbled on.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14149>

v3dv: Fix V3DV_HAS_SURFACE preprocessor condition

Currently V3DV_HAS_SURFACE is always defined.
There is no WSI for Android in mesa3d, therefore WSI related extensions
should not be exposed.

1. Define V3DV_HAS_SURFACE only for platforms which has WSI implemented.
2. Rename V3DV_HAS_SURFACE -> V3DV_USE_WSI_PLATFORM to align naming
with other platforms.

Fixes dEQP-VK.wsi.android.surface#query_protected_capabilities

Fixes: 79e445143054 ("v3dv: move extensions table to v3dv_device")
Signed-off-by: Roman Stratiienko <roman.o.stratiienko@globallogic.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14144>

intel/compiler: Use a struct for brw_compile_bs parameters

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14139>

intel/compiler: Use a struct for brw_compile_gs parameters

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14139>

intel/compiler: Use a struct for brw_compile_tes parameters

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14139>

intel/compiler: Use a struct for brw_compile_tcs parameters

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14139>

crocus: cleanup bo exports for external objects

This might have led to a leak in firefox/webrender/webgl scenarios

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Fixes: f3630548f1da ("crocus: initial gallium driver for Intel gfx 4-7")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14167>

radeonsi: unroll loops of up to 128 iterations

It's not exactly 128 because longer loop bodies scale the number down.

This improves perf for VP13/Creo and Piano. Most other tests either didn't
show any difference or are CPU-bound.

v2:
- The lowering passes had to be moved to the optimization loop because unrolling creates lowerable variables.
- Piano has some pattern that looks like corruption and the pattern changed with loop unrolling.
  The pattern is present on other drivers as well.

v3:
- I removed the Piano test from CI traces because the image is random. The output was wrong even before
  this MR, and now it's randomly wrong.

|   PERCENTAGE DELTAS    |  Shaders |    SGPRs |    VGPRs |SpillSGPR |SpillVGPR | PrivVGPR |  Scratch | CodeSize | MaxWaves |
|------------------------|----------|----------|----------|----------|----------|----------|----------|----------|----------|
| alien_isolation        |      2936|    .     |    0.02 %|    .     |    .     |    .     |    .     |    0.83 %|    .     |
| deadcore               |        76|   18.47 %|    .     |    .     |    .     |    .     |    .     |  167.69 %|    .     |
| deus_ex_mankind_div..  |      1410|    0.10 %|    0.15 %|    .     |    .     |    .     |    .     |    1.70 %|    .     |
| f1-2015                |       775|    0.37 %|    0.16 %|    .     |    .     |    .     |    .     |    3.25 %|   -0.07 %|
| hitman                 |      1413|    0.10 %|   -0.03 %|    6.45 %|    .     |    .     |    .     |    0.61 %|    0.03 %|
| metro_2033_redux       |      2670|    .     |    .     |    .     |    .     |    .     |    .     |    0.13 %|    0.01 %|
| pixmark-piano-0.7.0    |         2|    .     |   14.29 %| -100.00 %|    .     |    .     |    .     |   78.07 %|   -4.76 %|
| reflections_subway     |        98|   -0.53 %|    .     |    .     |    .     |    .     |    .     |    7.64 %|    .     |
| thea                   |       172|    0.12 %|   -0.81 %|    .     |    .     |    .     |    .     |    0.65 %|    0.15 %|
| ubershaders            |        54|    .     |    .     |    .     |    .     |    .     |    .     |   61.13 %|    .     |
| ue4_effects_cave       |       290|    0.05 %|    .     |    .     |    .     |    .     |    .     |    2.62 %|    .     |
| vp13-creo              |        26|   -3.38 %|   -4.20 %|    .     |    .     |    .     |    .     |   88.56 %|    2.62 %|
| vp13-sw                |       100|   -0.36 %|   -9.14 %|    .     | -100.00 %|    .     | -100.00 %|  -17.97 %|    0.39 %|
| vp20-creo              |        22|   -0.82 %|   -3.33 %|    .     |    .     |    .     |    .     |   81.59 %|    1.51 %|
| vp20-sw                |       296|   -4.51 %|   -0.63 %|    .     |    .     |    .     |    .     |   58.93 %|    0.20 %|
|------------------------|----------|----------|----------|----------|----------|----------|----------|----------|----------|
| All affected           |       189|    3.05 %|   -2.87 %|  500.00 %| -100.00 %|    .     | -100.00 %|  135.61 %|    1.32 %|
|------------------------|----------|----------|----------|----------|----------|----------|----------|----------|----------|
| Total                  |     57794|    0.01 %|   -0.02 %|    0.27 %|   -3.13 %|    .     |   -2.89 %|    1.73 %|    .     |

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13966>

radeonsi: add shader profiles that disable binning

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13966>

radeonsi: print more stats for shader-db

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13966>

radeonsi: add Wave32 heuristics and shader profiles

This generally works well.

There are new cases that select Wave32, and there are shader profiles
which adjust that.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13966>

glsl: fix setting compiled_source_sha1 without a shader cache

We need to set it even if Cache == NULL.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13966>

nir: add nir_has_divergent_loop function

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13966>

nir: serialize divergent fields

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13966>

nir: disable a NIR test due to undebuggable & locally unreproducible CI failures

debian-vulkan but not any other CI pipeline consistently fails with:
    FileNotFoundError: [Errno 2] No such file or directory: 'nir_tests.xml'

I have to assume that either debian-vulkan is broken, or the NIR test
infrastructure is broken. That's not all. I got the same failure when
I wanted to add a new test, which means the CI is preventing us from adding
new NIR tests, which is a very serious problem with the CI or NIR tests.
The python error doesn't imply that it's a test failure, so something else
is broken. If you don't want such commits to happen again, print better
error messages.

See also the discussion in the MR.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13966>

nir: handle more intrinsics in divergence analysis

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13966>

drisw: do an MSAA resolve when copying the backbuffer

When calling glXCopySubBuffer, we must resolve the backbuffer before
copying it the frontbuffer.

Fixes piglit's glx/glx-copy-sub-buffer on virgl.

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11714>

virgl: flush cmd buffer when flushing frontbuffer

When a resource is multisampled, we usually submit a multisampling
resolving blit before we present it or use it in some other way, but
currently we don't always flush the cmd buffer before flushing the
frontbuffer, this commit fixes that.

Fixes piglit's glx/glx-copy-sub-buffer MSAA cases on vtest, in
conjunction with other commits of this series.

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11714>

virgl/vtest: implement resource_create_front

This is required for glXCopySubBufferMESA to work.

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11714>

virgl/vtest: use correct resource stride in flush_frontbuffer

The displaytarget's resource stride is alignment is currently 64-bytes,
where the shared resource stride is unaligned.

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11714>

util: Use ralloc for strings in cache test

Also avoid warnings about asprintf result not being checked.

Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14054>

util: Convert cache test to use gtest

Replace a bunch of helper functions for checking results with ones
from GTest.

Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14054>

intel/dev: Add gtt_size to devinfo

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13647>

anv: Stop doing too much per-sample shading

We were setting anv_pipeline::sample_shading_enable based on
sampleShadingEnable without looking at minSampleShading.  We would then
pass this value into nir_lower_wpos_center which would add sample_pos to
frag_coord.  Then the back-end compiler picks up on the existence of
sample_pos and forces persample dispatch.  This leads to doing
per-sample dispatch whenever sampleShadingEnable = VK_TRUE regardless of
the value of minSampleShading.  This is almost certainly costing us
perf somewhere.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14022>

iris: Update the initial CCS state on XeHP

We can't map the CCS on this platform to initialize it into the
PASS_THROUGH state. This can cause issues with optimizations in the
driver that rely on this state.

For example, after rendering to a surface with AUX_NONE, we can then
render to it with AUX_CCS_E without an ambiguate in between (if the CCS
in the PASS_THROUGH state). If that state was incorrect and the aux was
actually compressed, there can be rendering corruption because the
contents may be misinterpreted on the second render.

Use a more accurate initial aux state to avoid these issues.

One notable change in behavior here is that aux surfaces can be created
with fast-cleared blocks even though the caller may specify a modifier
that doesn't support fast clears. This should be fine, so long as all HW
units that can access these surfaces can handle that bit-pattern. We
haven't seen an applicable restriction yet.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>

iris: Modify the comment about zeroing CCS

Among other changes, we highlight the fact that we'll map the CCS -
something we can't do on XeHP.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>

iris: Don't assert a NULL aux BO during aux config

The assert was introduced in a function that allocated an auxiliary
surface BO, iris_resource_alloc_aux. After refactors, the function it's
in now, iris_resource_configure_aux, no longer does this allocation.
Drop the assert because its purpose is unclear and it's no longer
relevant for CCS on XeHP.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>

iris: Don't allocate and initialize CCS on XeHP

The memory for CCS on XeHP can't be mapped by the CPU.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>

iris: Drop row pitch param from iris_get_ccs_surf

This parameter won't be used for XeHP, because we can't directly control
the row pitch of the CCS independently from the main surface.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>

iris: Don't allocate a clear color BO for some Z/S

The only depth/stencil aux usage that can actually use the BO is
ISL_AUX_USAGE_HIZ_CCS_WT. Even with that aux usage, iris may disable
sampling depending on the surface configuration.

Allocate the clear color BO when it'd be usable, not just when the
auxiliary surface size is non-zero on ICL+. This prepares for CCS on
XeHP, which won't have an auxiliary surface.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>

iris: Simplify iris_get_aux_clear_color_state_size

isl_dev.ss.clear_color_state_size is already zero on BDW and SKL. Drop
the redundant platform check and return the field directly.

We're going to have this function return zero more often and it will do
so uniformly using if-statements. We choose to remove the redundant
expression instead of adding a redundant if-statement.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>

iris: Move some BO setup to iris_resource_init_aux_buf

To ease verification, place the assignment and reference of the aux BO
right before the same operations are done for the clear color BO. Also,
move the call to map_aux_addresses that's in the same if-block.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>

iris: Use the aux BO and surf less during init

res->aux.bo and res->aux.surf will be NULL and zeroed, respectively, for
CCS on XeHP. Move and modify iris_resource_init_aux_buf to support this.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>

iris: Change a param of iris_resource_init_aux_buf

Have iris_resource_init_aux_buf compute the clear color state size
(with an iris_screen struct) instead of passing it in directly.

We're going to move the function call soon. This keeps us from having to
move a passed in variable along with it.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>

intel/blorp: Modify get_fast_clear_rect for XeHP

The alignment and scale down values have changed on this platform.

To support drivers that won't use a CCS surface on this platform, this
patch computes the CCS fast clear rectangle using the main surface.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>

intel/blorp: Modify the SKL+ CCS resolve rectangle

According to Bspec 2424, "Render Target Resolve":

   The Resolve Rectangle size is same as Clear Rectangle size from SKL+.

Use get_fast_clear_rect in blorp_ccs_resolve for SKL+.

Note that the Bspec differs from Vol7 of the Sky Lake PRM, which only
specifies aligning by the scaledown factors.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>

intel/isl: Require aux map for some 64K alignment

The comment states that 64K alignment of surfaces is required when an
aux map is present on the platform. However, the code checks for GFX12
instead of dev->info->has_aux_map. Update the code to match the comment.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13555>

ci/windows: Remove line numbers from assertions in spirv2dxil tests

Reviewed-by: Enrico Galli <enrico.galli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14156>

etnaviv: fix alpha blend with dither on older GPUs

While setting up DITHER_MODE allows alpha blending to work properly
together with dithering on new GPUs (those with PE_DITHER_FIX), older
cores still change the render target. As dithering is optional and
implementation defined we can simply disable it on the affected GPUs,
when alpha blending is enabled to work around this bug.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13396>

nir/nir_opt_move,sink: Include load_ubo_vec4 as a load_ubo instr.

We weren't doing much motion in nir-to-tgsi because we considered all our
lowered load-ubos as unmovable.

softpipe shader-db:

total temps in shared programs: 563942 -> 563136 (-0.14%)
temps in affected programs: 9833 -> 9027 (-8.20%)

r300 shader-db:

instructions in affected programs: 22858 -> 23575 (3.14%)
temps in affected programs: 2039 -> 1813 (-11.08%)

(NIR had given r300 -19% instrs for +40% temps, so this feels like a
worthwhile trade back).

Reivewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14138>

mesa: fix GL_MAX_SAMPLES with GLES2

EXT_multisampled_render_to_texture on GLES2 allows the
GL_MAX_SAMPLES_EXT enum to be used.

Move the condition from the GLES3 section to the GLES2 one so
that it stops returning GL_INVALID_ENUM in that case.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13967>

egl: add config debug printout

Feature to print out EGL returned configs for debug purposes.

'eglChooseConfig' and 'eglGetConfigs' debug information printout is
enabled when the log level equals '_EGL_DEBUG'. The configs are
printed, and if any of them are "chosen" they are marked with their
index in the chosen configs array.

v2:
   a) re-factor the code in line with review comments
   b) rename function _snprintfStrcat, split it out and put into the
      src/util/u_string.h, make it a separate patch.
v3:
   remove unnecessary 'const' qualifiers from the function prototype
v4:
   a) re-factor the code in line with review comments
   b) move util_strnappend from utils back to eglconfigdebug.c. In my
      opinion this function is the best way of achieving the desired
      result, so it still used but made private to eglconfigdebug.c.
v5:
   a) drop unused parameter from function signature
   b) more const annotations
   c) directly access config parameters instead of going
      through _eglGetConfigKey

Signed-off-by: Silvestrs Timofejevs <silvestrs.timofejevs@imgtec.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13705>

egl: introduce a log level getter function

Being able to retrieve the log level can be useful to enable/disable
debug code. The alternative, which is calling 'getenv' function every
time to retrieve the log level, is more "expensive".

Signed-off-by: Silvestrs Timofejevs <silvestrs.timofejevs@imgtec.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13705>

intel/l3: Make DG1 urb-size exception more generic

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14136>

aco: improve clrx disassembly

- remove uninteresting lines of output
- remove binary offset before instructions, for easier diffing
- replace generated labels with block numbers
- add encoded instructions at the end of lines, like LLVM dissaembly
- print constant data instead of trying to disassemble it

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14042>

microsoft/compiler: Remove algebaric pass for inot

Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14140>

microsoft/compiler: Implement inot

Fixes: cb283616 ("nir/algebraic: Small optimizations for SpvOpFOrdNotEqual and SpvOpFUnordEqual")
Reviewed-by: Enrico Galli <enrico.galli@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14140>

v3dv: account for 64bit time_t on 32bit arches

This makes is a bit more portable, especially on 32bit architectures
with 64bit time_t defaults. Especially on musl its a must.

Fixes
../mesa-21.3.0/src/broadcom/vulkan/v3dv_bo.c:71:15: error: format specifies type 'long' but the argument has type 'time_t' (aka 'long long') [-Werror,-Wformat]
              time.tv_sec);
              ^~~~~~~~~~~

Also reported here [1]

[1] https://github.com/agherzan/meta-raspberrypi/issues/969

Signed-off-by: Khem Raj <raj.khem@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14118>

radv: do not perform depth/stencil resolves for suspended render pass

From the Vulkan spec:

    "Store and resolve operations are only performed at the end of a
     render pass instance that does not specify the
     VK_RENDERING_SUSPENDING_BIT_KHR flag."

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14112>

Revert "radv: Add bufferDeviceAddressMultiDevice support."

This was a workaround for fixing a crash with Baldur's Gate 3 at start
but the game fixed it since.

This reverts commit 1fe375e7cf8da6d0313b7954ae76120cde92db14.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14134>

intel/fs: Drop high_quality_derivatives

We've never bothered to hook it up in crocus or iris.  If we do in the
future, it should probably be a NIR pasa anyway.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14056>

intel/compiler: Get rid of wm_prog_key::frag_coord_adds_sample_pos

This hasn't actually done anything for a while.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14056>

intel/fs,vec4: Drop prog_data binding tables

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14056>

intel/blorp: Stop depending on prog_data binding tables

Instead, set BLORP_TEXTURE_BT_INDEX on the texture instructions
directly.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14056>

intel/fs,vec4: Drop support for shader time

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14056>

intel/fs,vec4: Drop uniform compaction and pull constant support

The only driver using these was i965 and it's gone now.  This is all
dead code.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14056>

crocus: wm_prog_key::key_alpha_test uses GL enums

Fixes: f3630548f1da ("crocus: initial gallium driver for Intel gfx 4-7")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14141>

turnip: Fix operator precedence in address calculation macros for queries

Fixes crash in Oblivion, Skyrim, Crysis running through DXVK on 32b
systems.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5723
Fixes: 937dd76426b2b372a18be35e1416eed291524af7 "turnip: Implement VK_KHR_performance_query"

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14148>

nir_to_tgsi: Enable nir_opt_move.

This moves some ops down to when they're needed, generally reducing the
number of temps in use.  It's not always a win -- sometimes you can end up
moving a generator of a component used by a nir_op_vec down, which means
that op's sources stay live while the vec (whose register likely gets
coalesced with the ops creating it) is also live.  But it's generally
good.

softpipe results:

temps in affected programs: 18115 -> 18026 (-0.49%)
imm in affected programs: 19 -> 22 (15.79%)

r300 results:

instructions in affected programs: 174 -> 178 (2.30%)
vinst in affected programs: 156 -> 160 (2.56%)
sinst in affected programs: 54 -> 50 (-7.41%)
temps in affected programs: 2634 -> 2169 (-17.65%)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14096>

r300: Request NIR shaders from mesa/st and use NIR-to-TGSI.

This brings us into parity on state tracker paths with most other
supported drivers, and a lot of additional optimization on our shaders.

Results on a subset of shader-db that doesn't crash:

instructions in affected programs: 59502 -> 47991 (-19.35%)
vinst in affected programs: 17633 -> 15197 (-13.82%)
sinst in affected programs: 9296 -> 7319 (-21.27%)
flowcontrol in affected programs: 627 -> 310 (-50.56%)
presub in affected programs: 4220 -> 1554 (-63.18%)
temps in affected programs: 5775 -> 8570 (48.40%)
lits in affected programs: 215 -> 37 (-82.79%)

The temps (register usage) increase is unfortunate, but it seems that
instruction counts tend to be our limit before reg counts are.

Fixes: #3354
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14096>

r300: Disable loop unrolling on r500.

It's buggy, and we should just trust GLSL or NIR to do unrolling for us.

Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14096>

nir_to_tgsi: Make !native_integers front face input match glsl_to_tgsi.

Avoids regression on r300, which has 0.0 vs 1.0 frontface despite what
tgsi.rst says.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14096>

nir/nir_to_tgsi: Add support for "if" statements with !native_integers

Previously we've only used this on HW that had all ifs lowered.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14096>

r300/ci: Add some piglit expectations.

Not a full run, but a bit of sanity-check for the NTT change.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14096>

docs: Remove no-longer-accurate text about the xlib driver

Mesa hasn't supported color-index rendering in a long time, and
gallium's xlib target doesn't respect MESA_GAMMA.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14125>

intel/stub: Implement I915_PARAM_HAS_USERPTR_PROBE

Just say no for now.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14132>

intel/stub: Implement DRM_I915_QUERY_MEMORY_REGIONS

Borrowed from sim-drm.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14132>

intel/stub: Implement DRM_I915_QUERY_ENGINE_INFO

Borrowed from sim-drm.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14132>

intel/stub: Suppress warnings about DRM_I915_QUERY_PERF_CONFIG

There's not a useful way to implement this, so just silence the warning
to cleanup shader-db runs.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14132>

aco: don't create unnecessary addition in indirect get_sampler_desc()

I don't think this has any effect on GFX9+ because the addition is
combined into the load.

fossil-db (polaris10):
Totals from 12595 (9.29% of 135627) affected shaders:
SGPRs: 1054348 -> 1054860 (+0.05%); split: -0.02%, +0.07%
VGPRs: 667240 -> 667320 (+0.01%); split: -0.01%, +0.02%
CodeSize: 82761508 -> 82512816 (-0.30%); split: -0.30%, +0.00%
MaxWaves: 62182 -> 62181 (-0.00%)
Instrs: 16072934 -> 16010764 (-0.39%); split: -0.39%, +0.00%
Latency: 582819635 -> 582287964 (-0.09%); split: -0.13%, +0.04%
InvThroughput: 276460536 -> 276417613 (-0.02%); split: -0.06%, +0.05%
VClause: 261656 -> 261654 (-0.00%); split: -0.01%, +0.01%
SClause: 680952 -> 680854 (-0.01%); split: -0.05%, +0.04%
Copies: 1727202 -> 1727742 (+0.03%); split: -0.12%, +0.15%
Branches: 547050 -> 547033 (-0.00%); split: -0.01%, +0.00%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14043>

aco: Clean up and fix quad group instructions with WQM.

According to the Vulkan spec chapter 9.25 Helper Invocations,
quad group operations have to be executed by helper invocations.

This commit cleans up the code for quad group instructions by
unifying the code path of quad broadcast with the others, and then
calling emit_wqm just once at the end.

Fixes: 93c8ebfa780ebd1495095e794731881aef29e7d3
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5570
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13929>

loader: Restore i915g support.

The cleanup of i915c cleaned up our PCI ID list.

Fixes: 0cad451f007f ("classic/i915: Remove driver")
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14131>

glx: fix regression for drawable type detection

Newer version of XServer supporting GLX_DRAWABLE_TYPE query also
support query with raw X11 window ID besides GLXWindow ID. So we
should not limit the suppported type to GLXPbuffer when query
success.

Otherwise can't start GLX application on newer XServer with:

  libGL error: GLX drawable type is not supported
  libGL error: GLX drawable type is not supported
  X Error of failed request:  GLXBadContext
    Major opcode of failed request:  149 (GLX)
    Minor opcode of failed request:  5 (X_GLXMakeCurrent)
    Serial number of failed request:  35
    Current serial number in output stream:  35

Fixes: 6625c960c58 ("glx: check drawable type before create drawble")

Tested-by: Mike Lothian <mike@fireburn.co.uk>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14120>

intel/compiler: Don't store "scalar stage" bits on Gfx8 or Gfx9

Since 1d71b1a311239, only Gfx7 and earlier have any vec4 stages ever.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14128>

intel/compiler: Don't predicate a WHILE if there is a CONT

Previously a predicated BREAK that appeared immediately before the WHILE
would get merged into the WHILE.  This doesn't work if other flow
control (e.g., a CONT) can transfer directly to the WHILE.

On Intel platforms, this fixes the CTS test
dEQP-VK.graphicsfuzz.stable-binarysearch-tree-nested-if-and-conditional.

No shader-db changes on any Intel platform.

When this commit was first created (over a month before it is going to
land), there were some regressions that were prevented by other commits
in MR !13095.  That does not appear to be the case now, so I don't know
what changed.  Basically, the treatment of discard as a combination of
demote and terminate causes additional continues in some loops, and
those continues trigger this bug.  The other commits from that MR
prevent those continues from being generated in the first place.

All Intel platforms had simlar fossil-db results. (Ice Lake shown)
Instructions in all programs: 144419989 -> 144419995 (+0.0%)
SENDs in all programs: 6947332 -> 6947332 (+0.0%)
Loops in all programs: 38277 -> 38277 (+0.0%)
Spills in all programs: 204075 -> 204075 (+0.0%)
Fills in all programs: 319480 -> 319480 (+0.0%)

A few shaders in Doom 2016 were hurt by one instruction each.  It seems
likely that these shaders would have experienced at least some
mis-rendering.

Closes: #4213
Fixes: d13bcdb3a9f ("i965/fs: Extend predicated break pass to predicate WHILE.")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14128>

treewide: drop mtypes/macros includes from main

These aren't required in lots of places, so remove them.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14127>

v3dv: Fix dEQP-VK.info#instance_extensions test

When mesa3d is built without VK_USE_PLATFORM_DISPLAY_KHR definition,
dEQP test fails:

    dEQP    : Test case 'dEQP-VK.info.instance_extensions'..
    dEQP    :   Fail (Extension VK_KHR_get_display_properties2 is missing
                                                 dependency: VK_KHR_display)
    dEQP    : DONE!

Enable KHR_get_display_properties2 only if VK_USE_PLATFORM_DISPLAY_KHR
is enabled.

Fixes: f884c2e3be36 ("v3dv: implement VK_KHR_get_display_properties2")
Signed-off-by: Roman Stratiienko <roman.o.stratiienko@globallogic.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14047>

venus: prefer VIRTGPU_BLOB_MEM_HOST3D for shmems

They are logically contiguously in the host.  More importantly, they
enable host process isolation.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13800>

d3d12: Use overall resource format + plane format to get format info

Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14123>

d3d12: Allow creating planar resources

Also handle opening planar resources with a single handle, instead
of per-plane handles.

Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14123>

d3d12: Handle opening planar resources

Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14123>