aux/tc: handle stride mismatch during rp-optimized subdata

to avoid splitting renderpasses, this subdata optimization handles the usual
driver dance of staging buffer -> gpu copy

if the pbo stride doesn't match the image format's stride, however, then
a direct copy will yield broken pixels and the image will misrender. to avoid this,
detect stride mismatch and translate the single subdata call into a sequence
of non-overlapping subdata calls that the driver can magically figure out
while continuing to not split renderpasses

fixes #9589

cc: mesa-stable

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24849>

docs: add one more 23.1.x release

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25090>

docs: update calendar for 23.1.7

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25090>

docs: add sha256sum for 23.1.7

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25090>

docs: add release notes for 23.1.7

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25090>

rusticl: don't store ptrs to nir_variables across opt passes.

If we use NIR_DEBUG=serialize all these ptrs will be left hanging,
just store the var locations and look them up after opt passes.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25072>

d3d12: Extend video screen AV1 encode tile support checking

Add fallback case to take into account driver reported tile restrictions if
default hardcoded tile configurations are not supported by driver

Reviewed-by: Tanner Van De Walle <tvandewalle@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25070>

util/vl_vlc: Use UINT64_MAX instead of ~0UL with MSVC compiler

vl_vlc_removebits fails on MSVC where ~0UL is taken as 32 bits.
Use the UINT64_MAX constant instead in that case.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25059>

docs: update Anv documentation about dynamic state emission

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>

anv: split BLEND_STATE packing from BLEND_STATE_POINTERS emit

This way when blorp changes the 3DSTATE_BLEND_STATE_POINTERS, we can
just reemit the prior Vulkan state without repacking any of the values
in the BLEND_STATE structure.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>

anv: remove unused state emission

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>

anv: add new low level emission & dirty state tracking

A single Vulkan state can map to multiple fields in different GPU
instructions. This change introduces the bottom half of a simplified
emission mechanism where we do the following :
          Vulkan runtime state
                   |
                   V
        Intermediate driver state
                   |
                   V
         Instruction programming

This way we can detect that the intermediate state didn't change and
avoid HW instruction emission.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>

vulkan/runtime: add helper to name dirty states

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>

anv: split pipeline programming into instructions

The goal of this change it to move away from a single batch buffer
containing all kind of pipeline instructions to a list of instructions
we can emit separately.

We will later implement pipeline diffing and finer state tracking that
will allow fewer instructions to be emitted.

This changes the following things :

   * instead of having a batch & partially packed instructions, move
     everything into the batch

   * add a set of pointer in the batch that allows us to point to each
     instruction (almost... we group some like URB instructions,
     etc...).

At pipeline emission time, we just go through all of those pointers
and emit the instruction into the batch. No additional packing is
involved.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>

anv: add a flag tracking occlusion query count change

We'll use this later to know when to reemit
3DSTATE_STREAMOUT::ForceRendering

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>

anv: split 3DSTATE_VFG emission

Leave the static part in genX_pipeline.c and only repack the dynamic
part in genX_gfx_state.c

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>

anv: split 3DSTATE_TE packing between static & dynamic parts

We can reduce the amount of packing we do by only packing the dynamic
part.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>

anv: categorize partial/final pipeline instruction

The old gfx8 field doesn't apply anymore.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>

anv: rename files to represent their usage

gfx8_cmd_buffer.c does not apply to gfx8 anymore for instance, it can
also be included in all builds.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>

anv: move all dynamic state emission to cmd_buffer_flush_dynamic_state

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>

intel/decoder: implement accumulated prints

Useful when you want to compare 2 batches with different ordering in
instruction emission. Also when the driver tries to avoid re-emitting
state.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>

intel/anv: batch stats util

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>

anv: change anv_batch_emit_merge to also do packing

Instead of having that function do only merging of 2 sets of dwords,
it can also do the packing of the new dynamic values. This saves us a
bunch of local structures to declare and calling the packing functions
ourselves.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>

anv: remove ReorderMode from pipeline 3DSTATE_GS emission

This bit is set in the dynamic state emission. This is currently not
breaking anything because LEADING=0.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 71ebd9b9d7 ("anv,hasvk: respect provoking vertex setting on geometry shaders")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24536>

blorp: remove unused variable

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24719>

hasvk: add state cache invalidation back before fast clears

Prior to 87149cc545, blorp added a state cache invalidation prior to
fast clears. This got dropped on Hasvk.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 87149cc545 ("blorp: update and move fast clear PIPE_CONTROLs to drivers")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24719>

nouveau/mme: SPDX everything

For all the Fermi stuff, I've credited Mary because she wrote it before
joining Collabora.  For everything else, credit Collabora.

Acked-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25085>

nouveau/nil: SPDX everything

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25085>

nvk: SPDX everything

I chose to use "Collabora Ldt. and Red Hat Inc." as the author line.  I
could have gone through and manually checked every single file but I
think it's better to spread the blame around.  No one should actually
trust those lines anyway.  That's what git blame is for.

Acked-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25085>

nvk: Add include guards to nvk_bo_sync.h

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25085>

nvk: Clean up includes

Drop a bunch of totally unnecessary stuff from xf86drm.h from
nvk_private.h and limit it to vk_util and vk_log.  In particular, we
drop nvk_entrypoints.h which is auto-generated, allowing NVK headers to
be included in other parts of the tree.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25085>

r600/sfn: Simplify dependency chain for index loads on EG

Address loads that just load the index register don't need to chain
up like loads if the address register that are used for indirect
register loads. With the latter it is important that the load and the
address register use are in the same clause. For index register loads
this is scheduled accordingly.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24638>

r600/sfn: factor out resource as extra class

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24638>

r600/sfn: drop unused ControlFlowInstr type enum

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24638>

r600/sfn: Make use of four clause local registers

The hardware is actually configures like this, but for fma64
we have to sacrifice a "normal" register to allocate z and w
channels, even though the result written there is not used.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24638>

intel/fs: limit register flag interaction of FIND_*LIVE_CHANNEL

Those instructions do not access the flag registers on Gfx8+. Removing
the interaction enables CSE to remove more of those instructions.

Results are a bit mixed (DG2 vulkan fossils):

  ACO:
  Totals from 127 (5.97% of 2128) affected shaders:
  Instrs: 139966 -> 138972 (-0.71%); split: -0.85%, +0.14%
  Cycles: 1685747 -> 1667480 (-1.08%); split: -2.35%, +1.26%
  Max live registers: 10582 -> 10544 (-0.36%)
  Max dispatch width: 1048 -> 1040 (-0.76%)

  Cyberpunk 2077:
  Totals from 2879 (27.95% of 10301) affected shaders:
  Instrs: 4264789 -> 4225666 (-0.92%); split: -1.01%, +0.09%
  Cycles: 72380209 -> 71619521 (-1.05%); split: -1.63%, +0.58%
  Subgroup size: 30624 -> 30632 (+0.03%)
  Spill count: 98 -> 101 (+3.06%)
  Fill count: 90 -> 93 (+3.33%)
  Scratch Memory Size: 8192 -> 9216 (+12.50%)
  Max live registers: 217807 -> 217098 (-0.33%); split: -0.59%, +0.26%
  Max dispatch width: 23792 -> 24112 (+1.34%)

  Gaining 40 SIMD16 shaders

  Rise Of The Tomb Raider:
  Totals from 622 (5.06% of 12289) affected shaders:
  Instrs: 437380 -> 434760 (-0.60%); split: -0.72%, +0.12%
  Cycles: 261843085 -> 261580703 (-0.10%); split: -0.73%, +0.63%
  Max live registers: 27731 -> 27766 (+0.13%); split: -1.01%, +1.14%
  Max dispatch width: 5832 -> 5432 (-6.86%); split: +0.27%, -7.13%

  Loosing 26 SIMD32 shaders

  Strange Brigade:
  Totals from 1298 (31.48% of 4123) affected shaders:
  Instrs: 1504408 -> 1487968 (-1.09%); split: -1.17%, +0.08%
  Cycles: 20735976 -> 20443216 (-1.41%); split: -1.60%, +0.19%
  Max live registers: 89911 -> 89957 (+0.05%)

DG2 shader-db run:

  total instructions in shared programs: 23130895 -> 23130036 (<.01%)
  instructions in affected programs: 260956 -> 260097 (-0.33%)
  helped: 234
  HURT: 101
  helped stats (abs) min: 1 max: 54 x̄: 6.36 x̃: 4
  helped stats (rel) min: 0.05% max: 8.16% x̄: 2.01% x̃: 1.90%
  HURT stats (abs)   min: 1 max: 37 x̄: 6.23 x̃: 3
  HURT stats (rel)   min: 0.02% max: 5.67% x̄: 0.89% x̃: 0.55%
  95% mean confidence interval for instructions value: -3.62 -1.51
  95% mean confidence interval for instructions %-change: -1.33% -0.94%
  Instructions are helped.

  total loops in shared programs: 6071 -> 6071 (0.00%)
  loops in affected programs: 0 -> 0
  helped: 0
  HURT: 0

  total cycles in shared programs: 898610645 -> 898557166 (<.01%)
  cycles in affected programs: 18308201 -> 18254722 (-0.29%)
  helped: 315
  HURT: 48
  helped stats (abs) min: 1 max: 19312 x̄: 404.23 x̃: 128
  helped stats (rel) min: 0.02% max: 28.98% x̄: 3.92% x̃: 2.65%
  HURT stats (abs)   min: 2 max: 14478 x̄: 1538.60 x̃: 409
  HURT stats (rel)   min: <.01% max: 23.24% x̄: 3.34% x̃: 0.41%
  95% mean confidence interval for cycles value: -333.68 39.03
  95% mean confidence interval for cycles %-change: -3.51% -2.41%
  Inconclusive result (value mean confidence interval includes 0).

  total spills in shared programs: 5964 -> 5964 (0.00%)
  spills in affected programs: 0 -> 0
  helped: 0
  HURT: 0

  total fills in shared programs: 6909 -> 6909 (0.00%)
  fills in affected programs: 0 -> 0
  helped: 0
  HURT: 0

  total sends in shared programs: 1040266 -> 1040266 (0.00%)
  sends in affected programs: 0 -> 0
  helped: 0
  HURT: 0

  LOST:   3
  GAINED: 1

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24553>

pvr: Cleanup comments in pvr_physical_device_get_supported_*()

pvr_physical_device_get_supported_extensions() contained unneeded
/* clang-format off */ guards.

The section comments in pvr_physical_device_get_supported_features()
also now match the pattern in pvr_physical_device_get_properties().

Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Vlad Schiller <vlad-radu.schiller@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25033>

ci: enforce -Wimplicit-const-int-float-conversion for clang

All -Wimplicit-const-int-float-conversion warnings are fixed and ci
can drop -Wno-error=implicit-const-int-float-conversion.

Signed-off-by: Vignesh Raman <vignesh.raman@collabora.com>
Acked-by: Helen Koike <helen.koike@collabora.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24362>

Do explicit cast to suppress clang warnings

Do explicit cast to suppress the below clang warnings,
../src/mesa/main/get.c:86:31: error: implicit conversion from 'int' to 'float' changes value from 2147483647 to 2147483648 [-Werror,-Wimplicit-const-int-float-conversion]
   return ( ((F) * 65536.0f > INT_MAX) ? INT_MAX :

../src/mesa/main/texparam.c:967:27: error: implicit conversion from 'int' to 'float' changes value from 2147483647 to 2147483648 [-Werror,-Wimplicit-const-int-float-conversion]
                ((param > INT_MAX) ? INT_MAX : (GLint) (param + 0.5)) :

../src/mesa/main/texparam.c:2609:65: error: implicit conversion from 'int' to 'float' changes value from 2147483647 to 2147483648 [-Werror,-Wimplicit-const-int-float-conversion]
         *params = LCLAMPF(obj->Sampler.Attrib.MinLod, INT_MIN, INT_MAX);

../src/mesa/main/texparam.c:2624:65: error: implicit conversion from 'int' to 'float' changes value from 2147483647 to 2147483648 [-Werror,-Wimplicit-const-int-float-conversion]
         *params = LCLAMPF(obj->Sampler.Attrib.MaxLod, INT_MIN, INT_MAX);

../src/mesa/main/texparam.c:2648:72: error: implicit conversion from 'int' to 'float' changes value from 2147483647 to 2147483648 [-Werror,-Wimplicit-const-int-float-conversion]
         *params = LCLAMPF(obj->Sampler.Attrib.MaxAnisotropy, INT_MIN, INT_MAX);

../src/mesa/main/texparam.c:2693:66: error: implicit conversion from 'int' to 'float' changes value from 2147483647 to 2147483648 [-Werror,-Wimplicit-const-int-float-conversion]
         *params = LCLAMPF(obj->Sampler.Attrib.LodBias, INT_MIN, INT_MAX);

../src/gallium/drivers/freedreno/a3xx/fd3_emit.c:731:43: error: implicit conversion from 'unsigned int' to 'float' changes value from 4294967295 to 4294967296 [-Werror,-Wimplicit-const-int-float-conversion]
         OUT_RING(ring, (uint32_t)(zmin * 0xffffffff));

../src/gallium/drivers/freedreno/a3xx/fd3_emit.c:732:43: error: implicit conversion from 'unsigned int' to 'float' changes value from 4294967295 to 4294967296 [-Werror,-Wimplicit-const-int-float-conversion]
         OUT_RING(ring, (uint32_t)(zmax * 0xffffffff));

../src/nouveau/codegen/nv50_ir_peephole.cpp:1647:30: error: implicit conversion from 'unsigned int' to 'float' changes value from 4294967295 to 4294967296 [-Werror,-Wimplicit-const-int-float-conversion]
      CASE(TYPE_U32, u32, 0, UINT32_MAX, 0, INT32_MAX, 0, UINT32_MAX);

../src/nouveau/codegen/nv50_ir_peephole.cpp:1648:38: error: implicit conversion from 'int' to 'float' changes value from 2147483647 to 2147483648 [-Werror,-Wimplicit-const-int-float-conversion]
      CASE(TYPE_S32, s32, INT32_MIN, INT32_MAX, INT32_MIN, INT32_MAX, 0, INT32_MAX);

../src/gallium/drivers/radeonsi/si_nir_lower_vs_inputs.c:400:51: error: implicit conversion from 'unsigned long long' to 'double' changes value from 18446744073709551615 to 18446744073709551616 [-Werror,-Wimplicit-const-int-float-conversion]
         loads[chan] = nir_fmul_imm(b, tmp, 1.0 / BITFIELD64_MASK(bits));

../src/gallium/drivers/radeonsi/si_nir_lower_vs_inputs.c:408:43: error: implicit conversion from 'unsigned long long' to 'double' changes value from 18446744073709551615 to 18446744073709551616 [-Werror,-Wimplicit-const-int-float-conversion]
         tmp = nir_fmul_imm(b, tmp, 1.0 / BITFIELD64_MASK(bits - 1));

Signed-off-by: Vignesh Raman <vignesh.raman@collabora.com>
Acked-by: Helen Koike <helen.koike@collabora.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24362>

pvr: Remove PVR_WINSYS_BO_FLAG_ZERO_ON_ALLOC flag

There has been a recent change to the new powervr KMD to always zero buffer
objects at allocation time to avoid information leaks. This change was made to
address upstream feedback [1]. The result is that the
PVR_WINSYS_BO_FLAG_ZERO_ON_ALLOC no longer makes a difference when using this
KMD.

As the powervr KMD is the one we actually care about, it makes sense to mirror
this change when using the downstream pvrsrvkm KMD in order to avoid differences
in behaviour between the two KMDs. As this makes the
PVR_WINSYS_BO_FLAG_ZERO_ON_ALLOC flag entirely redundant, remove it.

[1] https://lists.freedesktop.org/archives/dri-devel/2023-August/418042.html

Signed-off-by: Vlad Schiller <vlad-radu.schiller@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24930>

iris: migrate preemption streamwout wa to WA infra

Fixes: db6c374 ('iris: disable preemption for 3DPRIMITIVE during streamout')
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25080>

zink/ci: merge piglit testing with deqp-runner for RADV

This avoids using an extra script to run GLCTS+piglit.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25062>

zink/ci: merge GLCTS testing with GLESx for RADV

Both testsuites used to be executed separately because of spurious
failures/hangs but they seem fixed now.

GLCTS+GLES might be faster to run now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25062>

ci/farms: no need to check RUNNER_TAG for Collabora farm

Since Google Freedreno and Collabora farm definition split,
we don't need to check for runner tag.

Reported-by: Eric Engestrom <eric@igalia.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24961>

radv: add support for DGC with SQTT

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25035>

radv: avoid emitting SQTT markers for DGC calls

This confuses RGP.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25035>

intel/genxml: Fix comparing xml when node counts differ

This fix is more relevant to MR !20593. Normally when sorting the
number of nodes will be equivalent today, so this bug will not be
encountered. But in !20593, we can shrink (--import) or grow the
number of elements (--flatten) when the genxml_import.py tool is used.

Fixes: e60a0b16163 ("intel/genxml: Move sorting & writing into GenXml class")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24902>

intel/genxml: Ignore tail leading/trailing whitespace in node_validator()

When importing or flattening genxml with the genxml_import.py script
in MR !20593, it can lead to the tail portion of xml items differing
in whitespace.

If we strip the trailing and leading whitespace from the tail string,
and the strings are equivalent, then we can consider the xml items to
be equivalent.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24903>

intel/dev/xe: Move placeholder subslice info into XEHP_FEATURES

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24418>

radv/video: use correct enum value for max level IDC

Signed-off-by: Chris Spencer <spencercw@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24649>

anv/video: use correct enum value for max level IDC

Signed-off-by: Chris Spencer <spencercw@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24649>

ac/llvm: don't convert undef to 0 because nir_opt_undef does it now

TOTALS FROM AFFECTED SHADERS (29663/58918)
  Code Size: 39163724 -> 37842360 (-3.37 %) bytes
  Max Waves: 394813 -> 396334 (0.39 %)
  Outputs: 84616 -> 84616 (0.00 %)
  Patch Outputs: 0 -> 0 (0.00 %)

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24059>

nir: remove nir_op_unpack_64 handling from nir_opt_undef

It's no longer needed because undef is replaced with 0 in this case.

It also has a bug that it doesn't freeze the undef value if undef has
multiple uses.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24059>

nir: replace undef only used by ALU opcodes with 0 or NaN

If undef is consumed by an FP opcode, replace it with NaN to eliminate
that opcode, else replace it with 0, but there are exceptions, such as
when undef is used by stores or phis, it's not touched.

This also contains workarounds for viewperf shaders.

radeonsi:
TOTALS FROM AFFECTED SHADERS (1987/58918)
  Code Size: 5158692 -> 5143796 (-0.29 %) bytes
  Max Waves: 22456 -> 22513 (0.25 %)
  Outputs: 3726 -> 3726 (0.00 %)
  Patch Outputs: 0 -> 0 (0.00 %)

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24059>

intel/clflush: Add support for clflushopt instruction

Rework:
 * Split clflushopt into a separate file as recommended by Ken.
   If we enable -mclflush on all driver source compilation, then
   gcc may insert uses of it on processors that don't support it.
 * Add uintptr_t casting to cpu_caps->cacheline usage

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>

meson: Check for the __builtin_ia32_clflushopt function

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>

util/u_cpu_detect: Detect clflushopt support

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>

util/u_cpu_detect: Drop unused has_tsc

This will allow us to add has_clflushopt without spilling into an new
unsigned.

Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>

anvil,hasvk: Use intel_flush_range_no_fence to flush command buffers

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>

intel/common: Add intel_flush_range_no_fence

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>

anvil,hasvk: Replace intel_clflush_range with intel_flush_range

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>

intel/common: Move intel_clflush.h to intel_mem.h/intel_mem.c

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>

anvil,hasvk: Rename need_clflush to need_flush

$ git grep -l need_clflush | xargs sed -i 's/need_clflush/need_flush/g'

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22379>

rusticl/mesa: create contexts with PIPE_CONTEXT_NO_LOD_BIAS

It's not a thing in OpenCL

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25067>

d3d12: Video Decode - Remove unnecessary copy for texture array case

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25069>

drirc: enable `vk_wsi_force_swapchain_to_current_extent` for "Serious Sam Fusion"

This game handles swapchain size incorrecly and can crash because of
it.

Enable this driconf as a workaround.

Fixes: 6139493ae38 ("vulkan/wsi: return VK_SUBOPTIMAL_KHR for sw/x11 on window resize")
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24818>

drirc: enable `vk_wsi_force_swapchain_to_current_extent` for "The Talos Principle"

This game handles swapchain size incorrecly and can crash because of
it.

Enable this driconf as a workaround.

Fixes: 6139493ae38 ("vulkan/wsi: return VK_SUBOPTIMAL_KHR for sw/x11 on window resize")
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24818>

vulkan/wsi: add `vk_wsi_force_swapchain_to_current_extent` driconf

Add a driconf to force the swapchain size to match
`VkSurfaceCapabilities2KHR::currentExtent` as a workaround for
misbehaved games

Fixes: 6139493ae38 ("vulkan/wsi: return VK_SUBOPTIMAL_KHR for sw/x11 on window resize")
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24818>

llvmpipe: move to nir lowering for fquantize2f16

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24988>

driconf: use lower_depth_range_rate for The Spirit and The Mouse

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9738
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25029>

Revert "ci: disable Google Freedreno farm, currently timeouting on all jobs"

This reverts commit fc46062ee52e8c09f10bb8cc80e00b73b592e6f4.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25058>

frontends/va: Support chroma sample location in postproc

Rename vlVaSetCscMatrix to vlVaSetProcParameters because it now does
more than just setting csc matrix.

Acked-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24869>

gallium/auxiliary/vl: Support chroma sample location in compute shaders

Used only in YUV to RGB video_buffer shader for now.

Acked-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24869>

gallium/auxiliary/vl: Clamp coordinates in compute shaders

Video textures include padding, so this is needed to avoid sampling
outside of src rect due to scaling or additional offset.
Fixes wrong colors on right/bottom edge.

Acked-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24869>

gallium/auxiliary/vl: Map range when updating constants

Use WRITE | DISCARD_RANGE to avoid having to read back the csc matrix
and luma min/max values.

Acked-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24869>

gallium/auxiliary: Fix util_compute_blit half texel offset with scaling

Video textures include padding, so make sure to not sample outside
src rect. Also remove the parameter and always use the offset.

When not scaling, this fixes blurry output.
When scaling, this fixes incorrect color at right/bottom edge.

Acked-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24869>

zink: polaris ci updates

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25056>

asahi: Skip LOD bias lowering for GLES

This reduces silliness in Dolphin ubershaders by eliminating the double
lowering. It also makes the GLES shader assembly nicer to read.

Dolphin ubershader performance at 4K on MMG improved by about 0.5%. Not massive,
but definitely noticeable and reduces the delta to macOS.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>

gallium,mesa/st: Add PIPE_CONTEXT_NO_LOD_BIAS flag

While desktop GL supports sampler LOD bias, GLES does not. To support the GL use
case, all Gallium drivers are expected to handle sampler LOD bias. However, this
may require shader code to implement (lowering tex to txb, txl to fadd+txl) and
cost resources to push the LOD bias constants into the shader. The issue is
compounded with something like Dolphin's GLES renderer, which does this LOD bias
emulation itself -- meaning that LOD bias is lowered twice when using Dolphin
with GLES! As such, this commit adds a context flag for frontends to communicate
that they will never use sampler LOD bias, allowing the driver to omit the
lowering as a GLES fast path (or, for Dolphin, for performance parity between
GLES and GL).

This will be used on Asahi. It could also be used to optimize a path on
Mali-T720 supported in Panfrost, though I don't intend to write that patch.

Originally https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25034

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>

asahi: Conditionally expose cube arrays

With =deqp. I don't want this exposed before geometry shaders since we run dEQP
(GLES) far more than Piglit (GL), and we need geometry shaders to get adequate
regression testing via dEQP-GLES.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>

asahi: Handle linear 1D Arrays

Lowered to linear 2D Arrays, handle them like that. Fixes 1D Array case of
arb_shader_image_size-builtin.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>

asahi: Forbid linear 1D Array images

Porbably a theoretical case, but these fall down the 2D path so better not allow
it at any rate.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>

agx: Run opt_idiv_const after lowering texture

Shaves 10 instructions off the cube map array lowering.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>

agx: Lower coordinates for cube map array images

Annoyingly different from texture coordinates.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>

agx: Handle cube arrays when clamping arrays

Need to adjust the component.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>

ail: Force page-alignment for layered attachments

When rendering to a layered depth/stencil attachment, we specify the layer
stride in pages. That means that depth/stencil targets must be page-aligned to
be rendered to correctly.

If we're merely sampling, not rendering, we do not need the extra alignment. So
we add a flag to handle this case so we keep passing the generated ail tests.

Fixes KHR-GLES31.core.texture_cube_map_array.color_depth_attachments

Similarly, we page-align colour attachments. I don't have a good theoretical
justification for this part, but it seems to be necessary and layered rendering
fails otherwise. Possibly the PBE requires page-aligned layers unconditionally?

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>

asahi: Translate cube array dimension

Yet another enum.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>

agx: Add unit test for cmp+sel fusing

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>

agx: Add unit test for if_cmp fusing

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>

agx: Fuse compares into selects

This lets us save a LOT of instructions at the cost of increased register
pressure. However, on my shader-db, this is still coming out ahead since no
shaders are hurt for thread count/spills, and only 1/10 of the shaders helped
for instruction count are hurt for register pressure. The shaders most hurt
for pressure have very low pressure (7 -> 15 is the worst case) and you need a
certain number of registers to use a 4 source instruction at all. Analyzing the
hurt shaders, nothing concerns me too much ... this isn't as bad as I feared.

So I think at this point it's worth ripping off the bandage, given the massive
potential for instruction count win. This is a big improvement for some of the
shaders I'm working on for my $SECRET_PROJECT.

   total instructions in shared programs: 1784943 -> 1775169 (-0.55%)
   instructions in affected programs: 644211 -> 634437 (-1.52%)
   helped: 3498
   HURT: 38
   Instructions are helped.

   total bytes in shared programs: 11720734 -> 11643224 (-0.66%)
   bytes in affected programs: 4370986 -> 4293476 (-1.77%)
   helped: 3572
   HURT: 36
   Bytes are helped.

   total halfregs in shared programs: 474094 -> 475165 (0.23%)
   halfregs in affected programs: 12821 -> 13892 (8.35%)
   helped: 65
   HURT: 247
   Halfregs are HURT.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>

agx: Fuse conditions into if's

Simple greedy thing that has the potential to inflate register pressure but
reduces instructions. Thanks to the recent loop work that turns if { break }
into while_icmp, this also implicitly handles fusing conditions into loops,
which is what actually prompted this.

Surprisingly, this helps register pressure on my shader-db (no change to thread
count), I guess by eliminating the boolean temps in case where the sources are
used multiple times.

   total instructions in shared programs: 1786561 -> 1784943 (-0.09%)
   instructions in affected programs: 128557 -> 126939 (-1.26%)
   helped: 474
   HURT: 13
   Instructions are helped.

   total bytes in shared programs: 11733236 -> 11720734 (-0.11%)
   bytes in affected programs: 976034 -> 963532 (-1.28%)
   helped: 521
   HURT: 13
   Bytes are helped.

   total halfregs in shared programs: 474245 -> 474094 (-0.03%)
   halfregs in affected programs: 1869 -> 1718 (-8.08%)
   helped: 28
   HURT: 7
   Halfregs are helped.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>

agx: Generate unfused comparison pseudo ops

So we can optimize them easier.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>

agx: Add pseudo-instructions for icmp/fcmp

Easier to optimize with.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>

agx: Only use nest by 1 for loops w/o continue

Apple doesn't do this, but it should be equivalent and it makes it easier to see
that we can use while_icmp for break_if_icmp in loops that don't use continue
(which Apple does do). So, the effect of this commit is to use while_icmp for
most breaks, which saves an instruction.

   total instructions in shared programs: 1764199 -> 1764076 (<.01%)
   instructions in affected programs: 24149 -> 24026 (-0.51%)
   helped: 78
   HURT: 0
   Instructions are helped.

   total bytes in shared programs: 11609306 -> 11608322 (<.01%)
   bytes in affected programs: 164604 -> 163620 (-0.60%)
   helped: 78
   HURT: 0
   Bytes are helped.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>

agx: Add helper to determine if a NIR loop uses continue

We need to emit extra instructions to handle continues, but if we don't have
any, we can omit those.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>

agx: Omit while_icmp without continue

The only role of the while_icmp at the end of a NIR loop is to make continue
jumps work. If, after emitting the loop, we learn that there are no continues,
there is no need to insert a while_icmp since it would be a no-op anyway.

   total instructions in shared programs: 1764311 -> 1764199 (<.01%)
   instructions in affected programs: 26321 -> 26209 (-0.43%)
   helped: 82
   HURT: 0
   Instructions are helped.

   total bytes in shared programs: 11609978 -> 11609306 (<.01%)
   bytes in affected programs: 178842 -> 178170 (-0.38%)
   helped: 82
   HURT: 0
   Bytes are helped.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>

agx: Omit push_exec at top level

In general, loops need a push_exec at the start for correctness. However, a
push_exec at the top level (non-nested) is a no-op, so we can omit and save a
few cycles.

   total instructions in shared programs: 1764350 -> 1764311 (<.01%)
   instructions in affected programs: 7339 -> 7300 (-0.53%)
   helped: 36
   HURT: 0
   Instructions are helped.

   total bytes in shared programs: 11610212 -> 11609978 (<.01%)
   bytes in affected programs: 48638 -> 48404 (-0.48%)
   helped: 36
   HURT: 0
   Bytes are helped.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>

agx: Detect conditional breaks

Search for code like

   if ... {
      break
   }

and replace with a break_if pseudo-instruction for optimized handling, since the
break_if lowering is better than the original code.

   total instructions in shared programs: 1764596 -> 1764350 (-0.01%)
   instructions in affected programs: 24540 -> 24294 (-1.00%)
   helped: 78
   HURT: 0
   Instructions are helped.

   total bytes in shared programs: 11611196 -> 11610212 (<.01%)
   bytes in affected programs: 166458 -> 165474 (-0.59%)
   helped: 78
   HURT: 0
   Bytes are helped.

shader-db probably understates the benefit here, since this optimizes the body
of loops.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>

agx: Use agx_first_instr

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>

agx: Add agx_first/last_instr helpers

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>