Chia-I Wu [Fri, 21 Apr 2023 05:21:04 +0000 (22:21 -0700)]
vulkan: add vk_ahb_format_to_image_format
There should be no functional change.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22619>
Chia-I Wu [Fri, 21 Apr 2023 06:46:30 +0000 (23:46 -0700)]
vulkan: define inline stubs when android api level < 26
This allows us to reduce ANDROID #ifdef's.
v2: always include vk_android.h in radv_formats.c
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22619>
Chia-I Wu [Fri, 21 Apr 2023 01:02:23 +0000 (18:02 -0700)]
vulkan: rename vk_image::ahardware_buffer_format
Rename it to ahb_format.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22619>
Chia-I Wu [Fri, 21 Apr 2023 05:09:26 +0000 (22:09 -0700)]
vulkan: make sure vk_image_view::format is never UNDEFINED
Remove redundant override in anv and hasvk as well.
Fixed
android.graphics.cts.BasicVulkanGpuTest#testBasicBufferImportAndRenderingExternalFormat
for radv.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22619>
Chia-I Wu [Thu, 20 Apr 2023 23:58:17 +0000 (16:58 -0700)]
vulkan: make sure vk_image::format is never UNDEFINED
vk_image::android_external_format is only used for sanity check and is
removed.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22619>
Chia-I Wu [Fri, 21 Apr 2023 05:07:05 +0000 (22:07 -0700)]
hasvk: Use the common vk_ycbcr_conversion object
Based on commit
30a91d333d1 ("anv: Use the common vk_ycbcr_conversion
object").
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22619>
Chia-I Wu [Fri, 21 Apr 2023 04:55:18 +0000 (21:55 -0700)]
hasvk/android: Use VkFormat for externalFormat
Same as commit
18feb32df0a ("anv/android: Use VkFormat for
externalFormat"), but for hasvk.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22619>
Chia-I Wu [Fri, 21 Apr 2023 04:55:12 +0000 (21:55 -0700)]
hasvk: Refactor Android externalFormat handling in CreateYcbcrConversion
Same as commit
9fc046a87dc ("anv: Refactor Android externalFormat
handling in CreateYcbcrConversion"), but for hasvk.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22619>
Jesse Natalie [Thu, 11 May 2023 02:50:40 +0000 (19:50 -0700)]
dzn: Enable KHR_shader_integer_dot_product
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22952>
Jesse Natalie [Thu, 11 May 2023 02:11:59 +0000 (19:11 -0700)]
microsoft/compiler: Enable packed dot product intrinsics for SM6.4+
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22952>
Jesse Natalie [Wed, 10 May 2023 20:48:01 +0000 (13:48 -0700)]
microsoft/compiler: Take inputs from callers before providing nir options
The base nir options were assuming all bit sizes were supported at
shader model 6.2. Multiple callers were then changing properties
based on actual support.
Standardize behavior by providing the majority of things that can
impact nir options when getting them. Some callers (e.g. meta blit
shaders or libclc) don't bother, because they are known to have
contents that are unaffected by these options. Other callers might
munge more properties afterwards, but this minimizes that.
Note that lower_helper_invocation was incorrectly being turned off
for SM6.6+ by some callers, despite load_helper_invocation being
unimplemented by the backend.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22952>
Jesse Natalie [Wed, 10 May 2023 20:47:28 +0000 (13:47 -0700)]
dzn: Enable 64-bit ints and floats
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22952>
Jesse Natalie [Wed, 10 May 2023 20:39:56 +0000 (13:39 -0700)]
d3d12: Convert from D3D shader model to Mesa shader model earlier
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22952>
Jesse Natalie [Wed, 10 May 2023 23:02:46 +0000 (16:02 -0700)]
spirv2dxil: Support int64 and doubles
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22952>
Alyssa Rosenzweig [Wed, 10 May 2023 18:01:23 +0000 (14:01 -0400)]
zink: Always set a blend state for shader-db
If we're compiling shaders in shader-db, with shader-db's ./run and
ZINK_DEBUG=shaderdb, we won't get much state set on the graphics pipeline, since
shader-db doesn't actually do any rendering. For a driver like RADV, that is
*almost* ok... Since we use dynamic vertex input, we don't need to make up any
state for vertex inputs; since we use dynamic rendering, we don't need to make
up any render attachments. All of that being said, we *do* need to make up a
blend state to ensure that the Vulkan driver doesn't optimize away all of
store_derefs in the fragment shader (and in turn, optimize the entire fragment
shader away, if there are no image/SSBO writes.) So set the obvious blend state,
fixing fragment shaders in shader-db with zink + radv.
I don't know why other people would want to use Zink with shader-db, but for me
it's an easy way to test ACO, at least until radeonsi gains aco support.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22948>
Caio Oliveira [Fri, 28 Apr 2023 16:46:10 +0000 (09:46 -0700)]
spirv: Use NIR_PASS for spirv2nir --optimize
This allows us to use NIR_DEBUG=print to see each step.
Also use an OPT macro to make code slightly more readable.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22764>
Caio Oliveira [Fri, 28 Apr 2023 16:40:25 +0000 (09:40 -0700)]
spirv: Do more on spirv2nir --optimize
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22764>
Lionel Landwerlin [Thu, 11 May 2023 12:08:37 +0000 (15:08 +0300)]
intel/mi_builder: fixup tests for newer kernel uAPI
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22966>
José Roberto de Souza [Thu, 27 Apr 2023 21:14:22 +0000 (14:14 -0700)]
anv: Set memory types supported by Xe KMD
Due the lack of APIs to set mmap modes, Xe KMD can't support the same
memory types as i915.
So here adding a i915 and Xe function to set memory types supported
by each KMD.
Iris function iris_xe_bo_flags_to_mmap_mode() has a table with all the
mmaps modes of each type of placement.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22906>
Leo Liu [Mon, 1 May 2023 15:50:51 +0000 (11:50 -0400)]
radeonsi: Use vcn version instead of CHIP family for VCNs
Decouple it from CHIP family, based on HW query infomation.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22904>
Leo Liu [Mon, 1 May 2023 15:46:15 +0000 (11:46 -0400)]
amd: Add vcn ip version info
And make it support for kernel w/wo ip_discovery.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22904>
Leo Liu [Tue, 25 Apr 2023 16:20:10 +0000 (12:20 -0400)]
radeonsi: Remove redundant vcn_decode from info
Use the number of queue instead.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22904>
MouriNaruto [Thu, 11 May 2023 15:22:50 +0000 (23:22 +0800)]
dzn: Fix segmentation fault when Direct3D 12 user mode
driver from at least one of GPUs is not available.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22961>
Alyssa Rosenzweig [Tue, 25 Apr 2023 17:52:32 +0000 (13:52 -0400)]
agx: Optimize multiplies
We have an imad instruction and our iadd has a small immediate shift on the
second source. Together, these allow expressing lots of integer multiplies more
efficiently. Add some rules to optimize these now that the backend compiler can
ingest the optimized forms.
Half-register changes are from load_const scheduling changing in some vertex
shaders.
total instructions in shared programs: 1539092 -> 1537949 (-0.07%)
instructions in affected programs: 167896 -> 166753 (-0.68%)
total bytes in shared programs:
10543012 ->
10533866 (-0.09%)
bytes in affected programs: 1218068 -> 1208922 (-0.75%)
total halfregs in shared programs: 483180 -> 483448 (0.06%)
halfregs in affected programs: 1942 -> 2210 (13.80%)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22695>
Alyssa Rosenzweig [Fri, 28 Apr 2023 18:49:25 +0000 (14:49 -0400)]
agx: Fix packing of imsub instructions
The negate for imad is on the third source (a * b - c), not the second source.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22695>
Alyssa Rosenzweig [Tue, 25 Apr 2023 18:50:24 +0000 (14:50 -0400)]
agx: Handle imadshl_agx, imsubshl_agx
Same hardware instructions as iadd/isub/imad/imsub, just with the extra input
represented in NIR as required.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22695>
Alyssa Rosenzweig [Tue, 25 Apr 2023 18:37:07 +0000 (14:37 -0400)]
nir: Model AGX-specific multiply-shift-add
Models `(a * b) + (c << d)` in general, as implemented in various forms on AGX.
This will be fused with backend NIR opt algebraic rules, both for the literal
pattern as well as to strength reduce certain multiplications, e.g. replacing
a * 5 with `a + (a << 2)` expressed as imadshl_agx(a, 1, a, 2).
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22695>
Alyssa Rosenzweig [Tue, 25 Apr 2023 18:48:56 +0000 (14:48 -0400)]
agx: Use nir_alu_src_as_uint
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22695>
Alyssa Rosenzweig [Tue, 25 Apr 2023 18:50:01 +0000 (14:50 -0400)]
pan/bi: Use nir_alu_src_as_uint
Fixes some theoretical issues with swizzle handling. Unsure if this could cause
actual end-to-end miscompiles.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22695>
Alyssa Rosenzweig [Tue, 25 Apr 2023 18:39:23 +0000 (14:39 -0400)]
nir: Add nir_alu_src_as_uint helper
We have a few ALU instructions that take a constant source. Technically, they
have a swizzle so you can't just nir_src_as_uint them, even though a bunch of
backends do. To help backends do the right thing, add a helper that's just as
easy to use that will chase the swizzle properly.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22695>
Lionel Landwerlin [Tue, 9 May 2023 08:34:05 +0000 (11:34 +0300)]
anv: fixup workaround
16011411144
We're missing it for the memcpy with streamout
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
5cc4075f95 ("anv, iris: Add Wa_16011411144 for DG2")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22930>
Tapani Pälli [Sun, 7 May 2023 18:28:54 +0000 (21:28 +0300)]
egl/loader: move crtc resource infrastructure as common helper
Patch moves (and renames) the infrastructure to fix compilation
failures when dri3 is not enabled in the build.
Fixes:
3170b63314f ("loader: Add infrastructure for tracking active CRTC resources");
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8476
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22897>
Georg Lehmann [Tue, 2 May 2023 09:54:26 +0000 (11:54 +0200)]
aco: also reassign p_extract_vector post ra
Foz-DB Navi21:
Totals from 1223 (0.91% of 134864) affected shaders:
CodeSize: 6923888 -> 6913516 (-0.15%)
Instrs: 1293744 -> 1291151 (-0.20%)
Latency:
16928653 ->
16925035 (-0.02%); split: -0.02%, +0.00%
InvThroughput: 2985304 -> 2984775 (-0.02%); split: -0.02%, +0.00%
VClause: 32260 -> 32319 (+0.18%)
SClause: 54952 -> 54949 (-0.01%)
Copies: 83968 -> 81377 (-3.09%)
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22821>
Georg Lehmann [Wed, 3 May 2023 09:24:19 +0000 (11:24 +0200)]
aco: Assert that operands have the same byte offset when reassigning split vectors
This can not happen because the post-RA optimizer doesn't support sub dword
writes at the moment, but everytime I look at this I wonder if there might
be a bug here.
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22821>
Daniel Schürmann [Thu, 4 May 2023 10:48:08 +0000 (12:48 +0200)]
vulkan/pipeline_cache: don't log warnings for internal caches
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22850>
Lionel Landwerlin [Wed, 10 May 2023 05:16:59 +0000 (08:16 +0300)]
Revert "intel/compiler: make uses_pos_offset a tri-state"
This reverts commit
5489033fa8568ecacafe32ceab36f89f2e14f3dc.
The problem I was trying to address is that we were programming the
3DSTATE_PS::PositionXYOffsetSelect bit differently with GPL (CENTROID)
than without (NONE).
I failed to understand that this bit also impacts the thread payload
layout. GPL fragment shaders don't know ahead of time if pos_offset is
going to be used. It'll be choosen at runtime base on push constant
bits. So we need to program this bit different just to have a payload
matching the compiled shader code.
This fixes the freedoom replay with GPL FS shader in SIMD32.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22938>
Juan A. Suarez Romero [Thu, 11 May 2023 06:39:36 +0000 (08:39 +0200)]
v3d/ci: annotate failures
Annotate some of the failures with the root cause.
Remove also some tests that are actually skipped.
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22953>
Chia-I Wu [Mon, 13 Mar 2023 21:35:55 +0000 (14:35 -0700)]
amd/drm-shim: add amdgpu drm-shim
This is enough to run offscreen apps such as vulkaninfo or deqp-vk.
v2: remove unnecessary idep_amdgfxregs_h dependency
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21892>
Chia-I Wu [Wed, 10 May 2023 18:27:42 +0000 (11:27 -0700)]
drm-shim: apply file overrides for open
loader_get_pci_driver calls os_read_file on linux to get the pci id, and
os_read_file uses open instead of fopen.
This allows loader_get_pci_driver to work rather than falling back to
loader_get_kernel_driver_name.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22951>
Jesse Natalie [Tue, 9 May 2023 21:57:08 +0000 (14:57 -0700)]
microsoft/compiler: Do basic I/O analysis for dependency tables
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22949>
Jesse Natalie [Mon, 8 May 2023 21:40:47 +0000 (14:40 -0700)]
microsoft/compiler: Allocate space for I/O and viewID dependency tables before instruction processing
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22949>
Danylo Piliaiev [Thu, 25 Aug 2022 15:25:30 +0000 (18:25 +0300)]
tu: Re-enable bufferDeviceAddressCaptureReplay
We cannot immidiately free VMA range when BO is freed, we have to
wait until kernel stops considered BO as busy and frees its internal
VMA range. Otherwise userspace and kernel VMA will get desynchronized.
To fix this and re-enable replaying of BDA we place BO's information
into a queue. The queue is drained:
- On BO allocation;
- When we cannot allocate an iova passed from the client.
For more information about this see:
https://gitlab.freedesktop.org/mesa/mesa/-/issues/7106
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18254>
Rob Clark [Wed, 10 May 2023 17:42:17 +0000 (10:42 -0700)]
tu: Move queue deletion to last
For zombie vma tracking, we'll need access to the queue at bo deletion
time. This simplest way to make that work is just move queue deletion
to late in device teardown.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18254>
Danylo Piliaiev [Tue, 11 Oct 2022 15:51:08 +0000 (17:51 +0200)]
tu: Move VMA heap to the logical device
Since last commit drm fd is being created on per logical device
granularity, which means each logical device has its own
address space. So VMA heap could be moved to logical device.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18254>
Danylo Piliaiev [Tue, 11 Oct 2022 13:43:31 +0000 (15:43 +0200)]
tu: Create drm fd per logical device
The main reason is to simplify BO managment when
bufferDeviceAddressCaptureReplay would be enabled.
Having to track some BO information in physical device and some
info in logical device gets challenging when BOs are shared
between logical devices.
Other benefits:
- Isolation from hangs in other logical devices;
- Each logical device limited only by its own address space size.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18254>
Emma Anholt [Wed, 10 May 2023 18:24:59 +0000 (11:24 -0700)]
ci/zink+anv: Skip a couple more long tests pre-merge.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22866>
Emma Anholt [Mon, 8 May 2023 19:51:31 +0000 (12:51 -0700)]
ci: Re-enable some piglit tests that should be fast enough post-uprev.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22866>
Collabora's Gfx CI Team [Sat, 6 May 2023 00:04:20 +0000 (00:04 +0000)]
Uprev Piglit to
536975d94a40cf76a69fcfa786c2513eccd0c989
https://gitlab.freedesktop.org/mesa/piglit/-/compare/
79a084c56b6dd79f7c3a97b57a72963121ebb1e6...
536975d94a40cf76a69fcfa786c2513eccd0c989
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22866>
Emma Anholt [Mon, 8 May 2023 23:37:09 +0000 (16:37 -0700)]
zink: Don't flag legacy_shadow_mask for RED-only reads in the shader.
It is very common in games to read just the .x channel of a vec4 shadow
result (since GL defaults to either LUMINANCE or RED depth mode depending
on context). So, we can avoid shader recompiles to handle the other
components, in that case.
Fixes some recompiles in CS:GO.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22912>
Emma Anholt [Mon, 8 May 2023 22:31:19 +0000 (15:31 -0700)]
zink: Fix silly void * type in rewrite_tex_dest.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22912>
Emma Anholt [Mon, 8 May 2023 23:12:42 +0000 (16:12 -0700)]
zink: Explain some of the current pathway for shadow sampling.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22912>
Emma Anholt [Tue, 9 May 2023 19:40:23 +0000 (12:40 -0700)]
mesa: Fix precompile of GLSL programs with shadow samplers.
Reduces fp variant recompiles on google's CS:GO trace on zink+anv from 115
to 31.
Fixes:
0843d4cbc354 ("nir: switch to a normal sampler for ARB program with not depth textures")
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22928>
Emma Anholt [Tue, 9 May 2023 19:21:35 +0000 (12:21 -0700)]
mesa: Fix debug logging of fp compile compare func.
When we're doing COMPARE_FUNC_ALWAYS, that's not part of a shader
precompile miss.
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22928>
Jiadong Zhu [Sat, 6 May 2023 09:35:05 +0000 (17:35 +0800)]
ac: enable SHADOW_GLOBAL_CONFIG for preemptible ib
SHADOW_GLOBAL_CONFIG is mandatory for mid command buffer preemmption.
Fixes:
69014d8c94f (radeonsi: implement CP register shadowing)
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22916>
Konstantin Seurer [Sun, 7 May 2023 09:53:21 +0000 (11:53 +0200)]
nir/lower_io: Emit less iadd(x, 0)
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22890>
Rob Clark [Sun, 7 May 2023 15:17:05 +0000 (08:17 -0700)]
freedreno/a5xx+a6xx: Don't allocate LRZ for z32
We don't do LRZ in this case, so no point in allocating the LRZ buffer.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22895>
Rob Clark [Sun, 23 Apr 2023 17:48:41 +0000 (10:48 -0700)]
freedreno/a6xx: Actually use LRZ for ms
We know the z value after the fallback clear. But we need to set
rsc->lrz_valid _after_ the fallback clear invalidates it.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22895>
Rob Clark [Sun, 23 Apr 2023 14:21:33 +0000 (07:21 -0700)]
freedreno/a6xx: Move LRZ clears to gmem
If we have multiple LRZ clears, emit them all at once. This also avoids
redundant LRZ clears if app does multiple clears in sequence.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22895>
Rob Clark [Sat, 22 Apr 2023 20:06:15 +0000 (13:06 -0700)]
freedreno/a6xx: New subpass on mid-frame clears
If we get a mid-frame clear, split out a new subpass rather than having
to fall-back to u_blitter clears.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22895>
Rob Clark [Sat, 22 Apr 2023 19:44:59 +0000 (12:44 -0700)]
freedreno/a6xx: Per-subpass LRZ
Allow the LRZ buffer to be re-allocated if a mid-frame depth clear
starts a new subpass.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22895>
Rob Clark [Sat, 22 Apr 2023 18:00:05 +0000 (11:00 -0700)]
freedreno/a6xx: Introduce batch subpasses
Just the scaffolding for now, nothing actually creates multiple sub-
passes yet. For now, only planning to use this for a6xx, as other
gens are doing clears on 3d.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22895>
Rob Clark [Sat, 22 Apr 2023 17:36:36 +0000 (10:36 -0700)]
freedreno/a6xx: Split tile loads and clears
This will give better visibility in perfetto, and prepares for the next
commit where we could have per-subpass clears.
While we are at it, start adopting vulkan terms for tile load/store. No
need to be pointlessly different.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22895>
Rob Clark [Sat, 22 Apr 2023 18:07:58 +0000 (11:07 -0700)]
freedreno/a6xx: Switch to batch->cleared
batch->fast_cleared will be per-subpass. But we can use the cleared
bitmask instead in the few places where we just need to know if there
was a clear in any subpass. For the conditional-ib it is even
preferable since we know a clear touched the contents of the tile so
we know what the result of the conditional would be.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22895>
Rob Clark [Sat, 22 Apr 2023 16:55:57 +0000 (09:55 -0700)]
freedreno/a6xx: Simplify per-tile conditional IBs
Handle the logic which decides between conditional or unconditional IB
in one place.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22895>
Rob Clark [Wed, 19 Apr 2023 22:21:11 +0000 (15:21 -0700)]
freedreno/a6xx: Add ctx->emit_sysmem()
Once we introduce subpass, it won't be just a single IB. But per
subpass clears + IB. So interoduce a sysmem counterpart for
emit_tile().
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22895>
Rob Clark [Wed, 19 Apr 2023 16:33:06 +0000 (09:33 -0700)]
freedreno/a6xx: Move LRZ clear to blitter
This is where it belongs. And will simplify moving LRZ clears to
fd6_gmem.cc
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22895>
Rob Clark [Sat, 22 Apr 2023 19:32:21 +0000 (12:32 -0700)]
freedreno/batch: Add helper to set fb state
Stop open-coding and add a helper.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22895>
Mike Blumenkrantz [Wed, 10 May 2023 14:49:14 +0000 (10:49 -0400)]
zink: disable always zs feedback loop on radv
this shouldn't have been enabled
Fixes:
56fb2580642 ("zink: replace mixed_zs with zs feedback loops")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22946>
Yiwei Zhang [Wed, 10 May 2023 05:38:58 +0000 (05:38 +0000)]
anv: apply ANV_BO_ALLOC_IMPLICIT_SYNC for external memory
This is necessary to make anv work with clients like VA-API which relies
on implicit fencing only. The bahavior matches iris i915_batch_submit.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22937>
Eric Engestrom [Wed, 10 May 2023 10:16:49 +0000 (11:16 +0100)]
ci: bump bin/ci/ deps to support python 3.11
Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22943>
Luigi Santivetti [Mon, 3 Apr 2023 09:02:02 +0000 (10:02 +0100)]
pvr: add GUARD_SIZE_DEFAULT for CDM and VDM control stream links 1 and 2
Signed-off-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22631>
Luigi Santivetti [Thu, 20 Apr 2023 10:46:03 +0000 (11:46 +0100)]
pvr: use PVR_DW_TO_BYTES for stream_link_space calculation
Signed-off-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22631>
Timur Kristóf [Sat, 6 May 2023 16:00:00 +0000 (18:00 +0200)]
aco: Initialize vcmpx field in get_cmp_info.
Fixes:
578d0a19341a5df2be555e19396a20c81d79c7a9
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22885>
Timur Kristóf [Sat, 6 May 2023 15:03:22 +0000 (17:03 +0200)]
aco: Don't allow any VALU instruction to write m0.
Fixes:
d5398b62da1913e7224c826da0dbd5fa88436f18
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22885>
Simon Ser [Thu, 8 Dec 2022 16:14:02 +0000 (17:14 +0100)]
vulkan/wsi/wayland: add 16-bit formats
Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20234>
Iago Toral Quiroga [Thu, 4 May 2023 11:23:28 +0000 (13:23 +0200)]
broadcom/compiler: increase peephole limit to 24 instructions
This helps by reducing the number of branches with their corresponding
delay slots, at the expense of additional register pressure. It also helps
a lot with SFU stalls, probably because removing control-flow blocks
gives us more QPU scheduling flexibility to hide them.
Shader-db results below correspond to the "closed shaders" set, since the
full set is very dominated by the massive impact this change has on Skia's
shaders (for the better), so this is probably more representative of real
impact:
total instructions in shared programs:
11887255 ->
11854898 (-0.27%)
instructions in affected programs: 538170 -> 505813 (-6.01%)
helped: 1653
HURT: 43
Instructions are helped.
total threads in shared programs: 385924 -> 385872 (-0.01%)
threads in affected programs: 236 -> 184 (-22.03%)
helped: 22
HURT: 48
Inconclusive result (%-change mean confidence interval includes 0).
total uniforms in shared programs: 3552808 -> 3547894 (-0.14%)
uniforms in affected programs: 157486 -> 152572 (-3.12%)
helped: 1673
HURT: 35
Uniforms are helped.
total max-temps in shared programs: 2062403 -> 2064720 (0.11%)
max-temps in affected programs: 18209 -> 20526 (12.72%)
helped: 168
HURT: 369
Max-temps are HURT.
total spills in shared programs: 1937 -> 1994 (2.94%)
spills in affected programs: 79 -> 136 (72.15%)
helped: 0
HURT: 1
total fills in shared programs: 2652 -> 2717 (2.45%)
fills in affected programs: 115 -> 180 (56.52%)
helped: 0
HURT: 1
total sfu-stalls in shared programs: 19349 -> 18010 (-6.92%)
sfu-stalls in affected programs: 2321 -> 982 (-57.69%)
helped: 674
HURT: 74
Sfu-stalls are helped.
total inst-and-stalls in shared programs:
11906604 ->
11872908 (-0.28%)
inst-and-stalls in affected programs: 541339 -> 507643 (-6.22%)
helped: 1656
HURT: 43
Inst-and-stalls are helped.
total nops in shared programs: 245740 -> 238085 (-3.12%)
nops in affected programs: 19282 -> 11627 (-39.70%)
helped: 1335
HURT: 76
Nops are helped.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22922>
Samuel Pitoiset [Tue, 9 May 2023 09:50:34 +0000 (11:50 +0200)]
radv/ci: stop setting MESA_SPIRV_LOG_LEVEL
Use the default VTN logging level which is warning.
Suggested-by: Emma Anholt <emma@anholt.net>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6263
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Martin Roukala <martin.roukala@mupuf.org>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22917>
Samuel Pitoiset [Tue, 9 May 2023 09:52:55 +0000 (11:52 +0200)]
spirv: ignore SpvDecorationInvariant warning on struct members
Similar to SpvDecorationRestrict, looks like it's also incorrectly
generated by glslang.
This will allow RADV/CI to leave MESA_SPIRV_LOG_LEVEL as default
(ie. only warnings).
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Martin Roukala <martin.roukala@mupuf.org>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22917>
Simon Ser [Fri, 5 May 2023 15:44:38 +0000 (17:44 +0200)]
radv: advertise LINEAR filter support for multiplanar/subsampled
It seems like radv supports this but doesn't advertise it.
Signed-off-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22875>
Kurt Kartaltepe [Sun, 7 May 2023 19:55:48 +0000 (12:55 -0700)]
drirc: Set limit_trig_input_range option for Nier games
Resolves ambient occlusion rendering in Replicant
Resolves grass and ocean animations in Automata, and maybe more.
Both of these games have shaders that expect trig values to work across
large ranges with good precision.
Closes #7656
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22894>
Juan A. Suarez Romero [Thu, 27 Apr 2023 12:15:18 +0000 (14:15 +0200)]
v3d: apply proper clamping when setting up RT
Ensure the render target values are in the proper range.
This fixes `spec@!opengl 3.0@render-integer`.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22733>
Juan A. Suarez Romero [Thu, 27 Apr 2023 12:13:14 +0000 (14:13 +0200)]
v3d: upgrade V3D 4.1 to 4.2 version
Some of the new features require at least V3D 4.2. And actually, 4.2 is
the version used by the Raspberry Pi 4 hardware.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22733>
Juan A. Suarez Romero [Thu, 27 Apr 2023 12:11:23 +0000 (14:11 +0200)]
v3d: add per hw-version caller macro
Instead of hardcoding conditionals to know which hardwared-based version
of a function to call, just wrap them in a macro to use
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22733>
Daniel Schürmann [Tue, 25 Apr 2023 17:44:17 +0000 (19:44 +0200)]
radv/rt: store stack_sizes per stage instead of per group
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22503>
Daniel Schürmann [Wed, 26 Apr 2023 10:26:27 +0000 (12:26 +0200)]
radv/rt: use vk_multialloc for radv_ray_tracing_pipeline
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22503>
Daniel Schürmann [Fri, 14 Apr 2023 14:34:27 +0000 (16:34 +0200)]
radv/rt: refactor radv_rt_pipeline_compile()
This patch moves the NIR shader creation into radv_rt_pipeline_compile()
and simplifies radv_rt_pipeline_create().
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22503>
Daniel Schürmann [Fri, 14 Apr 2023 13:50:13 +0000 (15:50 +0200)]
radv/rt: unify radv_rt_pipeline_create() and radv_rt_pipeline_library_create()
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22503>
Daniel Schürmann [Fri, 14 Apr 2023 12:53:02 +0000 (14:53 +0200)]
radv/rt: unify radv_ray_tracing_lib_pipeline and radv_ray_tracing_pipeline
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22503>
Daniel Schürmann [Fri, 14 Apr 2023 12:09:01 +0000 (14:09 +0200)]
radv/rt: change base of radv_ray_tracing_lib_pipeline to radv_compute_pipeline
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22503>
Iván Briano [Tue, 9 May 2023 18:53:37 +0000 (11:53 -0700)]
anv: enable graphics pipeline libraries by default
Since we are disabling mesh, which has issues with gpl, enable gpl by
default now, leaving the renamed environment variable as a way to
disable it for debug purposes.
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22910>
Iván Briano [Mon, 8 May 2023 21:22:15 +0000 (14:22 -0700)]
anv: put EXT_mesh_shader behind an environment variable
We are seeing frequent hangs in other workloads when something using
mesh shaders runs at the same time, so gate the feature behind an
environment variable until we figure out what's going on.
v2: (Sagar)
- Give the mesh enabled variable a more descriptive name
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22910>
Mike Blumenkrantz [Tue, 9 May 2023 14:14:20 +0000 (10:14 -0400)]
zink: also cache swapchain semaphores
a semaphore is a semaphore, as they say
Fixes:
7399b2241f8 ("zink: move semaphore caching to zink_reset_batch_state()")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22935>
Mike Blumenkrantz [Wed, 3 May 2023 17:16:25 +0000 (13:16 -0400)]
zink: block more flushes during unordered blits
Fixes:
89aa3635932 ("zink: block oom flushes during unordered blits")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22931>
Mike Blumenkrantz [Tue, 9 May 2023 23:28:18 +0000 (19:28 -0400)]
zink: adjust bindless texel buffer handle before indexing
buffer handle ids are offset by ZINK_MAX_BINDLESS_HANDLES, but the actual
index is zero-based
Fixes:
99ba529feed ("zink: implement descriptor buffer handling of bindless texture")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22931>
Mike Blumenkrantz [Tue, 9 May 2023 23:17:39 +0000 (19:17 -0400)]
zink: compare desc set to detect bindless vars in separate shaders
the bindless flag here isn't set, so this check did nothing
Fixes:
e3b746e3a31 ("zink: use GPL to handle (simple) separate shader objects")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22931>
Mike Blumenkrantz [Tue, 9 May 2023 22:19:19 +0000 (18:19 -0400)]
zink: bind bindless db set when updating separate shader db sets
this otherwise doesn't bind a bindless set and hangs
Fixes:
e3b746e3a31 ("zink: use GPL to handle (simple) separate shader objects")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22931>
Mike Blumenkrantz [Tue, 9 May 2023 20:32:08 +0000 (16:32 -0400)]
zink: set debug callback on context
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22899>
Mike Blumenkrantz [Tue, 9 May 2023 18:50:36 +0000 (14:50 -0400)]
zink: add perf_debug for "interesting" shader compiles
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22899>
Mike Blumenkrantz [Tue, 9 May 2023 18:45:09 +0000 (14:45 -0400)]
zink: make mesa_logw separate from perf_debug
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22899>
Mike Blumenkrantz [Mon, 8 May 2023 12:54:01 +0000 (08:54 -0400)]
zink: add ZINK_DEBUG=nobgc
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22899>