Francesco Dolcini [Thu, 15 Jun 2023 09:50:57 +0000 (11:50 +0200)]
arm64: dts: ti: add verdin am62 dahlia
Add Toradex Verdin AM62 Dahlia.
Link: https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kit
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Link: https://lore.kernel.org/r/20230615095058.33890-5-francesco@dolcini.it
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Francesco Dolcini [Thu, 15 Jun 2023 09:50:56 +0000 (11:50 +0200)]
arm64: dts: ti: add verdin am62
This patch adds the device tree to support Toradex Verdin AM62 a
computer on module which can be used on different carrier boards
and the Toradex Verdin Development Board carrier board.
The module consists of an TI AM62 family SoC (either AM623 or AM625), a
TPS65219 PMIC, a Gigabit Ethernet PHY, 512MB to 2GB of LPDDR4 RAM, an
eMMC, a TLA2024 ADC, an I2C EEPROM, an RX8130 RTC, and optional Parallel
RGB to MIPI DSI bridge plus an optional Bluetooth/Wi-Fi module.
Anything that is not self-contained on the module is disabled by
default.
So far there is no display nor USB role switch supported, apart of that
all the other functionalities are fine.
Link: https://developer.toradex.com/hardware/verdin-som-family/modules/verdin-am62/
Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62
Link: https://www.toradex.com/products/carrier-board/verdin-development-board-kit
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Link: https://lore.kernel.org/r/20230615095058.33890-4-francesco@dolcini.it
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Francesco Dolcini [Thu, 15 Jun 2023 09:50:54 +0000 (11:50 +0200)]
dt-bindings: arm: ti: add toradex,verdin-am62 et al.
Add toradex,verdin-am62 for Toradex Verdin AM62 SoM, its
nonwifi and wifi variants and the carrier boards (Dahlia,
Verdin Development Board and Yavia) they may be mated in.
Link: https://developer.toradex.com/hardware/verdin-som-family/modules/verdin-am62/
Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230615095058.33890-2-francesco@dolcini.it
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Wadim Egorov [Thu, 4 May 2023 14:01:43 +0000 (16:01 +0200)]
arm64: dts: ti: Add basic support for phyBOARD-Lyra-AM625
The phyCORE-AM62x [1] is a SoM (System on Module) featuring TI's AM62x SoC.
It can be used in combination with different carrier boards.
This module can come with different sizes and models for
DDR, eMMC, SPI NOR Flash and various SoCs from the AM62x family.
A development Kit, called phyBOARD-Lyra [2] is used as a carrier board
reference design around the AM62x SoM.
Supported features:
* Debug UART
* SPI NOR Flash
* eMMC
* 2x Ethernet
* Micro SD card
* I2C EEPROM
* I2C RTC
* GPIO Expander
* LEDs
* USB
For more details, see:
[1] Product page SoM: https://www.phytec.com/product/phycore-am62x
[2] Product page CB: https://www.phytec.com/product/phyboard-am62x
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20230504140143.1425951-2-w.egorov@phytec.de
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Wadim Egorov [Thu, 4 May 2023 14:01:42 +0000 (16:01 +0200)]
dt-bindings: arm: ti: Add bindings for PHYTEC AM62x based hardware
Add devicetree bindings for AM62x based phyCORE-AM62 SoM
and phyBOARD-Lyra RDK.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20230504140143.1425951-1-w.egorov@phytec.de
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Mon, 24 Apr 2023 17:36:21 +0000 (12:36 -0500)]
arm64: dts: ti: k3-j7200-mcu-wakeup: Remove 0x unit address prefix from nodename
unit-address should not use a 0x prefix.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230424173623.477577-2-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Thu, 1 Jun 2023 18:31:47 +0000 (13:31 -0500)]
arm64: dts: ti: k3-j721e-som-p0: Enable wakeup_i2c0 and eeprom
Enable wakeup_i2c and use un-used pinmux. While at it, describe the
board detection eeprom present on the board.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230601183151.1000157-6-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Tue, 30 May 2023 18:53:35 +0000 (13:53 -0500)]
arm64: dts: ti: k3-am64: Add ESM support
Add Error Signaling Module (ESM) instances in MCU and MAIN domains.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230530185335.79942-3-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Tue, 30 May 2023 18:53:34 +0000 (13:53 -0500)]
arm64: dts: ti: k3-am62: Add ESM support
Add Error Signaling Module (ESM) instances in MCU and MAIN domains.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230530185335.79942-2-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Neha Malcom Francis [Thu, 4 May 2023 08:05:26 +0000 (13:35 +0530)]
arm64: dts: ti: k3-j7200: Add ESM support
Add address entry mapping ESM on J7200.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Link: https://lore.kernel.org/r/20230504080526.133149-4-n-francis@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Neha Malcom Francis [Thu, 4 May 2023 08:05:25 +0000 (13:35 +0530)]
arm64: dts: ti: k3-j721e: Add ESM support
Add address entry mapping ESM on J721E.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Link: https://lore.kernel.org/r/20230504080526.133149-3-n-francis@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Neha Malcom Francis [Thu, 4 May 2023 08:05:24 +0000 (13:35 +0530)]
dt-bindings: misc: esm: Add ESM support for TI K3 devices
Document the binding for TI K3 ESM (Error Signaling Module) block.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230504080526.133149-2-n-francis@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Fri, 2 Jun 2023 15:35:54 +0000 (10:35 -0500)]
arm64: dts: ti: k3-j721s2-som-p0: Enable wakeup_i2c0 and eeprom
Enable wakeup_i2c and use un-used pinmux. While at it, describe the
board detection eeprom present on the board.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20230602153554.1571128-7-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Fri, 2 Jun 2023 15:35:53 +0000 (10:35 -0500)]
arm64: dts: ti: k3-j721s2-common-proc-board: Add uart pinmux
Define the wakeup uart pin-mux for completeness and add explicit
muxing for mcu_uart0. This allows the device tree usage in bootloader
and firmwares that can configure the same appropriately.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20230602153554.1571128-6-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Fri, 2 Jun 2023 15:35:52 +0000 (10:35 -0500)]
arm64: dts: ti: k3-am68-sk-som: Enable wakeup_i2c0 and eeprom
Enable wakeup_i2c. While at it, describe the board detection eeprom
present on the board.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Sinthu Raja <sinthu.raja@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20230602153554.1571128-5-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Fri, 2 Jun 2023 15:35:51 +0000 (10:35 -0500)]
arm64: dts: ti: k3-am68-sk-base-board: Add uart pinmux
Define the wakeup uart pin-mux for completeness and add explicit
muxing for mcu_uart0. This allows the device tree usage in bootloader
and firmwares that can configure the same appropriately.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20230602153554.1571128-4-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Sinthu Raja [Fri, 2 Jun 2023 15:35:50 +0000 (10:35 -0500)]
arm64: dts: ti: k3-am68-sk-base-board: Add pinmux for RPi Header
Add pinmux required to bring out the i2c and gpios on 40-pin RPi
expansion header on the AM68 SK board.
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20230602153554.1571128-3-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Sinthu Raja [Fri, 2 Jun 2023 15:35:49 +0000 (10:35 -0500)]
arm64: dts: ti: k3-j721s2: Fix wkup pinmux range
The WKUP_PADCONFIG register region in J721S2 has multiple non-addressable
regions, accordingly split the existing wkup_pmx region as follows to avoid
the non-addressable regions and include the rest of valid WKUP_PADCONFIG
registers. Also update references to old nodes with new ones.
wkup_pmx0 -> 13 pins (WKUP_PADCONFIG 0 - 12)
wkup_pmx1 -> 11 pins (WKUP_PADCONFIG 14 - 24)
wkup_pmx2 -> 72 pins (WKUP_PADCONFIG 26 - 97)
wkup_pmx3 -> 1 pin (WKUP_PADCONFIG 100)
Fixes:
b8545f9d3a54 ("arm64: dts: ti: Add initial support for J721S2 SoC")
Cc: <stable@vger.kernel.org> # 6.3
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
Signed-off-by: Thejasvi Konduru <t-konduru@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20230602153554.1571128-2-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Udit Kumar [Sun, 11 Jun 2023 11:11:40 +0000 (16:41 +0530)]
arm64: dts: ti: k3-j7200: Drop SoC level aliases
Aiases are defined at board level, so dropping from soc level
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230611111140.3189111-7-u-kumar1@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Udit Kumar [Sun, 11 Jun 2023 11:11:39 +0000 (16:41 +0530)]
arm64: dts: ti: k3-j7200-common-proc-board: Define aliases at board level
Define aliases at board level
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230611111140.3189111-6-u-kumar1@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Udit Kumar [Sun, 11 Jun 2023 11:11:38 +0000 (16:41 +0530)]
arm64: dts: ti: k3-j7200-common-proc-board: Add uart pinmux
Add main, mcu, wakeup domain uart0 pin mux into common board file and it's
reference to uart node.
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230611111140.3189111-5-u-kumar1@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Udit Kumar [Sun, 11 Jun 2023 11:11:37 +0000 (16:41 +0530)]
arm64: dts: ti: k3-j7200-common-proc-board: remove duplicate main_i2c0 pin mux
main_i2c0 pin mux was duplicated in som and common file.
So removing duplicated node from common file.
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230611111140.3189111-4-u-kumar1@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Udit Kumar [Sun, 11 Jun 2023 11:11:36 +0000 (16:41 +0530)]
arm64: dts: ti: k3-j7200: Configure pinctrl for timer IO pads
There are timer IO pads in the MCU domain, and in the MAIN domain. These
pads can be muxed for the related timers.
There are timer IO control registers for input and output. The registers
for CTRLMMR_TIMER*_CTRL and CTRLMMR_MCU_TIMER*_CTRL are used to control
the input. The registers for CTCTRLMMR_TIMERIO*_CTRL and
CTRLMMR_MCU_TIMERIO*_CTRL the output.
The multiplexing is documented in TRM "5.1.2.3.1.4 Timer IO Muxing Control
Registers" and "5.1.3.3.1.5 Timer IO Muxing Control Registers", and the
CASCADE_EN bit is documented in TRM "12.6.3.1 Timers Overview".
For chaining timers, the timer IO control registers also have a CASCADE_EN
input bit in the CTRLMMR_TIMER*_CTRL in the registers. The CASCADE_EN bit
muxes the previous timer output, or possibly and external TIMER_IO pad
source, to the input clock of the selected timer instance for odd numered
timers. For the even numbered timers, the CASCADE_EN bit does not do
anything. The timer cascade input routing options are shown in TRM
"Figure 12-3224. Timers Overview". For handling beyond multiplexing, the
driver support for timer cascading should be likely be handled via the
clock framework.
The MCU timer controls are also marked as reserved for
usage by the MCU firmware.
Cc: Nishanth Menon <nm@ti.com>
Cc: Vignesh Raghavendra <vigneshr@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230611111140.3189111-3-u-kumar1@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Udit Kumar [Sun, 11 Jun 2023 11:11:35 +0000 (16:41 +0530)]
arm64: dts: ti: k3-j7200: Add general purpose timers
There are 20 general purpose timers on j721e that can be used for
things like PWM using pwm-omap-dmtimer driver. There are also
additional ten timers in the MCU domain which are meant for MCU
firmware usage and hence marked reserved by default.
The odd numbered timers have the option of being cascaded to even
timers to create a 64 bit non-atomic counter which is racy in simple
usage, hence the clock muxes are explicitly setup to individual 32 bit
counters driven off system crystal (HFOSC) as default.
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230611111140.3189111-2-u-kumar1@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Thu, 1 Jun 2023 18:31:51 +0000 (13:31 -0500)]
arm64: dts: ti: k3-j721e: Drop SoC level aliases
Drop the SoC level aliases as these need to be done at board level.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230601183151.1000157-10-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Thu, 1 Jun 2023 18:31:50 +0000 (13:31 -0500)]
arm64: dts: ti: k3-j721e-common-proc-board: Define aliases at board level
Define the aliases at the board level instead of using generic aliases
at SoC level.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230601183151.1000157-9-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Thu, 1 Jun 2023 18:31:49 +0000 (13:31 -0500)]
arm64: dts: ti: k3-j721e-sk: Define aliases at board level
Define the aliases at the board level instead of using generic aliases
at SoC level.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230601183151.1000157-8-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Thu, 1 Jun 2023 18:31:48 +0000 (13:31 -0500)]
arm64: dts: ti: k3-j721e-beagleboneai64: Add wakeup_uart pinmux
Define the wakeup uart pin-mux for completeness. This allows the
device tree usage in bootloader and firmwares that can configure the
same appropriately.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230601183151.1000157-7-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Thu, 1 Jun 2023 18:31:47 +0000 (13:31 -0500)]
arm64: dts: ti: k3-j721e-som-p0: Enable wakeup_i2c0 and eeprom
Enable wakeup_i2c and use un-used pinmux. While at it, describe the
board detection eeprom present on the board.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230601183151.1000157-6-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Thu, 1 Jun 2023 18:31:46 +0000 (13:31 -0500)]
arm64: dts: ti: j721e-common-proc-board: Add uart pinmux
Explicitly define the pinmux rather than depend on bootloader configured
pinmux for the platform.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230601183151.1000157-5-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Thu, 1 Jun 2023 18:31:45 +0000 (13:31 -0500)]
arm64: dts: ti: j721e-som/common-proc-board: Add product links
Add product links to get reference to schematics and design files
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230601183151.1000157-4-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Thu, 1 Jun 2023 18:31:44 +0000 (13:31 -0500)]
arm64: dts: ti: k3-j721e-sk: Enable wakeup_i2c0 and eeprom
Enable wakeup_i2c and use un-used pinmux. While at it, describe the
board detection eeprom present on the board.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230601183151.1000157-3-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Thu, 1 Jun 2023 18:31:43 +0000 (13:31 -0500)]
arm64: dts: ti: k3-j721e-sk: Add missing uart pinmuxes
Rather than depend on the default pinmuxes, explicitly describe the
pinmux
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230601183151.1000157-2-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Andrew Davis [Thu, 1 Jun 2023 18:49:33 +0000 (13:49 -0500)]
arm64: dts: ti: k3-am64: Use phandle to stdout UART node
Using a phandle makes it clear which UART we are choosing without needing
to resolve through an alias first.
Especially useful for boards like the TI J721s2-EVM where the alias is
"serial2" but it actually resolves to the 8th UART instance(main_uart8).
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230601184933.358731-2-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Andrew Davis [Thu, 1 Jun 2023 18:49:32 +0000 (13:49 -0500)]
arm64: dts: ti: k3-am64: Only set UART baud for used ports
As the binding for "current-speed" states, this should only be used
when the baud rate of an attached device cannot be detected. This is
the case for our attached on-board USB-to-UART converter used for
early kernel console. For all other unconnected/disabled ports this
can be configured in userspace later, DT is not the place for device
configuration, especially when there are already standard ways to
set serial baud in userspace.
Remove setting baud for all disabled serial ports and move setting
it for the couple enabled ports down into the board files.
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230601184933.358731-1-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Dasnavis Sabiya [Fri, 2 Jun 2023 21:49:37 +0000 (16:49 -0500)]
arm64: dts: ti: k3-am69-sk: Add pinmux for RPi Header
Add pinmux required to bring out the i2c and gpios on 40 pin RPi
expansion header on AM69 SK board.
Signed-off-by: Dasnavis Sabiya <sabiya.d@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20230602214937.2349545-9-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Fri, 2 Jun 2023 21:49:36 +0000 (16:49 -0500)]
arm64: dts: ti: k3-am69-sk: Enable wakeup_i2c0 and eeprom
Enable wakeup_i2c and use un-used pinmux. While at it, describe the
board detection eeprom present on the board.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20230602214937.2349545-8-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Fri, 2 Jun 2023 21:49:35 +0000 (16:49 -0500)]
arm64: dts: ti: k3-am69-sk: Add mcu and wakeup uarts
Add wakeup and MCU uart. This allows the device tree usage in
bootloader and firmwares that can configure the same appropriately.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20230602214937.2349545-7-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Fri, 2 Jun 2023 21:49:34 +0000 (16:49 -0500)]
arm64: dts: ti: k3-am69-sk: Enable mcu network port
Enable networking for NFS and basic networking functionality.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20230602214937.2349545-6-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Fri, 2 Jun 2023 21:49:33 +0000 (16:49 -0500)]
arm64: dts: ti: k3-am69-sk: Fix main_i2c0 alias
main_i2c0 is aliased as i2c0 which creates a problem for u-boot R5
SPL attempting to reuse the same definition in the common board
detection logic as it looks for the first i2c instance as the bus on
which to detect the eeprom to understand the board variant involved.
Switch main_i2c0 to i2c3 alias allowing us to introduce wkup_i2c0
and potentially space for mcu_i2c instances in the gap for follow on
patches.
Fixes:
635fb18ba008 ("arch: arm64: dts: Add support for AM69 Starter Kit")
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20230602214937.2349545-5-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Fri, 2 Jun 2023 21:49:32 +0000 (16:49 -0500)]
arm64: dts: ti: k3-j784s4-evm: Enable wakeup_i2c0 and eeprom
Enable wakeup_i2c and use un-used pinmux. While at it, describe the
board detection eeprom present on the board.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20230602214937.2349545-4-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Fri, 2 Jun 2023 21:49:31 +0000 (16:49 -0500)]
arm64: dts: ti: k3-j784s4-evm: Add mcu and wakeup uarts
Add wakeup and MCU uart. This allows the device tree usage in
bootloader and firmwares that can configure the same appropriately.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20230602214937.2349545-3-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Thejasvi Konduru [Wed, 3 May 2023 08:31:43 +0000 (14:01 +0530)]
arm64: dts: ti: k3-j784s4: Fix wakeup pinmux range and pinctrl node offsets
The wkup_pmx register region in j784s4 has multiple non-addressable
regions, hence the existing wkup_pmx region is split as follows to
avoid the non-addressable regions. The pinctrl node offsets are
also corrected as per the newly split wkup_pmx* nodes.
wkup_pmx0 -> 13 pins (WKUP_PADCONFIG 0 - 12)
wkup_pmx1 -> 11 pins (WKUP_PADCONFIG 14 - 24)
wkup_pmx2 -> 72 pins (WKUP_PADCONFIG 26 - 97)
wkup_pmx3 -> 1 pin (WKUP_PADCONFIG 100)
Fixes:
4664ebd8346a ("arm64: dts: ti: Add initial support for J784S4 SoC")
Signed-off-by: Thejasvi Konduru <t-konduru@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230503083143.32369-1-t-konduru@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Fri, 2 Jun 2023 21:49:30 +0000 (16:49 -0500)]
arm64: dts: ti: k3-j784s4-evm: Fix main_i2c0 alias
main_i2c0 is aliased as i2c0 which creates a problem for u-boot R5
SPL attempting to reuse the same definition in the common board
detection logic as it looks for the first i2c instance as the bus on
which to detect the eeprom to understand the board variant involved.
Switch main_i2c0 to i2c3 alias allowing us to introduce wkup_i2c0
and potentially space for mcu_i2c instances in the gap for follow on
patches.
Fixes:
e20a06aca5c9 ("arm64: dts: ti: Add support for J784S4 EVM board")
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20230602214937.2349545-2-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Neha Malcom Francis [Mon, 5 Jun 2023 11:04:43 +0000 (16:34 +0530)]
arm64: dts: ti: k3-j721s2: Change CPTS clock parent
MAIN_PLL0 has a flag set in DM (Device Manager) that removes it's
capability to re-initialise clock frequencies. CPTS and RGMII has
MAIN_PLL3 as their parent which does not have this flag. While RGMII
needs this reinitialisation to default frequency to be able to get
250MHz with its divider, CPTS can not get its required 200MHz with its
divider. Thus, move CPTS clock parent on J721S2 from MAIN_PLL3_HSDIV1 to
MAIN_PLL0_HSDIV6.
(Note: even GTC will be moved from MAIN_PLL3 to MAIN_PLL0 in U-Boot side
for the same reason)
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Link: https://lore.kernel.org/r/20230605110443.84568-1-n-francis@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Dasnavis Sabiya [Mon, 5 Jun 2023 17:45:51 +0000 (23:15 +0530)]
arm64: dts: ti: k3-am69-sk: Add eMMC mmc0 support
Add support for eMMC card connected to main sdhci0 instance.
Signed-off-by: Dasnavis Sabiya <sabiya.d@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230605174551.160262-1-sabiya.d@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Tue, 6 Jun 2023 18:22:20 +0000 (13:22 -0500)]
arm64: dts: ti: k3-am68-sk-base-board: Fixup reference to phandles array
When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230606182220.3661956-15-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Tue, 6 Jun 2023 18:22:19 +0000 (13:22 -0500)]
arm64: dts: ti: k3-am654-base-board: Fixup reference to phandles array
When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230606182220.3661956-14-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Tue, 6 Jun 2023 18:22:18 +0000 (13:22 -0500)]
arm64: dts: ti: k3-am65-iot*: Fixup reference to phandles array
When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.
Cc: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230606182220.3661956-13-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Tue, 6 Jun 2023 18:22:17 +0000 (13:22 -0500)]
arm64: dts: ti: k3-am64-sk: Fixup reference to phandles array
When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230606182220.3661956-12-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Tue, 6 Jun 2023 18:22:16 +0000 (13:22 -0500)]
arm64: dts: ti: k3-am64-evm: Fixup reference to phandles array
When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230606182220.3661956-11-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Tue, 6 Jun 2023 18:22:15 +0000 (13:22 -0500)]
arm64: dts: ti: k3-am625-sk: Fixup reference to phandles array
When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230606182220.3661956-10-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Tue, 6 Jun 2023 18:22:14 +0000 (13:22 -0500)]
arm64: dts: ti: k3-j721s2-common-proc-board: Fixup reference to phandles array
When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle
and cell arguments easier to catch. Fix the outliers to be consistent
with the rest of the usage.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230606182220.3661956-9-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Tue, 6 Jun 2023 18:22:13 +0000 (13:22 -0500)]
arm64: dts: ti: k3-j7200-som/common-proc-board: Fixup reference to phandles array
When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle
and cell arguments easier to catch. Fix the outliers to be consistent
with the rest of the usage.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230606182220.3661956-8-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Tue, 6 Jun 2023 18:22:12 +0000 (13:22 -0500)]
arm64: dts: ti: k3-am642-phyboard-electra-rdk: Fixup reference to phandles array
When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle
and cell arguments easier to catch. Fix the outliers to be consistent
with the rest of the usage.
Cc: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230606182220.3661956-7-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Tue, 6 Jun 2023 18:22:11 +0000 (13:22 -0500)]
arm64: dts: ti: k3-j721e-beagleboneai64: Fixup reference to phandles array
When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.
Cc: Robert Nelson <robertcnelson@gmail.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230606182220.3661956-6-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Tue, 6 Jun 2023 18:22:10 +0000 (13:22 -0500)]
arm64: dts: ti: k3-j721e-beagleboneai64: Move eeprom WP gpio pinctrl to eeprom node
Move the eeprom WP GPIO mux configuration to be part of the eeprom node
instead of the I2C node.
Cc: Robert Nelson <robertcnelson@gmail.com>
Suggested-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230606182220.3661956-5-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Tue, 6 Jun 2023 18:22:09 +0000 (13:22 -0500)]
arm64: dts: ti: k3-j721e-beagleboneai64: Move camera gpio pinctrl to gpio node
Move the GPIO mux configuration needed for camera module to work to the
GPIO node instead of the I2C node.
Camera nodes are maintained as overlay files, but the common mux is
always needed to ensure that camera probes fine and ensuring the mux
is configured as part of the GPIO module allows for the multiple
overlay files to be simpler.
Cc: Robert Nelson <robertcnelson@gmail.com>
Suggested-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230606182220.3661956-4-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Tue, 6 Jun 2023 18:22:08 +0000 (13:22 -0500)]
arm64: dts: ti: k3-j721e-som-p0/common-proc-board: Fixup reference to phandles array
When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230606182220.3661956-3-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Tue, 6 Jun 2023 18:22:07 +0000 (13:22 -0500)]
arm64: dts: ti: k3-j721e-sk: Fixup reference to phandles array
When referring to array of phandles, using <> to separate the array
entries is better notation as it makes potential errors with phandle and
cell arguments easier to catch. Fix the outliers to be consistent with
the rest of the usage.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230606182220.3661956-2-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Wed, 31 May 2023 21:32:15 +0000 (16:32 -0500)]
arm64: dts: ti: k3-j784s4: Configure pinctrl for timer IO
There are timer IO pads in the MCU domain, and in the MAIN domain.
These pads can be muxed for the related timers.
The details of the multiplexing can be found in the register
documentation and Technical Reference Manual[1].
These are similar to J721e/J7200, but have different mux capabilities.
[1] http://www.ti.com/lit/zip/spruj52
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20230531213215.602395-7-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Wed, 31 May 2023 21:32:14 +0000 (16:32 -0500)]
arm64: dts: ti: k3-j784s4: Add general purpose timers
There are 20 general purpose timers on j784s4 that can be used for
things like PWM using pwm-omap-dmtimer driver. There are also
additional ten timers in the MCU domain which are meant for MCU
firmware usage and hence marked reserved by default.
Though the count is similar to J721e/J7200/j721s2, the device IDs
and clocks used in j784s4 are different with the option of certain
clocks having options of additional clock muxes. Since there is very
minimal reuse, it is cleaner to integrate as part of SoC files itself.
The defaults are configured for clocking the timers from system
clock(HFOSC0).
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20230531213215.602395-6-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Wed, 31 May 2023 21:32:13 +0000 (16:32 -0500)]
arm64: dts: ti: k3-j721s2: Configure pinctrl for timer IO
There are timer IO pads in the MCU domain, and in the MAIN domain. These
pads can be muxed for the related timers.
The details of the multiplexing can be found in the register
documentation and Technical Reference Manual[1].
These are similar to J721e/J7200, but have different mux capabilities.
[1] https://www.ti.com/lit/zip/spruj28
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20230531213215.602395-5-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Wed, 31 May 2023 21:32:12 +0000 (16:32 -0500)]
arm64: dts: ti: k3-j721s2: Add general purpose timers
There are 20 general purpose timers on j721s2 that can be used for
things like PWM using pwm-omap-dmtimer driver. There are also
additional ten timers in the MCU domain which are meant for MCU
firmware usage and hence marked reserved by default.
Though the count is similar to J721e/J7200, the device IDs and clocks
used in j721s2 are different with the option of certain clocks having
options of additional clock muxes. Since there is very minimal reuse,
it is cleaner to integrate as part of SoC files itself. The defaults
are configured for clocking the timers from system clock(HFOSC0).
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20230531213215.602395-4-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Wed, 31 May 2023 21:32:11 +0000 (16:32 -0500)]
arm64: dts: ti: k3-j721e: Configure pinctrl for timer IO
There are timer IO pads in the MCU domain, and in the MAIN domain. These
pads can be muxed for the related timers.
There are timer IO control registers for input and output. The registers
for CTRLMMR_TIMER*_CTRL and CTRLMMR_MCU_TIMER*_CTRL are used to control
the input. The registers for CTCTRLMMR_TIMERIO*_CTRL and
CTRLMMR_MCU_TIMERIO*_CTRL the output.
The multiplexing is documented in Technical Reference Manual[1] under
"Timer IO Muxing Control Registers" and "Timer IO Muxing Control
Registers", and the "Timers Overview" chapters.
We do not expose the cascade_en bit due to the racy usage of
independent 32 bit registers in-line with the timer instantiation in
the device tree. The MCU timer controls are also marked as reserved for
usage by the MCU firmware.
[1] http://www.ti.com/lit/pdf/spruil1
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20230531213215.602395-3-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Wed, 31 May 2023 21:32:10 +0000 (16:32 -0500)]
arm64: dts: ti: k3-j721e: Add general purpose timers
There are 20 general purpose timers on j721e that can be used for
things like PWM using pwm-omap-dmtimer driver. There are also
additional ten timers in the MCU domain which are meant for MCU
firmware usage and hence marked reserved by default.
The odd numbered timers have the option of being cascaded to even
timers to create a 64 bit non-atomic counter which is racy in simple
usage, hence the clock muxes are explicitly setup to individual 32 bit
counters driven off system crystal (HFOSC) as default.
These instantiation differs from J7200 and other SoCs with the device
IDs and clocks involved for muxing.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20230531213215.602395-2-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Tue, 30 May 2023 16:59:00 +0000 (11:59 -0500)]
arm64: dts: ti: k3-j784s4-mcu-wakeup: Add sa3_secproxy and mcu_sec_proxy
Security Management Subsystem(SMS) has it's own unique secure
proxy as part of Security Accelerator (SA3) module. This is used
for communicating with ROM and for special usecases such as HSM
operations. In addition MCU island has it's own secure proxy for
usecases involving the MCU micro controllers. These are in addition
to the one in the main domain DMSS subsystem that is used for general
purpose communication.
Describe the nodes for use with bootloaders and firmware that require
these communication paths which uses interrupts to corresponding micro
controller interrupt controller. Mark the node as disabled since these
instances do not have interrupts routed to the main processor by
default for a complete description of the node.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230530165900.47502-8-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Tue, 30 May 2023 16:58:59 +0000 (11:58 -0500)]
arm64: dts: ti: k3-j721s2-mcu-wakeup: Add sa3_secproxy and mcu_sec_proxy
Security Management Subsystem(SMS) has it's own unique secure
proxy as part of Security Accelerator (SA3) module. This is used
for communicating with ROM and for special usecases such as HSM
operations. In addition MCU island has it's own secure proxy for
usecases involving the MCU micro controllers. These are in addition
to the one in the main domain DMSS subsystem that is used for general
purpose communication.
Describe the nodes for use with bootloaders and firmware that require
these communication paths which uses interrupts to corresponding micro
controller interrupt controller. Mark the node as disabled since these
instances do not have interrupts routed to the main processor by
default for a complete description of the node.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230530165900.47502-7-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Tue, 30 May 2023 16:58:58 +0000 (11:58 -0500)]
arm64: dts: ti: k3-j721e-mcu: Add mcu_secproxy
MCU domain has it's own secure proxy for communicating with ROM and
for R5 micro controller firmware operations. This is in addition to
the one in the main domain NAVSS subsystem that is used for general
purpose communication.
Describe the node for use with bootloaders and firmware that require
this communication path which uses interrupts to corresponding micro
controller interrupt controller. Mark the node as disabled since this
instance does not have interrupts routed to the main processor by
default for a complete description of the node.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230530165900.47502-6-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Tue, 30 May 2023 16:58:57 +0000 (11:58 -0500)]
arm64: dts: ti: k3-j7200-mcu: Add mcu_secproxy
MCU domain has it's own secure proxy for communicating with ROM and
for R5 micro controller firmware operations. This is in addition to
the one in the main domain NAVSS subsystem that is used for general
purpose communication.
Describe the node for use with bootloaders and firmware that require
this communication path which uses interrupts to corresponding micro
controller interrupt controller. Mark the node as disabled since this
instance does not have interrupts routed to the main processor by
default for a complete description of the node.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://lore.kernel.org/r/20230530165900.47502-5-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Tue, 30 May 2023 16:58:56 +0000 (11:58 -0500)]
arm64: dts: ti: k3-am65-mcu: Add mcu_secproxy
MCU domain has it's own secure proxy for communicating with ROM and
for R5 micro controller firmware operations. This is in addition to
the one in the main domain NAVSS subsystem that is used for general
purpose communication.
Describe the node for use with bootloaders and firmware that require
this communication path which uses interrupts to corresponding micro
controller interrupt controller. Mark the node as disabled since this
instance does not have interrupts routed to the main processor by
default for a complete description of the node.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230530165900.47502-4-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Tue, 30 May 2023 16:58:55 +0000 (11:58 -0500)]
arm64: dts: ti: k3-am62a-main: Add sa3_secproxy
Security Management Subsystem(SMS) has it's own unique secure
proxy as part of Security Accelerator (SA3) module. This is used
for communicating with ROM and for special usecases such as HSM
operations. This is in addition to the one in the main domain DMSS
subsystem that is used for general purpose communication.
Describe the node for use with bootloaders and firmware that require
this communication path which uses interrupts to corresponding micro
controller interrupt controller. Mark the node as disabled since this
instance does not have interrupts routed to the main processor by
default for a complete description of the node.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230530165900.47502-3-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nitin Yadav [Tue, 30 May 2023 16:58:54 +0000 (11:58 -0500)]
arm64: dts: ti: k3-am62-main: Add sa3_secproxy
Security Management Subsystem(SMS) has it's own unique secure
proxy as part of Security Accelerator (SA3) module. This is used
for communicating with ROM and for special usecases such as HSM
operations. This is in addition to the one in the main domain DMSS
subsystem that is used for general purpose communication.
Describe the node for use with bootloaders and firmware that require
this communication path which uses interrupts to corresponding micro
controller interrupt controller. Mark the node as disabled since this
instance does not have interrupts routed to the main processor by
default for a complete description of the node.
Signed-off-by: Nitin Yadav <n-yadav@ti.com>
[nm@ti.com: Update commit message, minor updates]
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230530165900.47502-2-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Wed, 7 Jun 2023 13:20:43 +0000 (08:20 -0500)]
arm64: dts: ti: k3-am65-iot2050-common: Rename rtc8564 nodename
Just use "rtc" as the nodename to better match with the bindings.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230607132043.3932726-4-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Wed, 7 Jun 2023 13:20:42 +0000 (08:20 -0500)]
arm64: dts: ti: k3-am65-main: Drop deprecated ti,otap-del-sel property
ti,otap-del-sel has been deprecated in favor of ti,otap-del-sel-legacy.
Drop the duplicate and misleading ti,otap-del-sel property.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230607132043.3932726-3-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Wed, 7 Jun 2023 13:20:41 +0000 (08:20 -0500)]
arm64: dts: ti: k3-am65-main: Fix mcan node name
s/mcan/can to stay in sync with bindings conventions.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230607132043.3932726-2-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Vaishnav Achath [Sat, 13 May 2023 14:17:11 +0000 (19:47 +0530)]
arm64: dts: ti: k3-am642-sk/evm: Describe OSPI flash partition info
Describe OSPI flash partition information through device tree, this
helps to remove passing partition information through the mtdparts
commandline parameter which requires maintaining the partition
information in a string format. AM64 SK and EVM has a S28 64 MiB OSPI
flash with sector size of 256 KiB thus the size of the smallest partition
is chosen as 256 KiB, the partition names and offsets are chosen according
to the corresponding name and offsets in bootloader.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Link: https://lore.kernel.org/r/20230513141712.27346-6-vaishnav.a@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Vaishnav Achath [Sat, 13 May 2023 14:17:10 +0000 (19:47 +0530)]
arm64: dts: ti: k3-am654-baseboard: Describe OSPI flash partition info
Describe OSPI flash partition information through device tree, this
helps to remove passing partition information through the mtdparts
commandline parameter which requires maintaining the partition
information in a string format. AM654 baseboard has a MT35XU512ABA
64 MiB OSPI flash with sector size of 128 KiB thus the size of the
smallest partition is chosen as 128 KiB, the partition names and
offsets are chosen according to the corresponding name and offsets
in bootloader.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Link: https://lore.kernel.org/r/20230513141712.27346-5-vaishnav.a@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Vaishnav Achath [Sat, 13 May 2023 14:17:09 +0000 (19:47 +0530)]
arm64: dts: ti: k3-j7200-som: Describe OSPI and Hyperflash partition info
Describe OSPI and Hyperflash partition information through device tree,
this helps to remove passing partition information through the mtdparts
commandline parameter which requires maintaining the partition information
in a string format. J7200 SoM has a S28 64 MiB OSPI flash with sector size
of 256 KiB thus the size of the smallest partition is chosen as 256 KiB,
the SoM also has a 64 MiB Hyperflash present on it, the partition names
and offsets are chosen according to the corresponding name and offsets
in bootloader.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Link: https://lore.kernel.org/r/20230513141712.27346-4-vaishnav.a@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Vaishnav Achath [Sat, 13 May 2023 14:17:08 +0000 (19:47 +0530)]
arm64: dts: ti: k3-j721e-sk: Describe OSPI flash partition info
Describe OSPI flash partition information through device tree, this
helps to remove passing partition information through the mtdparts
commandline parameter which requires maintaining the partition
information in a string format. J721E SK has a S28 64 MiB OSPI flash
with sector size of 256 KiB thus the size of the smallest partition is
chosen as 256 KiB, the partition names and offsets are chosen according
to the corresponding name and offsets in bootloader.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Link: https://lore.kernel.org/r/20230513141712.27346-3-vaishnav.a@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Vaishnav Achath [Sat, 13 May 2023 14:17:07 +0000 (19:47 +0530)]
arm64: dts: ti: k3-j721e: Describe OSPI and QSPI flash partition info
Describe OSPI and QSPI flash partition information through device tree,
this helps to remove passing partition information through the mtdparts
commandline parameter which requires maintaining the partition information
in a string format. J721E SoM has a MT35 64 MiB OSPI flash and MT25 64 MiB
QSPI flash both with sector size of 128 KiB thus the size of the smallest
partition is chosen as 128KiB, the partition names and offsets are chosen
according to the corresponding name and offsets in bootloader.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Link: https://lore.kernel.org/r/20230513141712.27346-2-vaishnav.a@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Apurva Nandan [Thu, 4 May 2023 08:03:05 +0000 (13:33 +0530)]
arm64: dts: ti: k3-j784s4-evm: Add support for OSPI and QSPI flashes
J784S4 has S28HS512T OSPI flash connected to OSPI0 and MT25QU512A QSPI
flash connected to OSPI1, enable support for the same. Also describe
the partition information according to the offsets in the bootloader.
Co-developed-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Link: https://lore.kernel.org/r/20230504080305.38986-3-a-nandan@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Apurva Nandan [Thu, 4 May 2023 08:03:04 +0000 (13:33 +0530)]
arm64: dts: ti: k3-j784s4-mcu-wakeup: Add FSS OSPI0 and FSS OSPI1
TI K3 J784S4 has the Cadence OSPI controllers OSPI0 and OSPI1 on FSS
bus for interfacing with OSPI flashes. Add the nodes to allow using
SPI flashes.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Link: https://lore.kernel.org/r/20230504080305.38986-2-a-nandan@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Wadim Egorov [Fri, 5 May 2023 13:10:12 +0000 (15:10 +0200)]
arm64: dts: ti: Add LED controller to phyBOARD-Electra
With commit
9f6ffd0da650 ("dt-bindings: leds: Convert PCA9532 to dtschema"),
we can now add the LED controller without introducing new dtbs_check warnings.
Add missing I2C LED controller.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Link: https://lore.kernel.org/r/20230505131012.2027309-1-w.egorov@phytec.de
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Vaishnav Achath [Sat, 13 May 2023 12:33:13 +0000 (18:03 +0530)]
arm64: dts: ti: k3-j721e-common-proc-board: Add OSPI/Hyperflash select pinmux
J721E common processor board has an onboard mux for selecting whether
the OSPI signals are externally routed to OSPI flash or Hyperflash. The
mux state signal input is tied to WKUP_GPIO0_8 and is used by bootloader
for enabling the corresponding node accordingly. Add pinmux for the same.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Link: https://lore.kernel.org/r/20230513123313.11462-5-vaishnav.a@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Vaishnav Achath [Sat, 13 May 2023 12:33:12 +0000 (18:03 +0530)]
arm64: dts: ti: k3-j7200-common-proc-board: Add OSPI/Hyperflash select pinmux
J7200 common processor board has an onboard mux for selecting whether
the OSPI signals are externally routed to OSPI flash or Hyperflash. The
mux state signal input is tied to WKUP_GPIO0_6 and is used by bootloader
for enabling the corresponding node accordingly. Add pinmux for the same.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Link: https://lore.kernel.org/r/20230513123313.11462-4-vaishnav.a@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Vaishnav Achath [Sat, 13 May 2023 12:33:11 +0000 (18:03 +0530)]
arm64: dts: ti: k3-j721e-som-p0: Add HyperFlash node
J721E SoM has a HyperFlash and HyperRam connected to HyperBus memory
controller, add corresponding node, pinmux and partitions for the same.
HyperBus is muxed with OSPI and only one controller can be active at a
time, therefore keep HyperBus node disabled. Bootloader will detect the
external mux state through a wkup gpio and enable the node as required.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Link: https://lore.kernel.org/r/20230513123313.11462-3-vaishnav.a@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Vaishnav Achath [Sat, 13 May 2023 12:33:10 +0000 (18:03 +0530)]
arm64: dts: ti: k3-j721e-mcu-wakeup: Add HyperBus node
J721E has a Flash SubSystem that has one OSPI and one HyperBus with
muxed datapath and another independent OSPI. Add DT nodes for HyperBus
controller and keep it disabled and model the data path selection mux as a
reg-mux.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Link: https://lore.kernel.org/r/20230513123313.11462-2-vaishnav.a@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Andrew Davis [Mon, 15 May 2023 17:21:37 +0000 (12:21 -0500)]
arm64: dts: ti: k3-j721e: Enable MDIO nodes at the board level
MDIO nodes defined in the top-level J721e SoC dtsi files are incomplete
and will not be functional unless they are extended with a pinmux.
As the attached PHY is only known about at the board integration level,
these nodes should only be enabled when provided with this information.
Disable the MDIO nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230515172137.474626-5-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Andrew Davis [Mon, 15 May 2023 17:21:36 +0000 (12:21 -0500)]
arm64: dts: ti: k3-am64: Enable Mailbox nodes at the board level
Mailbox nodes defined in the top-level AM64x SoC dtsi files are incomplete
and may not be functional unless they are extended with a chosen interrupt
and connection to a remote processor.
As the remote processors depend on memory nodes which are only known at
the board integration level, these nodes should only be enabled when
provided with the above information.
Disable the Mailbox nodes in the dtsi files and only enable the ones that
are actually used on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230515172137.474626-4-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Andrew Davis [Mon, 15 May 2023 17:21:35 +0000 (12:21 -0500)]
arm64: dts: ti: k3-j721e: Enable PCIe nodes at the board level
PCIe nodes defined in the top-level J721e SoC dtsi files are incomplete
and will not be functional unless they are extended with a SerDes PHY.
And usually only one of the two modes can be used at a time as they
share a SerDes link.
As the PHY and mode is only known at the board integration level, these
nodes should only be enabled when provided with this information.
Disable the PCIe nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230515172137.474626-3-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Andrew Davis [Mon, 15 May 2023 17:21:34 +0000 (12:21 -0500)]
arm64: dts: ti: k3-j721e: Remove PCIe endpoint nodes
These nodes are example nodes for the PCIe controller in "endpoint" mode.
By default the controller is in "root complex" mode and there is already a
DT node for the same.
Examples should go in the bindings or other documentation.
Remove this node.
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230515172137.474626-2-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Andrew Davis [Mon, 15 May 2023 17:21:33 +0000 (12:21 -0500)]
arm64: dts: ti: k3-j721e-beagleboneai64: Fix mailbox node status
Mailbox nodes are now disabled by default. The BeagleBoard AI64 DT
addition went in at around the same time and must have missed that
change so the mailboxes are not re-enabled. Do that here.
Fixes:
fae14a1cb8dd ("arm64: dts: ti: Add k3-j721e-beagleboneai64")
Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230515172137.474626-1-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Bhavya Kapoor [Tue, 2 May 2023 09:08:14 +0000 (14:38 +0530)]
arm64: dts: ti: k3-j784s4-main: Enable support for high speed modes
eMMC tuning was incomplete earlier, so support for high speed modes was
kept disabled. Remove no-1-8-v property to enable support for high
speed modes for eMMC in J784S4 SoC.
Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
Link: https://lore.kernel.org/r/20230502090814.144791-1-b-kapoor@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Bhavya Kapoor [Tue, 2 May 2023 08:11:17 +0000 (13:41 +0530)]
arm64: dts: ti: k3-j784s4-evm: Add pinmux information for ADC
J784S4 has two instances of 8 channel ADCs in MCU domain. Add pinmux
information for both ADC nodes.
Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
Link: https://lore.kernel.org/r/20230502081117.21431-3-b-kapoor@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Bhavya Kapoor [Tue, 2 May 2023 08:11:16 +0000 (13:41 +0530)]
arm64: dts: ti: k3-j784s4-mcu-wakeup: Add support for ADC nodes
J784S4 has two instances of 8 channel ADCs in MCU domain. Add support
for both ADC nodes.
Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
Link: https://lore.kernel.org/r/20230502081117.21431-2-b-kapoor@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Jyri Sarha [Tue, 9 May 2023 10:23:53 +0000 (15:53 +0530)]
arm64: dts: ti: am65x: Add Rocktech OLDI panel DT overlay
The OLDI-LCD1EVM add on board has Rocktech RK101II01D-CT panel[1] with
integrated touch screen. The integrated touch screen is Goodix GT928.
This panel connects with AM65 GP-EVM[2].
Add DT nodes for these and connect the endpoint nodes with DSS.
[1]: Panel link
https://www.digimax.it/en/tft-lcd/20881-RK101II01D-CT
[2]: AM654 LCD EVM:
https://www.ti.com/tool/TMDSLCD1EVM
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
[abhatia1@ti.com: Make cosmetic and 6.4 kernel DTSO syntax changes]
Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Reviewed-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20230509102354.10116-2-a-bhatia1@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Bhavya Kapoor [Mon, 24 Apr 2023 09:38:27 +0000 (15:08 +0530)]
arm64: dts: ti: k3-j721e-main: Update delay select values for MMC subsystems
Update the delay values for various speed modes supported, based on
the revised august 2021 J721E Datasheet.
[1] - Table 7-77. MMC0 DLL Delay Mapping for All Timing Modes and
Table 7-86. MMC1/2 DLL Delay Mapping for All Timing Modes, in
https://www.ti.com/lit/ds/symlink/tda4vm.pdf,
(SPRSP36J – FEBRUARY 2019 – REVISED AUGUST 2021)
Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
Link: https://lore.kernel.org/r/20230424093827.1378602-1-b-kapoor@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Tue, 18 Apr 2023 21:37:40 +0000 (16:37 -0500)]
arm64: dts: ti: k3-am62x-sk-common: Improve documentation of mcasp1_pins
Include documentation of the AMC package pin name as well to keep it
consistent with the rest of the pinctrl documentation.
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230418213740.153519-5-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Nishanth Menon [Tue, 18 Apr 2023 21:37:39 +0000 (16:37 -0500)]
arm64: dts: ti: k3-am62x-sk-common: Add eeprom
Add board EEPROM support to device tree
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20230418213740.153519-4-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>