Brian Paul [Fri, 15 Jul 2016 13:08:13 +0000 (07:08 -0600)]
svga: handle mismatched number of samplers, sampler views
in svga_init_shader_key_common(). Since the CSO module only tracks
sampler views for fragment shaders, the number of samplers and sampler
views can be mismatched for other types of shaders. This situation
triggered an assertion in Chrome with maps.google.com
This patch adds defensive code to handle that situation.
Fixes VMware bug 1694027
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Leo Liu [Mon, 11 Jul 2016 19:27:16 +0000 (15:27 -0400)]
st/omx/enc: check uninitialized list from task release
The uninitialized list should be checked and returned.
Thank Julien for the notification and suggested fix.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Samuel Pitoiset [Tue, 12 Jul 2016 12:17:44 +0000 (14:17 +0200)]
nv50/ir: add missing string for SV_WORK_DIM
Fixes: 2aa1197 ("nouveau: Add support for SV_WORK_DIM")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Marek Olšák [Thu, 14 Jul 2016 20:07:46 +0000 (22:07 +0200)]
Revert "radeon/llvm: Use alloca instructions for larger arrays"
This reverts commit
513fccdfb68e6a71180e21827f071617c93fd09b.
Bioshock Infinite hangs with that.
Jan Vesely [Sun, 26 Jun 2016 02:06:09 +0000 (22:06 -0400)]
r600,compute: Reserve vtx 3 for kernel arguments
Using vtx 0 does not work for dynamic offsets.
v2: add explanatory comment
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Marek Olšák [Wed, 13 Jul 2016 16:51:36 +0000 (18:51 +0200)]
radeon/uvd: fail to create a decoder if RUVD_MSG_CREATE submission fails
This is the bare minimum for reporting the error to the user.
Reviewed-by: Christian König <christian.koenig@amd.com>
Marek Olšák [Wed, 13 Jul 2016 16:31:16 +0000 (18:31 +0200)]
winsys/amdgpu: return an error on IB submission failures
Reviewed-by: Christian König <christian.koenig@amd.com>
Marek Olšák [Wed, 13 Jul 2016 13:16:20 +0000 (15:16 +0200)]
gallium/radeon: add a return value to cs_flush
Required by our UVD code.
Reviewed-by: Christian König <christian.koenig@amd.com>
Jason Ekstrand [Wed, 13 Jul 2016 21:26:50 +0000 (14:26 -0700)]
glsl/types: Use _mesa_hash_data for hashing function types
This is way better than the stupid string approach especially since you
could overflow the string. Again, I thought I had something better at one
point but it obviously got lost.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Wed, 13 Jul 2016 21:25:11 +0000 (14:25 -0700)]
glsl/types: Fix function type comparison function
It was returning true if the function types have different lengths rather
than false. This was new with the SPIR-V to NIR pass and I thought I'd
fixed it a while ago but it may have gotten lost in rebasing somewhere.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
francians@gmail.com [Thu, 30 Jun 2016 17:16:08 +0000 (19:16 +0200)]
freedreno/a4xx: Fix sign compare warnings
Signed-off-by: Rob Clark <robdclark@gmail.com>
francians@gmail.com [Thu, 30 Jun 2016 17:16:07 +0000 (19:16 +0200)]
freedreno/a3xx: Fix sign compare warnings
Signed-off-by: Rob Clark <robdclark@gmail.com>
francians@gmail.com [Thu, 30 Jun 2016 17:16:06 +0000 (19:16 +0200)]
freedreno/a2xx: Fix sign compare warnings
Signed-off-by: Rob Clark <robdclark@gmail.com>
Boyuan Zhang [Wed, 13 Jul 2016 22:51:14 +0000 (18:51 -0400)]
radeon/vce: handle newly added parameters
Replace the previous hardcoded value with newly defined parameters
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Boyuan Zhang [Wed, 13 Jul 2016 22:51:13 +0000 (18:51 -0400)]
st/omx: assign previous values to new structure
Assign previously hardcoded values for OMX to newly defined
structure. As a result, OMX behaviour will not change at all.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Boyuan Zhang [Wed, 13 Jul 2016 22:51:11 +0000 (18:51 -0400)]
vl: add parameters for VAAPI encode
Allow to specify more parameters in the encoding interface
which previously just hardcoded in the encoder
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Christian König [Wed, 13 Jul 2016 12:54:31 +0000 (14:54 +0200)]
st/mesa: fix reference counting bug in st_vdpau
Otherwise we leak the resources created for the DMA-buf descriptors.
Signed-off-by: Christian König <christian.koenig@amd.com>
Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Tested-and-Reviewed by: Leo Liu <leo.liu@amd.com>
Ack-by: Tom St Denis <tom.stdenis@amd.com>
Eric Anholt [Fri, 6 May 2016 01:11:04 +0000 (18:11 -0700)]
vc4: Emit resets of the uniform stream at the starts of blocks.
If a block might be entered from multiple locations, then the uniform
stream will (probably) be at different points, and we need to make sure
that it's pointing where we expect it to be. The kernel also enforces
that any block reading a uniform resets uniforms, to prevent reading
outside of the uniform stream by using looping.
Eric Anholt [Wed, 27 Apr 2016 19:14:07 +0000 (12:14 -0700)]
vc4: Add support for scheduling of branch instructions.
For now we don't fill the delay slots, and instead just drop in NOPs.
Eric Anholt [Wed, 16 Mar 2016 00:53:36 +0000 (17:53 -0700)]
vc4: Move the QPU instructions to schedule into each block.
We'll want to schedule them individually, to handle delay slots.
Eric Anholt [Sat, 9 Jul 2016 00:06:18 +0000 (17:06 -0700)]
vc4: Disable vc4_opt_vpm in the presence of control flow.
It's a really valuable pass currently, but it will be a mess to rewrite
for control flow. For now, just disable it if we have multiple blocks
present.
Eric Anholt [Fri, 8 Jul 2016 23:23:38 +0000 (16:23 -0700)]
vc4: Convert vc4_opt_dead_code to work in the presence of control flow.
With control flow, we can't be sure that we'll see the uses of a variable
before its def as we walk backwards. Given that NIR is eliminating our
long chains of dead code, a simple solution for now seems fine.
This slightly changes the order of some optimizations, and so an opt_vpm
happens before opt_dce, causing 3 dead MOVs to be turned into dead FMAXes
in Minecraft:
instructions in affected programs: 52 -> 54 (3.85%)
Eric Anholt [Wed, 13 Jul 2016 20:37:56 +0000 (13:37 -0700)]
vc4: Update copy propagation for control flow.
Previously, we could assume that a MOV from a temp was always an available
copy, because all temps were SSA in NIR, and their non-SSA state in QIR
was just due to the fact that they were from a bcsel or pack_unorm_4x8, so
we could use the current value of the temp after that series of QIR
instructions to define it.
However, this is no longer the case with control flow. Instead, we track
a new array of MOVs defined within the block that haven't had their source
or dest killed yet, and use that primarily. We fall back to looking
through the QIR defs array to handle across-block MOVs, but now require
that copies from the SSA defs have an SSA src as well.
Samuel Iglesias Gonsálvez [Thu, 7 Jul 2016 07:19:43 +0000 (09:19 +0200)]
i965/fs: emit DIM instruction to load 64-bit immediates in HSW
v2 (Matt):
- Use brw_imm_df() as source argument of DIM instruction.
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Samuel Iglesias Gonsálvez [Thu, 7 Jul 2016 11:55:32 +0000 (13:55 +0200)]
i965/eu: set DF imm value to the source of DIM
According to HSW's PRM, vol02b, the DIM instruction has the following
restriction:
"Restriction : src0 must be immediate. src0 must specify the :f (F, Float)
type encoding but is an immediate 64-bit DF (Double Float) value. dst
must have type DF."
This commit allows to upload the immediate 64-bit DF value to the source
of a DIM instruction even when it is of float type encoding.
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Samuel Iglesias Gonsálvez [Thu, 7 Jul 2016 06:38:22 +0000 (08:38 +0200)]
i965: enable the emission of the DIM instruction
v2 (Matt):
- Take a DF source argument for the DIM instruction emission
in the visitors.
- Indentation.
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Thu, 14 Jul 2016 03:11:30 +0000 (20:11 -0700)]
anv: Add a stub for CmdCopyQueryPoolResults on Ivy Bridge
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Timothy Arceri [Thu, 14 Jul 2016 00:27:06 +0000 (10:27 +1000)]
i965: fix compiler warnings for 32bit build
Reviewed-by: Matt Turner <mattst88@gmail.com>
Tim Rowley [Wed, 13 Jul 2016 15:30:46 +0000 (10:30 -0500)]
Revert "gallium: Force blend color to 16-byte alignment"
This reverts commit
d8d6091a846ac2a40a011d512d6d57f6c8442e6a.
Heap allocations may be only 8-byte aligned on 32-bit system, and so having
members with 16-byte alignment (such as in the case where pipe_blend_color is
embedded in radeonsi's si_context) is undefined behavior which indeed causes
crashes when compiled with gcc -O3.
Cc: <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96835
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Acked-by: Chuck Atkins <chuck.atkins@kitware.com>
Jason Ekstrand [Fri, 3 Jun 2016 23:37:19 +0000 (16:37 -0700)]
isl/state: Add support for handling auxiliary surfaces
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Tue, 21 Jun 2016 23:16:59 +0000 (16:16 -0700)]
isl: Add an auxiliary surface usage enum
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Sat, 9 Jul 2016 05:12:10 +0000 (22:12 -0700)]
isl: Add support for color control surfaces
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Sat, 9 Jul 2016 02:37:27 +0000 (19:37 -0700)]
isl: Add support for multisample compression surfaces
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Sat, 9 Jul 2016 02:36:33 +0000 (19:36 -0700)]
isl: Add support for HiZ surfaces
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Sat, 9 Jul 2016 05:11:06 +0000 (22:11 -0700)]
isl: Kill off isl_format_layout::bs
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Sat, 9 Jul 2016 05:04:18 +0000 (22:04 -0700)]
isl: Take bpb rather than bs in tiling_get_info
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Sat, 9 Jul 2016 05:10:11 +0000 (22:10 -0700)]
isl: Use bpb in a few places where it's more natural than bs
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Tue, 12 Jul 2016 21:17:18 +0000 (14:17 -0700)]
isl: Use bpb for determining YUV image padding
When we initially dropped bpb in favor of bs, we accidentally didn't change
this one line properly. This brings it back to what it should be.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Sat, 9 Jul 2016 04:55:34 +0000 (21:55 -0700)]
isl: Bring back isl_format_layout::bpb
A while ago we got rid of the bits-per-block because we thought we didn't
need it. We're about to introduce some very useful 1 and 2-bit formats so
we really should be able to handle them again.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Sat, 9 Jul 2016 00:24:19 +0000 (17:24 -0700)]
isl: Change the physical size of a W-tile to 128x32
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Sat, 9 Jul 2016 00:10:59 +0000 (17:10 -0700)]
isl: Rework the way we define tile sizes.
This is based on a very long set of discussions between Chad and myself
about how we should properly represent HiZ and CCS buffers. The end result
of that discussion was that a tiling actually has two different sizes, a
logical size in elements, and a physical size in bytes and rows. This
commit reworks ISL's pitch and size calculations to work in terms of these
two sizes.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Fri, 8 Jul 2016 22:08:20 +0000 (15:08 -0700)]
isl: Rework the way we handle surface padding
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Tue, 12 Jul 2016 21:57:30 +0000 (14:57 -0700)]
isl: Use ARRAY_PITCH_SPAN_FULL for depth/stencil surfaces on gen7
We helpfully inserted a PRM quotation about how we need to use
ARRAY_PITCH_SPAN_FULL and then set it to COMPACT. Oops...
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Fri, 8 Jul 2016 21:57:19 +0000 (14:57 -0700)]
isl: Stop multiplying height by block size
The row pitch already specifies the size of a row of elements.
Multiplying by the block height simply causes us to allocate as muc as 12
times more memory than needed for compressed textures.
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Fri, 8 Jul 2016 20:59:05 +0000 (13:59 -0700)]
isl: Get rid of tiling_get_extent
It was unused
Reviewed-by: Chad Versace <chad.versace@intel.com>
Jason Ekstrand [Wed, 13 Jul 2016 18:35:29 +0000 (11:35 -0700)]
nir/spirv: Don't multiply the push constant block size by 4
I have no idea why we were multiplying by 4 before. The offsets we get
from SPIR-V are in bytes and so is nir->num_uniforms so there's no need to
do any adjustment whatsoever.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Wed, 13 Jul 2016 18:35:24 +0000 (11:35 -0700)]
anv/pipeline: Assert that the number of uniforms from NIR fits
Marek Olšák [Tue, 5 Jul 2016 00:54:43 +0000 (02:54 +0200)]
radeonsi: report accurate SGPR and VGPR spills
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 3 Jul 2016 18:00:17 +0000 (20:00 +0200)]
radeonsi: add a workaround for a compute VGPR-usage LLVM bug
v2: use abort(), describe which LLVM version is affected
Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 12 Jul 2016 17:58:28 +0000 (19:58 +0200)]
radeonsi: use LLVMGetTypeKind to tell if an input is an array of descriptors
just a cleanup
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 1 Jul 2016 14:25:01 +0000 (16:25 +0200)]
radeonsi: replace !tbaa with !invariant.load
no change in generated code thanks to dereferenceable(n)
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 12 Jul 2016 16:52:55 +0000 (18:52 +0200)]
radeonsi: set dereferenceable attribute on descriptor arrays
This allows moving the loads arbitrarily in the Sinking pass.
26002 shaders in 14643 tests
Totals:
SGPRS: 2080160 -> 2080160 (0.00 %)
VGPRS: 798875 -> 797826 (-0.13 %)
Spilled SGPRs: 108485 -> 79165 (-27.03 %)
Spilled VGPRs: 327 -> 327 (0.00 %)
Scratch VGPRs: 1656 -> 1652 (-0.24 %) dwords per thread
Code Size:
36127192 ->
35559780 (-1.57 %) bytes
LDS: 767 -> 767 (0.00 %) blocks
Max Waves: 212464 -> 212672 (0.10 %)
Wait states: 0 -> 0 (0.00 %)
PERCENTAGES / App Shaders SGPRs VGPRs SpillSGPR SpillVGPR Scratch CodeSize MaxWaves Waits
(unknown) 4 . . . . . . . .
0ad 6 . . . . . . . .
alien_isolation 2938 . 0.04 % -8.53 % . . -0.71 % -0.06 % .
anholt 10 . . . . . . . .
batman_arkham_origins 589 . -0.58 % -79.54 % . . -6.72 % 0.57 % .
bioshock-infinite 1769 . -0.65 % -89.32 % . . -4.73 % 0.48 % .
borderlands2 3968 . -0.31 % -51.21 % . . -4.09 % 0.22 % .
brutal-legend 338 . -0.03 % -2.95 % . . -0.06 % . .
civilization_beyond.. 116 . . -14.17 % . . -0.88 % . .
counter_strike_glob.. 1142 . . . . . . . .
dirt-showdown 541 . -0.56 % -40.14 % . -3.45 % -1.82 % 0.35 % .
dolphin 22 . . . . . 0.16 % . .
dota2 1747 . . . . . 0.01 % . .
europa_universalis_4 76 . -0.23 % -42.11 % . . -0.96 % . .
f1-2015 774 . -0.09 % -28.89 % . . -2.60 % 0.09 % .
furmark-0.7.0 4 . . . . . . . .
gimark-0.7.0 10 . . . . . . . .
glamor 16 . . . . . . . .
humus-celshading 4 . . . . . . . .
humus-domino 6 . . . . . . . .
humus-dynamicbranching 24 . 0.71 % . . . 0.29 % -0.45 % .
humus-hdr 10 . . . . . . . .
humus-portals 2 . . . . . . . .
humus-volumetricfog.. 6 . . . . . . . .
left_4_dead_2 1762 . . . . . . . .
metro_2033_redux 2670 . -0.10 % -7.15 % . . -0.03 % . .
nexuiz 80 . . . . . . . .
pixmark-julia-fp32 2 . . . . . . . .
pixmark-julia-fp64 2 . . . . . . . .
pixmark-piano-0.7.0 2 . . . . . . . .
pixmark-volplosion-.. 2 . . . . . . . .
plot3d-0.7.0 8 . . . . . . . .
portal 474 . . . . . . . .
sauerbraten 7 . . . . . . . .
serious_sam_3_bfe 392 . . -13.20 % . . -1.81 % . .
supertuxkart 4 . . . . . . . .
talos_principle 324 . -0.21 % -18.39 % . . -2.73 % 0.14 % .
team_fortress_2 808 . . . . . . . .
tesseract 430 . 0.08 % -68.57 % . . -0.45 % . .
tessmark-0.7.0 6 . . . . . . . .
thea 172 . . . . . 0.03 % . .
ue4_effects_cave 299 . -0.04 % -10.15 % . . -0.25 % 0.04 % .
ue4_elemental 586 . -0.02 % -13.93 % . . -0.13 % 0.02 % .
ue4_lightroom_inter.. 74 . -0.17 % -70.00 % . . -1.27 % . .
ue4_realistic_rende.. 92 . . -32.58 % . . -0.35 % . .
unigine_heaven 322 . 0.12 % -54.17 % . . -1.42 % -0.12 % .
unigine_sanctuary 264 . . . . . . . .
unigine_tropics 210 . . . . . . . .
unigine_valley 278 . -0.15 % -40.74 % . . -2.00 % 0.09 % .
unity 72 . . . . . 0.03 % . .
warsow 176 . . . . . . . .
warzone2100 4 . . . . . 0.13 % . .
witcher2 1040 . -0.03 % -86.28 % . . -0.28 % 0.01 % .
xcom_enemy_within 1236 . -0.24 % -63.54 % . . -0.93 % 0.18 % .
yofrankie 82 . -0.61 % -100.00 % . . -0.83 % 0.41 % .
-----------------------------------------------------------------------------------------------------------
Total 26002 . -0.13 % -27.03 % . -0.24 % -1.57 % 0.10 % .
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 12 Jul 2016 16:49:57 +0000 (18:49 +0200)]
gallivm: add helper lp_add_attr_dereferenceable
Not sure if this is the right way to do it, but it seems to work.
v2: make it a no-op on LLVM <= 3.5
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 1 Jul 2016 14:22:05 +0000 (16:22 +0200)]
radeonsi: clean up shader value metadata code
No change in behavior.
BTW, tbaa_md_kind == 1, which was the magic number in the code.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 1 Jul 2016 18:13:08 +0000 (20:13 +0200)]
radeonsi: remove LLVMNoUnwindAttribute uses
always set by gallivm
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 11 Jul 2016 17:14:33 +0000 (19:14 +0200)]
radeonsi: fix a typo in SI_PARAM_LINEAR_* handling
introduced in
476e9cee1d0cbe321c401277214e6c36ce5b18c9
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 1 Jul 2016 18:00:47 +0000 (20:00 +0200)]
gallium/radeon: normalize the code style
no change in behavior
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 8 Jul 2016 16:03:56 +0000 (18:03 +0200)]
radeonsi: just save buffer sizes instead of buffers while recording IBs
whole buffer objects are not needed
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Jon Turney [Tue, 5 Jul 2016 09:40:05 +0000 (10:40 +0100)]
Add c99_alloca.h include to fix compilation on Cygwin
Fix compilation on Cygwin, since
50b22354, by adding c99_alloca.h include,
which should know how to portably make the alloc() prototype available.
Signed-off-by: Jon Turney <jon.turney@dronecode.org.uk>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Topi Pohjolainen [Wed, 13 Jul 2016 08:03:54 +0000 (11:03 +0300)]
i965/blorp: Cleanup leftovers from push constant disabling
Setup for pixel shader push constants is the same as for other
stages. Note that on gen8+ the if-else branches were identical
and the generation check for packet size redundant.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Topi Pohjolainen [Tue, 12 Jul 2016 19:09:42 +0000 (22:09 +0300)]
i965/blorp/gen7+: Bring back push constant setup
This is partial revert of commit
cc2d0e64.
It looks that even though blorp disables a stage the corresponding
3DSTATE_CONSTANT_XS packet is needed to be programmed. Hardware
seems to try to fetch the constants even for disabled stages.
Therefore care needs to be taken that the constant buffer is
set up properly. Blorp will continue to trash it into non-existing
such as before.
It is possible that this could be omitted on SKL where the
constant buffer is considered when the corresponding binding table
settings are changed. Bspec:
"The 3DSTATE_CONSTANT_* command is not committed to the shader
unit until the corresponding (same shader)
3DSTATE_BINDING_TABLE_POINTER_* command is parsed."
However, as CONSTANT_XS packet itself does not seem to stall on its
own, it is safer to emit the packets for SKL also.
Possible alternative to blorp trashing could have been to setup
defaults in the beginning of each batch buffer. However, hardware
doesn't seem to tolerate these packets being programmed multiple
times per primitive. Bspec for IVB:
"It is invalid to execute this command more than once between
3D_PRIMITIVE commands."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96878
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Nicolai Hähnle [Sun, 10 Jul 2016 14:13:28 +0000 (16:13 +0200)]
radeonsi: silence Coverity warning
Coverity's analysis is too weak to understand that
r600_init_flushed_depth(_, _, NULL) only returns true when
flushed_depth_texture was assigned a non-NULL value.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Samuel Iglesias Gonsálvez [Fri, 8 Jul 2016 07:33:45 +0000 (09:33 +0200)]
i965/fs: do d2x lowering before simd splitting
So that we can have gen7 split large writes produced by this lowering pass.
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Iago Toral Quiroga [Fri, 1 Apr 2016 09:54:47 +0000 (11:54 +0200)]
i965/fs: do pack lowering before simd splitting
So that we can have gen7 split large writes produced by the pack lowering.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Samuel Iglesias Gonsálvez [Mon, 20 Jun 2016 10:13:14 +0000 (12:13 +0200)]
i965/fs: do not require force_writemask_all with exec_size 4
So far we only used instructions with this size in situations where we
did not operate per-channel and we wanted to ignore the execution mask,
but gen7 fp64 will need to emit code with a width of 4 that needs
normal execution masking.
v2:
- Modify the assert instead of deleting it (Curro)
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Iago Toral Quiroga [Wed, 30 Mar 2016 12:00:31 +0000 (14:00 +0200)]
i965/fs/gen7: split instructions that run into exec masking bugs
In fp64 we can produce code like this:
mov(16) vgrf2<2>:UD, vgrf3<2>:UD
That our simd lowering pass would typically split in instructions with a
width of 8, writing to two consecutive registers each. Unfortunately, gen7
hardware has a bug affecting execution masking and as a result, the
second GRF register write won't work properly. Curro verified this:
"The problem is that pre-Gen8 EUs are hardwired to use the QtrCtrl+1
(where QtrCtrl is the 8-bit quarter of the execution mask signals
specified in the instruction control fields) for the second
compressed half of any single-precision instruction (for
double-precision instructions it's hardwired to use NibCtrl+1,
at least on HSW), which means that the EU will apply the wrong
execution controls for the second sequential GRF write if the number
of channels per GRF is not exactly eight in single-precision mode (or
four in double-float mode)."
In practice, this means that we cannot write more than one
consecutive GRF in a single instruction if the number of channels
per GRF is not exactly eight in single-precision mode (or four
in double-float mode).
This patch makes our SIMD lowering pass split this kind of instructions
so that the split versions only write to a single register. In the
example above this means that we split the write in 4 instructions, each
one writing 4 UD elements (width = 4) to a single register.
v2 (Curro):
- Make explicit that the thing about hardwiring NibCtrl+1 for the second
compressed half is known to happen in Haswell and the issue with IVB
might not be exactly the same.
- Assign max_width instead of returning early so that we can handle
multiple restrictions affecting to the same instruction.
- Avoid division by 0 if the instruction does not write any registers.
- Ignore instructions what have WE_all set.
- Use the instruction execution type size instead of the dst type size.
v3 (Curro):
- Move the implementation down so it is not placed in the middle of another
workaround.
- Declare channels_per_grf as const.
- Don't break the loop early if we find a BAD_FILE source.
- Fix the number of channels that the hardware shifts for the second half
of a compressed instruction to be 8 in single precision and 4 in double
precision.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Iago Toral Quiroga [Mon, 11 Jul 2016 11:25:52 +0000 (13:25 +0200)]
i965/fs: use the new helper function to create double immediates
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Iago Toral Quiroga [Wed, 9 Mar 2016 13:12:43 +0000 (14:12 +0100)]
i965/fs: add a helper function to create double immediates
Gen7 hardware does not support double immediates so these need
to be moved in 32-bit chunks to a regular vgrf instead. Instead
of doing this every time we need to create a DF immediate,
create a helper function that does the right thing depending
on the hardware generation.
v2:
- Define setup_imm_df() as an independent function (Curro)
- Create a specific builder to get rid of some instruction field
assignments (Curro).
v3:
- Get devinfo from builder (Kenneth)
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Anholt [Tue, 3 May 2016 18:30:32 +0000 (11:30 -0700)]
vc4: Validate QPU uniform pointer updates.
Eric Anholt [Mon, 2 May 2016 20:35:21 +0000 (13:35 -0700)]
vc4: Add support for NIR loops and break/continue.
Eric Anholt [Fri, 11 Mar 2016 00:03:45 +0000 (16:03 -0800)]
vc4: Add support for emitting NIR IF nodes.
Eric Anholt [Wed, 27 Apr 2016 23:01:24 +0000 (16:01 -0700)]
vc4: Add support for storing to NIR registers in a non-SSA fashion.
Previously, there were occasionally NIR registers in our programs, but
they were always actually used SSA-only. Now that we're trying to support
control flow, we need to actually conditionally move to registers based on
whether channels are active or not.
Eric Anholt [Mon, 11 Jul 2016 17:55:18 +0000 (10:55 -0700)]
vc4: Add a flag in the screen to track control flow support.
For now it's still always false, but I need it in place for kernel
backwards compat support as I extend the backend for control flow.
Eric Anholt [Tue, 15 Mar 2016 20:55:28 +0000 (13:55 -0700)]
vc4: Define a QIR branch instruction
This uses the branch condition code in inst->cond to jump to either
successor[0] (condition matches) or successor[0] (condition doesn't
match).
Eric Anholt [Tue, 15 Mar 2016 20:53:02 +0000 (13:53 -0700)]
vc4: Add kernel support for branching in shader validation.
We're already checking that branch instructions are within the
contents of the shader and the proper PROG_END sequence is present.
The other thing we need in the presence of branching is to verify that
the shader doesn't overflow past the end of the uniforms stream.
To do that, we require that at the start of any basic block reading
uniforms have the following instructions:
load_imm temp, <offset within uniform stream>
add unif_addr, temp, unif
The instructions are generated by userspace, and the kernel verifies
that the load_imm is of the expected offset, and that the add adds it
to a uniform. We track which uniform in the stream that is, and at
draw call time fix up the uniform stream to have the address of the
start of the shader's uniforms for that draw call.
Signed-off-by: Eric Anholt <eric@anholt.net>
Eric Anholt [Sat, 2 Jul 2016 17:03:05 +0000 (10:03 -0700)]
vc4: Add a bitmap of branch targets in kernel validation.
This isn't used yet, it's just a first step toward loop validation.
During the main parsing of instructions, we need to know when we hit a new
basic block so that we can reset validated state.
Eric Anholt [Fri, 3 Jun 2016 19:48:59 +0000 (12:48 -0700)]
vc4: Track the current instruction into the validation_state.
This reduces how much we need to pass around as arguments, which was
becoming more of a problem with looping validation.
Eric Anholt [Tue, 15 Mar 2016 20:43:54 +0000 (13:43 -0700)]
vc4: Add QPU support for generating BRANCH instructions.
Eric Anholt [Wed, 6 Jul 2016 19:49:52 +0000 (12:49 -0700)]
vc4: Print live variable start/ends during QIR dumping.
This only happens when live variables are set up, which is not in the
normal dump, but is set up when we've failed to register allocate.
Eric Anholt [Thu, 10 Mar 2016 20:53:57 +0000 (12:53 -0800)]
vc4: Implement live intervals using a CFG.
Right now our CFG is always a trivial single basic block, but that will
change when enable loops.
Eric Anholt [Tue, 19 Jan 2016 22:15:54 +0000 (14:15 -0800)]
vc4: Make vc4_qir_schedule handle each block in the program.
Basically we just treat each block independently. The only inter-block
scheduling I can think of that would be be interesting would be to move
texture result collection to after a short loop/if block that doesn't do
texturing. However, the kernel disallows that as part of its security
validation.
Eric Anholt [Sat, 9 Jul 2016 00:10:38 +0000 (17:10 -0700)]
vc4: Convert uniforms lowering to work with multiple blocks.
We still decide which uniform to lower based on how many
instructions-that-need-lowering use that uniform, but now we emit a new
temporary uniform load in each of the basic blocks containing an
instruction being lowered.
This commit is best reviewed with diff -b.
Eric Anholt [Fri, 8 Jul 2016 23:59:15 +0000 (16:59 -0700)]
vc4: Convert vc4_opt_peephole_sf to work with control flow.
We need to apply the peephole pass to each of the blocks in the program.
We don't do dataflow analysis for SF across blocks, but we also don't
generate code that would need us to do so.
Eric Anholt [Fri, 8 Jul 2016 22:42:15 +0000 (15:42 -0700)]
vc4: Create a basic block structure and move the instructions into it.
The optimization passes and scheduling aren't actually ready for multiple
blocks with control flow yet (as seen by the "cur_block" references in
them instead of iterating over blocks), but this creates the structures
necessary for converting them.
Eric Anholt [Fri, 8 Jul 2016 22:24:34 +0000 (15:24 -0700)]
vc4: Add a "qir_for_each_inst_inorder" macro and use it in many places.
We have the prior list_foreach() all over the code, but I need to move
where instructions live as part of adding support for control flow. Start
by just converting to a helper iterator macro. (The simpler
"qir_for_each_inst()" will be used for the for-each-inst-in-a-block
iterator macro later)
Eric Anholt [Wed, 6 Jul 2016 22:21:53 +0000 (15:21 -0700)]
vc4: Also enable phi elimination.
This avoids a bunch of code gen regressions when enabling loops in vc4.
Prior to that, the GLSL that would have generated these optimizable phi
nodes was being lowered to csels between either (undef, a) or (a, a), and
those were being dealt with by nir_opt_undef and nir_opt_algebraic.
Eric Engestrom [Tue, 12 Jul 2016 22:29:34 +0000 (23:29 +0100)]
vc4: fix memory leak
The allocation has succeeded by that point, so it needs to be freed.
CovID: 1358929
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Eric Anholt <eric@anholt.net>
Eric Anholt [Mon, 11 Jul 2016 23:46:20 +0000 (16:46 -0700)]
vc4: Close our screen's fd on screen close.
We're passed in a freshly dup()ed fd on screen create, so we should close
it on exit. Debugged by Hugh Cole-Baker.
Eric Anholt [Wed, 6 Jul 2016 22:00:45 +0000 (15:00 -0700)]
nir: Add optimization for (a || True == True)
This was appearing in vc4 VS/CS in mupen64, due to vertex attrib lowering
producing some constants that were getting compared.
total instructions in shared programs: 112276 -> 112198 (-0.07%)
instructions in affected programs: 2239 -> 2161 (-3.48%)
total estimated cycles in shared programs: 283102 -> 283038 (-0.02%)
estimated cycles in affected programs: 2365 -> 2301 (-2.71%)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tim Rowley [Wed, 29 Jun 2016 15:47:31 +0000 (09:47 -0600)]
swr: [rasterizer core] correct MSAA behavior for conservative rasterization
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Tim Rowley [Mon, 27 Jun 2016 21:50:58 +0000 (15:50 -0600)]
swr: [rasterizer core] conservative rast backend changes
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Tim Rowley [Mon, 20 Jun 2016 05:37:57 +0000 (23:37 -0600)]
swr: [rasterizer] buckets cleanup
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Tim Rowley [Thu, 16 Jun 2016 19:53:28 +0000 (13:53 -0600)]
swr: [rasterizer core] make all api functions call GetContext
Small api cleanup. Make all api functions call GetContext instead
of locally casting handle. Makes debugging easier by providing a
single point to track context changes.
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Tim Rowley [Tue, 14 Jun 2016 23:54:34 +0000 (17:54 -0600)]
swr: [rasterizer] add support for llvm-3.9
v2: use signed compare, remove unneeded vmask
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Tim Rowley [Wed, 6 Jul 2016 21:26:16 +0000 (16:26 -0500)]
swr: [rasterizer jitter] fix llvm-3.7 compile
d3d97f8 broke llvm-3.7, which has a mismatched API for
setDataLayout/getDataLayout.
Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
Brian Paul [Tue, 12 Jul 2016 15:42:16 +0000 (09:42 -0600)]
docs: remove duplicated line in 12.0.1 release notes file
Signed-off-by: Brian Paul <brianp@vmware.com>
Leo Liu [Mon, 4 Jul 2016 20:32:48 +0000 (16:32 -0400)]
st/omx/dec: convert decoder video buffer to progressive
with encode tunneling
The idea of encode tunneling is to use video buffer directly for encoder,
but currently the encoder doesn’t support interlaced surface, the OMX
decoder set progressive surface before on that purpose.
Since now we are polling the driver for interlacing information for
decoder, we got the interlaced as preferred as other APIs(VDPAU, VA-API),
thus breaking the transcode with tunneling.
The solution is when with tunnel detected, re-allocate progressive target
buffers, and then converting the interlaced decoder results to there.
This has been tested with transcode results bit to bit matching as before
with surface from progressive to progressive.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Tested-by: Julien Isorce <j.isorce@samsung.com>
Leo Liu [Wed, 6 Jul 2016 16:42:37 +0000 (12:42 -0400)]
vl/compositor: set layer of y or uv to render
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Tested-by: Julien Isorce <j.isorce@samsung.com>
Leo Liu [Wed, 6 Jul 2016 16:34:02 +0000 (12:34 -0400)]
vl/compositor: add weave to yuv shader
This shader will make interlaced yuv to progressive yuv.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Tested-by: Julien Isorce <j.isorce@samsung.com>
Leo Liu [Mon, 4 Jul 2016 19:59:00 +0000 (15:59 -0400)]
vl/compositor: move weave shader out from rgb weaving
We'll use weave shader in the later patch.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Tested-by: Julien Isorce <j.isorce@samsung.com>