Raphael Isemann [Mon, 30 Mar 2020 11:48:26 +0000 (13:48 +0200)]
[lldb] Make TestExprDiagnostics.py pass again after enabling Fix-Its in test
Commit
83c81c0a469482888482983c302c09c02680ae7c enabled Fix-Its for top-level
expressions which change the error message of this test here as Clang comes
up with a strange Fix-It for this expression. This patch just changes the
test to declare a void variable so that Clang doesn't see a way to
recover with a Fix-It and change the error message.
Georgii Rymar [Fri, 27 Mar 2020 13:57:32 +0000 (16:57 +0300)]
[llvm-readobj][test] - Simplify hash-symbols test.
We are able to reduce `-DBITS=32/64` to reduce this test case.
I've rewrote the comments we had to generalize them and
fix wrong computations they contained.
Differential revision: https://reviews.llvm.org/D76924
Simon Pilgrim [Mon, 30 Mar 2020 11:22:06 +0000 (12:22 +0100)]
[X86][AVX] lowerV4X128Shuffle - attempt to widen to 2x256 to simplify shuffles
If we are lowering to X86ISD::SHUF128 we are going to lose track of individual 128-bit lanes that are UNDEF, so if we can widen these to guarantee that they are sequential with their neighbour we should. This helps with later shuffle combines.
Krasimir Georgiev [Mon, 30 Mar 2020 11:13:07 +0000 (13:13 +0200)]
[clang-format] only parse C# generic type constraints in C#
Commit "[clang-format] Handle C# generic type constraints",
https://github.com/llvm/llvm-project/commit/
dcbcec4822f47ec5b638dd9c20dcebd464569dae
regressed the formatting of code containing `where` as an identifier in other
languages.
Florian Hahn [Mon, 30 Mar 2020 10:13:41 +0000 (11:13 +0100)]
[Matrix] Rename emitChainedMatrixMultiply to emitMatrixMultiply (NFC).
The Chained in the name potentially leads to confusion. Also updated the
comment to drop the unnecessary mention of tile-sized.
Florian Hahn [Mon, 30 Mar 2020 09:59:54 +0000 (10:59 +0100)]
[AMDGPU] Drop const for value that is copied (NFC).
This fixes
warning: loop variable 'Def' of type 'const llvm::Register' creates a copy from type 'const llvm::Register' [-Wrange-loop-analysis]
llvm::Register just contains a single unsigned and should be copied.
Reviewers: rampitec
Reviewed By: rampitec
Differential Revision: https://reviews.llvm.org/D77011
Florian Hahn [Sun, 29 Mar 2020 18:17:16 +0000 (19:17 +0100)]
[CVP] Add additional icmp for ranges with undef to test.
Raphael Isemann [Mon, 30 Mar 2020 09:50:55 +0000 (11:50 +0200)]
[lldb] Make Fix-Its also apply to top-level expressions
Summary:
Currently top-level expressions won't automatically get Fix-Its applied. The reason
for that is that we only set the `m_fixed_text` member if we have a wrapping
source code (I.e. `m_source_code` is not zero and is wrapping some expressions).
This patch just always sets `m_fixed_text` to get this working.
Reviewers: labath, jingham
Reviewed By: labath
Subscribers: JDevlieghere
Differential Revision: https://reviews.llvm.org/D77042
Qiu Chaofan [Mon, 30 Mar 2020 09:46:12 +0000 (17:46 +0800)]
[NFC] [PowerPC] Update and add tests for ori
Use script to update test for ori with 32-bit imms, and add test for
ori with 64-bit imms.
Raphael Isemann [Mon, 30 Mar 2020 08:46:18 +0000 (10:46 +0200)]
[lldb][NFC] Cleanup Fix-It code
Sam Parker [Mon, 30 Mar 2020 08:54:25 +0000 (09:54 +0100)]
[ARM][LowOverheadLoops] Add horizontal reduction support
Add a bit more logic into the 'FalseLaneZeros' tracking to enable
horizontal reductions and also make the VADDV variants
validForTailPredication.
Differential Revision: https://reviews.llvm.org/D76708
Haojian Wu [Fri, 27 Mar 2020 20:40:30 +0000 (21:40 +0100)]
[AST] Fix a crash on invalid bitwidth exprs when preserving the recoveryexprs.
Summary:
If the bitwith expr contains errors, we mark the field decl invalid.
This patch also tweaks the behavior of ObjCInterfaceDecl to be consistent with
existing RecordDecl -- getObjCLayout method is only called with valid decls.
Reviewers: sammccall
Subscribers: cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D76953
Balázs Kéri [Mon, 30 Mar 2020 07:23:07 +0000 (09:23 +0200)]
[Analyzer][MallocChecker] No warning for kfree of ZERO_SIZE_PTR.
Summary:
The kernel kmalloc function may return a constant value ZERO_SIZE_PTR
if a zero-sized block is allocated. This special value is allowed to
be passed to kfree and should produce no warning.
This is a simple version but should be no problem. The macro is always
detected independent of if this is a kernel source code or any other
code.
Reviewers: Szelethus, martong
Reviewed By: Szelethus, martong
Subscribers: rnkovacs, xazax.hun, baloghadamsoftware, szepet, a.sidorin, mikhail.ramalho, Szelethus, donat.nagy, dkrupp, gamesh411, Charusso, martong, ASDenysPetrov, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D76830
Hanhan Wang [Mon, 30 Mar 2020 08:20:08 +0000 (01:20 -0700)]
[mlir] Fix typos in DeclarativeRewrites.md
Differential Revision: https://reviews.llvm.org/D77040
Raphael Isemann [Mon, 30 Mar 2020 07:41:06 +0000 (09:41 +0200)]
[lldb] Run TestFixIts on non-Darwin platforms
This test also passes on my Linux machine, so this seems too strict.
Raphael Isemann [Mon, 30 Mar 2020 07:19:59 +0000 (09:19 +0200)]
[lldb][NFC] Cleanup TestFixIts.py
Guillaume Chatelet [Fri, 27 Mar 2020 16:09:31 +0000 (16:09 +0000)]
[Alignment][NFC] Return Align for SelectionDAGNodes::getOriginalAlignment/getAlignment
Summary:
Also deprecate getOriginalAlignment, getAlignment will take much more time as it is pervasive through the codebase (including TableGened files).
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790
Reviewers: courbet
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D76933
Adam Balogh [Mon, 30 Mar 2020 07:22:10 +0000 (09:22 +0200)]
[Analyzer] Rename test `iterator-modelling.cpp` to `iterator-modeling.cpp`
Typo fix.
Adam Balogh [Thu, 5 Mar 2020 19:09:15 +0000 (20:09 +0100)]
[Analyzer] Fix for incorrect use of container and iterator checkers
Iterator checkers (and planned container checkers) need the option
aggressive-binary-operation-simplification to be enabled. Without this
option they may cause assertions. To prevent such misuse, this patch adds
a preventive check which issues a warning and denies the registartion of
the checker if this option is disabled.
Differential Revision: https://reviews.llvm.org/D75171
David Green [Sat, 28 Mar 2020 16:22:05 +0000 (16:22 +0000)]
[ARM] MVE VMOV.i64
In the original batch of MVE VMOVimm code generation VMOV.i64 was left
out due to the way it was done downstream. It turns out that it's fairly
simple though. This adds the codegen for it, similar to NEON.
Bigendian is technically incorrect in this version, which John is fixing
in a Neon patch.
Craig Topper [Mon, 30 Mar 2020 03:19:04 +0000 (20:19 -0700)]
[TTI][X86] Fix the value passed to IsUnsigned for cost modeling of experimental.vector.reduce.smin/smax/umin/umax.
We were passing true for smax/smin and false for umax/umin.
Max Kazantsev [Mon, 30 Mar 2020 05:13:02 +0000 (12:13 +0700)]
[NFC] Remove obsolete checks followed by fix of isGuaranteedToTransferExecutionToSuccessor
In past, isGuaranteedToTransferExecutionToSuccessor contained some weird logic
for volatile loads/stores that was ultimately removed by patch D65375. It's time to
remove a piece of dependent logic that used to be a workaround for the code which
is now deleted.
Reviewed By: uenoku
Differential Revision: https://reviews.llvm.org/D76918
River Riddle [Mon, 30 Mar 2020 05:00:26 +0000 (22:00 -0700)]
[mlir][NFC] Update dialect/op documentation to be consistent
Summary:
This revision performs a lot of different cleanups on operation documentation to ensure that they are consistent, e.g. using mlir code blocks, formatting, etc.
This revision also includes the auto-generated documentation into the hand-written documentation for the dialects that have a specific top-level dialect file. This updates the documentation for all dialects aside from SPIRV and STD. These dialects will be updated in a followup.
Differential Revision: https://reviews.llvm.org/D76734
River Riddle [Mon, 30 Mar 2020 04:49:44 +0000 (21:49 -0700)]
[mlir][NFC] Use the auto-generated op documentation in the standard dialect documentation
Summary: This revision updates the dialect documentation to use the auto-generated markdown for operations. This allows for updating some out-of-date bits of documentation, and allows for displaying a large of number of newly added operations that did not have a counter part in Standard.md.
Differential Revision: https://reviews.llvm.org/D76743
River Riddle [Mon, 30 Mar 2020 04:38:11 +0000 (21:38 -0700)]
[mlir][Diagnostics] Don't print note source line if it is the same as the previous diagnostic
Summary: This revision updates the SourceMgrDiagnosticHandler to not print the source location of a note if it is the same location as the previously printed diagnostic. This helps avoid redundancy, and potential confusion, when looking at the diagnostic output.
Differential Revision: https://reviews.llvm.org/D76787
Juneyoung Lee [Sat, 28 Mar 2020 06:11:09 +0000 (15:11 +0900)]
[LangRef] Clarify the semantics of branch on undef
Summary:
This patch clarifies the semantics of branching on undef value.
Defining `br undef` as undefined behavior explains optimizations that use branch conditions, such as CVP (D76931) and GVN (propagateEquality).
For `switch cond`, it is defined to raise UB if cond is an expression containing undef && cond is not frozen &&
it may yield different values.
This allows that at the destination block the branch condition can be assumed to be frozen already (otherwise UB was already triggered).
This condition is slightly stricter than MemorySanitizer, which allows undef-y condition if it always leads to the same destination,
but it does not break MemorySanitizer because we are giving stricter constraint.
Reviewers: efriedma, fhahn, nikic, spatel, jdoerfert, nlopes
Reviewed By: nlopes
Subscribers: regehr, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D76973
Richard Smith [Mon, 30 Mar 2020 02:31:21 +0000 (19:31 -0700)]
PR45350: Handle unsized array CXXConstructExprs in constant evaluation
of array new expressions with runtime bound.
Jun Ma [Fri, 27 Mar 2020 07:27:05 +0000 (15:27 +0800)]
[Coroutines 2/2] Improve symmetric control transfer feature
Differential Revision: https://reviews.llvm.org/D76913
Jun Ma [Fri, 27 Mar 2020 07:15:28 +0000 (15:15 +0800)]
[Coroutines 1/2] Improve symmetric control transfer feature
Differential Revision: https://reviews.llvm.org/D76911
Alexandre Ganea [Mon, 30 Mar 2020 01:51:45 +0000 (21:51 -0400)]
[LLD][ELF] Put back rounding which was lost in
8404aeb56a73ab24f9b295111de3b37a37f0b841
David Zarzycki [Sun, 29 Mar 2020 01:25:07 +0000 (21:25 -0400)]
Revert "[libc++] NFC: Simplify substitutions by using lit recursive substitutions"
This reverts commit
cd7f9751c30092033a5e97591876f972daf61989 which has
unintended breakage to non-libcxx projects when using the documented way
of building LLVM. (See the Getting Started guide. I.e. one big CMake setup.)
Craig Topper [Sun, 29 Mar 2020 22:54:34 +0000 (15:54 -0700)]
[X86] Add sse4.1 RUNs lines to the min/max reduction cost model tests.
Mostly this matches the sse4.2 we already had command lines for.
Except in the i64 case since sse4.1 doesn't have pcmpgtq.
Daan Sprenkels [Sun, 29 Mar 2020 21:25:39 +0000 (17:25 -0400)]
[InstCombine] Add tests for trunc (extelt x); (NFC)
Baseline tests for D76983 (PR45314)
Differential Revision: https://reviews.llvm.org/D77024
Craig Topper [Sun, 29 Mar 2020 07:27:33 +0000 (00:27 -0700)]
[X86] Add sse4.2 command lines to min/max reduction tests.
SSE4.2 has the pcmpgtq instruction which we will use in
vXi64 reductions when its available.
Benjamin Kramer [Sun, 29 Mar 2020 20:30:06 +0000 (22:30 +0200)]
[ARMMVE] Create fewer temporary SmallVectors
Shrinks clang by 40k.
Richard Smith [Sun, 29 Mar 2020 20:13:57 +0000 (13:13 -0700)]
Don't claim template names that name non-templates are undeclared.
Fangrui Song [Thu, 19 Mar 2020 05:28:21 +0000 (22:28 -0700)]
[ELF][test] Improve arm-exidx-output.s to test different output text sections
Delete arm-exidx-link.s which is now covered by arm-exidx-output.s
Differential Revision: https://reviews.llvm.org/D76409
David Green [Sat, 28 Mar 2020 16:11:37 +0000 (16:11 +0000)]
[ARM] VMOV.64 immediate tests. NFC
LLVM GN Syncbot [Sun, 29 Mar 2020 19:24:34 +0000 (19:24 +0000)]
[gn build] Port
854f268ca62
Benjamin Kramer [Sun, 29 Mar 2020 19:09:07 +0000 (21:09 +0200)]
[MC] Move deprecation infos from MCTargetDesc to MCInstrInfo
This allows emitting it only when the feature is used by a target.
Shrinks Release+Asserts clang by 900k.
Nathan Ridge [Sun, 29 Mar 2020 19:13:13 +0000 (15:13 -0400)]
[clangd] Handle clang-tidy suppression comments for diagnostics inside macro expansions
Summary:
Not handling this was a side-effect of being overly cautious when trying
to avoid reading files for which clangd doesn't have the source mapped.
Fixes https://github.com/clangd/clangd/issues/266
Reviewers: sammccall
Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, kadircet,
usaxena95, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D75286
Nathan Ridge [Sun, 29 Mar 2020 19:12:58 +0000 (15:12 -0400)]
clang-format fixes in ClangTidyDiagnosticConsumer.cpp and DiagnosticsTets.cpp
Subscribers: jkorous, arphaman, kadircet, usaxena95, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D77023
Simon Pilgrim [Sun, 29 Mar 2020 18:44:39 +0000 (19:44 +0100)]
[X86][AVX] Combine 128/256-bit lane shuffles with zeroable upper subvectors to EXTRACT_SUBVECTOR (PR40720)
As explained on PR40720, EXTRACTF128 is always as good/better than VPERM2F128/SHUF128, and we can use the implicit zeroing of the uppers.
Simon Pilgrim [Sun, 29 Mar 2020 18:40:42 +0000 (19:40 +0100)]
Fix -Wdocumentation warning. NFC.
gcc was misinterpreting the template code snippet as html.
Simon Pilgrim [Sun, 29 Mar 2020 17:48:02 +0000 (18:48 +0100)]
[X86] Add isAnyZero shuffle mask helper
Nikita Popov [Sun, 29 Mar 2020 17:20:11 +0000 (19:20 +0200)]
[InstCombine] Erase old mul when creating umulo
As we don't return the result of replaceInstUsesWith(), we are
responsible for erasing the instruction.
There is a small subtlety here in that we need to do this after
the other uses of Builder, which uses the original multiply as
the insertion point.
NFC apart from worklist order changes.
Nikita Popov [Sun, 29 Mar 2020 18:07:46 +0000 (20:07 +0200)]
[InstCombine] Use replaceOperand() in demanded elements simplification
To make sure that dead operands get DCEd. This fixes the largest
source of leftover dead operands we see in tests.
NFC apart from worklist changes.
Uday Bondhugula [Sat, 28 Mar 2020 18:36:10 +0000 (00:06 +0530)]
[MLIR] Add missing asserts in interchangeLoops util, doc comment update
Add missing assert checks for input to mlir::interchangeLoops utility.
Rename interchangeLoops -> permuteLoops; update doc comments to clarify
inputs / return val. Other than the assert checks, this is NFC.
Signed-off-by: Uday Bondhugula <uday@polymagelabs.com>
Differential Revision: https://reviews.llvm.org/D77003
Nikita Popov [Sun, 29 Mar 2020 17:59:00 +0000 (19:59 +0200)]
[InstCombine] Use replaceOperand() in assoc cast simplification
To make sure the old operands are DCEd.
NFC apart from worklist order.
Nikita Popov [Sun, 29 Mar 2020 17:50:23 +0000 (19:50 +0200)]
[InstCombine] Erase old add when optimizing add overflow
We don't return the replaceInstUsesWith() result, so we're
responsible for cleaning up.
NFC apart from worklist order changes.
Uday Bondhugula [Sat, 28 Mar 2020 05:59:52 +0000 (11:29 +0530)]
Introduce support for lib function aligned_alloc in TLI / memory builtins
Aligned_alloc is a standard lib function and has been in glibc since
2.16 and in the C11 standard. It has semantics similar to malloc/calloc
for several analyses/transforms. This patch introduces aligned_alloc
in target library info and memory builtins. Subsequent ones will
make other passes aware and fix https://bugs.llvm.org/show_bug.cgi?id=44062
This change will also be useful to LLVM generators that need to allocate
buffers of vector elements larger than 16 bytes (for eg. 256-bit ones),
element boundary alignment for which is not typically provided by glibc malloc.
Signed-off-by: Uday Bondhugula <uday@polymagelabs.com>
Differential Revision: https://reviews.llvm.org/D76970
Matt Arsenault [Sun, 29 Mar 2020 17:07:43 +0000 (13:07 -0400)]
GlobalISel: Add matcher for G_SHL
Matt Arsenault [Sat, 28 Mar 2020 23:04:47 +0000 (19:04 -0400)]
AMDGPU/GlobalISel: Remove redundant virtual
Matt Arsenault [Sun, 29 Mar 2020 14:40:12 +0000 (10:40 -0400)]
AMDGPU: Fix using wrong instruction for FP conversion
This was was never actually hit, but FTRUNC was clearly not the intent
here.
Matt Arsenault [Sun, 29 Mar 2020 14:10:28 +0000 (10:10 -0400)]
AMDGPU: Add some additional tests for v_cvt_ubyte* formation
Use functions now that we have them for less boilerplate in the
output.
Matt Arsenault [Sun, 29 Mar 2020 14:29:04 +0000 (10:29 -0400)]
AMDGPU: Fix typo
Sanjay Patel [Sun, 29 Mar 2020 17:58:04 +0000 (13:58 -0400)]
[VectorCombine] skip debug intrinsics first for efficiency
Sanjay Patel [Sun, 29 Mar 2020 17:31:44 +0000 (13:31 -0400)]
[InstCombine] make test independent of branch undef/UB; NFC
Simon Pilgrim [Sun, 29 Mar 2020 17:26:56 +0000 (18:26 +0100)]
[X86][AVX] Add tests for 512-bit shuffle patterns that could reduce to subvector extractions
Simon Pilgrim [Sun, 29 Mar 2020 17:17:09 +0000 (18:17 +0100)]
Remove unnecessary empty comments from test check lines. NFC.
Nikita Popov [Sun, 29 Mar 2020 16:55:59 +0000 (18:55 +0200)]
[InstCombine] Simplify select of cmpxchg transform
Rather than converting to a dummy select with equal true and false
ops, just directly return the resulting value.
As a side-effect, this fixes missing DCE of the previously replaced
operand.
Florian Hahn [Sun, 29 Mar 2020 16:05:29 +0000 (17:05 +0100)]
[OpenMP] set_bits iterator yields unsigned elements, no reference (NFC).
BitVector::set_bits() returns an iterator range yielding unsinged
elements, which always will be copied while const & gives the impression
that there will be no copy. Newer version of clang complain:
warning: loop variable 'SetBitsIt' is always a copy because the range of type 'iterator_range<llvm::BitVector::const_set_bits_iterator>' (aka 'iterator_range<const_set_bits_iterator_impl<llvm::BitVector> >') does not return a reference [-Wrange-loop-analysis]
Reviewers: jdoerfert, rnk
Reviewed By: rnk
Differential Revision: https://reviews.llvm.org/D77010
Nikita Popov [Sun, 29 Mar 2020 15:38:23 +0000 (17:38 +0200)]
[InstCombine] Fix worklist management in varargs transform
Add a replaceUse() helper to mirror replaceOperand() for the
rare cases where we're working directly on uses.
NFC apart from worklist order changes.
Nikita Popov [Sun, 29 Mar 2020 15:25:42 +0000 (17:25 +0200)]
[InstCombine] Erase original add when creating saddo
Usually when we replaceInstUsesWith() we also return the original
instruction, and InstCombine will take care of erasing it. Here
we don't do that, so we need to manually erase it.
NFC apart from worklist order changes.
Nikita Popov [Sun, 29 Mar 2020 15:08:04 +0000 (17:08 +0200)]
[InstCombine] Use replaceOperand() in a few more places
To make sure the old operands get DCEd.
NFC apart from worklist order changes.
Simon Pilgrim [Sun, 29 Mar 2020 15:41:37 +0000 (16:41 +0100)]
[X86][AVX] Combine 128-bit lane shuffles with a zeroable upper half to EXTRACT_SUBVECTOR (PR40720)
As explained on PR40720, EXTRACTF128 is always as good/better than VPERM2F128, and we can use the implicit zeroing of the upper half.
I've added some extra tests to vector-shuffle-combining-avx2.ll to make sure we don't lose coverage.
Simon Pilgrim [Sun, 29 Mar 2020 11:51:52 +0000 (12:51 +0100)]
[X86] Rename matchShuffleAsByteRotate to matchShuffleAsElementRotate. NFC.
This was an inner helper function for the real matchShuffleAsByteRotate function, but it is more generic and is used directly for VALIGN lowering which doesn't work at the byte level.
Simon Pilgrim [Sun, 29 Mar 2020 11:41:14 +0000 (12:41 +0100)]
[X86][AVX] Add X86ISD::VALIGN target shuffle decode support
Allows us to combine VALIGN instructions with other shuffles - the combiner doesn't create VALIGN yet though.
Kazuaki Ishizaki [Sat, 28 Mar 2020 18:20:02 +0000 (03:20 +0900)]
[mlir] NFC: fix trivial typo in documents
Reviewers: mravishankar, antiagainst, nicolasvasilache, herhut, aartbik, mehdi_amini, bondhugula
Reviewed By: mehdi_amini, bondhugula
Subscribers: bondhugula, jdoerfert, mehdi_amini, rriddle, jpienaar, burmako, shauheen, antiagainst, nicolasvasilache, csigg, arpith-jacob, mgester, lucyrfox, aartbik, liufengdb, Joonsoo, bader, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D76993
Florian Hahn [Sun, 29 Mar 2020 10:35:17 +0000 (11:35 +0100)]
[VPlan] Use one VPWidenRecipe per original IR instruction. (NFC).
This patch changes VPWidenRecipe to only store a single original IR
instruction. This is the first required step towards modeling it's
operands as VPValues and also towards breaking it up into a
VPInstruction.
Discussed as part of D74695.
Reviewers: Ayal, gilr, rengolin
Reviewed By: gilr
Differential Revision: https://reviews.llvm.org/D76988
Nikita Popov [Sun, 29 Mar 2020 09:36:30 +0000 (11:36 +0200)]
[PostOrderIterator] Use SmallVector to store stack; NFC
We use a SmallPtrSet to track visited nodes, use a SmallVector
of the same size for the stack.
Simon Pilgrim [Sun, 29 Mar 2020 10:01:42 +0000 (11:01 +0100)]
[X86] X86CallFrameOptimization - generalize slow push code path
Replace the explicit isAtom() || isSLM() test with the more general (and more specific) slowTwoMemOps() check to avoid the use of the PUSHrmm push from memory case.
This is actually very tricky to test in anything but quite complex code, but the atomic-idempotent.ll tests seem to be the most straightforward to use.
Differential Revision: https://reviews.llvm.org/D76239
Aaron Smith [Sun, 29 Mar 2020 08:23:08 +0000 (01:23 -0700)]
[mlir] Add exp2 conversion to llvm.intr.exp2
Richard Diamond [Mon, 2 Mar 2020 18:08:57 +0000 (12:08 -0600)]
[AlignmentFromAssumptions] Fix a SCEV assertion resulting from address space differences.
Summary:
On targets with different pointer sizes, -alignment-from-assumptions could attempt to create SCEV expressions which use different effective SCEV types. The provided test illustrates the issue.
In `getNewAlignment`, AASCEV would be the (only) alloca, which would have an effective SCEV type of i32. But PtrSCEV, the GEP in this case, due to being in the flat/default address space, will have an effective SCEV of i64.
This patch resolves the issue by truncating PtrSCEV to AASCEV's effective type.
Reviewers: hfinkel, jdoerfert
Reviewed By: jdoerfert
Subscribers: jvesely, nhaehnle, hiraditya, javed.absar, kerbowa, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D75471
Craig Topper [Sat, 28 Mar 2020 22:30:13 +0000 (15:30 -0700)]
[X86] Add cost model test cases for fmin/fmax reduction.
Fangrui Song [Sat, 28 Mar 2020 23:48:59 +0000 (16:48 -0700)]
[MC][PowerPC] Make .reloc support arbitrary relocation types
Generalizes
ad7199f3e60a49db023099dcb879fcc9cdf94a2e (R_PPC_NONE/R_PPC64_NONE).
Joerg Sonnenberger [Tue, 17 Mar 2020 23:39:54 +0000 (00:39 +0100)]
Fix compatibility for __builtin_stdarg_start
The __builtin_stdarg_start is the legacy spelling of __builtin_va_start.
It should behave exactly the same, but for the last 9 years it would
behave subtly different for diagnostics. Follow the change from
29ad95b23217 to require custom type checking.
Matt Arsenault [Sat, 7 Sep 2019 23:07:47 +0000 (19:07 -0400)]
AMDGPU: Make use of default operands
Benjamin Kramer [Sat, 28 Mar 2020 21:06:12 +0000 (22:06 +0100)]
Put back initializers that were dropped in
0ab5b5b8581d9f2951575f7245824e6e4fc57dec
Found by msan.
Benjamin Kramer [Sat, 28 Mar 2020 20:38:50 +0000 (21:38 +0100)]
[COFF] Stabilize sort
Found by llvm::sort's expensive checks.
Benjamin Kramer [Sat, 28 Mar 2020 20:16:51 +0000 (21:16 +0100)]
[MDBuilder] Don't use stable sort for sorting integers.
Nikita Popov [Sat, 28 Mar 2020 20:16:48 +0000 (21:16 +0100)]
[InstCombine] Remove unreachable blocks before DCE
Dropping unreachable code may reduce use counts on other instructions,
so it's better to do this earlier rather than later.
NFC-ish, may only impact worklist order.
Nikita Popov [Sat, 28 Mar 2020 20:13:33 +0000 (21:13 +0100)]
[InstCombine] Merge two functions; NFC
Merge AddReachableCodeToWorklist() into prepareICWorklistFromFunction().
It's one logical step, and this makes it easier to move code.
Benjamin Kramer [Sat, 28 Mar 2020 17:47:26 +0000 (18:47 +0100)]
[ADT] Automatically forward llvm::sort to array_pod_sort if safe
This is safe if the iterator type is a pointer and the comparator is
stateless. The enable_if pattern I'm adding here only uses
array_pod_sort for the default comparator (std::less).
Using array_pod_sort has a potential performance impact, but I didn't
notice anything when testing clang. Sorting doesn't seem to be on the
hot path anywhere in LLVM.
Shrinks Release+Asserts clang by 73k.
Benjamin Kramer [Sat, 28 Mar 2020 19:16:41 +0000 (20:16 +0100)]
[AMDGPU] Stabilize sort order
Found by the expensive checks in llvm::sort.
Yonghong Song [Sun, 22 Mar 2020 05:54:20 +0000 (22:54 -0700)]
[BPF] support 128bit int explicitly in layout spec
Currently, bpf does not specify 128bit alignment in its
layout spec. So for a structure like
struct ipv6_key_t {
unsigned pid;
unsigned __int128 saddr;
unsigned short lport;
};
clang will generate IR type
%struct.ipv6_key_t = type { i32, [12 x i8], i128, i16, [14 x i8] }
Additional padding is to ensure later IR->MIR can generate correct
stack layout with target layout spec.
But it is common practice for a tracing program to be
first compiled with target flag (e.g., x86_64 or aarch64) through
clang to generate IR and then go through llc to generate bpf
byte code. Tracing program often refers to kernel internal
data structures which needs to be compiled with non-bpf target.
But such a compilation model may cause a problem on aarch64.
The bcc issue https://github.com/iovisor/bcc/issues/2827
reported such a problem.
For the above structure, since aarch64 has "i128:128" in its
layout string, the generated IR will have
%struct.ipv6_key_t = type { i32, i128, i16 }
Since bpf does not have "i128:128" in its spec string,
the selectionDAG assumes alignment 8 for i128 and
computes the stack storage size for the above is 32 bytes,
which leads incorrect code later.
The x86_64 does not have this issue as it does not have
"i128:128" in its layout spec as it does permits i128 to
be alignmented at 8 bytes at stack. Its IR type looks like
%struct.ipv6_key_t = type { i32, [12 x i8], i128, i16, [14 x i8] }
The fix here is add i128 support in layout spec, the same as
aarch64. The only downside is we may have less optimal stack
allocation in certain cases since we require 16byte alignment
for i128 instead of 8. But this is probably fine as i128 is
not used widely and in most cases users should already
have proper alignment.
Differential Revision: https://reviews.llvm.org/D76587
Benjamin Kramer [Sat, 28 Mar 2020 18:19:55 +0000 (19:19 +0100)]
Upgrade some instances of std::sort to llvm::sort. NFC.
Benjamin Kramer [Sat, 28 Mar 2020 18:21:56 +0000 (19:21 +0100)]
Remove constexpr that MSVC doesn't like
Reid Kleckner [Sat, 28 Mar 2020 18:03:14 +0000 (11:03 -0700)]
[CodeGen] Fix sinking local values in lpads with phis
There was already a test case for landingpads to handle this case, but I
had forgotten to consider PHI instructions preceding the EH_LABEL in the
landingpad.
PR45261
Nikita Popov [Sat, 28 Mar 2020 18:02:48 +0000 (19:02 +0100)]
[InstCombine] Use replaceOperand() API in GEP transforms
To make sure that replaced operands get DCEd. This drops one
iteration from gepphigep.ll, which is still not optimal.
This was the last test case performing more than 3 iterations.
NFC-ish, only worklist order should change.
Nikita Popov [Sat, 28 Mar 2020 17:44:35 +0000 (18:44 +0100)]
[InstCombine] Reduce code duplication in GEP of PHI transform; NFC
The `NewGEP->setOperand(DI, NewPN)` call was duplicated, and the
insertion of NewGEP is the same in both if/else, so we can extract it.
Benjamin Kramer [Sat, 28 Mar 2020 17:12:28 +0000 (18:12 +0100)]
Const-initialize ParsedAttrInfos
Gets rid of a 150k static initializer (Release clang)
Alexandre Ganea [Sat, 28 Mar 2020 17:54:44 +0000 (13:54 -0400)]
After
09158252f777c2e2f06a86b154c44abcbcf9bb74, fix build when -DLLVM_ENABLE_THREADS=OFF
Tested on Linux with Clang 9, and on Windows with Visual Studio 2019 16.5.1 with -DLLVM_ENABLE_THREADS=ON and OFF.
Nikita Popov [Fri, 21 Feb 2020 21:48:06 +0000 (22:48 +0100)]
[InstCombine] Fix worklist management in foldXorOfICmps()
Because this code does not use the IC-aware replaceInstUsesWith()
helper, we need to manually push users to the worklist.
This is NFC-ish, in that it may only change worklist order.
Nikita Popov [Sat, 28 Mar 2020 17:15:31 +0000 (18:15 +0100)]
[InstCombine] Change limit-max-iterations test case; NFC
This particular case will stop needing multiple iterations in
a followup change.
Matt Schulte [Sat, 28 Mar 2020 16:54:06 +0000 (09:54 -0700)]
[lld][ELF] Mark empty NOLOAD output sections SHT_NOBITS instead of SHT_PROGBITS
This fixes PR# 45336.
Output sections described in a linker script as NOLOAD with no input sections would be marked as SHT_PROGBITS.
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D76981
Enna1 [Sat, 28 Mar 2020 16:59:22 +0000 (17:59 +0100)]
[CorrelatedValuePropagation] Remove redundant if statement in processSelect()
This statement
if (ReplaceWith == S) ReplaceWith = UndefValue::get(S->getType());
is introduced in https://reviews.llvm.org/rG35609d97ae89b8e13f40f4e6b9b056954f8baa83
to fix a case where unreachable code can cause select instruction
simplification to fail. In https://reviews.llvm.org/rGd10480657527ffb44ea213460fb3676a6b1300aa,
we begin to perform a depth-first walk of basic blocks. This means
we will not visit unreachable blocks. So we do not need this the
special check any more.
Differential Revision: https://reviews.llvm.org/D76753
Martin Storsjö [Sat, 28 Mar 2020 15:37:59 +0000 (17:37 +0200)]
[AsmPrinter] Emit .weak directive for weak linkage on COFF for symbols without a comdat
MC already knows how to emulate the .weak directive (with its ELF
semantics; i.e., an undefined weak symbol resolves to 0, and a defined
weak symbol has lower link precedence than a strong symbol of the same
name) using COFF weak externals. Plumb this through the ASM printer too,
so that definitions marked with __attribute__((weak)) at the language
level (which gets translated to weak linkage at the IR level) have the
corresponding .weak directive emitted. Note that declarations marked
with __attribute__((weak)) at the language level (which translates to
extern_weak at the IR level) already have .weak directives emitted.
Weak*/linkonce* symbols without an associated comdat (in particular, ones
generated with __attribute__((weak)) in C/C++) were earlier emitted as
normal unique globals, as the comdat is required to provide the linkonce
semantics. This change makes sure they are emitted as .weak instead,
allowing other symbols to override them.
Rename the existing coff-weak.ll test to coff-linkonce.ll. I'm not
quite sure what that test covers, since the behavior being tested in it
(the emission of a one_only section) is just a result of passing
-function-sections to llc; the linkonce_odr makes no difference.
Add a new coff-weak.ll which tests the new directive emission.
Based on an previous patch by Shoaib Meenai.
Differential Revision: https://reviews.llvm.org/D44543
Alex Brachet [Sat, 28 Mar 2020 16:28:43 +0000 (12:28 -0400)]
[libc] Only use __has_builtin on clang
The preprocessor reads the whole line even if the first condition of an and is false so this broke when compiling on older gcc versions which don't recognize `__has_builtin`
Florian Hahn [Sat, 28 Mar 2020 15:20:10 +0000 (15:20 +0000)]
[SCCP] Remove LatticeVal alias now that transition is done (NFC).
The LatticeVal alias was introduced to reduce the diff size for the
transition to ValueLatticeElement, which is done now.
This patch removes the unnecessary alias and updates some very verbose
type uses with auto.