Hao Wu [Thu, 25 Aug 2011 11:20:35 +0000 (12:20 +0100)]
usb: penwell_otg: add runtime pm support
Add runtime pm support in penwell_otg transceiver driver.
Change-Id: I30f9bbb33efb3a0a6d8e313c6dd6dfefe656c3a8
Signed-off-by: Hao Wu <hao.wu@intel.com>
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Hao Wu [Thu, 25 Aug 2011 11:20:35 +0000 (12:20 +0100)]
usb: penwell_otg: add charging current negotiation and notification support
This patch adds charging current negotiation in Transceiver driver for
SDP/CDP/DCP cases and it also provides notification/query interfaces to
Battery driver for charging current information notification.
*It requires device controller/gadget driver modification to fully
support SDP/CDP cases.
Change-Id: I2d7db99bf16423d308a738bdc25206d9a90e2db4
Signed-off-by: Hao Wu <hao.wu@intel.com>
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Hao Wu [Thu, 25 Aug 2011 11:20:35 +0000 (12:20 +0100)]
usb: penwell_otg: add USB charger detection
This patch enables penwell USB OTG Transceiver driver USB Charger Detection
support. It can detect different types of USB charger based on MSIC.
SDP (Standard Downstream Port - USB Host port charger), DCP (Dedicated
Charging Port - USB Wall charger), CDP (Charging Downstream Port - Special
USB Host port charger).
Change-Id: I34009bb775bba53357f91a23c9190317d69d3654
Signed-off-by: Hao Wu <hao.wu@intel.com>
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Hao Wu [Thu, 25 Aug 2011 11:20:34 +0000 (12:20 +0100)]
usb: penwell_otg: Add Intel Penwell USB OTG Transceiver driver
Description
This driver tries to implement host/device role switch according to
OTG 2.0 spec on MFLD. The actual host and device functions are
accomplished in modified EHCI driver and Intel Penwell USB OTG device
controller driver. This is the first version and it only support Host
Peripheral role switch per different USB cable. Development work is
still on going, more features will be submitted soon after verified.
Dependency
CONFIG_INTEL_SCU_IPC - IPC driver.
Enable driver in Kernel
"Device Drivers" ---> "USB support" --->
"Intel Penwell USB OTG dual-role support"
Kernel configs
CONFIG_INTEL_SCU_IPC=y
CONFIG_USB=y
CONFIG_USB_OTG=y
CONFIG_USB_OTG_UTILS=y
CONFIG_PENWELL_OTG=y
Todo List
USB Charging Support
Power management (runtime)
MHL-USB coexistence
HNP/HNP Polling/SRP
ADP(Attach Detection Protocol) Support
Change-Id: Ie9daf11fc21f03be659ed6c8992a4ac904421e0f
Signed-off-by: Hao Wu <hao.wu@intel.com>
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Hao Wu [Fri, 26 Aug 2011 10:55:05 +0000 (11:55 +0100)]
usb: langwell_udc: Add hnp polling support
This patch adds get_status support for HNP polling in langwell_udc.
Change-Id: Ia700cb6a64d3c428de2fdd047960be6c98c1736b
Signed-off-by: Hao Wu <hao.wu@intel.com>
[Reapplied by hand due to other changes]
Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Sundar Iyer [Thu, 25 Aug 2011 11:20:34 +0000 (12:20 +0100)]
usb: langwell_udc: Init SRAM on S0i3 resume
On an exit from S0i3, the USB stack tries to access the SRAM
without initializing. Add SRAM initialization code to avoid
ECC error. This patch is for langwell_udc controller driver.
Change-Id: I92c80eed95094706020b8659a3db6585bdd8fca3
Signed-off-by: Sundar Iyer <sundar.iyer@intel.com>
Signed-off-by: Hao Wu <hao.wu@intel.com>
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
JiebingLi [Thu, 25 Aug 2011 11:20:34 +0000 (12:20 +0100)]
usb: langwell_udc: Fix max packet size calculations
This patch is used to fix max packet size issue in langwell_udc
controller driver. As max packct size is 1024 for ISO transfer, 0x7ff
(bit 0~10) should be used to compute the value. If 0x8ff is used, the
value may be wrongly set as 0 instead of 1024 or 512.
Change-Id: Ic78105f17d949d98c6f3c1667b0bac2c0fb8ae6c
Signed-off-by: JiebingLi <jiebing.li@intel.com>
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Philippe Skowronski [Thu, 25 Aug 2011 11:20:33 +0000 (12:20 +0100)]
usb: langwell_udc: cancel pending requests when controller is suspended.
It is safer to cancel pending requests before free dTD and dQH when
controller enters suspend state.
Change-Id: I5cb342093934af111ce70911908f492914c3001e
Signed-off-by: Philippe Skowronski <philippe.skowronski@intel.com>
Signed-off-by: Hao Wu <hao.wu@intel.com>
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Jacob Pan [Thu, 25 Aug 2011 11:20:33 +0000 (12:20 +0100)]
usb/gadget/langwell: do not hold spin_lock when sleep
Use GFP_ATOMIC to avoid going to sleep while holding spin_lock.
Fix based on following call trace.
[ 443.445677] [<
c102a8e8>] __might_sleep+0xf7/0xff
[ 443.445677] [<
c10bca9b>] dma_pool_alloc+0x27/0x2ec
[ 443.445677] [<
c12e4346>] ? langwell_ep_queue+0x1eb/0x25a
[ 443.445677] [<
c12e4346>] ? langwell_ep_queue+0x1eb/0x25a
[ 443.445677] [<
c12e3bd9>] req_to_dtd+0x37/0x10e
[ 443.445677] [<
c14d08bd>] ? _raw_spin_lock_irqsave+0x35/0x3e
[ 443.445677] [<
c12e4350>] langwell_ep_queue+0x1f5/0x25a
Change-Id: I6f15cf806444caaf8ddef8b899c083445eb24345
Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Hao Wu [Thu, 25 Aug 2011 11:20:33 +0000 (12:20 +0100)]
usb: langwell_udc: add HighSpeed/FullSpeed events notification
It adds notification to Intel Penwell otg transceiver driver for
HighSpeed/FullSpeed. This change mainly to support battery charging
current negotiation for Charging Downstream Port(CDP) case. USB OTG
Transceiver driver will notify battery driver about charging current
limitation change according to different Speed Mode (HS/FS).
Change-Id: Icc7f8004b8173cd74ae78d5fce90d3c57e94a847
Signed-off-by: Hao Wu <hao.wu@intel.com>
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Alan Cox [Thu, 25 Aug 2011 11:20:32 +0000 (12:20 +0100)]
usb: fixup missing size field for non transceiver build
Change-Id: I62a1f2ba9c8d1934f44d24c4a65c8d4e496aa91b
Signed-off-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Hao Wu [Thu, 25 Aug 2011 11:20:32 +0000 (12:20 +0100)]
usb: langwell_udc: set vbus_active flag according to state
This patch adds active bit setting in order to avoid issues
with composite gadget on pullup functions which query on this
bit.
Change-Id: I063bcd6021b2b322854d6e94e850c5fae6266b28
Signed-off-by: Hao Wu <hao.wu@intel.com>
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Jiebing Li [Thu, 25 Aug 2011 11:20:32 +0000 (12:20 +0100)]
usb: langwell_udc: enable PHY Low Power Mode for Penwell
This patch enables PHY Low Power mode to save power for Penwell case.
Change-Id: I2be3d772742de926c0791ec50d0c7d9c2f43a4d5
Signed-off-by: Jiebing Li <jiebing.li@intel.com>
Signed-off-by: Hao Wu <hao.wu@intel.com>
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Jiebing Li [Thu, 25 Aug 2011 11:20:07 +0000 (12:20 +0100)]
usb: langwell_udc: add Intel Penwell USB Device Controller support
Add Intel Penwell USB Device Controller Support in langwell_udc driver.
This driver will support both langwell/penwell USB Device controller with
this patch.
Change-Id: I50534ac35bc666849db6712eeeb943bd6bf27311
Signed-off-by: JiebingLi <jiebing.li@intel.com>
Signed-off-by: Hao Wu <hao.wu@intel.com>
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Sebastian Andrzej Siewior [Tue, 5 Jul 2011 13:39:48 +0000 (16:39 +0300)]
usb: gadget: fix up depencies
Both fusb300 and langwell udcs seem to only
work with 32-bit address space.
Change-Id: I3d7517574564356bddfde9a25877f594c37cc02c
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Fengwei Yin [Thu, 15 Sep 2011 07:44:14 +0000 (15:44 +0800)]
usb: gadget: allow multiple gadgets to be built
ported from AC tree:
193ab2a6070039e7ee2b9b9bebea754a7c52fd1b
Change-Id: Id5b4330c47ed0796a4421d596de82b63a663de52
Hao Wu [Thu, 25 Aug 2011 11:18:45 +0000 (12:18 +0100)]
usb: langwell_udc: use common OTG data structure for Intel MID platform
This patch provided the support to common OTG data structure.
Main changes:
- Notify otg related events using notifier and remove direct
access to otg data structure(state machine).
- Provide start_peripheral/stop_peripheral function to transceiver.
- Provide client register/unregister function.
modified: drivers/usb/gadget/langwell_udc.c
modified: drivers/usb/gadget/langwell_udc.h
Change-Id: Icfa1f5171a2459fe7d9098c842777b488bf48aaa
Signed-off-by: Hao Wu <hao.wu@intel.com>
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Felipe Balbi [Mon, 4 Jul 2011 08:12:32 +0000 (11:12 +0300)]
usb: gadget: langwell_udc: fix compile warnings
This patch fixes the following compile warnings:
drivers/usb/gadget/langwell_udc.c: In function ‘queue_dtd’:
drivers/usb/gadget/langwell_udc.c:596:2: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
drivers/usb/gadget/langwell_udc.c: In function ‘langwell_udc_probe’:
drivers/usb/gadget/langwell_udc.c:3274:2: warning: format ‘%d’ expects argument of type ‘int’, but argument 4 has type ‘size_t’ [-Wformat]
drivers/usb/gadget/langwell_udc.c:3289:2: warning: format ‘%d’ expects argument of type ‘int’, but argument 4 has type ‘size_t’ [-Wformat]
drivers/usb/gadget/langwell_udc.c: In function ‘langwell_udc_resume’:
drivers/usb/gadget/langwell_udc.c:3473:2: warning: format ‘%d’ expects argument of type ‘int’, but argument 4 has type ‘size_t’ [-Wformat]
drivers/usb/gadget/langwell_udc.c:3487:2: warning: format ‘%d’ expects argument of type ‘int’, but argument 4 has type ‘size_t’ [-Wformat]
Change-Id: I84e4ed2a9a084994582836cb92827b02b6537c1a
Signed-off-by: Felipe Balbi <balbi@ti.com>
Sebastian Andrzej Siewior [Tue, 28 Jun 2011 13:33:47 +0000 (16:33 +0300)]
usb: gadget: convert all users to the new udc infrastructure
peripheral drivers are using usb_add_gadget()/usb_del_gadget() to
register/unregister to the udc-core.
The udc-core will take the first available gadget driver and attach
function driver which is calling usb_gadget_register_driver(). This is
the same behaviour we have right now.
Only dummy_hcd was tested, the others were compiled tested.
Change-Id: I8f38315183c262e4697ce50f9965074092a64fb0
Cc: Alan Stern <stern@rowland.harvard.edu>
Cc: Anton Tikhomirov <av.tikhomirov@samsung.com>
Cc: Ben Dooks <ben-linux@fluff.org>
Cc: Dan Carpenter <error27@gmail.com>
Cc: Darius Augulis <augulis.darius@gmail.com>
Cc: Eric Miao <eric.y.miao@gmail.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Cc: Li Yang <leoli@freescale.com>
Cc: Michael Hennerich <michael.hennerich@analog.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Pavankumar Kondeti <pkondeti@codeaurora.org>
Cc: Roy Huang <roy.huang@analog.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Toshiharu Okada <toshiharu-linux@dsn.okisemi.com>
Cc: Xiaochen Shen <xiaochen.shen@intel.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Cc: Yuan-Hsin Chen <yhchen@faraday-tech.com>
Cc: cxie4 <cxie4@marvell.com>
Cc: linux-geode@lists.infradead.org
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Felipe Balbi [Tue, 28 Jun 2011 13:33:46 +0000 (16:33 +0300)]
usb: gadget: introduce UDC Class
this class will be used to abstract away several of the duplicated
operations scattered among the USB gadget controller drivers.
Later, we can add an atomic notifier to tell interested drivers about
what's happening with the controller. Notifications such as suspend,
resume, enumerated, etc. will be useful, at a minimum, for implementing
usb charger detection.
As part of the converting process usb_gadget_probe_driver() is no longer
part of each udc but pushed into the ->stap() callback. The same for his
couterpart.
The core is currently set explicit to 'n'. It will be changed to 'y' once
all users are converted since it provides functions which clash with
other drivers.
Change-Id: I7ea32afc0dafbd35d2c56e79ac631fcb6b52239d
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Acked-by: Michal Nazarewicz <mina86@mina86.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Fei Yang [Mon, 12 Sep 2011 22:01:37 +0000 (15:01 -0700)]
linux-2.6.36-intel-scu-ipcutil-allow-ipcutil-compile-as-module.patch
Change-Id: I168b5e7d3d6df31908a2edfaa821815b6dbe8bae
Signed-off-by: Fei Yang <fei.yang@intel.com>
Fei Yang [Mon, 12 Sep 2011 21:54:45 +0000 (14:54 -0700)]
IPC: Fix merge problems.
The latest version in 2.6.35 tree is using if-else statement in function
scu_ipc_ioctl, however in AC tree switch-case statement is used instead,
need to add break instruction accordingly.
Also CPU type checking is introduced in 2.6.35 tree, need to merge that
change for INTEL_SCU_IPC_FW_UPDATE.
In Linux 3.0 pm_qos_add_request doesn't allocate memory any more, the
function requires a pre-allocated struct pm_qos_request_list. make change
in intel_scu_ipc_init accordingly.
Change-Id: Ia36a46030f52ad3f68c0c8e9d101bb049460e2ec
Signed-off-by: Fei Yang <fei.yang@intel.com>
jianwei.yang [Wed, 15 Sep 2010 14:40:47 +0000 (16:40 +0200)]
Add MIP header update when FW is upgraded
The MIP header will also be updated when FW is upgraded through loadfw
Change-Id: I19bd38068cfea8bcbc8504b00e99a3e902634ff7
Signed-off-by: jianwei.yang <jianwei.yang@intel.com>
Samu Onkalo [Fri, 2 Sep 2011 12:01:08 +0000 (15:01 +0300)]
intel_scu_ipc: Drop to C6s0i0 when there is IPC communication ongoing
BZ: 8911
When a IPC command is issued the IPC driver waits for the completion
interrupt from the SCU by issuing a wait_for_competion_timeout API
this causes the IPC driver to sleep, invoking idle process, which then
triggers S0ix, this causes the SCU to disable the interrupts and the
pending IPC completion interrupt is never delivered this causes
IPC timeout to occur.
Fixed this by not doing S0ix by using PM Qos which prevents any deeper
than C6 states from happening. This restrictioin is removed once the
IPC command completes.
Change-Id: I97136b131c1d6019e505e1ab97ec67cec1a473d9
Signed-off-by: Samu Onkalo <samu.onkalo@intel.com>
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
Signed-off-by: Marie-Celine Dubut <marie.celinex.dubut@intel.com>
Reviewed-on: http://android.intel.com:8080/17210
Bin Yang [Wed, 24 Aug 2011 09:24:34 +0000 (17:24 +0800)]
ipc: upgrade ifwi at reboot
BZ: 5466
SCU FW has a limitation, that it cannot support any IPC
command after ifwi upgrading except for reboot. And it is
a risk to continue run kernel and SCU after ifwi upgrading.
After discussing with Pierre, we have this solution to upgrade
ifwi right before reboot.
This patch support to prepare for ifwi upgrading at kernel
runtime, then kick off the real upgrading at the end of system
reboot.
Change-Id: I3d4f5feefe3fbc5863e1a63958d529b040dc6660
Signed-off-by: Bin Yang <bin.yang@intel.com>
Li, Ning [Thu, 18 Aug 2011 07:13:39 +0000 (15:13 +0800)]
ipc: support to write umip unaligned
BZ: 6567
UMIP only supports four bytes aligment access. This patch
helps to read and modify UMIP atomic with unailigned length.
Change-Id: I69b036cce4d5820ba54eb15e03c2fba43a5a9686
Signed-off-by: Bin Yang <bin.yang@intel.com>
Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
Bin Yang [Tue, 16 Aug 2011 03:43:55 +0000 (11:43 +0800)]
ipc: workarround for SCU bug to retry umip/smip cmd
BZ: 6541
SCU is not a multi thread system. It has design limitation
to implement dekker's algorithm.
If IA is using eMMC, umip/smip command will be failed
immediately. But SCU does not cancel the mutex request.
Then, SCU will get the owner of this mutex after it is
released by IA. But SCU had completed umip/smip command,
and not aware of this owner change. So SCU will not release
the mutex and IA will lose the mutex later.
This patch is a workarround for this SCU limitation.
It keeps to send umip/smip command while it is failed.
When it is successful, SCU will release the mutex.
It should not be the final solution. SCU needs to fix
this issue in the future.
Change-Id: I87f5db6f558e37ba0e595cfe21835249c8e417f6
Signed-off-by: Bin Yang <bin.yang@intel.com>
Li, Ning [Mon, 8 Aug 2011 08:09:31 +0000 (16:09 +0800)]
ipc: enable IPC interrupt mode
BZ: 6898
IPC driver was polling the status busy bit to wait
for command completion. It was not effective.
This patch enhances driver to wait interrupt.
CPU is relaxed when IPC command is in progress.
Change-Id: I0107ebb74b7db316fd68eca859ec2c71e30d656d
Signed-off-by: Li, Ning <ning.li@intel.com>
Signed-off-by: Bin Yang <bin.yang@intel.com>
Fei Yang [Fri, 9 Sep 2011 17:06:50 +0000 (10:06 -0700)]
mrst: need to include gpio.h in mrst.c as the touchscreen code added for
Cypress TTSP makes reference to the GPIO API's
Change-Id: Ib11b05ab8b5ec9b1e85748072ab1f5c0f8e493a9
Signed-off-by: Fei Yang <fei.yang@intel.com>
Fei Yang [Thu, 8 Sep 2011 20:30:34 +0000 (13:30 -0700)]
CYTTSP: I2C read errors are seen during boot time when initializing
touchscreen. Problem is that CY_DELAY_SYSINFO is not accurately defined.
Making the delay 30ms to avoid I2C read error.
Need to revisit when hardware specification is available.
Change-Id: I44f408212d698524ce7603b85df18260d859b21f
Signed-off-by: Fei Yang <fei.yang@intel.com>
Jianwei Yang [Wed, 3 Aug 2011 04:36:55 +0000 (12:36 +0800)]
cyttsp: move early_suspend registration to the end of probe
BZ: 6424
early_suspend may be registered even if driver probe fails, this
will cause kernel panic when the early_suspend is executed without
driver registered.
Change-Id: If898bce838f40a4c28e7c4b997e742c541891618
Signed-off-by: Jianwei Yang <jianwei.yang@intel.com>
Sundar Iyer [Fri, 1 Jul 2011 10:20:04 +0000 (15:50 +0530)]
input/cyttsp: optimize msleeps in device initialization path
BZ: 4982
Optimize generous msleeps in the device initialization code
to reduce the total cyttsp boot time from 2839065 usecs to 249755 usecs.
This saves around ~2.5s of total platform boot time
Change-Id: I96bc9668a930251a5cbec5643d705b4b2aff6f7f
Signed-off-by: Sundar Iyer <sundar.iyer@intel.com>
Hong Liu [Thu, 23 Jun 2011 02:45:29 +0000 (10:45 +0800)]
cyttsp: fix compile error when CONFIG_PM is not configured
BZ: 3778
Touch controller needs to be active when updating the touch firmware.
It resumes the device if it is suspended. Make sure the call is guarded
by CONFIG_PM option.
And also disable irq unconditionally when updating firmware.
Change-Id: Ie77b94521d419839ae9346743b3827af60542bbb
Signed-off-by: Hong Liu <hong.liu@intel.com>
Hong Liu [Fri, 3 Jun 2011 08:19:57 +0000 (16:19 +0800)]
cyttsp: simplify event reporting and fix onFling issue
BZ: 1372
Simplify the multi-touch event report sequence for the cyttsp driver,
and with this improvement, we can modify the tracking id to be 0-based,
this solves the onFling not generated issue on Android, since Android
only generate onFling event for tracking id 0.
Change-Id: I61a8bc3d75776168ce38aba9019f0d536f382ee6
Signed-off-by: Hong Liu <hong.liu@intel.com>
Hong Liu [Mon, 25 Apr 2011 05:05:53 +0000 (13:05 +0800)]
cyttsp: fix touchscreen not working after S3 resume
BZ:1101
Gaurd the cyttsp core suspend function with the suspended state,
and move the legacy suspend/resume to the new dev_pm_ops.
Change-Id: Iaadd8935e94b27b8a985ac6b8bcf4de48a1ed7a5
Signed-off-by: Hong Liu <hong.liu@intel.com>
Hong Liu [Tue, 12 Apr 2011 01:41:51 +0000 (09:41 +0800)]
cyttsp: remove unnecessary pointer manipulation
We store the pointer to struct cyttsp as driver data in cyttsp_core_init,
and bus driver (cyttsp_i2c) will pass this driver data to cyttsp_core later.
Change-Id: I56c506ccace2fe81c14c9277cba3bc1316fdc50c
Signed-off-by: Hong Liu <hong.liu@intel.com>
Hong Liu [Tue, 12 Apr 2011 01:38:06 +0000 (09:38 +0800)]
cyttsp: implement early_suspend for cypress controller
Put the controller into deep sleep mode when display is off.
This gives a saving of ~5mW on the TMD panel during S0i3.
Change-Id: I69d1e182311c164ad9372a44f736f8a71826fa17
Signed-off-by: Hong Liu <hong.liu@intel.com>
Hong Liu [Mon, 11 Apr 2011 02:44:27 +0000 (10:44 +0800)]
cyttsp: correct return value for cyttsp suspend/resume func
Return 0 for success and < 0 for error, to make them be consistent with
kernel convention.
Change-Id: I7cb9293833ca4f178e177373c9dd9160d0c303ce
Signed-off-by: Hong Liu <hong.liu@intel.com>
Fei Yang [Thu, 8 Sep 2011 18:11:02 +0000 (11:11 -0700)]
TEMPORARY: iCDK touchscreen support
This patch is based on UMG 2.6.35 kernel. It provides support for
Cypress TTSP touchscreen that is in medfield iCDK. There are no changes
compared to UMG kernel except a few conflicts in platform file.
The driver is still using legacy PM functions which would need to be
converted to dev pm ops if we load this driver when doing S0i3 checks
NOT FOR UPSTREAM. Please wash hands after handling.
Change-Id: I464795f24af35c9b06dff19dd0f62b3846f57b72
Signed-off-by: Pauli Nieminen <pauli.nieminen@intel.com>
Octavian Purdila [Thu, 25 Aug 2011 11:14:04 +0000 (12:14 +0100)]
PCI core warns if the legacy PM and new PM functions are
present. Update the driver to only use the new power management
framework.
This patch fixes the following warning seen during suspend/resume:
<7>[ 24.193850] i2c-designware-pci 0000:08:13.0: suspend
<4>[ 24.193866] ------------[ cut here ]------------
<4>[ 24.193892] WARNING: at drivers/pci/pci-driver.c:605 pci_has_legacy_pm_support+0x48/0x4d()
<4>[ 24.193925] Hardware name: OakTrail
<4>[ 24.193936] Modules linked in:
<4>[ 24.193958] Pid: 2834, comm: kworker/u:22 Tainted: G W 2.6.36greenridge-01402-gc8047e6 #171
<4>[ 24.193974] Call Trace:
<4>[ 24.193999] [<
c1033a93>] warn_slowpath_common+0x66/0xc2
<4>[ 24.194025] [<
c1164143>] ? pci_has_legacy_pm_support+0x48/0x4d
<4>[ 24.194052] [<
c1033afe>] warn_slowpath_null+0xf/0x13
<4>[ 24.194079] [<
c1164143>] pci_has_legacy_pm_support+0x48/0x4d
<4>[ 24.194106] [<
c11643ff>] pci_pm_suspend+0x22/0x154
<4>[ 24.194131] [<
c11643dd>] ? pci_pm_suspend+0x0/0x154
<4>[ 24.194156] [<
c11e8a7a>] pm_op+0x3e/0x95
<4>[ 24.194182] [<
c11e931d>] __device_suspend+0x12e/0x194
<4>[ 24.194208] [<
c11e974d>] ? dpm_drv_timeout+0x0/0x47
<4>[ 24.194237] [<
c11e9729>] async_suspend+0x16/0x3a
<4>[ 24.194265] [<
c104de8e>] async_run_entry_fn+0x97/0x135
<4>[ 24.194291] [<
c1043c34>] process_one_work+0x1c9/0x2db
Signed-off-by: Octavian Purdila <octavian.purdila@intel.com>
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Dirk Brandewie [Thu, 25 Aug 2011 11:14:04 +0000 (12:14 +0100)]
i2c-designware: Add runtime power management support
Add runtime power management to the PCI driver.
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Dirk Brandewie [Thu, 25 Aug 2011 11:14:04 +0000 (12:14 +0100)]
i2c-designware: Add support for Designware core behind PCI devices.
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Dirk Brandewie [Thu, 25 Aug 2011 11:14:03 +0000 (12:14 +0100)]
i2c-designware: Push all register reads/writes into the core code.
Move all register manipulation code into the core, also move register
offset definitions to i2c-designware-core.c since the bus specific
portions of the driver no longer need/use them.
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Dirk Brandewie [Thu, 25 Aug 2011 11:14:03 +0000 (12:14 +0100)]
i2c-designware: Support multiple cores using same ISR
Add check to make sure that the core is enabled and has outstanding
interrupts. The activity bit is masked due to the fact that it will
stay active even after the controller has been disabled until the
contoller internal state machines have settled.
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Dirk Brandewie [Thu, 25 Aug 2011 11:14:03 +0000 (12:14 +0100)]
i2c-designware: move controller config to bus specific portion of driver
With multiple I2C adapters possible in the system each running at
(possibly) different speeds we need to move the controller
configuration bit field to the adapter.
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Dirk Brandewie [Thu, 25 Aug 2011 11:14:03 +0000 (12:14 +0100)]
i2c-designware: move i2c functionality bit field to be adapter specific
The functionality of the adapter depends on the configuration of the
IP block at silicon compile time and is adapter specific.
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Dirk Brandewie [Thu, 25 Aug 2011 11:14:02 +0000 (12:14 +0100)]
i2c-designware: Move retriveving the clock speed out of core code.
The clock frequecy supplied to the IP core is specific to a single
instance of the driver. This patch makes it possible to have multiple
Designware I2C cores in the system possibly running at different core
frequencies.
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Dirk Brandewie [Thu, 25 Aug 2011 11:14:02 +0000 (12:14 +0100)]
i2c-designware: split of i2c-designware.c into core and bus specific parts
This patch splits i2c-designware.c into three pieces:
i2c-designware-core.c, contains the code that interacts directly
with the core.
i2c-designware-platdrv.c, contains the code specific to the
platform driver using the core.
i2c-designware-core.h contains the definitions and declareations
shared by i2c-designware-core.c and i2c-designware-platdrv.c.
This patch is the first in a set to allow multiple instances of the
designware I2C core in the system.
Change-Id: Ib876d49780e55ade274026380326c550752e4193
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Seth Levy [Mon, 6 Jun 2011 23:42:44 +0000 (19:42 -0400)]
USB: net2272: driver for PLX NET2272 USB device controller
This is based on the last release from PLX:
http://www.plxtech.com/files/products/net2000/software/selectiontool/RE061204-net2272-linux2.6.18.tgz
I've managed to contact them and they've confirmed that this driver was
wholly written by PLX (Seth Levy). While they have no problem with it
being merged (and they've already licensed it as GPL), they don't have
any interest in doing so themselves as this is an old part for them.
ADI has long had an add-on card which has this part on it, so we've been
keeping it up-to-date out of tree. But now that PLX has confirmed the
source of the driver, we can can take the next step of cleaning it up and
getting it merged.
So here we are! I've done quite a large clean up of the driver and
attempted to address all the common issues. Hopefully in the process,
I haven't broken anything. While it seems to still work with the board
that I have access to, it is not a PCI variant. So I have not tested
any of the PCI logic myself (beyond clean compile). Perhaps someone who
actually has a card and cares can do so.
I'll try to address further feedback, but don't expect miracles. I'm
not really familiar with the part itself, just the platform glue.
Change-Id: Ife07cd1726128d06cf9f5df07108474996b46ca2
Signed-off-by: Seth Levy <seth.levy@plxtech.com>
Signed-off-by: Ash Aziz <ash.aziz@plxtech.com>
Signed-off-by: Roy Huang <roy.huang@analog.com>
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Illyas Mansoor [Tue, 6 Sep 2011 17:33:42 +0000 (23:03 +0530)]
PMU: fix lpmp3 trigger when lss_51, 52 in D0i0
When voice call + mp3 is on enabling s0i1/LPMP3 causes
system hang.
This is due to the target config for LPMP3 was set
to get triggered if LSS_08/09 + LSS_51/52 are in D0i0
and rest in D0i3.
Fixed this by add check for LSS_51/52 to be in D0i3 before
triggering LPMP3 ie., only LSS_08/09 can be in D0i0 for
triggering LPMP3.
Change-Id: I03866e3aa5325149303902a80b591a88ea19ff63
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
Illyas Mansoor [Tue, 30 Aug 2011 11:10:55 +0000 (16:40 +0530)]
PMU: fix divide by zero in pmu_stat_seq_printf
When echo clear > /d/mid_pmu_states is done,
and immediately "cat /d/mid_pmu_states" is
called, the variable init_2_now_time could be zero.
t = cpu_clock(raw_smp_processor_id());
t -= pmu_init_time;
init_2_now_time = (unsigned long) t;
remainder = do_div(t, init_2_now_time);
Fixed this by checking for init_2_now_time for zero.
Change-Id: I2bdd22526622327007e52cd93ebbe82fd78e72d2
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
Fei Yang [Fri, 26 Aug 2011 17:03:08 +0000 (10:03 -0700)]
PMU: PMU_SECURITY_LSS_04 and PMU_USB_OTG_LSS_06 can go to proper low power
state now after applying the following patches from umg 2.6.35 tree,
put these two LSS back to the s0i3 checklist.
commit
11724c02b5525f8acb4ba9ab9a6547055b49adb9
Author: Wu, Hao <hao.wu@intel.com>
Date: Fri Aug 5 01:28:58 2011 +0800
usb: set pci device state to D0 before run ehci quirks
BZ: 6580
As mid_pmu driver will set USB LSS_06 in D0i1 at init, so if
we didn't get USB back to D0 before run ehci quirks, it will
cause Fabric error due to controller regsiter access in D0i1.
Change-Id: I3ba147aecbfac30bcb57629e70919df210405be7
Signed-off-by: Wu, Hao <hao.wu@intel.com>
commit
135189c63e46a39a7ab3951495d03a5e8e9d6ab0
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date: Wed Aug 3 15:08:32 2011 +0530
mid_pmu: remove devices not supporting D0i3 in D0i0
BZ: 6580
Earlier we had put all devices that do not support D0i3 in D0i0 state
after investigation we found that putting USB LSS_06 in D0i1 causes
this Fabric error.
This is now fixed, hence removing forcing of D0i0
Change-Id: If5e3879610a3613472214aa835da35ca32c5c899
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
Change-Id: I6eecd53c736f07cb1b4f1a86529a8651877dd5ee
Signed-off-by: Fei Yang <fei.yang@intel.com>
Fei Yang [Thu, 25 Aug 2011 21:07:05 +0000 (14:07 -0700)]
PMU: patch from umg kernel 2.6.35 tree
commit
d0378332f33fbee63f6e5b5f44dd9b64c53c5525
Author: Bin Gao <bin.gao@intel.com>
Date: Fri Aug 12 10:44:11 2011 -0700
mid_pmu: add NC device power island state to mid_pmu debugfs interface
BZ: 7322
Currently mid_pmu debugfs interface("mid_pmu_states") only shows
power state of PCI devices in SC. For NC devices(display, camera,
etc.), there are just two simple variables display_off and
camera_off to track the current power status, but for both display
and camera, there are more than one power islands, for debug purpose,
we need present all these power islands states to debugfs interface.
This patch adds:
GFX, Decoder, Encoder, GL3, Display A/B/C and MIPI-DSI
island state to gfx/display device(00:02.0), and,
ISP and Iunit PHY island state to isp device(00:03.0).
Change-Id: If93f346c16b6a1a39462aff9920167c2e06c32ef
Signed-off-by: Bin Gao <bin.gao@intel.com>
Change-Id: If7f398e032f7b653a39fd91a74cea5be443a562f
Signed-off-by: Fei Yang <fei.yang@intel.com>
Fei Yang [Wed, 24 Aug 2011 22:36:35 +0000 (15:36 -0700)]
PMU: Make sure only attempt s0i3 after all CPUs are in C6, otherwise s0i3
rarely succeed, because of NO_ACK_C6.
changes merged from the following commits on umg 2.6.35 kernel tree
Signed-off-by: Fei Yang <fei.yang@intel.com>
commit
80aa40058f0a618c21c02fd2c883ab7dbe22c811
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date: Thu Apr 21 15:36:45 2011 -0700
intel_idle: s0ix support while some cpu offline
BZ: 1420
S0ix was not triggered if one of the cpus was put into softoffline
since the nr_cpus_in_c6 was not getting decremented while the cpus
go offline, hence it was never maching (nr_cpus-1)
we changed to (!atomic_add_unless(&nr_cpus_in_c6, 0, (num_online_cpus()-1)))
to take care of this scenario. S0ix is now working with cpu1 offline.
Change-Id: If46d3a18e8217e99980ffefd5eea567d41623888
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit
dab137cc309b0bf7cee682f5252caa9208905e49
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date: Thu Jan 13 22:18:10 2011 +0100
intel-idle: intel_mid s0ix implementation
Medfield introduces a new set of System States called System Idle states,
known as S0ix states. These S0ix states are low power active idle states
that the platform can be transitioned into and out of.
The entry into these states is triggered by user inactivity. The platform
can be restored to normal S0 state only through a wake event - the wake
event can range from a timer event, to a network related event (on SDIO
for example), or a event reported by the USB Host controller. Only
specific components can trigger such wake events.
PMU stack needs to perform unique actions for entering and exiting S0ix
states by programming the wake configuration registers in pmu1/pmu2 PMU's
so that the PMUs can restore the correct component state on a wake event.
Subsequently, OSPM's PMU driver configures the PMUs to enter the appropriate
S0ix state.
System Idle State i1 (S0i1) is a low power sleep state where large portions
of the entire platform are clock and power gated (depending on the capabilit
of the subsystem and as determined by OSPM). In this state, CPU core has
local state retention and on a wake, will start executing at the next
instruction after the MWAIT instruction which triggered the platform entry
into S0i1.
System Idle State i3 (i.e. S0i3) corresponds to a highest latency and lowest
power system idle state. This is similar to S0i1, except that the CPU core
does not have local state retention. The state has to be programmatically
saved to memory by OSPM's PMU driver. Upon exit from this state, the CPU
will be reset. Memory contents are retained but in low power/self-refresh
mode in S0i3.
This patch contains:
- the core logic of performing the required CPU architectural save and
restore for S0i3 entry and exit correspondingly.
- IA-specific assembly code with utilities that save/restore CPU state,
flushes TLB page and cache, reading/writing MSRs.
- wake code that IA Firmware jumps to on resuming from S0i3.
This also changes the existing intel idle driver to add s0ix hooks.
This code restores the previously saved CPU state and ensures that execution
can resume from the next instruction after MWAIT that caused the S0i3 entry.
Signed-off-by: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
Signed-off-by: Harinarayanan Seshadri <harinarayanan.seshadri@intel.com>
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
Change-Id: I0140852ede8184283c805928e0aabfc56e7e1773
Fei Yang [Sat, 20 Aug 2011 02:13:54 +0000 (19:13 -0700)]
CPUIDEL: Do not check number of substates for any states above C6 as these
are not real C states supported by the CPU, they are emulated c
states for s0ix support.
Change-Id: I71eaa74a7261c8919be1fa7efe151dce86c800df
Signed-off-by: Fei Yang <fei.yang@intel.com>
Fei Yang [Thu, 18 Aug 2011 00:17:58 +0000 (17:17 -0700)]
PMU: Remove global variables used as constant.
Add s0i3 support for Medfield.
Simplify s0i3 logic. mfld_s0i3_enter() enforces c6 so that
the idle driver doesn't need to call intel_idle after entering
s0i3.
Change-Id: I64898388fd1a1e18408c39c82bb0b1ed74b1a6f2
Signed-off-by: Fei Yang <fei.yang@intel.com>
Fei Yang [Thu, 18 Aug 2011 00:05:56 +0000 (17:05 -0700)]
MID PCI: correct cpu family checking logic
Change-Id: Ie54f16165c7cbca8007205f6dac0ce730e7d46da
Signed-off-by: Fei Yang <fei.yang@intel.com>
Kristen Carlson Accardi [Tue, 9 Aug 2011 13:26:04 +0000 (14:26 +0100)]
hsu: add runtime pm support
Doesn't appear to be much to do here, however having the suspend/resume
functions will allow the d3/d0 transitions to be sent by the pci core.
Signed-off-by: Kristen Carlson Accardi <kristen@linux.intel.com>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Fei Yang [Tue, 16 Aug 2011 22:26:43 +0000 (15:26 -0700)]
WAKELOCK: Enable wakelock in PMU driver for Android kernel
Change-Id: I5a7789f6df35a218359bc4756110c90bcb898f4a
Signed-off-by: Fei Yang <fei.yang@intel.com>
Len Brown [Fri, 12 Aug 2011 21:46:05 +0000 (22:46 +0100)]
TEST mfld pmu: delete constant "ioc" parameter
We used to ask for interrupts for all LSS commands.
Now we ask for interrupts for NO LSS commands.
In either case the "ioc" parameter is constant.
cleanup only: no functional change
Signed-off-by: Len Brown <len.brown@intel.com>
Len Brown [Fri, 12 Aug 2011 21:45:47 +0000 (22:45 +0100)]
TEST mfld pmu: Replace device power state command locking strategy
pmu_pci_set_power_state() calls would previously...
acquire semaphore "set_mode_complete_sem",
set global "interactive_cmd_sent",
issue the LSS command with IOC=1.
sleep on "set_mode_complete_sem" semaphore
As IOC was set, pmu_sc_irq() would be invoked,
which would see the global "interactive_cmd_sent"
and signal "set_mode_complete_sem"
This scheme can not work when pmu_pci_set_power_state()
is invoked from interrupt context, where sleeping
is prohibited.
Replace it with the scheme used by mrst_pmu:
pmu_pci_set_power_state() is synchronous -- it waits
for the SCU to be not-busy before and after commands.
Drivers may access devices immediately upon its return.
SMP entry to pmu_pci_set_power_state() is handled
via spinlock.
Signed-off-by: Len Brown <len.brown@intel.com>
Len Brown [Fri, 12 Aug 2011 21:45:29 +0000 (22:45 +0100)]
TEST mfld pmu: enable build
Signed-off-by: Len Brown <len.brown@intel.com>
Len Brown [Fri, 12 Aug 2011 21:44:44 +0000 (22:44 +0100)]
TEST mfld pmu: prevent Fabric Errors/Boot hang
Don't yet know why this hack-around is needed,
but it allows the pmu driver to load on the iCDK w/o killing the system.
Signed-off-by: Len Brown <len.brown@intel.com>
Len Brown [Fri, 12 Aug 2011 21:44:30 +0000 (22:44 +0100)]
TEST mfld pmu: differentiate MRST and MFLD pmu_pci_set_power_state
It is currently possible to build both MRST and MFLD into the kernel.
So we need to avoid a name conflict,
and bind the right version of pmu_pci_set_power_state().
Signed-off-by: Len Brown <len.brown@intel.com>
Len Brown [Fri, 12 Aug 2011 21:44:07 +0000 (22:44 +0100)]
TEST mfld pmu: sync mid_pci.c from mrst/meego tree
Signed-off-by: Len Brown <len.brown@intel.com>
Len Brown [Fri, 12 Aug 2011 21:43:52 +0000 (22:43 +0100)]
TEST mfld pmu: add arch/x86/platform/mfld/pmu.c
From UMG 2.6.35 tree: arch/x86/kernel/mid_pmu.c
commit
30365108003d6d71f508b5cf4429e9588a5928a0
Author: Fengwei Yin <fengwei.yin@intel.com>
Date: Mon Jul 11 11:16:33 2011 +0800
Revert "mid_pmu: do not issue set_command during s3 entry"
BZ: 4883
This reverts commit
a49316f33d6066dd13d85f577dce84dd0278d4d0.
Change-Id: If9a8c696f626a7d6d8fcd42da8e1563a5c1bf4f8
Signed-off-by: Fengwei Yin <fengwei.yin@intel.com>
commit
9f42b0f20930f74e6840a335db62b9089f7176da
Author: Prabu Renganathan <prabu.renganathan@intel.com>
Date: Fri Jun 17 18:28:36 2011 -0700
mid_pmu: pick D0i1 as USB low power state
BZ: 3497
HSD: 3337060
Fix for the Penwell bug where USB only supports D0i1
Signed-off-by: Prabu Renganathan <prabu.renganathan@intel.com>
Change-Id: Icb0c7c9ffb9889c2de7743ff326f74a9b2ab8771
commit
a49316f33d6066dd13d85f577dce84dd0278d4d0
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date: Wed Jun 29 13:43:02 2011 +0530
mid_pmu: do not issue set_command during s3 entry
BZ: 4139
during s3 entry dpm_suspend_noirq will call each of the drivers
suspend calls and that in turn calls set_power_state() calls,
we issue an interactive command to SCU and wait for the status
interrupt this takes a long time until all the devices are suspended.
This is not required since anyways after the devices are suspended
we do S3 that puts all the devices in D0i3.
We just cache the status of all the devices and configure that as
the wakeup states after S3. This reduces the time to enter S3.
Change-Id: Ice0f5b326335675890fa60ce6c546693d11d98f2
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit
1df781ef9bbc9b0fc453537da2a3b1861f363138
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date: Thu Jun 23 04:58:43 2011 +0530
mid_pmu: sparse warnings fixed
BZ: 3856
Fixed the following sparse warnings.
arch/x86/kernel/mid_pmu.c:302:18: warning: symbol 'pmu_wake_lock' was not declared. Should it be static?
arch/x86/kernel/mid_pmu.c:1126:15: warning: symbol 'pmu_get_cstate' was not declared. Should it be static?
arch/x86/kernel/mid_pmu.c:1813:3: warning: symbol 'medfield_lsses' was not declared. Should it be static?
arch/x86/kernel/mid_pmu.c:1874:5: warning: symbol 'medfield_lsses_num' was not declared. Should it be static?
arch/x86/kernel/mid_pmu.c:1876:6: warning: symbol 'lss_device_status' was not declared. Should it be static?
arch/x86/kernel/mid_pmu.c:2368:5: warning: symbol 'mid_suspend' was not declared. Should it be static?
fixed make namespacecheck issues.
Change-Id: I7731a0391b1433a7ecfa28bdd3265591d1389495
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit
c68b6b1636a4b898773a05a5651839806dd3314c
Author: Laurent Kappel <laurentx.kappel@intel.com>
Date: Wed Jul 6 20:22:10 2011 +0200
Revert "mid_pmu: s0i1 lpmp3 s0i3 s3 automatic selection"
This reverts commit
e899b6438b842047bef1bbdfdf9188bd09fab447.
Change-Id: I7d51be7532056ff81d89ce0bc2af8480ffc812ea
Signed-off-by: Laurent Kappel <laurentx.kappel@intel.com>
commit
e899b6438b842047bef1bbdfdf9188bd09fab447
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date: Fri Jun 17 10:13:31 2011 +0530
mid_pmu: s0i1 lpmp3 s0i3 s3 automatic selection
BZ: 2457
Automatically select s0i1, lpmp3, s0i3 or S3 does'nt happen currently,
it is based on "echo s0i1/3 > /sys/modules/mid_pmu/parameters/s0ix"
changed this to automatically select s0ix/lpmp3/s3 based on cpuidle
latency and wakelocks.
Change-Id: I5f3eef919aaac90d44e0d6ef0502c86f38da3ba2
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit
54f32f953f356027c774c3cf46462992eadc73a7
Author: Pierre Tardy <pierre.tardy@intel.com>
Date: Tue Jun 28 10:51:29 2011 +0200
REVERTME:mid_pmu: deactivate S3 on PR2
BZ: 4177
quite a lot of patches are pending to enable S3 on PR2.
Waiting for that we disable S3 by default on PR2
to be reverted as soon as PR2 drivers are S3 capable
Change-Id: I4de53e978fe850303617f8ace4ab9f073ce64d89
Signed-off-by: Pierre Tardy <pierre.tardy@intel.com>
commit
5e73c57d106f8c766a5a06221e2817a7c9a5b393
Author: Rajesh Poornachandran <rajesh.poornachandran@intel.com>
Date: Thu Jun 16 16:59:39 2011 -0700
Revert "Revert "mid_pmu: Moving NC power management logic to OSPM""
BZ: 1957
Currently the PM for north complex was done independently by Gfx and ISP drivers.
There was no synchronization between ISP and Gfx while sending the PM cmd.
OSPM patch to provide an API, pmu_nc_set_power_state. This API will take care
of talking to P-unit and getting the corresponding power islands to ON/OFF.
Gfx and ISP drivers need to use this API in their drivers.
Change-Id: I628dd8b03f5d09607e3c931e29943fcdb73613cb
Signed-off-by: Sujith Thomas <sujith.thomas@intel.com>
Signed-off-by: Rajesh Poornachandran <rajesh.poornachandran@intel.com>
commit
3b40317a7924fd4277b06992ea8755fe4d39094f
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date: Wed Jun 22 03:58:51 2011 +0530
mid_pmu: camera blocks s0ix when camera driver not present
BZ: 3762
With Camera driver removed we are not able to enter s0i1/3 S3, this is because
the camera_off variable will be '0' even if the driver is not configured.
conditionally set the variable '1' if camera device is not configured.
Change-Id: Ia582399c8f3f493255e387a1a8ec0612fc6b50d0
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit
dd6db50f98b6c0d368b9315124b65ec3b1aae2a1
Author: Erwan Mahe <erwanx.mahe@intel.com>
Date: Thu Jun 23 18:29:21 2011 +0200
Revert "Revert "mid_pmu: pick correct D0ix states in choose_state""
BZ: 2102
This reverts commit
41ff42ea4b74c89d7ed44b51e46ab7ae45b4b87c.
Change-Id: I5aa5658cf28696a3c79a939ea8644a3b3c4d73f0
commit
41ff42ea4b74c89d7ed44b51e46ab7ae45b4b87c
Author: Marie-Celine Dubut <marie.celinex.dubut@intel.com>
Date: Wed Jun 22 12:44:06 2011 +0200
Revert "mid_pmu: pick correct D0ix states in choose_state"
BZ 2102
This reverts commit
c60a2ae1f8b33abdabbff9c0de5a57ec6588df9d.
Change-Id: I7e7aed5071adabc824c303628ba855031892e70a
commit
c60a2ae1f8b33abdabbff9c0de5a57ec6588df9d
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date: Wed Jun 1 13:19:54 2011 +0530
mid_pmu: pick correct D0ix states in choose_state
BZ: 2102
currently pmu_pci_choose_state return PCI_D3hot for all devices.
For some of devices, it may not be possible to support PCI_D3hot state.
eg., HSU needs to be put in D0i1, chaabi needs to be put in
D0i2. It is not appropriate to always choose D0i3 for all devices
We choose the correct state that is appropriate for each device
for the platform.
This patch should be used only with a FW that is capable of supporting
Chaabi D0i2.
Change-Id: Ief7b64bc1ec37d4452ce3222454bdd6102d54c10
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit
c4e73f14acb7ffd39a5d965fc23b1f01673363b8
Author: Hari Kanigeri <hari.k.kanigeri@intel.com>
Date: Fri Jun 3 11:27:13 2011 -0600
mid_pmu: fix checkpatch violations and some cleanup in exit paths
BZ: 3066
Fix the following:
1. Checkpatch violations and cosmetic changes.
2. fix correct cleanup in the exit paths of the function mid_pmu_probe
Below log is related to checkpatch violations.
1. Checkpatch violations
=========================
ERROR: space required before the open parenthesis '('
+ if(pdev->device == 0x81c || pdev->device == 0x81b)
WARNING: line over 80 characters
+ for (i = 0; i < PMU_MAX_LSS_SHARE && intel_mid_pci_devices[index].dev_driver[i]; i++) {}
ERROR: trailing statements should be on next line
+ for (i = 0; i < PMU_MAX_LSS_SHARE && intel_mid_pci_devices[index].dev_driver[i]; i++) {}
WARNING: braces {} are not necessary for single statement blocks
+ for (i = 0; i < PMU_MAX_LSS_SHARE && intel_mid_pci_devices[index].dev_driver[i]; i++) {}
WARNING: line over 80 characters
+static pci_power_t pmu_pci_get_weakest_state_for_lss(int lss_index, struct pci_dev *pdev, pci_power_t state)
<cut here for brewity, please run checkpatch to see a complete list>
total: 122 errors, 14 warnings, 2340 lines checked
Change-Id: I1cdbd6a8b70d303611f0cd426ce63235010d0a07
Signed-off-by: Hari Kanigeri <hari.k.kanigeri@intel.com>
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit
3df93729faabfefb971badf3b51f8e652da3f288
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date: Mon Jun 13 01:52:20 2011 +0530
mid_pmu: abort s0i3 c6offload write access not set
BZ: 3356
OSPM waits (busy loop) for "write access" to C6 Offload area to be granted by
SCU. After sending S0ix command to SCU via the PM_CMD reg.
In current OSPM code we clear "enable MSR" bit if we find c6 offload "write
access" bit is not set, c6 offload wont happen, a c6 will still be issued. This
will trigger ack_c6, but in this case SCU will check offload signature to
makesure if offload has occurred, since it won't find the offload signature it
should abort s0ix entry.
We have busy loop'd considerable amount of time waiting for c6 "write
access" bit to be set we may have overshot the c6 latency, hence it is better
to demote the c6 to a c4.
Change-Id: Ie0027ff4efb8a418a7377ba30eb6a20d0a74087c
Signed-off-by: Illyas mansoor <illyas.mansoor@intel.com>
commit
4405feeea2eef28c40bda0e29817ee5ea223abe5
Author: MingmingX Zhang <mingmingx.zhang@intel.com>
Date: Mon Jun 13 10:05:08 2011 +0800
mid_pmu: delete repeated WARN in function mfld_s0i3_enter function
BZ: 3346
In function mfld_s0i3_enter, there are 2 WARN to check the same
error status. Delete the needless WARN_ON.
Change-Id: I8ba7cdab1eedf4bebdd3bfa599e3db795c56bdb0
Signed-off-by: MingmingX Zhang <mingmingx.zhang@intel.com>
commit
d332d4a59c01e1774cd4fdc28d97fe4d865989ee
Author: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
Date: Thu Feb 16 22:36:00 2006 +0530
pmu: adding atomisp as part of entry criterion for S0i3
BZ: 1339
In current build we dont look at the isp runtime status before
we enter S0i3 state. In this patch we check for the camera status
in addition to all other device states that we check today in S0i3.
Change-Id: If3f024fa22d0d744160b961e637e2b1c25e5e1c9
Signed-off-by: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
commit
397b53b9679edd28669876fbbb528a4f3a0daa7f
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date: Wed Jun 1 23:33:33 2011 +0530
mid_pmu: adding s0ix first_entry time and residency
BZ: 2709
Earlier mid_pmu stats did'nt have first entry time and
residency percentages. Also clear option was not available.
Implemented the same.
In order to clear pmu_stats please use the following command
mount -t debugfs none /d
echo "clear" > /d/mid_pmu_states
Change-Id: I4f24272a11b017d0decdb875880e0bc27eb6bf18
Signed-off-by: Sudharshan Ramachandra <sudarshan.n.ramachandra@intel.com>
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit
71fd1c6ca28e68e7d3b8279a594bd51296e8be79
Author: Erwan Mahe <erwanx.mahe@intel.com>
Date: Tue Jun 7 18:22:06 2011 +0200
mid_pmu: s3/S0i3 automatic selection
BZ: 2457
Once the screen saver times out system would do few cycles of S0i3
untill all the wakelocks are released then system will enter S3.This
will avoid echo s0i1/3/x > /sys/module/mid_pmu/parameter/s0ix. This
patch also increases the wakelock timeout for mid_pmu wakelock taken
at end of s3 to 1 sec.
Revert "Revert "mid_pmu: s3/S0i3 automatic selection""
=> Reinstate initial commit
This reverts commit
21b136056afcfe32626a76ce2a3afe653a860c55.
Change-Id: I19e2580bddc656c6ae809a6e1331bedc8579531b
Signed-off-by: Erwan Mahe <erwanx.mahe@intel.com>
commit
21b136056afcfe32626a76ce2a3afe653a860c55
Author: Erwan Mahe <erwanx.mahe@intel.com>
Date: Mon Jun 6 21:01:26 2011 +0200
Revert "mid_pmu: s3/S0i3 automatic selection"
This reverts commit
c589050d2d9a90b0a6a334f57c9008c630fb24f1.
Change-Id: I7e09f304b2eadffb27e83ab810c8a2edb8044fbd
Signed-off-by: Erwan Mahe <erwanx.mahe@intel.com>
commit
c589050d2d9a90b0a6a334f57c9008c630fb24f1
Author: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
Date: Mon Jun 6 10:38:11 2011 +0530
mid_pmu: s3/S0i3 automatic selection
BZ: 2457
Once the screen saver times out system would do few cycles of S0i3
untill all the wakelocks are released then system will enter S3.This
will avoid echo s0i1/3/x > /sys/module/mid_pmu/parameter/s0ix. This
patch also increases the wakelock timeout for mid_pmu wakelock taken
at end of s3 to 1 sec.
Change-Id: I5fc8e13ff0873d6dadd918ad8eabdaa0001e0950
Signed-off-by: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
commit
5e7997d26409e1e0f92c22c71b34fdcc4221e862
Author: Olivier Monnier <olivierx.monnier@intel.com>
Date: Fri Jun 3 11:28:01 2011 +0200
Revert "mid_pmu: s3/S0i3 automatic selection"
This reverts commit
f3ae17eb792bab5ab9bd5adcb0c5385cf9722c60.
Change-Id: I2186fa8813677fcec6bf981c97aaf75dcff5ad5b
Signed-off-by: Olivier Monnier <olivierx.monnier@intel.com>
commit
f3ae17eb792bab5ab9bd5adcb0c5385cf9722c60
Author: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
Date: Thu May 26 15:48:28 2011 +0530
mid_pmu: s3/S0i3 automatic selection
BZ 2457
Once the screen saver times out system would do few cycles of S0i3
untill all the wakelocks are released then system will enter S3.This
will avoid echo s0i1/3/x > /sys/module/mid_pmu/parameter/s0ix
Change-Id: I7cb82c3bb519d769f1905632e7066985676bffef
Signed-off-by: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
commit
53f93b022da79eadc22a2ac5c3adade98380cf84
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date: Mon May 16 00:26:13 2011 +0530
mid_pmu: demote c6 to c4 while s0ix is in progress
BZ: 2120
While S0ix aborts SCU waits for Ack_C6 timeout, IA comes out of
mwait and since the SCU is still waiting for Ack_C6 the S0ix
ACK_C6 timeout error interrupt is not recieved, meanwhile a new
C6 could be triggered from IA and this could trigger a Ack_C6
SCU can mistake this Ack_C6 as a ack for the previously aborted
S0ix and continue S0ix flow. This is not correct.
We check if the system is in S0ix progress state by checking
scu_ready_sem if its already acquired that means S0ix is in
progress and the subsequent C6 should be demoted to C4's
Change-Id: I1b60824b28f9b6579dd551faa8fe485d2074b712
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit
654da78fa8f45bcf4d64d9c0ea115d589f4374c4
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date: Sun May 15 23:44:23 2011 +0530
mid_pmu: c6 offload msr bit cleanup
BZ: 2116
We were using magic number for wmsr(0x120) for setting/clearing
offload bit.
Fixed this by creating #defines
Change-Id: I5fe4ec0568e48d12fe30074f8eebbc2a6411b4d8
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit
516322a23d3e7b1606d83753b121de66e79daa20
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date: Mon May 16 11:09:48 2011 +0530
mid_pmu: releasing scu_ready_sem in mfld_s3_enter
BZ: 2179
In function mfld_s3_enter we are checking if scu_ready_sem is already acquired.
The intention is to make sure we enter S3 only if scu_ready_sem is free, but if
its acquired instead of returning error we release the scu_ready_sem which is
incorrect.
removed the release of scu_ready_sem, if already acquired.
Change-Id: I4ce888ae1702e4cdcb8dd584a87d0d10fb6c84db
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit
8118849a0329d0e73761562443ae25c8b1cd3bf9
Author: Fengwei Yin <fengwei.yin@intel.com>
Date: Sun May 22 11:57:12 2011 +0800
Revert "mid_pmu: Moving NC power management logic to OSPM"
BZ: 2470
This reverts commit
594c7f0327dd02985fbcde1e0bd83c98e684097f.
commit
594c7f0327dd02985fbcde1e0bd83c98e684097f
Author: Sujith Thomas <sthoma3@umg-lab1.iind.intel.com>
Date: Thu May 12 10:51:38 2011 +0530
mid_pmu: Moving NC power management logic to OSPM
BZ: 1957
Currently the PM for north complex was done independently by Gfx and ISP drivers.
There was no synchronization between ISP and Gfx while sending the PM cmd.
OSPM patch to provide an API, pmu_nc_set_power_state.
This API will take care of talking to P-unit and getting the corresponding power
islands to ON/OFF. Gfx and ISP drivers need to use this API in their drivers.
Change-Id: I302c9a7a6bb10ae572d340affb2502443d6178fc
Signed-off-by: Sujith Thomas <sujith.thomas@intel.com>
commit
abfc3b5f6d6df8a5d5985c73f99a8dc72cd18853
Author: Pierre Tardy <pierre.tardy@intel.com>
Date: Mon May 16 16:49:50 2011 +0200
Revert "Revert "Revert "REVERTME:mid_pmu: disable s0i3 by default for HSI IFWIs"""
BZ: 2177
This reverts commit
eefaf8d45186b6ad465e67fb31cb4293c0a7a5fa.
and re-enable s0i3 by default on HSI based IFWI
Change-Id: Ib0289dcb5ef60b7750267aebb53f1bf38ab4ee3d
Signed-off-by: Pierre Tardy <pierre.tardy@intel.com>
commit
50154e4edbe93d9d0d72e3b318cbe83b7e21831a
Author: Pierre Tardy <pierre.tardy@intel.com>
Date: Mon May 16 13:32:44 2011 +0200
mid_pmu: add more trace_printk
BZ: 2139
in order to see wake sources, and errors from s0i3 and s3
Change-Id: If5d6ea297dde5d47ed79583c188d8457bb978076
Signed-off-by: Pierre Tardy <pierre.tardy@intel.com>
commit
47f329c5a5a244636b7805b991d6ba5e1e8c7bd7
Author: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
Date: Mon May 16 09:29:28 2011 +0530
pmu: fixing the aont mask fix for S3
BZ 1756
aont mask set for s3 was not proper which was not allowing to stay
in S3. this patch fixes the mask.
Change-Id: I8dc5a9372054d83a17184d289ea9ae7a621388bc
Signed-off-by: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
commit
c52543cfc2fbade1fac03796c2b0615141e46cea
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date: Tue May 10 12:00:08 2011 +0530
mid_pmu: fix incorrect residency for abort s0ix
BZ: 1885
In case of S0ix/Lpmp3 aborts for any reason we are still counting the
residency times, in case of failure we should not account this time
into actual s0ix/lpmp3 residency times.
corrected this by only accumulating times for successful s0ix exits.
Change-Id: Icdde3491fe786aec4c65795805bfec43d9c107f4
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit
e0c7284d712fdc0715726ad1dc7df4ac6e9b18c9
Author: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
Date: Tue May 10 16:45:05 2011 +0530
pmu: adding ignore wkc lss code needed for long s3
BZ 1756
This patch we add ignore wkc lss to add all those devices
which needs to be ignored as wake sources during entry to s3
state.
Change-Id: I73a46d23f3bee2ef8d979162a4d1b6a020fe4bae
Signed-off-by: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
commit
cba613f2bde66236706b9c0ba7f1fe6b5ff14ad7
Author: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
Date: Tue May 10 16:22:10 2011 +0530
pmu: renaming lss after new wkc implementation in scu
BZ 1756
This patch we are re assigning some of the lss to new lss
based on the WKC implementation in scu.
Change-Id: Ic7a9adf37194182b424dcdcc0d61cb09bba4a7a5
Signed-off-by: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
commit
43ea3ecf3ba252e6859f33d38d9c2bcd0e2c6f06
Author: Jean-Pierre Stierlin <jean-pierrex.stierlin@intel.com>
Date: Fri Apr 29 11:01:35 2011 +0200
mid_pmu: Disable S0i3 when HSI is not in D0i3
BZ: 1226
The platform should not enter S0i3 state when the HSI is still active
Add PMU_HSI_LSS_03 to the s0ix_lss and lpmp3_lss tables
Change-Id: I8ccddaa12d04b0af813820dad19fa96de7fe5e53
Signed-off-by: Jean-Pierre Stierlin <jean-pierrex.stierlin@intel.com>
commit
eefaf8d45186b6ad465e67fb31cb4293c0a7a5fa
Author: Erwan Mahe <erwanx.mahe@intel.com>
Date: Thu May 5 12:12:04 2011 +0200
Revert "Revert "REVERTME:mid_pmu: disable s0i3 by default for HSI IFWIs""
This reverts commit
a561e8620d08973fd5f9eea6a91488977fc3b539.
commit
a561e8620d08973fd5f9eea6a91488977fc3b539
Author: Erwan Mahe <erwanx.mahe@intel.com>
Date: Wed May 4 11:24:08 2011 +0200
Revert "REVERTME:mid_pmu: disable s0i3 by default for HSI IFWIs"
BZ: 1646
This reverts commit
18a41ce2756933e6200e05283e3ea172c7aa320d.
commit
d7a22f9c70e926ebe0bdb78a79153a5b8050a864
Author: Christophe Fiat <christophex.fiat@intel.com>
Date: Thu Apr 28 14:55:45 2011 +0200
mid_pmu: Add HSU in PMU Devices list blocking S0i3
BZ: 932 - Taskforce: Mtfld-Android No Driver with D3/D0i3 for UART0
Now that HSU is RT PM compliant, HSU can block s0i3 from happening when
Bt active.
put HSU LSS in the list of s0i3 and lpmp3 required lss.
Change-Id: I0a4be909433b470b0b1dfa021fcc997d200cd835
Signed-off-by: Christophe Fiat <christophex.fiat@intel.com>
Signed-off-by: Pierre Tardy <pierre.tardy@intel.com>
commit
2f408985f4aeeb807ff095f0e86669fc6a6b14aa
Author: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
Date: Wed Apr 20 23:30:00 2011 +0530
pmu: fixing wake sub system configuration on s3 exit
wake sub system configuration was being set to D0 state
on exit from S3. this is being reverted to state of devices
before entering S3 to follow the same path as S0i3 flow.
Change-Id: Ia6276b151b303912469511a5d1378e39b63d43b4
Signed-off-by: Vishwesh M. Rudramuni <vishwesh.m.rudramuni@intel.com>
commit
96045de5b1e64969513c05f103d2db0d63c43b83
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date: Fri Apr 15 22:58:54 2011 +0530
mid_pmu: change function name read_all_lss_states
read_all_lss_states reads the current runtime_pm status of
each SCU mapped pci driver and updates the current_status
on to the corresponding LSS.
The name leads to confusion since it implies reading of LSS
regs which is not the case.
Hence changing the name to update_all_lss_states
Change-Id: I4f87b6e62f619db6ae07538a5a88ca70bf47c6aa
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit
5d31bc498ade6f0ae46dad8298005724a0927ae2
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date: Thu Apr 14 00:05:28 2011 +0530
[HSD:3743029] mid_pmu: hack: fix HSI lss not found in pci_table issue
HSI drivers D0ix requested were not propogated to SCU
on examination it was found that IA fw does not have
the required driver to LSS mapping, hence the requests
were skipped in PMU driver.
Added a hack to fix this in PMU driver, revert this
once IA FW fixes this issue.
Change-Id: Iff5be2fa6a46dbd94dee787011b79ec347dcbaf3
Signed-off-by: Illyas mansoor <illyas.mansoor@intel.com>
commit
18a41ce2756933e6200e05283e3ea172c7aa320d
Author: Pierre Tardy <pierre.tardy@intel.com>
Date: Thu Apr 21 17:51:38 2011 +0200
REVERTME:mid_pmu: disable s0i3 by default for HSI IFWIs
HSI runtime_pm is not yet ready.
device will go s0i3 even if there is HSI activity
This causing lot of fabric errors.
We disable s0i3 by default if we find HSI device (0x833)
in the pci table.
to be reverted as soon as HSI runtime_pm is ready.
Change-Id: I9877c48ea78f0ea80528869ce978fb575385e621
Signed-off-by: Pierre Tardy <pierre.tardy@intel.com>
commit
16a0bab0a9b9ae6cbcc4ec826315ef1d87cdc25d
Author: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
Date: Thu Apr 7 15:01:02 2011 +0530
mid_pmu: enable full suspend to RAM (S3) (path#1)
Enabling full suspend path in the pmu driver.
use IRQF_NO_SUSPEND to keep irq alive during s3 path
while we are at it removed unused irq parameter
Changed the s0i3 wake lock in a timed wake lock for wakeup.
This wakelocks stays locked until someone writes
echo "s3s3" >/sys/modules/mid_pmu/parameters/s0ix
So that system will still default to s0i3 until s3 is
ready for everybody
this patch also updates the s3 statistics.
Change-Id: Ic496f3d96e70e9d37370413d9019e9a451d1b9c6
Signed-off-by: Vishwesh M. Rudramuni <vishwesh.m.rudramuni@intel.com>
Signed-off-by: Pierre Tardy <pierre.tardy@intel.com>
commit
1ec1299dd7c6854d9902640592003ec508f53bfc
Author: Pierre Tardy <pierre.tardy@intel.com>
Date: Tue Apr 12 10:52:43 2011 +0200
mid_pmu: add more powerfull s0ix statistics
Current statistics only do s0ix entry count
This adds timing statistics.
This is mainly intended for automated tests, in order to make
automated test have time spend in s0ix, and be able to do regressions
over daily builds.
There is also placeholder for s3 statistics that is not yet implemented.
Change-Id: Ib2eed8e87f66c4efe8ca52767a76021576040333
Signed-off-by: Pierre Tardy <pierre.tardy@intel.com>
commit
bdb518ae8e9af2a27857cad22b6650b0bd20d9c8
Author: Pierre Tardy <pierre.tardy@intel.com>
Date: Fri Apr 8 17:26:27 2011 +0200
mid_pmu: suspend devices not in pci-table
We suspend devices that are in the target config, and that are
not in the pci table
Some devices are indeed not advertised in pci
table for certain firmwares. This is the case for HSI firmwares,
SPI3 device is not advertised, and would then prevent s0i3.
Change-Id: I319fcb8fe6ee3fa4a8272d2f2389aa4804a99699
Signed-off-by: Pierre Tardy <pierre.tardy@intel.com>
commit
09bfcd007dd40dcead807525203baffe1371bb41
Author: Pierre Tardy <pierre.tardy@intel.com>
Date: Wed Mar 2 18:35:03 2011 +0100
mid_pmu/android: take a wakelock if s0i3 is not possible
Change-Id: Icc3b1509873d76ad8afb63f04a8e52025c6c5c10
commit
3452915bdf4a946d0b969e646f00f2205a3b71b2
Author: Liu, ShuoX <shuox.liu@intel.com>
Date: Tue Mar 15 11:37:26 2011 +0800
modify s0ix default val for s0i3 debug
Change-Id: I9ca88d1420768702b6550039d8313b61dafc5788
commit
cfda66e44bc142f836c2e550211997759aa0d8e2
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date: Wed Mar 30 16:23:28 2011 +0530
mid_pmu: cleanup added explicit LSS ids for s0ix entry
Currently the LSS that need to be checked for S0ix/LPMP3
entry is hardcoded making it difficult to read the sub
system values.
Added #defines for all the sub system LSS id's, using this
defined the target config values to check against the SSS
register values, that tells which subsystems need to in D0i3
to issue S0i1/3 or LPMP3 commands.
Also added a way to keep always ON LSS to be in D0i0.
Added check for Keyboard, UART0/1/2 LSS in S0i1/lpmp3/S0i3 SSS
config registers.
Removed LSS 40, 41 from ignore_lss list.
Change-Id: Ifd28b58f11c66232dc2993b3946c672bbe9931a3
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit
4e082fe683a0d9b22b9ef0c6675705ba75a7dceb
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date: Wed Mar 30 16:22:21 2011 +0530
mid_pmu: update current driver status during first interactive command
At the time of pmu driver initialization we set all the LSS to be in D0i0
state, this causes some of the drivers to be in forced D0i0 state in
SCU, whereas there actual state could be D0i3, hence there could be
potential power impact until next cycle of D0i0->D0i3 from the driver.
To avoid this we acquire the lock, allow drivers to get blocked in
pmu_pci_set_power_state(), then reflect the current driver state in
SCU for all SCU managed drivers via setting the appropriate LSS values
by issuing interactive command.
This will ensure we reflect correct driver state during pmu driver
initialization.
Change-Id: I01caf76d6a32b38a556e7309457ab0e829b5dca4
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit
a1e3d9fd3db6a395f9f45a233fc4a757e610700c
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date: Wed Mar 30 16:21:47 2011 +0530
mid_pmu: added some counters
Added counter to keep track of number of S0ix
and error counts.
Change-Id: I20d55781038a4732e50f98e0163eada394450702
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit
37c03045efcd790183acdbd3cb94db59566bdb6d
Author: Pierre Tardy <pierre.tardy@intel.com>
Date: Mon Mar 21 14:47:53 2011 +0100
mid_pmu: allow several devices to be on the same lss
HSU devices are in HW in the same lss.
There is a workaround in IAFW, that will not advertise the correct lss
for HSU0 and HSU1. This does not solve anything, as HSU0 driver will start
to make fabric errors as soon as HSU2 is suspended.
We generically solve the issue by maintaining a table of devices
present in the same lss. For such very short list, we do not take the
overhead of using linked list. but rather use a 4 slots table for each lss.
This patch contains ss hardcode for HSU0 and HSU1. To be removed when
IAFW remove the bad workaround.
Change-Id: I11240c225edc92984cca7e5e176bbebab6df2d5d
Signed-off-by: Pierre Tardy <pierre.tardy@intel.com>
commit
aa7111008d6f823807dd117b4384ba66415eff40
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date: Fri Mar 18 12:10:59 2011 +0530
mid_pmu: hack: replace lss 16 with 9
IA FW is reporting Audio DMA subsytem id as 16, whereas it should report 9
fixed this in the code, need to remove this once IA FW fixes this.
Change-Id: I22b6bc9e425b43dae00233fd43b7bcf756c62c8b
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit
feef0283493d0309bcf6c2021807e0150dc079d9
Author: Yanmin Zhang <yanmin.zhang@intel.com>
Date: Tue Mar 8 16:18:49 2011 +0800
Add a new interface under debugfs, pmu_sss_states, to output pmu sss registers. We could use it to check every subsystem state. mid_pmu_states saves device (subsystem) states intercepted by pci_set_power_state, while pmu_sss_states gets the states from pmu hardware registers.
Change-Id: If0d9cb3b4286d1ea89064d9b94df29ed1ae2f7fa
commit
fb7d10c9d7ba74245c1e14b739d207c920dab637
Author: mgross <mark.gross@intel.com>
Date: Thu Mar 3 10:34:48 2011 +0800
revert me asap block suspend to ram with wakelock
Change-Id: I89812515397690f6dc99446a0f04c15bf2ac567e
Signed-off-by: mgross <mark.gross@intel.com>
commit
0d15acc903de50173abffbc8e7830749e46c4ef6
Author: mgross <mark.gross@intel.com>
Date: Mon Feb 28 15:18:46 2011 -0800
Stub to enable pm_suspend and android early suspend calls to start
working.
With this change (and the propper config file) you can enter early
suspend and start enabling android power managment.
Change-Id: I80c10a33f8fc80221502761175ed372a379ae779
commit
0c2cb76662387a575c6f41b9f91a85cd76064f55
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date: Sat Feb 5 14:52:41 2011 +0100
mid_pmu: cleanup: fix sparse check warnings
moved all #defines to mid_pmu.h
fixed warnings after installing sparse tool
Fixed the following warnings from sparse.
with make C=2 >& sparse.log command.
arch/x86/kernel/mid_pmu.c:46:3: warning: symbol 'pci_dev_index' was not declared. Should it be static?
arch/x86/kernel/mid_pmu.c:1175:70: warning: incorrect type in argument 2 (different address spaces)
arch/x86/kernel/mid_pmu.c:1175:70: expected void volatile [noderef] <asn:2>*addr
arch/x86/kernel/mid_pmu.c:1175:70: got unsigned int *
arch/x86/kernel/mid_pmu.c:1180:76: warning: incorrect type in argument 2 (different address spaces)
arch/x86/kernel/mid_pmu.c:1180:76: expected void volatile [noderef] <asn:2>*addr
arch/x86/kernel/mid_pmu.c:1180:76: got unsigned int *
arch/x86/kernel/mid_pmu.c:322:5: warning: symbol 'get_target_platform_state' was not declared. Should it be static?
arch/x86/kernel/mid_pmu.c:691:6: warning: symbol 'mfld_s0i1_enter' was not declared. Should it be static?
arch/x86/kernel/mid_pmu.c:717:5: warning: symbol 'mfld_s0i3_enter' was not declared. Should it be static?
arch/x86/kernel/mid_pmu.c:844:5: warning: symbol 'is_msi_enabled' was not declared. Should it be static?
arch/x86/kernel/mid_pmu.c:1191:59: got unsigned int *
arch/x86/kernel/mid_pmu.c:1502:13: warning: incorrect type in assignment (different address spaces)
arch/x86/kernel/mid_pmu.c:1502:13: expected struct mrst_pmu_reg *pmu
arch/x86/kernel/mid_pmu.c:1502:13: got void [noderef] <asn:2>*
arch/x86/kernel/mid_pmu.c:1567:27: expected void [noderef] <asn:2>*<noident>
arch/x86/kernel/mid_pmu.c:1567:27: got struct mrst_pmu_reg *static [toplevel] *<noident>
...
and similar warnings.
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit
cf3aa8b17adab4006d49f01aa66bd184f9598eb8
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date: Fri Feb 4 01:12:34 2011 +0100
mid_pmu: wait for interactive command complete in pmu_init
At the time of pmu_init we set all the LSS's into D0i0 mode
by sending an interactive command. This command was not
waiting for interactive complete semaphore that is released
from pmu interrupt handler.
Also interrupt handler was registered after pmu_init, which
should be the otherway.
This will ensure the interrupt handler is registered before
calling pmu_init and also after interactive command is sent
in pmu_init() we wait for interactive command complete semaphore.
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit
9d8e0e6094afb88033a3e85cb92e905a8f87cb60
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date: Fri Feb 4 00:14:00 2011 +0100
mid_pmu: wake source counter statistics
We need a way to tell which logical subsystem woke up from S0i3
Wake status register provides this information.
We provide a way to capture how many times each LSS
woke up the system from S0i3, by reading Wake status
register and incrementing a counter for each LSS.
This is printed as part of /sys/kernel/debug/mid_pmu_states
Signed-off-by: Pierre Tardy <pierre.tardy@intel.com>
Acked-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit
54c94eb1ef0d810458a6d4b3b558a356fce54493
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date: Mon Jan 31 04:22:59 2011 +0100
mid_pmu: clear cpu offload cntrl reg in error scenarios
For S0i3 case we need to set the offload cntrl reg to copy the contents
of IA C6 SRAM to SC always on SRAM. In case of error if S0i3 fails for
some reason, or on S0ix successful completion this bit needs to be cleared.
We ensure it's set during S0i3 entry and is cleared in interrupt handler.
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit
98cb52baaeb1c7d058ec3a12db943f7c60918605
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date: Fri Jan 28 05:37:37 2011 +0100
mid_pmu: bug fix: change lpmp3 command value
For LPMP3, trigger must be based on "core must be idle" (cmbi)
and not just C6. Hence LPMP3 was breaking.
After setting cmbi bit as the trigger, LPMP3 usecase works.
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit
4908f77de188bae7b61b39113747eef2f2bd9b83
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date: Fri Jan 28 05:36:18 2011 +0100
mid_pmu: disable scu semaphore watchdog by default
SCU semaphore watchdog is getting triggered with 500ms
timeout value, because of which we see synchronization
issues, providing an option to selectively enabling it.
By default disabled.
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit
8e35a33d7754c82fb89e48d25ff3988e4cc03977
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date: Thu Jan 27 03:38:19 2011 +0100
mid_pmu: bug fix: fixed device lss reporting lss0 wrongly
The MSB of "logical subsystem" byte tells if the device is managed
by SCU, the MSB was not being checked before getting the LSS
values.
This was causing drivers that were not part of SCU getting
LSS value '0'
By checking the MSB of "logical sub sytemid" byte from PCI config
we will get to know if this driver actually belongs to SCU, and
hence avoid multiple drivers with LSS value 0.
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit
33d19d30ff22685f18f184183b1e675d8fe94fea
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date: Mon Jan 17 08:22:32 2011 +0100
mid_pmu: driver that controls pmus of intel_mid platforms
Mobile Internet Devices based on the Intel "Medfield" platform have two
Platform Management Units (PMU). The first PMU (pmu1) comprises of the
Silverthorne CPU, Graphics, Video encode/decode and Display engines,
The second PMU (pmu2) is the IO hub.
The Platform Management Unit (PMU) driver is a Medfield-specific power
management driver. Intel's MID provides fine tuned knobs for
platform level. Intel's Medfield MID provides control for platform
level power management and the OS Power Management solution guides the
power states that the subsystems and CPU needs to be in depending on the
current usage and power policy set by the user.
The purpose of the Medfield Power Management architecture is to turn
off subsystems without affecting the end user functionality/usability of
the system.
The Power Management scheme uses the concept of operating modes, which
define the configuration of all the subsystems under each of the usage model
that the user might put the system in. Based on current platform usage,
OSPM decides the target power states for the sub systems, and the PMU
driver implements the OS-HW interface.
"Intel" Medfield PMU driver interfaces with two power management units
(PMU) pmu1 & pmu2. On receiving commands PMU driver interfaces
with the pmu1 & pmu2 via a well defined register interface to drive the
required power management flows.
This patch contains:
- key definitions for the PMU driver.
- core logic of the PMU driver as it interfaces with pmu1 & pmu2 for
different platform power management flows.
Signed-off-by: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
Signed-off-by: Rajeev D Muralidhar <rajeev.d.muralidhar@intel.com>
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
Len Brown [Fri, 12 Aug 2011 21:43:35 +0000 (22:43 +0100)]
TEST mfld pmu: add arch/x86/platform/mfld/pmu.h
from UMG 2.6.35 tree: arch/x86/kernel/mid_pmu.h
commit
1df781ef9bbc9b0fc453537da2a3b1861f363138
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date: Thu Jun 23 04:58:43 2011 +0530
mid_pmu: sparse warnings fixed
BZ: 3856
Fixed the following sparse warnings.
arch/x86/kernel/mid_pmu.c:302:18: warning: symbol 'pmu_wake_lock' was not declared. Should it be static?
arch/x86/kernel/mid_pmu.c:1126:15: warning: symbol 'pmu_get_cstate' was not declared. Should it be static?
arch/x86/kernel/mid_pmu.c:1813:3: warning: symbol 'medfield_lsses' was not declared. Should it be static?
arch/x86/kernel/mid_pmu.c:1874:5: warning: symbol 'medfield_lsses_num' was not declared. Should it be static?
arch/x86/kernel/mid_pmu.c:1876:6: warning: symbol 'lss_device_status' was not declared. Should it be static?
arch/x86/kernel/mid_pmu.c:2368:5: warning: symbol 'mid_suspend' was not declared. Should it be static?
fixed make namespacecheck issues.
Change-Id: I7731a0391b1433a7ecfa28bdd3265591d1389495
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit
5e73c57d106f8c766a5a06221e2817a7c9a5b393
Author: Rajesh Poornachandran <rajesh.poornachandran@intel.com>
Date: Thu Jun 16 16:59:39 2011 -0700
Revert "Revert "mid_pmu: Moving NC power management logic to OSPM""
BZ: 1957
Currently the PM for north complex was done independently by Gfx and ISP drivers.
There was no synchronization between ISP and Gfx while sending the PM cmd.
OSPM patch to provide an API, pmu_nc_set_power_state. This API will take care
of talking to P-unit and getting the corresponding power islands to ON/OFF.
Gfx and ISP drivers need to use this API in their drivers.
Change-Id: I628dd8b03f5d09607e3c931e29943fcdb73613cb
Signed-off-by: Sujith Thomas <sujith.thomas@intel.com>
Signed-off-by: Rajesh Poornachandran <rajesh.poornachandran@intel.com>
commit
dd6db50f98b6c0d368b9315124b65ec3b1aae2a1
Author: Erwan Mahe <erwanx.mahe@intel.com>
Date: Thu Jun 23 18:29:21 2011 +0200
Revert "Revert "mid_pmu: pick correct D0ix states in choose_state""
BZ: 2102
This reverts commit
41ff42ea4b74c89d7ed44b51e46ab7ae45b4b87c.
Change-Id: I5aa5658cf28696a3c79a939ea8644a3b3c4d73f0
commit
41ff42ea4b74c89d7ed44b51e46ab7ae45b4b87c
Author: Marie-Celine Dubut <marie.celinex.dubut@intel.com>
Date: Wed Jun 22 12:44:06 2011 +0200
Revert "mid_pmu: pick correct D0ix states in choose_state"
BZ 2102
This reverts commit
c60a2ae1f8b33abdabbff9c0de5a57ec6588df9d.
Change-Id: I7e7aed5071adabc824c303628ba855031892e70a
commit
c60a2ae1f8b33abdabbff9c0de5a57ec6588df9d
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date: Wed Jun 1 13:19:54 2011 +0530
mid_pmu: pick correct D0ix states in choose_state
BZ: 2102
currently pmu_pci_choose_state return PCI_D3hot for all devices.
For some of devices, it may not be possible to support PCI_D3hot state.
eg., HSU needs to be put in D0i1, chaabi needs to be put in
D0i2. It is not appropriate to always choose D0i3 for all devices
We choose the correct state that is appropriate for each device
for the platform.
This patch should be used only with a FW that is capable of supporting
Chaabi D0i2.
Change-Id: Ief7b64bc1ec37d4452ce3222454bdd6102d54c10
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit
c4e73f14acb7ffd39a5d965fc23b1f01673363b8
Author: Hari Kanigeri <hari.k.kanigeri@intel.com>
Date: Fri Jun 3 11:27:13 2011 -0600
mid_pmu: fix checkpatch violations and some cleanup in exit paths
BZ: 3066
Fix the following:
1. Checkpatch violations and cosmetic changes.
2. fix correct cleanup in the exit paths of the function mid_pmu_probe
Below log is related to checkpatch violations.
1. Checkpatch violations
=========================
ERROR: space required before the open parenthesis '('
+ if(pdev->device == 0x81c || pdev->device == 0x81b)
WARNING: line over 80 characters
+ for (i = 0; i < PMU_MAX_LSS_SHARE && intel_mid_pci_devices[index].dev_driver[i]; i++) {}
ERROR: trailing statements should be on next line
+ for (i = 0; i < PMU_MAX_LSS_SHARE && intel_mid_pci_devices[index].dev_driver[i]; i++) {}
WARNING: braces {} are not necessary for single statement blocks
+ for (i = 0; i < PMU_MAX_LSS_SHARE && intel_mid_pci_devices[index].dev_driver[i]; i++) {}
WARNING: line over 80 characters
+static pci_power_t pmu_pci_get_weakest_state_for_lss(int lss_index, struct pci_dev *pdev, pci_power_t state)
<cut here for brewity, please run checkpatch to see a complete list>
total: 122 errors, 14 warnings, 2340 lines checked
Change-Id: I1cdbd6a8b70d303611f0cd426ce63235010d0a07
Signed-off-by: Hari Kanigeri <hari.k.kanigeri@intel.com>
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit
d332d4a59c01e1774cd4fdc28d97fe4d865989ee
Author: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
Date: Thu Feb 16 22:36:00 2006 +0530
pmu: adding atomisp as part of entry criterion for S0i3
BZ: 1339
In current build we dont look at the isp runtime status before
we enter S0i3 state. In this patch we check for the camera status
in addition to all other device states that we check today in S0i3.
Change-Id: If3f024fa22d0d744160b961e637e2b1c25e5e1c9
Signed-off-by: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
commit
53f93b022da79eadc22a2ac5c3adade98380cf84
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date: Mon May 16 00:26:13 2011 +0530
mid_pmu: demote c6 to c4 while s0ix is in progress
BZ: 2120
While S0ix aborts SCU waits for Ack_C6 timeout, IA comes out of
mwait and since the SCU is still waiting for Ack_C6 the S0ix
ACK_C6 timeout error interrupt is not recieved, meanwhile a new
C6 could be triggered from IA and this could trigger a Ack_C6
SCU can mistake this Ack_C6 as a ack for the previously aborted
S0ix and continue S0ix flow. This is not correct.
We check if the system is in S0ix progress state by checking
scu_ready_sem if its already acquired that means S0ix is in
progress and the subsequent C6 should be demoted to C4's
Change-Id: I1b60824b28f9b6579dd551faa8fe485d2074b712
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit
654da78fa8f45bcf4d64d9c0ea115d589f4374c4
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date: Sun May 15 23:44:23 2011 +0530
mid_pmu: c6 offload msr bit cleanup
BZ: 2116
We were using magic number for wmsr(0x120) for setting/clearing
offload bit.
Fixed this by creating #defines
Change-Id: I5fe4ec0568e48d12fe30074f8eebbc2a6411b4d8
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit
8118849a0329d0e73761562443ae25c8b1cd3bf9
Author: Fengwei Yin <fengwei.yin@intel.com>
Date: Sun May 22 11:57:12 2011 +0800
Revert "mid_pmu: Moving NC power management logic to OSPM"
BZ: 2470
This reverts commit
594c7f0327dd02985fbcde1e0bd83c98e684097f.
commit
594c7f0327dd02985fbcde1e0bd83c98e684097f
Author: Sujith Thomas <sthoma3@umg-lab1.iind.intel.com>
Date: Thu May 12 10:51:38 2011 +0530
mid_pmu: Moving NC power management logic to OSPM
BZ: 1957
Currently the PM for north complex was done independently by Gfx and ISP drivers.
There was no synchronization between ISP and Gfx while sending the PM cmd.
OSPM patch to provide an API, pmu_nc_set_power_state.
This API will take care of talking to P-unit and getting the corresponding power
islands to ON/OFF. Gfx and ISP drivers need to use this API in their drivers.
Change-Id: I302c9a7a6bb10ae572d340affb2502443d6178fc
Signed-off-by: Sujith Thomas <sujith.thomas@intel.com>
commit
cba613f2bde66236706b9c0ba7f1fe6b5ff14ad7
Author: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
Date: Tue May 10 16:22:10 2011 +0530
pmu: renaming lss after new wkc implementation in scu
BZ 1756
This patch we are re assigning some of the lss to new lss
based on the WKC implementation in scu.
Change-Id: Ic7a9adf37194182b424dcdcc0d61cb09bba4a7a5
Signed-off-by: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
commit
821d3f9513a5126201531e804c98b3618456d637
Author: Jean-Pierre Stierlin <jean-pierrex.stierlin@intel.com>
Date: Thu May 5 18:19:43 2011 +0200
OSPM: Add HSI as wake source in s0i3
BZ: 1705
HSI wake event was disabled in SCU configuration
Revert a hack to disable HSI wake event to the SCU due to spurious interrupts.
Change-Id: I2e9173fdf79fa158394a4b0b5894f643d3a43b8f
commit
cfda66e44bc142f836c2e550211997759aa0d8e2
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date: Wed Mar 30 16:23:28 2011 +0530
mid_pmu: cleanup added explicit LSS ids for s0ix entry
Currently the LSS that need to be checked for S0ix/LPMP3
entry is hardcoded making it difficult to read the sub
system values.
Added #defines for all the sub system LSS id's, using this
defined the target config values to check against the SSS
register values, that tells which subsystems need to in D0i3
to issue S0i1/3 or LPMP3 commands.
Also added a way to keep always ON LSS to be in D0i0.
Added check for Keyboard, UART0/1/2 LSS in S0i1/lpmp3/S0i3 SSS
config registers.
Removed LSS 40, 41 from ignore_lss list.
Change-Id: Ifd28b58f11c66232dc2993b3946c672bbe9931a3
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit
885ebc4f559cdaa19b3dddd02faa2dba246ae689
Author: Sundar Iyer <sundar.iyer@intel.com>
Date: Tue Mar 22 15:03:51 2011 +0530
mid_pmu: correct D0ix states during S0i3
Enable the UART0/1/2 and the KBD modules to be put into D0i3 states
during the S0i3.
Change-Id: Idec4907699ba23506900a249a130cecaed85dc82
Signed-off-by: Sundar Iyer <sundar.iyer@intel.com>
commit
56ab6e9474f2e04f50ddede8f2b6db9e1dc852c1
Author: Sundar Iyer <sundar.iyer@intel.com>
Date: Wed Mar 9 13:19:29 2011 +0530
mid_pmu: correct USB Dx state during S0i3 entry
Enable D0i3 state for the USB during S0i3 entry. Making this
change realizes power figures for the USB rail from ~16mW to ~.4mW
Signed-off-by: Sundar Iyer <sundar.iyer@intel.com>
commit
0c2cb76662387a575c6f41b9f91a85cd76064f55
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date: Sat Feb 5 14:52:41 2011 +0100
mid_pmu: cleanup: fix sparse check warnings
moved all #defines to mid_pmu.h
fixed warnings after installing sparse tool
Fixed the following warnings from sparse.
with make C=2 >& sparse.log command.
arch/x86/kernel/mid_pmu.c:46:3: warning: symbol 'pci_dev_index' was not declared. Should it be static?
arch/x86/kernel/mid_pmu.c:1175:70: warning: incorrect type in argument 2 (different address spaces)
arch/x86/kernel/mid_pmu.c:1175:70: expected void volatile [noderef] <asn:2>*addr
arch/x86/kernel/mid_pmu.c:1175:70: got unsigned int *
arch/x86/kernel/mid_pmu.c:1180:76: warning: incorrect type in argument 2 (different address spaces)
arch/x86/kernel/mid_pmu.c:1180:76: expected void volatile [noderef] <asn:2>*addr
arch/x86/kernel/mid_pmu.c:1180:76: got unsigned int *
arch/x86/kernel/mid_pmu.c:322:5: warning: symbol 'get_target_platform_state' was not declared. Should it be static?
arch/x86/kernel/mid_pmu.c:691:6: warning: symbol 'mfld_s0i1_enter' was not declared. Should it be static?
arch/x86/kernel/mid_pmu.c:717:5: warning: symbol 'mfld_s0i3_enter' was not declared. Should it be static?
arch/x86/kernel/mid_pmu.c:844:5: warning: symbol 'is_msi_enabled' was not declared. Should it be static?
arch/x86/kernel/mid_pmu.c:1191:59: got unsigned int *
arch/x86/kernel/mid_pmu.c:1502:13: warning: incorrect type in assignment (different address spaces)
arch/x86/kernel/mid_pmu.c:1502:13: expected struct mrst_pmu_reg *pmu
arch/x86/kernel/mid_pmu.c:1502:13: got void [noderef] <asn:2>*
arch/x86/kernel/mid_pmu.c:1567:27: expected void [noderef] <asn:2>*<noident>
arch/x86/kernel/mid_pmu.c:1567:27: got struct mrst_pmu_reg *static [toplevel] *<noident>
...
and similar warnings.
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit
33d19d30ff22685f18f184183b1e675d8fe94fea
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date: Mon Jan 17 08:22:32 2011 +0100
mid_pmu: driver that controls pmus of intel_mid platforms
Mobile Internet Devices based on the Intel "Medfield" platform have two
Platform Management Units (PMU). The first PMU (pmu1) comprises of the
Silverthorne CPU, Graphics, Video encode/decode and Display engines,
The second PMU (pmu2) is the IO hub.
The Platform Management Unit (PMU) driver is a Medfield-specific power
management driver. Intel's MID provides fine tuned knobs for
platform level. Intel's Medfield MID provides control for platform
level power management and the OS Power Management solution guides the
power states that the subsystems and CPU needs to be in depending on the
current usage and power policy set by the user.
The purpose of the Medfield Power Management architecture is to turn
off subsystems without affecting the end user functionality/usability of
the system.
The Power Management scheme uses the concept of operating modes, which
define the configuration of all the subsystems under each of the usage model
that the user might put the system in. Based on current platform usage,
OSPM decides the target power states for the sub systems, and the PMU
driver implements the OS-HW interface.
"Intel" Medfield PMU driver interfaces with two power management units
(PMU) pmu1 & pmu2. On receiving commands PMU driver interfaces
with the pmu1 & pmu2 via a well defined register interface to drive the
required power management flows.
This patch contains:
- key definitions for the PMU driver.
- core logic of the PMU driver as it interfaces with pmu1 & pmu2 for
different platform power management flows.
Signed-off-by: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
Signed-off-by: Rajeev D Muralidhar <rajeev.d.muralidhar@intel.com>
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
Len Brown [Fri, 12 Aug 2011 21:43:16 +0000 (22:43 +0100)]
TEST mfld pmu: add include/linux/intel_mid_pm.h -- for now
needed to compile mfld pmu driver
from UMG 2.6.35 tree:
commit
1df781ef9bbc9b0fc453537da2a3b1861f363138
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date: Thu Jun 23 04:58:43 2011 +0530
mid_pmu: sparse warnings fixed
BZ: 3856
Fixed the following sparse warnings.
arch/x86/kernel/mid_pmu.c:302:18: warning: symbol 'pmu_wake_lock' was not declared. Should it be static?
arch/x86/kernel/mid_pmu.c:1126:15: warning: symbol 'pmu_get_cstate' was not declared. Should it be static?
arch/x86/kernel/mid_pmu.c:1813:3: warning: symbol 'medfield_lsses' was not declared. Should it be static?
arch/x86/kernel/mid_pmu.c:1874:5: warning: symbol 'medfield_lsses_num' was not declared. Should it be static?
arch/x86/kernel/mid_pmu.c:1876:6: warning: symbol 'lss_device_status' was not declared. Should it be static?
arch/x86/kernel/mid_pmu.c:2368:5: warning: symbol 'mid_suspend' was not declared. Should it be static?
fixed make namespacecheck issues.
Change-Id: I7731a0391b1433a7ecfa28bdd3265591d1389495
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit
0704c9bfd967b44da1e61a05f8789052bc6fbd29
Author: Sujith Thomas <sujith.thomas@intel.com>
Date: Wed May 25 14:55:42 2011 +0530
mid_pmu: Defining the OSPM macros to handle CONFIG_INTEL_MID_PM disabled
BZ: 1957
Currently the OSPM macros are not defined during CONFIG_INTEL_MID_PM disabled.
This is breaking the compilation in Gfx and ISP drivers whenc CONFIG_PM is disabled.
Now the OSPM macros are defined irrespective of CONFIG_INTEL_MID_PM flag.
Change-Id: I6cf6185d712b728e5733c473d8a2947c36c62e03
Signed-off-by: Sujith Thomas <sujith.thomas@intel.com>
commit
5e73c57d106f8c766a5a06221e2817a7c9a5b393
Author: Rajesh Poornachandran <rajesh.poornachandran@intel.com>
Date: Thu Jun 16 16:59:39 2011 -0700
Revert "Revert "mid_pmu: Moving NC power management logic to OSPM""
BZ: 1957
Currently the PM for north complex was done independently by Gfx and ISP drivers.
There was no synchronization between ISP and Gfx while sending the PM cmd.
OSPM patch to provide an API, pmu_nc_set_power_state. This API will take care
of talking to P-unit and getting the corresponding power islands to ON/OFF.
Gfx and ISP drivers need to use this API in their drivers.
Change-Id: I628dd8b03f5d09607e3c931e29943fcdb73613cb
Signed-off-by: Sujith Thomas <sujith.thomas@intel.com>
Signed-off-by: Rajesh Poornachandran <rajesh.poornachandran@intel.com>
commit
53f93b022da79eadc22a2ac5c3adade98380cf84
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date: Mon May 16 00:26:13 2011 +0530
mid_pmu: demote c6 to c4 while s0ix is in progress
BZ: 2120
While S0ix aborts SCU waits for Ack_C6 timeout, IA comes out of
mwait and since the SCU is still waiting for Ack_C6 the S0ix
ACK_C6 timeout error interrupt is not recieved, meanwhile a new
C6 could be triggered from IA and this could trigger a Ack_C6
SCU can mistake this Ack_C6 as a ack for the previously aborted
S0ix and continue S0ix flow. This is not correct.
We check if the system is in S0ix progress state by checking
scu_ready_sem if its already acquired that means S0ix is in
progress and the subsequent C6 should be demoted to C4's
Change-Id: I1b60824b28f9b6579dd551faa8fe485d2074b712
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
commit
8118849a0329d0e73761562443ae25c8b1cd3bf9
Author: Fengwei Yin <fengwei.yin@intel.com>
Date: Sun May 22 11:57:12 2011 +0800
Revert "mid_pmu: Moving NC power management logic to OSPM"
BZ: 2470
This reverts commit
594c7f0327dd02985fbcde1e0bd83c98e684097f.
commit
594c7f0327dd02985fbcde1e0bd83c98e684097f
Author: Sujith Thomas <sthoma3@umg-lab1.iind.intel.com>
Date: Thu May 12 10:51:38 2011 +0530
mid_pmu: Moving NC power management logic to OSPM
BZ: 1957
Currently the PM for north complex was done independently by Gfx and ISP drivers.
There was no synchronization between ISP and Gfx while sending the PM cmd.
OSPM patch to provide an API, pmu_nc_set_power_state.
This API will take care of talking to P-unit and getting the corresponding power
islands to ON/OFF. Gfx and ISP drivers need to use this API in their drivers.
Change-Id: I302c9a7a6bb10ae572d340affb2502443d6178fc
Signed-off-by: Sujith Thomas <sujith.thomas@intel.com>
commit
4d0d20d8deda873a1e027ec2710675f58d2e9c7a
Author: Rajesh Poornachandran <rajesh.poornachandran@intel.com>
Date: Thu May 5 10:01:30 2011 -0700
GFX/PM: Export GFX APIs to power-gate NC IPs.
BZ: 791
Export GFX APIs (ospm_power_island_up/down) to be used by GFX, Video & Camera driver to power-gate NC IPs.
Change-Id: Iadbc9513bf90df952063ef148245fbcf6d451dd7
Signed-off-by: Rajesh Poornachandran <rajesh.poornachandran@intel.com>
commit
37c03045efcd790183acdbd3cb94db59566bdb6d
Author: Pierre Tardy <pierre.tardy@intel.com>
Date: Mon Mar 21 14:47:53 2011 +0100
mid_pmu: allow several devices to be on the same lss
HSU devices are in HW in the same lss.
There is a workaround in IAFW, that will not advertise the correct lss
for HSU0 and HSU1. This does not solve anything, as HSU0 driver will start
to make fabric errors as soon as HSU2 is suspended.
We generically solve the issue by maintaining a table of devices
present in the same lss. For such very short list, we do not take the
overhead of using linked list. but rather use a 4 slots table for each lss.
This patch contains ss hardcode for HSU0 and HSU1. To be removed when
IAFW remove the bad workaround.
Change-Id: I11240c225edc92984cca7e5e176bbebab6df2d5d
Signed-off-by: Pierre Tardy <pierre.tardy@intel.com>
commit
33d19d30ff22685f18f184183b1e675d8fe94fea
Author: Illyas Mansoor <illyas.mansoor@intel.com>
Date: Mon Jan 17 08:22:32 2011 +0100
mid_pmu: driver that controls pmus of intel_mid platforms
Mobile Internet Devices based on the Intel "Medfield" platform have two
Platform Management Units (PMU). The first PMU (pmu1) comprises of the
Silverthorne CPU, Graphics, Video encode/decode and Display engines,
The second PMU (pmu2) is the IO hub.
The Platform Management Unit (PMU) driver is a Medfield-specific power
management driver. Intel's MID provides fine tuned knobs for
platform level. Intel's Medfield MID provides control for platform
level power management and the OS Power Management solution guides the
power states that the subsystems and CPU needs to be in depending on the
current usage and power policy set by the user.
The purpose of the Medfield Power Management architecture is to turn
off subsystems without affecting the end user functionality/usability of
the system.
The Power Management scheme uses the concept of operating modes, which
define the configuration of all the subsystems under each of the usage model
that the user might put the system in. Based on current platform usage,
OSPM decides the target power states for the sub systems, and the PMU
driver implements the OS-HW interface.
"Intel" Medfield PMU driver interfaces with two power management units
(PMU) pmu1 & pmu2. On receiving commands PMU driver interfaces
with the pmu1 & pmu2 via a well defined register interface to drive the
required power management flows.
This patch contains:
- key definitions for the PMU driver.
- core logic of the PMU driver as it interfaces with pmu1 & pmu2 for
different platform power management flows.
Signed-off-by: Vishwesh M Rudramuni <vishwesh.m.rudramuni@intel.com>
Signed-off-by: Rajeev D Muralidhar <rajeev.d.muralidhar@intel.com>
Signed-off-by: Illyas Mansoor <illyas.mansoor@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
Len Brown [Fri, 12 Aug 2011 21:42:29 +0000 (22:42 +0100)]
TEST mrst idle: update to latest MRST idle code
replace:
arch/x86/kernel/platform/mrst/pmu.c
arch/x86/kernel/platform/mrst/pmu.h
drivers/idle/intel_idle.c (also: sync w/ 3.1, retain penwell entry)
mrst_s0i3.c, mrst_s0i3_asm.S
minor associated changes:
arch/x86/include/asm/mrst.h
arch/x86/kernel/smpboot.c
n.b. Actual s0i3 support is EXCLUDED from intel_idle for now
Change-Id: Ibd214229062f19a8814ef2371a05f1239758bfa3
Signed-off-by: Len Brown <len.brown@intel.com>
Fei Yang [Tue, 16 Aug 2011 20:50:36 +0000 (13:50 -0700)]
Revert "Drop pmu code from medfield gb-stable on top of linux 3.0."
cherry-pick Len Brown's PMU driver from Alan Cox's linux-3.0-mid-ref tree
This reverts commit
8b0274a0b21b27e82e532b9d7deaf0bbdf5f50b4.
Fei Yang [Wed, 27 Jul 2011 18:56:29 +0000 (11:56 -0700)]
Drop pmu code from medfield gb-stable on top of linux 3.0.
Change-Id: Ifc99ac7c2711dae585b3325a9c603bb79816c739
Signed-off-by: Fei Yang <fei.yang@intel.com>
Arjan van de Ven [Fri, 15 Jul 2011 13:39:31 +0000 (14:39 +0100)]
cpuidle: Add support for the Penwell processor to intel_idle.c
The Penwell Atom processor is very similar to the Lincroft processor
in terms of power behavior.. add the device ID.
Change-Id: Idbac8ec87b7ed42a9bc169df2d96172e7685d71f
Signed-off-by: Arjan van de Ven <arjan@linux.intel.com>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Dirk Brandewie [Fri, 15 Jul 2011 13:39:07 +0000 (14:39 +0100)]
x86: mrst: Add vrtc driver which serves as a wall clock device
Moorestown platform doesn't have a m146818 RTC device like traditional
x86 PC, but a firmware emulated virtual RTC device(vrtc), which provides
some basic RTC functions like get/set time. vrtc serves as the only
wall clock device on Moorestown platform.
[ tglx: Changed the exports to _GPL ]
Signed-off-by: Feng Tang <feng.tang@intel.com>
Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
Signed-off-by: Alan Cox <alan@linux.intel.com>
LKML-Reference: <
20101110172837.3311.40483.stgit@localhost.localdomain>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Arjan van de Ven [Fri, 15 Jul 2011 13:39:36 +0000 (14:39 +0100)]
sfi-cpufreq: remove reading the P state from the hardware
Reading the P state data from the HW MSR is actually undefined, and does
not work in various circumstances in practice. (The assumption that
you get a value back that you can match to your own table is very iffy
and not actually correct)
It's also not needed....
Change-Id: Ibb43a9b1752a858ad40fec8cadc402cf6bea2e31
Signed-off-by: Arjan van de Ven <arjan@linux.intel.com>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Arjan van de Ven [Fri, 15 Jul 2011 13:39:36 +0000 (14:39 +0100)]
sfi-cpufreq: The KConfig entry should depend on SFI not MRST
with CONFIG_X86_MRST meaning something very different now...
it's clear that the proper dependency should have been on CONFIG_SFI
Change-Id: Ie49f3d8c9734bf938a2a427448dc8826ab0f69c3
Signed-off-by: Arjan van de Ven <arjan@linux.intel.com>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Arjan van de Ven [Fri, 15 Jul 2011 13:39:31 +0000 (14:39 +0100)]
sfi-cpufreq: delete write-never read-only variable
The SFI cpufreq driver had a variable that never got initialized, but
did get printk'd...
.. which is leaking kernel memory to the user.
Since it's not used... just delete it
Change-Id: I31626b7d317d999a912c492da4242e118e3e9e1c
Signed-off-by: Arjan van de Ven <arjan@linux.intel.com>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Arjan van de Ven [Fri, 15 Jul 2011 13:39:30 +0000 (14:39 +0100)]
sfi-cpufreq.c: remove set_cpu_to_gfm() function
The set_cpu_to_gfm() function worked around a bug in a prerelease firmware;
there's no need for this sort of low level MSR banging anymore at this point
in time.... remove the code.
Change-Id: Id969642ebbee26ceb06fa726aa0c04d9aba46f2a
Signed-off-by: Arjan van de Ven <arjan@linux.intel.com>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Arjan van de Ven [Fri, 15 Jul 2011 13:39:30 +0000 (14:39 +0100)]
sfi-cpufreq.c: fix how the number of cpus is calculated
The driver used "u64" as the size of an SFI table format..
... which actually was an incorrect size.
Fix the code by using a proper sizeof()
with this fix, the right number of cpus gets detected,
and the P state code actually works!
Change-Id: I6e7911bd14eccc54b5449b9568c58d5363872fe8
Signed-off-by: Arjan van de Ven <arjan@linux.intel.com>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Arjan van de Ven [Fri, 15 Jul 2011 13:39:30 +0000 (14:39 +0100)]
sfi-cpufreq.c: checkpatch.pl cleanups
Fix various checkpatch violations
Change-Id: I777a3d0a72f73407d3d1190a80361ec4b4572277
Signed-off-by: Arjan van de Ven <arjan@linux.intel.com>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Arjan van de Ven [Fri, 15 Jul 2011 13:39:30 +0000 (14:39 +0100)]
sfi-cpufreq.c: remove redundant CPUID feature check
If the firmware reports a frequency table, the CPU supports multiple
frequencies, no need to check that extra.
Change-Id: I596cb7dd28eaeb5fd5826e071358c409d620d07e
Signed-off-by: Arjan van de Ven <arjan@linux.intel.com>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Arjan van de Ven [Fri, 15 Jul 2011 13:39:30 +0000 (14:39 +0100)]
sfi-cpufreq.c: fix the hardware coordination logic
The platforms that support SFI only support hardware coordination of P states.
This means that all the logic in the driver around CPU masks was just overly
complicated without any good reason.
This patch simplifies the driver by just going for one cpu at a time.
Change-Id: Ibface5db4ea457417475a959943369aee38a04f9
Signed-off-by: Arjan van de Ven <arjan@linux.intel.com>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Arjan van de Ven [Fri, 15 Jul 2011 13:39:29 +0000 (14:39 +0100)]
sfi-cpufreq.c: remove the strict checking feature
the sfi-cpufreq.c driver has a "debug the hardware" feature where
it will check after entry if a P state was actually entered.
This is no longer needed, so lets remove the code.
Change-Id: I7700f6e28845085a54c771d1e880ea09d0605bab
Signed-off-by: Arjan van de Ven <arjan@linux.intel.com>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Arjan van de Ven [Fri, 15 Jul 2011 13:39:29 +0000 (14:39 +0100)]
sfi-cpufreq: make use of rdmsr_on_cpu()
The kernel has a function to read msr values on different cpus;
sfi-cpufreq has this open coded. By using rdmsr_on_cpu(),
several functions can just be removed.
Change-Id: Ib6740c5bffeb48cc295df1f11ce060dc9a796c5e
Signed-off-by: Arjan van de Ven <arjan@linux.intel.com>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Arjan van de Ven [Fri, 15 Jul 2011 13:39:29 +0000 (14:39 +0100)]
sfi-cpufreq.c: remove some unused included
some of the #include'd headers were not used;
also reorder the #includes so that linux comes before asm and before local.
Change-Id: I34b83efe30771e6e4f050c7762874527383a8cbb
Signed-off-by: Arjan van de Ven <arjan@linux.intel.com>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Arjan van de Ven [Fri, 15 Jul 2011 13:39:29 +0000 (14:39 +0100)]
sfi-cpufreq: use the generic mperf library
The kernel has a nice library for getting mperf/aperf data in cpufreq drivers.
This patch makes the sfi-cpufreq driver use this library.
Change-Id: I41a774ed83bb16c14409435e46308a75c6fcdfeb
Signed-off-by: Arjan van de Ven <arjan@linux.intel.com>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Arjan van de Ven [Fri, 15 Jul 2011 13:39:28 +0000 (14:39 +0100)]
sfi: Initial import of the SFI P state driver from the UMG 2.6.35 kernel git
This patch is a pretty much straight import and port to 2.6.39 of the UMG
SFI P state driver. Cleanups to follow in later patches.
Change-Id: I2ad97eb2ad9fdc55c8deab7d1365bf36cfb8b91b
Signed-off-by: Arjan van de Ven <arjan@linux.intel.com>
Signed-off-by: Alan Cox <alan@linux.intel.com>
mgross [Wed, 20 Jul 2011 00:05:41 +0000 (17:05 -0700)]
hack to compile re-vert and do better later
Change-Id: I56a6db438004ddd2d1906df9b718846bd8adbf91
Alan Cox [Fri, 15 Jul 2011 13:39:28 +0000 (14:39 +0100)]
mrst: Don't do idle set up on non MRST hardware
Change-Id: I4be71a25f7857d6c47f2ebe42566b18572ca353c
Signed-off-by: Alan Cox <alan@linux.intel.com>
Feng Tang [Fri, 15 Jul 2011 13:39:28 +0000 (14:39 +0100)]
x86/mrst: Add platform data for Max3110 devices
Those info will be used when spi controller driver setup
max3110 as a slave device
Change-Id: I20262ed7bca2d6ab52af8043e84787709d82e575
Signed-off-by: Feng Tang <feng.tang@intel.com>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Dirk Brandewie [Fri, 15 Jul 2011 13:39:28 +0000 (14:39 +0100)]
spi/spi-dw.h: Expose interface for platform code to register external CS
Some platforms use a chip select mechanism other than that provided by
the controller. Expose the mechanism for the platform code to
register the external chip select control function with the driver.
Change-Id: If2807645a629833ebd50bab9073c56d70ea1826d
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Dirk Brandewie [Fri, 15 Jul 2011 13:39:27 +0000 (14:39 +0100)]
spi-dw-pci: Add runtime power management
This patch adds runtime power management to the PCI variant of the
designware SPI host controller driver.
Change-Id: Id083e554248d4f0558108e6363d097ad306198ef
Signed-off-by: Kristen Carlson Accardi <kristen@linux.intel.com>
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Dirk Brandewie [Fri, 15 Jul 2011 13:39:27 +0000 (14:39 +0100)]
spi/spi-dw: Rework message processing
This patch reworks the message pump worker thread function to run
until all messages queued to the driver have been handled. The
function to handle individual spi_transfers is now a synchronus
function the tasklet to handle spi_transfers has been removed. Work
for the worker thread is only queued in host controller transfer
function.
Psuedo code for new thread function:
message = get_message()
while (message){
for_each_transfer_in_msg(message){
transfer_setup(transfer)
do_transfer()
}
complete_message()
message = get_message()
}
Changes that fell out of the message thread changes:
Non-DMA transfers that are larger than the size of the controller FIFO
are handled as interrupt driven transfers.
Common FIFO handling functions shared PIO and interrupt transfers.
Simplified queue stop/start funcitons.
Cleanup fixes:
Changed exported all exported function names to have spi_dw_ prefix
Set fifo lenght in dw_spi_mid_init()
Added dw_spi_{en,dis}able inline functions to replace spi_enable_chip()
Added dw_spi_{mask,umask}_intr inline functions
Change-Id: I6a5f015ff1dbfa5d41297ca4c37bd3fbd9859959
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Dirk Brandewie [Fri, 15 Jul 2011 13:39:27 +0000 (14:39 +0100)]
spi/spi-dw: Rename internal functions to match file naming convention.
Rename internal functions and data structures to match file name
convention also change the Moorsetown {MRST/mrst} names to be generic
to the driver since the driver is in use in multiple SOC's.
Change-Id: I94fa9837b97fa42d5cc617c722f1fd8ebf61ac17
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Alan Cox [Fri, 15 Jul 2011 13:39:35 +0000 (14:39 +0100)]
config: Allow a Medfield selection
We have nothing much Medfield specific - yet but this is the boiler plate for it
Allowing Medfield only does need one fix up for the idle driver - we want the
same idle behaviour as Moorestown but we don't have the PMU hook
Change-Id: I9e27ffb0c78e59a1beaf292971bc55517099b9ff
Signed-off-by: Alan Cox <alan@linux.intel.com>
Alan Cox [Fri, 15 Jul 2011 13:39:35 +0000 (14:39 +0100)]
config: Update dependancies for multi MID devices
We have some stuff shared between Moorestown and Medfield so mark the
Kconfig entries for them as requiring X86_INTEL_MID
Change-Id: I26b87b5e96264c4e0758465cc4f79947491f8b38
Signed-off-by: Alan Cox <alan@linux.intel.com>
Alan Cox [Fri, 15 Jul 2011 13:39:35 +0000 (14:39 +0100)]
config: introduce an INTEL_MID configuration
We need to carve up the configuration between
- MID general
- Moorestown specific
- Medfield specific
- Future devices
As a base point create an INTEL_MID configuration property. We make the existing
MRST configuration a sub-option. This means that the rest of the kernel config
can still use X86_MRST checks without anything going backwards.
After this is merged future patches will tidy up which devices are MID and
which are X86_MRST, as well as add options for Medfield.
Change-Id: Idbe1121c0b7928273eeca7bb5494d9dff320eca1
Signed-off-by: Alan Cox <alan@linux.intel.com>
Alan Cox [Fri, 15 Jul 2011 13:40:05 +0000 (14:40 +0100)]
This patch is based on umg's 2.6.35 kernel which adds support for
a few new commands. It also has a few fixes and and adapt to the
upstram ipc driver structure.
key changes are:
- new ioctl commands to support fw upgrade and access to mip header,
hand-off buffer and revision
- consolidated fw update logic with moorestown
- misc clean up such as uncessary header files, typos
the fw update flow has not been tested since scu fw support is not
officially released. there is also issue with the current userspace
utiltity which hardcoding search for ipcutil driver as misc char
driver. The overall firmware update flow between ipcutil driver and
userspace should be revisited in that it does not use the existing
request_firmware interface, instead it relies on ioctl calls specific
to the driver. This will likely to happen after fw update support is
in the official scu fw release.
Most ipc commands has been tested with success on iCDK, including
access to MSIC registers, vRTC, OSNIB read. But there are occasional
ipc command timeout on mip and vrtc access. needs futher investigation
with fw team.
Change-Id: I755b5b21b769180a33261e5be71a63e58ea88a1b
Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Mathias Nyman [Fri, 15 Jul 2011 13:39:53 +0000 (14:39 +0100)]
x86: rtc: Don't register a platform RTC device for Intel MID platforms
Intel MID x86 platforms have a memory mapped virtual RTC instead.
No MID platform have the default ports (and accessing them may do weird stuff)
Change-Id: I768f4918f485fa4fc7d27002a9ac2ed8eef6363c
Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Dirk Brandewie [Fri, 15 Jul 2011 13:39:36 +0000 (14:39 +0100)]
mrst: Change early printk to depend on X86_INTEL_MID
Moorestown and Medfield have the same SPI controller IP block. Make
early printk support depend on the common X86_INTEL_MID config option.
Change-Id: I21c4c06d5b371a498e8a0ebce14d483aabc8cf2d
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Dirk Brandewie [Fri, 15 Jul 2011 13:39:23 +0000 (14:39 +0100)]
x86/mrst: Add support for Penwell clock calibration
Change-Id: Ib5ceb933b65bea16b622af6080a08c06224b4ea2
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Signed-off-by: Alan Cox <alan@linux.intel.com>
projects / kernel / kernel-mfld-blackbay.git / log