Tao Zhou [Wed, 24 Jul 2019 07:13:27 +0000 (15:13 +0800)]
drm/amdgpu: add RREG64/WREG64(_PCIE) operations
add 64 bits register access functions
v2: implement 64 bit functions in low level
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Dennis Li <dennis.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Wed, 31 Jul 2019 12:28:13 +0000 (20:28 +0800)]
drm/amdgpu: add ras error count after each query (v2)
v1: increase ras ce/ue error count
v2: log the number of correctable and uncorrectable errors
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Dennis Li <dennis.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 17 Jul 2019 13:49:53 +0000 (21:49 +0800)]
drm/amdgpu: querry umc error count
check umc error count in both ras querry function and
ras interrupt handler
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Dennis Li <dennis.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 17 Jul 2019 13:47:44 +0000 (21:47 +0800)]
drm/amdgpu: init umc v6_1 functions for vega20
init umc callback function for vega20 in sw early init phase
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Dennis Li <dennis.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 31 Jul 2019 12:23:01 +0000 (20:23 +0800)]
drm/amdgpu: add umc v6_1 query error count support
Implement umc query_ras_error_count function to support querry
both correctable and uncorrectable error
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Dennis Li <dennis.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 24 Jul 2019 06:36:49 +0000 (14:36 +0800)]
drm/amdgpu: add umc v6_1_1 IP headers
the change introduces IP headers for unified memory controller (umc)
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Dennis Li <dennis.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 24 Jul 2019 06:13:53 +0000 (14:13 +0800)]
drm/amdgpu: add rsmu v_0_0_2 ip headers
remote smu (rsmu) is a sub-block used as ip register interface,
error handling, reset generation.etc
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Dennis Li <dennis.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 23 Jul 2019 11:42:03 +0000 (19:42 +0800)]
drm/amdgpu: add amdgpu_umc_functions structure
This is common structure as UMC callback function
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Dennis Li <dennis.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 17 Jul 2019 09:52:28 +0000 (17:52 +0800)]
drm/amdgpu: init RSMU and UMC ip base address for vega20
the driver needs to program RSMU and UMC registers to
support vega20 RAS feature
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Dennis Li <dennis.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 17 Jul 2019 09:34:46 +0000 (17:34 +0800)]
drm/amdgpu: move some ras data structure to amdgpu_ras.h
These are common structures that can be included by IP specific
source files
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Dennis Li <dennis.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 31 Jul 2019 15:47:26 +0000 (10:47 -0500)]
drm/amdgpu: drop drmP.h from vcn_v2_5.c
Unused.
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 31 Jul 2019 15:45:52 +0000 (10:45 -0500)]
drm/amdgpu: drop drmP.h from vcn_v2_0.c
And fix the fallout.
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 31 Jul 2019 15:43:40 +0000 (10:43 -0500)]
drm/amdgpu: drop drmP.h from sdma_v5_0.c
And fix the fallout.
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 31 Jul 2019 15:39:40 +0000 (10:39 -0500)]
drm/amdgpu: drop drmP.h from nv.c
And fix up the fallout.
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 31 Jul 2019 15:34:39 +0000 (10:34 -0500)]
drm/amdgpu: drop drmP.h from navi10_ih.c
And fix the fallout.
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 31 Jul 2019 15:31:44 +0000 (10:31 -0500)]
drm/amdgpu: drop drmP.h in gfx_v10_0.c
And fix the fallout.
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 31 Jul 2019 15:27:57 +0000 (10:27 -0500)]
drm/amdgpu: drop drmP.h from amdgpu_amdkfd_gfx_v10.c
Unused.
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 31 Jul 2019 15:26:39 +0000 (10:26 -0500)]
drm/amdgpu: drop drmP.h in amdgpu_amdkfd_arcturus.c
Unused.
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 25 Jul 2019 08:40:51 +0000 (16:40 +0800)]
drm/amd/powerplay: determine the features to enable by pptable only
Per current logics, the features to enable are determined together
by driver and pptable. This is not efficient in co-debug with
firmware team.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Thu, 25 Jul 2019 09:22:01 +0000 (17:22 +0800)]
drm/amdgpu: correct irq type used for sdma ecc
we should pass irq type, instead of irq client id,
to irq_get/put interface
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 31 Jul 2019 03:52:37 +0000 (22:52 -0500)]
drm/amd/powerplay: make power limit retrieval as asic specific
The power limit retrieval should be done per asic. Since we may
need to lookup in the pptable and that's really asic specific.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 23 Jul 2019 12:28:14 +0000 (20:28 +0800)]
drm/amd/powerplay: correct arcturus current clock level calculation
There may be 1Mhz delta between target and actual frequency. That
should be taken into consideration for current level check.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 23 Jul 2019 09:30:35 +0000 (17:30 +0800)]
drm/amd/powerplay: support UMD PSTATE settings on arcturus
Enable arcturus UMD PSTATE support.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 23 Jul 2019 03:42:24 +0000 (11:42 +0800)]
drm/amd/powerplay: fix arcturus real-time clock frequency retrieval
Make sure we can still get the accurate gfxclk/uclk/socclk frequency
even on dpm disabled.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Fri, 19 Jul 2019 08:06:29 +0000 (16:06 +0800)]
drm/amd/powerplay: remove redundancy debug log in smu
remove redundacy debug log in smu.
eg:
[ 6897.969447] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6897.969448] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6897.969448] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6899.024114] amdgpu: [powerplay] Unsupported SMU message: 38
[ 6899.024151] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6899.024151] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6899.024152] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6900.078296] amdgpu: [powerplay] Unsupported SMU message: 38
[ 6900.078332] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6900.078332] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6900.078333] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6901.133230] amdgpu: [powerplay] Unsupported SMU message: 38
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 22 Jul 2019 09:03:02 +0000 (17:03 +0800)]
drm/amd/powerplay: correct the bitmask used in arcturus
Those bitmask prefixed by "SMU_" should be used.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 22 Jul 2019 08:26:04 +0000 (16:26 +0800)]
drm/amd/powerplay: add missing arcturus feature maps
Add missing feature maps for arcturus.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 22 Jul 2019 04:09:38 +0000 (12:09 +0800)]
drm/amd/powerplay: support fan speed retrieval on arcturus
Support arcturus fan speed retrieval.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 19 Jul 2019 09:18:34 +0000 (17:18 +0800)]
drm/amd/powerplay: support real-time clock retrieval on arcturus
Enable arcturus real-time clock retrieval.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 29 Jul 2019 18:18:37 +0000 (13:18 -0500)]
drm/amd/powerplay: support sensor reading on arcturus
Support sensor reading for gpu loading, power and
temperatures.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 22 Jul 2019 07:55:52 +0000 (15:55 +0800)]
drm/amd/powerplay: init arcturus SMU metrics table on bootup
Initialize arcturus SMU metrics table.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 22 Jul 2019 02:42:29 +0000 (10:42 +0800)]
drm/amd/powerplay: correct UVD/VCE/VCN power status retrieval
VCN should be used for Vega20 later ASICs while UVD and VCE
are for previous ASICs.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 22 Jul 2019 02:27:21 +0000 (10:27 +0800)]
drm/amd/powerplay: correct Navi10 VCN powergate control (v2)
No VCN DPM bit check as that's different from VCN PG. Also
no extra check for possible double enablement/disablement
as that's already done by VCN.
v2: check return value of smu_feature_set_enabled
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 22 Jul 2019 01:57:27 +0000 (09:57 +0800)]
drm/amd/powerplay: support VCN powergate status retrieval for SW SMU
Commonly used for VCN powergate status retrieval for SW SMU.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 22 Jul 2019 01:55:36 +0000 (09:55 +0800)]
drm/amd/powerplay: support VCN powergate status retrieval on Raven
Enable VCN powergate status report on Raven.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 22 Jul 2019 01:51:59 +0000 (09:51 +0800)]
drm/amd/powerplay: add new sensor type for VCN powergate status
VCN is widely used in new ASICs and different from tranditional
UVD and VCE.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Tue, 16 Jul 2019 07:21:54 +0000 (15:21 +0800)]
drm/amdgpu: update more sdma instances irq support
Update for sdma ras ecc_irq and other minors.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Mon, 15 Jul 2019 10:00:50 +0000 (18:00 +0800)]
drm/amd/include: adjust base offset of SMUIO and THM for Arcturus
Arcturus has different _BASE_IDX value in some HWIP_offset.h. To make source
files like smu_v11_0.c and soc15.c that include HWIP_offset.h of Vega20
reusable for Arcturus, align this base offset with Vega20.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 17 Jul 2019 01:34:13 +0000 (09:34 +0800)]
drm/amd/powerplay: hold on the arcturus gfx dpm support in driver
As for now, only "Prefetcher" is guarded to be working from
SMU firmware.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 16 Jul 2019 03:03:10 +0000 (11:03 +0800)]
drm/amdgpu: correct VCN powergate routine for acturus
Arcturus VCN should powergate in the way as Navi.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 12 Jul 2019 08:53:28 +0000 (16:53 +0800)]
drm/amd/powerplay: enable arcturus powerplay
Arcturus powerplay is ready to use.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 12 Jul 2019 08:50:52 +0000 (16:50 +0800)]
drm/amd/powerplay: initialize arcturus MP1 and THM base address
Initialize base address for those IPs which are used in powerplay.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 31 Jul 2019 04:30:07 +0000 (23:30 -0500)]
drm/amd/powerplay: enable SW SMU routine support for arcturus
Enable arcturus SW SMU routines.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 29 Jul 2019 17:43:28 +0000 (12:43 -0500)]
drm/amd/powerplay: update arcturus_ppt.c/h V3
Arcturus ASIC specific powerplay interfaces.
V2: correct SMU msg naming
drop unnecessary debugs
V3: rebase (Alex)
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 12 Jul 2019 08:28:02 +0000 (16:28 +0800)]
drm/amd/powerplay: update arcturus_ppsmc.h
Correct header and fix typo.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 12 Jul 2019 08:24:34 +0000 (16:24 +0800)]
drm/amd/powerplay: update smu11_driver_if_arcturus.h
It guides how driver should interface with SMU in arcturus.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 31 Jul 2019 03:50:14 +0000 (22:50 -0500)]
drm/amd/powerplay: add SW SMU interface for dumping pptable out (v2)
This is especially useful in early bring up phase.
v2: disabled by default (Alex)
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Le Ma <Le.Ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 10 Jul 2019 01:29:57 +0000 (09:29 +0800)]
drm/amd/powerplay: add smcdpminfo table v4_6 support
New smcdpminfo table used in arcturus.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jay Cornwall [Sun, 28 Jul 2019 21:00:59 +0000 (16:00 -0500)]
drm/amdkfd: Save/restore vcc on gfx10
VCC moved out of user SGPR allocation in gfx10. It's now stored
in SGPRs 106-107.
Also fixes incorrect SGPR read offsets.
Cc: Shaoyun Liu <shaoyun.liu@amd.com>
Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: shaoyunl <shaoyun.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jay Cornwall [Sun, 28 Jul 2019 20:25:05 +0000 (15:25 -0500)]
drm/amdkfd: Save/restore flat_scratch_lo/hi on gfx10
These moved from SGPRs in gfx9 to HWREG in gfx10.
Cc: Shaoyun Liu <shaoyun.liu@amd.com>
Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: shaoyunl <shaoyun.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jay Cornwall [Sun, 28 Jul 2019 20:24:40 +0000 (15:24 -0500)]
drm/amdkfd: Fix gfx10 wave64 VGPR context restore
Copy/paste error, first 4 VGPRs are separated by 64 dwords (256 bytes).
Cc: Shaoyun Liu <shaoyun.liu@amd.com>
Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: shaoyunl <shaoyun.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Tue, 30 Jul 2019 13:45:33 +0000 (09:45 -0400)]
drm/amd/display: Support uclk switching for DCN2
[Why]
We were previously forcing the uclk for every state to max and reducing
the switch time to prevent uclk switching from occuring. This workaround
was previously needed in order to avoid hangs + underflow under certain
display configurations.
Now that DC has the proper fix complete we can drop the hacks and
improve power for most display configurations.
[How]
We still need the function pointers hooked up to grab the real uclk
states from pplib. The rest of the prior hack can be reverted.
The key requirements here are really just DC support, updated firmware,
and support for disabling p-state support when needed in pplib/smu.
When these requirements are met uclk switching works without underflow
or hangs.
Fixes:
02316e963a5a ("drm/amd/display: Force uclk to max for every state")
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Tue, 30 Jul 2019 13:08:34 +0000 (09:08 -0400)]
drm/amd/display: Embed DCN2 SOC bounding box
[Why]
In order to support uclk switching on NV10 the SOC bounding box
needs to be updated.
[How]
We currently read the constants from the gpu info FW, but supporting
workarounds in DC for different versions of the FW adds additional
complexity to the codebase.
NV10 has been released so it's cleanest to keep the bounding box and
source code in sync by embedding the bounding box like we do for
other ASICs.
Fixes:
02316e963a5a ("drm/amd/display: Force uclk to max for every state")
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Wang Xiayang [Sat, 27 Jul 2019 09:30:30 +0000 (17:30 +0800)]
drm/amdgpu: fix a potential information leaking bug
Coccinelle reports a path that the array "data" is never initialized.
The path skips the checks in the conditional branches when either
of callback functions, read_wave_vgprs and read_wave_sgprs, is not
registered. Later, the uninitialized "data" array is read
in the while-loop below and passed to put_user().
Fix the path by allocating the array with kcalloc().
The patch is simplier than adding a fall-back branch that explicitly
calls memset(data, 0, ...). Also it does not need the multiplication
1024*sizeof(*data) as the size parameter for memset() though there is
no risk of integer overflow.
Signed-off-by: Wang Xiayang <xywang.sjtu@sjtu.edu.cn>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Tue, 30 Jul 2019 09:17:03 +0000 (11:17 +0200)]
drm/amdgpu: fix error handling in amdgpu_cs_process_fence_dep
We always need to drop the ctx reference and should check
for errors first and then dereference the fence pointer.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kenneth Feng [Mon, 29 Jul 2019 09:51:55 +0000 (17:51 +0800)]
drm/amdgpu/powerplay: provide the interface to disable uclk switch for DAL
provide the interface for DAL to disable uclk switch on navi10.
in this case, the uclk will be fixed to maximum.
this is a workaround when display configuration causes underflow issue.
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Thong Thai [Thu, 25 Jul 2019 15:26:56 +0000 (11:26 -0400)]
drm/amd/amdgpu/vcn_v2_0: Move VCN 2.0 specific dec ring test to vcn_v2_0
VCN 2.0 firmware now requires a packet start command to be sent before
any other decode ring buffer command.
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 26 Jul 2019 19:14:15 +0000 (14:14 -0500)]
drm/amdgpu/gfx10: update golden settings for navi14
Updated settings for hw team.
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Thu, 25 Jul 2019 03:47:44 +0000 (11:47 +0800)]
drm/amd/powerplay: implment sysfs feature status function in smu
1. Unified feature enable status format in sysfs
2. Rename ppfeature to pp_features to adapt other pp sysfs node name
3. this function support all asic, not asic related function.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Acked-by: Rui Huang <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Thu, 25 Jul 2019 03:57:25 +0000 (11:57 +0800)]
drm/amd/powerplay: move smu_feature_update_enable_state to up level
this function is not ip or asic related function,
so move it to top level as public api in smu.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Thu, 25 Jul 2019 03:08:42 +0000 (11:08 +0800)]
drm/amd/powerplay: add smu feature name support
add smu_get_feature_name support in smu.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Thu, 25 Jul 2019 02:32:48 +0000 (10:32 +0800)]
drm/amd/powerplay: add smu message name support
add smu_get_message_name support in smu.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Thu, 25 Jul 2019 01:59:46 +0000 (09:59 +0800)]
drm/amd/powerplay: move smu types to smu_types.h
move some enum type (message, feature, clock) to smu_types.h.
these types is too long in amdgpu_smu.h, and not clearly.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Joseph Greathouse [Fri, 26 Jul 2019 20:52:05 +0000 (15:52 -0500)]
drm/amdgpu: Default disable GDS for compute+gfx
Units in the GDS block default to allowing all VMIDs access to all
entries. Disable shader access to the GDS, GWS, and OA blocks from all
compute and gfx VMIDs by default. For compute, HWS firmware will set
up the access bits for the appropriate VMID when a compute queue
requires access to these blocks.
The driver will handle enabling access on-demand for graphics VMIDs.
Leaving VMID0 with full access because otherwise HWS cannot save or
restore values during task switch.
v2: Fixed code and comment styling.
Signed-off-by: Joseph Greathouse <Joseph.Greathouse@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Thong Thai [Thu, 25 Jul 2019 15:21:58 +0000 (11:21 -0400)]
drm/amd/amdgpu/vcn_v2_0: Mark RB commands as KMD commands
Sets the CMD_SOURCE bit for VCN 2.0 Decoder Ring Buffer commands. This
bit was previously set by the RBC HW on older firmware. Newer firmware
uses a SW RBC and this bit has to be set by the driver.
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 26 Jul 2019 16:04:39 +0000 (11:04 -0500)]
drm/amdgpu/display: fix the build without CONFIG_DRM_AMD_DC_DSC_SUPPORT
Some code was missing the CONFIG_DRM_AMD_DC_DSC_SUPPORT guard.
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Andrey Grodzovsky [Fri, 26 Jul 2019 13:24:35 +0000 (09:24 -0400)]
drm/amdgpu: Fix amdgpu_display_supported_domains logic.
Add restriction to dissallow GTT domain if the relevant BO
doesn't have USWC flag set to avoid the APU hang scenario.
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 26 Jul 2019 03:28:58 +0000 (22:28 -0500)]
drm/amdgpu/powerplay: use proper revision id for navi
The PCI revision id determines the sku.
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 25 Jul 2019 16:44:59 +0000 (11:44 -0500)]
drm/amdgpu: put the SMC into the proper state on reset/unload
When doing a GPU reset or unloading the driver, we need to
put the SMU into the apprpriate state for the re-init after
the reset or unload to reliably work.
I don't think this is necessary for BACO because the SMU actually
controls the BACO state to it needs to be active.
For suspend (S3), the asic is put into D3 so the SMU would be
powered down so I don't think we need to put the SMU into
any special state.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 25 Jul 2019 15:55:57 +0000 (10:55 -0500)]
drm/amdgpu/powerplay: add set_mp1_state for vega12
This sets the SMU into the proper state for various
operations (shutdown, unload, GPU reset, etc.).
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 25 Jul 2019 15:55:25 +0000 (10:55 -0500)]
drm/amdgpu/powerplay: add set_mp1_state for vega10
This sets the SMU into the proper state for various
operations (shutdown, unload, GPU reset, etc.).
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 25 Jul 2019 15:43:28 +0000 (10:43 -0500)]
drm/amdgpu/powerplay: add set_mp1_state for vega20
This sets the SMU into the proper state for various
operations (shutdown, unload, GPU reset, etc.).
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 31 Jul 2019 02:27:03 +0000 (21:27 -0500)]
drm/amdgpu/powerplay: return success if set_mp1_state is not set
Some asics (APUs) don't have this callback so we want to return
success. Avoids spurious error messages on APUs.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 25 Jul 2019 14:41:53 +0000 (09:41 -0500)]
drm/amdgpu/powerplay: add a new interface to set the mp1 state
This is required for certain cases such as various GPU resets
(mode1, mode2), BACO, shutdown, unload, etc. to put the SMU into
the appropriate state for when the hw is re-initialized.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 24 Jul 2019 04:48:21 +0000 (23:48 -0500)]
drm/amdgpu: add reset_method asic callback for navi
Navi uses either mode1 or baco depending on various
conditions.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 24 Jul 2019 04:47:06 +0000 (23:47 -0500)]
drm/amdgpu: add reset_method asic callback for soc15
APUs only support mode2 reset. dGPUs use either mode1 or
baco depending on various conditions.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 24 Jul 2019 04:46:12 +0000 (23:46 -0500)]
drm/amdgpu: add reset_method asic callback for vi
VI always uses the legacy pci based reset.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 24 Jul 2019 04:45:39 +0000 (23:45 -0500)]
drm/amdgpu: add reset_method asic callback for cik
CIK always uses the legacy pci based reset.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 24 Jul 2019 04:44:54 +0000 (23:44 -0500)]
drm/amdgpu: add reset_method asic callback for si
SI always uses the legacy pci based reset.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 24 Jul 2019 04:27:21 +0000 (23:27 -0500)]
drm/amdgpu: add an asic callback to determine the reset method
Sometimes the driver may have to behave differently depending
on the method we are using to reset the GPU.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 25 Jul 2019 02:12:42 +0000 (10:12 +0800)]
drm/amd/powerplay: enable SW SMU reset functionality
Move SMU irq handler register to sw_init as that's totally
software related. Otherwise, it will prevent SMU reset working.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 25 Jul 2019 04:10:34 +0000 (12:10 +0800)]
drm/amd/powerplay: fix null pointer dereference around dpm state relates
DPM state relates are not supported on the new SW SMU ASICs. But still
it's not OK to trigger null pointer dereference on accessing them.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 24 Jul 2019 06:06:09 +0000 (14:06 +0800)]
drm/amd/powerplay: minor fixes around SW SMU power and fan setting
Add checking for possible invalid input and null pointer. And
drop redundant code.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Shirish S [Tue, 16 Jul 2019 09:19:48 +0000 (14:49 +0530)]
drm/amd/display: enable S/G for RAVEN chip
enables gpu_vm_support in dm and adds
AMDGPU_GEM_DOMAIN_GTT as supported domain
v2:
Move BO placement logic into amdgpu_display_supported_domains
v3:
Use amdgpu_bo_validate_uswc in amdgpu_display_supported_domains.
v4:
amdgpu_bo_validate_uswc moved to sepperate patch.
Signed-off-by: Shirish S <shirish.s@amd.com>
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Andrey Grodzovsky [Wed, 24 Jul 2019 15:09:03 +0000 (11:09 -0400)]
drm/amdgpu: Add check for USWC support for amdgpu_display_supported_domains
This verifies we don't add GTT as allowed domain for APUs when USWC
is disabled.
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Acked-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Andrey Grodzovsky [Wed, 24 Jul 2019 14:04:27 +0000 (10:04 -0400)]
drm/amdgpu: Create helper to clear AMDGPU_GEM_CREATE_CPU_GTT_USWC
Move the logic to clear AMDGPU_GEM_CREATE_CPU_GTT_USWC in
amdgpu_bo_do_create into standalone helper so it can be reused
in other functions.
v4:
Switch to return bool.
v5: Fix typos.
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Acked-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Andrey Grodzovsky [Mon, 15 Jul 2019 22:04:08 +0000 (18:04 -0400)]
drm/amdgpu: Fix hard hang for S/G display BOs.
HW requires for caching to be unset for scanout BO
mappings when the BO placement is in GTT memory.
Usually the flag to unset is passed from user mode
but for FB mode this was missing.
v2:
Keep all BO placement logic in amdgpu_display_supported_domains
Suggested-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Tested-by: Shirish S <shirish.s@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jonathan Kim [Thu, 11 Jul 2019 17:14:02 +0000 (13:14 -0400)]
drm/amdgpu: adding xgmi error monitoring
monitor xgmi errors via mc pie status through fica registers.
Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com>
Reviewed-by: Kent Russell <Kent.Russell@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jonathan Kim [Tue, 9 Jul 2019 19:47:57 +0000 (15:47 -0400)]
drm/amdgpu: add perfmon and fica atomics for df
adding perfmon and fica atomic operations to adhere to data fabrics finite
state machine requirements for indirect register access.
Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com>
Reviewed-by: Kent Russell <Kent.Russell@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jay Cornwall [Wed, 24 Jul 2019 17:26:08 +0000 (12:26 -0500)]
drm/amdkfd: Remove dead code from gfx8/gfx9 trap handlers
Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jay Cornwall [Wed, 24 Jul 2019 17:23:42 +0000 (12:23 -0500)]
drm/amdkfd: Replace gfx10 trap handler with correct branch
Previously submitted code was taken from an incorrect branch and
was non-functional.
Cc: Oak Zeng <oak.zeng@amd.com>
Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-By: Oak Zeng <oak.zeng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jay Cornwall [Tue, 23 Jul 2019 00:21:13 +0000 (19:21 -0500)]
drm/amdkfd: Fix lost single step exceptions in gfx9 trap handler
If the trap is entered due to MODE.DEBUG_EN=1 and SAVECTX is raised
concurrently the handler cannot identify the source of the exception.
This causes the debugger to lose single step exception notification
when a context save request arrives at the same time.
When MODE.DEBUG_EN=1 and STATUS.HALT=0 (exception not already handled)
jump to the second-level trap handler upon entering the trap. The
second-level trap will set STATUS.HALT=1 and return to the shader.
If SAVECTX was raised then control flow will return to the trap, which
will then handle the context save request.
Cc: Tony Tye <tony.tye@amd.com>
Cc: Laurent Morichetti <laurent.morichetti@amd.com>
Cc: Qingchuan Shi <qingchuan.shi@amd.com>
Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
Reviewed-by: Laurent Morichetti <laurent.morichetti@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jay Cornwall [Tue, 23 Jul 2019 19:40:07 +0000 (14:40 -0500)]
drm/amdkfd: Use SQC when TCP would fail in gfx9 context save.
When a wavefront raises TRAPSTS.XNACK_ERROR with STATUS.ALLOW_REPLAY=0
subsequent memory instructions have undefined behavior. In practice
SQC stores continue to work but TCP stores do not.
Context save is permitted to fail after XNACK error because the
wavefront will be halted and subsequently terminated. However the
debugger has an interest in retrieving the wavefront VGPR/LDS state.
Detect the out-of-spec case and use SQC stores during context save
in place of TCP stores.
Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
tiancyin [Tue, 16 Jul 2019 10:25:01 +0000 (18:25 +0800)]
drm/amdgpu/gmc10: fix pte mytpe field error for navi14
navi14 share same PTE format with navi10.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: tiancyin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
James Zhu [Tue, 23 Jul 2019 20:45:19 +0000 (16:45 -0400)]
drm/amdgpu: use VCN firmware offset for cache window
Since we are using the signed FW now, and also using PSP firmware loading,
but it's still potential to break driver when loading FW directly
instead of PSP, so we should add offset.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Tue, 23 Jul 2019 11:56:52 +0000 (19:56 +0800)]
drm/amd/powerplay: fix temperature granularity error in smu11
in this patch,
drm/amd/powerplay: add callback function of get_thermal_temperature_range
the driver missed temperature granularity change on other temperature.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 23 Jul 2019 08:23:28 +0000 (16:23 +0800)]
drm/amd/powerplay: some cosmetic fixes
Drop redundant check, duplicate check, duplicate setting
and fix the return value.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 23 Jul 2019 06:27:20 +0000 (14:27 +0800)]
drm/amd/powerplay: no pptable transfer and dpms enabled with "dpm=0"
Honor the 'dpm' module parameter setting on SW SMU routine as what
we did on previous ASICs. SMU FW loading is still proceeded even
with "dpm=0".
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Colin Ian King [Tue, 23 Jul 2019 14:23:12 +0000 (15:23 +0100)]
drm/amd/display: fix a missing null check on a failed kzalloc
Currently the allocation of config may fail and a null pointer
dereference on config can occur. Fix this by added a null
check on a failed allocation of config.
Addresses-Coverity: ("Dereference null return")
Fixes:
c2cd9d04ecf0 ("drm/amd/display: Hook up calls to do stereo mux and dig programming to stereo control interface")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chuhong Yuan [Tue, 23 Jul 2019 11:10:08 +0000 (19:10 +0800)]
drm/radeon: Use dev_get_drvdata where possible
Instead of using to_pci_dev + pci_get_drvdata,
use dev_get_drvdata to make code simpler.
Signed-off-by: Chuhong Yuan <hslester96@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>