Karmjit Mahil [Thu, 5 Jan 2023 15:02:00 +0000 (15:02 +0000)]
pvr: Set SPMSCRATCHBUFFER flag.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21102>
Karmjit Mahil [Tue, 29 Nov 2022 16:08:03 +0000 (16:08 +0000)]
pvr: Update comment about ZS and MSAA buffers for pvrsrvkm submission.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21102>
Karmjit Mahil [Tue, 29 Nov 2022 15:48:13 +0000 (15:48 +0000)]
pvr: Acquire scratch buffer on framebuffer creation.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21102>
Karmjit Mahil [Tue, 22 Nov 2022 16:28:29 +0000 (16:28 +0000)]
pvr: Add SPM scratch buffer infrastructure.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21102>
Lionel Landwerlin [Tue, 8 Nov 2022 14:43:33 +0000 (16:43 +0200)]
intel/ds: track end of pipe bits
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
Lionel Landwerlin [Fri, 4 Nov 2022 14:20:56 +0000 (16:20 +0200)]
anv: rename a few internal functions to highlight gfx use
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
Lionel Landwerlin [Thu, 3 Nov 2022 07:27:01 +0000 (09:27 +0200)]
anv: rename RT pipeline function helper
Making it clear this is intended for RT pipelines only.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
Lionel Landwerlin [Wed, 9 Mar 2022 13:31:34 +0000 (15:31 +0200)]
intel/fs: make alpha_to_coverage a tristate
That way in some cases we can do this dynamically.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
Jason Ekstrand [Fri, 3 Dec 2021 16:45:58 +0000 (10:45 -0600)]
intel/fs: Rework dynamic coarse handling
Use 2 flags for PI & RT messages.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
Jason Ekstrand [Fri, 3 Dec 2021 16:45:48 +0000 (10:45 -0600)]
intel/fs: Break out yet another FB write helper
This new helper, do_emit_fb_writes() does the actual walk over all the
render targets to emit each of the different FB writes. We want this in
a helper because we're about to go a bit crazy with coarse.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
Jason Ekstrand [Tue, 23 Nov 2021 18:48:27 +0000 (12:48 -0600)]
intel/fs/validate: Assert SEND [extended] descriptors are uniform
This is required by code-gen since it generates a 1-wide OR and it'll
blow up if the register width > 1. It's also way better than the "your
register is the wrong size" assert you get from the more generic
validation check.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
Jason Ekstrand [Fri, 19 Nov 2021 19:44:35 +0000 (13:44 -0600)]
intel/compiler: Convert wm_prog_key::multisample_fbo to a tri-state
This allows us to communicate to the back-end that we don't actually
know if the framebuffer is multisampled or not. No drivers set anything
but ALWAYS/NEVER and we still have a few ALWAYS/NEVER assumptions but
those should be asserted.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
Jason Ekstrand [Fri, 19 Nov 2021 22:34:19 +0000 (16:34 -0600)]
intel/compiler: Convert wm_prog_key::persample_interp to a tri-state
This allows for the possibility that we may not know at compile time if
sample shading is enabled through the API. While we're here, also
document exactly what this bit means so we don't confuse ourselves.
v2: Fixup coarse pixel values (Lionel)
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
Jason Ekstrand [Fri, 19 Nov 2021 22:32:24 +0000 (16:32 -0600)]
intel/fs: Make per-sample and coarse dispatch tri-state
Whenever one of them is BRW_SOMETIMES, we depend on dynamic flag pushed
in as a push constant. In this case, we have to often have to do the
calculation both ways and SEL the result. It's a bit more code but
decouples MSAA from the shader key.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
Jason Ekstrand [Fri, 19 Nov 2021 17:57:03 +0000 (11:57 -0600)]
intel/compiler: Convert brw_wm_aa_enable to brw_sometimes
There are other cases where we want a tri-state logic like this. May as
well have one enum for all the cases.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
Jason Ekstrand [Mon, 22 Nov 2021 20:30:32 +0000 (14:30 -0600)]
intel/fs: Return early in a couple builtin setup helpers
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
Jason Ekstrand [Fri, 19 Nov 2021 23:57:42 +0000 (17:57 -0600)]
intel/compiler: Use SHADER_OPCODE_SEND for PI messages
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
Jason Ekstrand [Fri, 19 Nov 2021 19:36:28 +0000 (13:36 -0600)]
nir: Remove nir_lower_io_force_sample_interpolation
It's no longer used.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
Jason Ekstrand [Fri, 19 Nov 2021 22:11:44 +0000 (16:11 -0600)]
intel/nir: Lower barycentrics to per-sample in a dedicated pass
This is more similar to what we do for single-sample and it should be
more clear going forward once our lowering gets more complex.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
Jason Ekstrand [Fri, 19 Nov 2021 21:30:08 +0000 (15:30 -0600)]
intel/compiler: Document wm_prog_key::persample_interp
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21094>
Marek Olšák [Wed, 25 Jan 2023 01:44:10 +0000 (20:44 -0500)]
amd: don't hardcode real VGPR allocation granularity on gfx10.3 and gfx11
That's how it really works.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20967>
Marek Olšák [Tue, 31 Jan 2023 05:52:59 +0000 (00:52 -0500)]
amd,util: fix how lod bias is converted to fixed-point
according to internal docs
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20967>
Marek Olšák [Mon, 30 Jan 2023 13:35:22 +0000 (08:35 -0500)]
amd/surface: clean up is_dcc_supported_by_L2
no functional change, though this removes "<=" for navi10, which was
never true in the "<" case
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20967>
Marek Olšák [Mon, 30 Jan 2023 12:56:31 +0000 (07:56 -0500)]
radeonsi: clean up si_set_mutable_tex_desc_fields
- sink code into existing branches
- remove unnecessary clearing of fields
- no functional change
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20967>
Marek Olšák [Fri, 27 Jan 2023 05:33:41 +0000 (00:33 -0500)]
amd: define new SET_*_REG_PAIRS packets
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20967>
Marek Olšák [Wed, 25 Jan 2023 06:26:52 +0000 (01:26 -0500)]
radeonsi/gfx11: don't add alpha to mrt0 format for A2C if exporting via mrtz
If alpha-to-coverage is exported via mrtz, don't upgrade the mrt0 format
to one with an alpha channel.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20967>
Marek Olšák [Wed, 25 Jan 2023 06:15:02 +0000 (01:15 -0500)]
radeonsi/gfx11: don't add mrt0 export for alpha-to-coverage if mrtz is present
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20967>
Alyssa Rosenzweig [Fri, 3 Feb 2023 14:59:04 +0000 (09:59 -0500)]
nir/lower_clip: Only emit 1 discard
If we have multiple clip planes, rather than emit multiple discards we can just
OR together the discard criteria. Then a nir_opt_algebraic rule kicks in to
optimize out the flt/.../flt/ior/.../ior into fmin/.../fmin/flt, generating
much less code at the end.
Written while debugging an unrelated issue with the clip lowering.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21103>
Mike Blumenkrantz [Thu, 2 Feb 2023 15:47:31 +0000 (10:47 -0500)]
zink: conditionally enable PIPE_CAP_NULL_TEXTURES
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21072>
Mike Blumenkrantz [Thu, 2 Feb 2023 15:47:04 +0000 (10:47 -0500)]
radeonsi: set PIPE_CAP_NULL_TEXTURES
fixes #8163
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21072>
Mike Blumenkrantz [Thu, 2 Feb 2023 15:45:20 +0000 (10:45 -0500)]
gallium: add PIPE_CAP_NULL_TEXTURES
this allows drivers to indicate that they support sampling from null
textures instead of using fallback textures
for now, this is only used for depth-based fallback textures
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21072>
Konstantin Seurer [Sun, 22 Jan 2023 12:00:14 +0000 (13:00 +0100)]
radv: Scalarize global IO with LLVM enabled
Fixes the "atomic store operand must have integer, pointer, or floating point type!" error with RADV_DEBUG=llvm,checkir.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20840>
Konstantin Seurer [Wed, 4 Jan 2023 15:49:08 +0000 (16:49 +0100)]
ac/llvm: Fix validation error with global io
Fixes:
afd645f0576 ("ac/llvm: remove LLVMBuildGEP usages")
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20521>
Konstantin Seurer [Wed, 4 Jan 2023 15:48:29 +0000 (16:48 +0100)]
radv/llvm: Use the shader names as module name
This makes it easier to identify which (if any) shaders fail validation.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20521>
Konstantin Seurer [Sat, 4 Feb 2023 10:57:44 +0000 (11:57 +0100)]
radv/rq: Use 16 stack entries if there is only one ray query
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21120>
Asahi Lina [Thu, 2 Feb 2023 03:16:01 +0000 (12:16 +0900)]
meson: Fix Asahi build on macOS
!19950 introduced a dependency between NIR and Vulkan headers, and the
Vulkan headers try to include X11 headers we cannot find on macOS.
Disable this (we have no plans for Vulkan on the macOS testing platform
anyway).
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21059>
Alyssa Rosenzweig [Sat, 4 Feb 2023 17:03:21 +0000 (12:03 -0500)]
agx: Don't scalarize preambles in NIR
Scalarizing preambles in NIR isn't really necessary, we can do it more
efficiently in the backend. This makes the final NIR a lot less annoying to
read; the backend IR was already nice to read thanks to all the scalarized moves
being copypropped. Plus, this is a lot simpler.
No shader-db changes.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21122>
Alyssa Rosenzweig [Sat, 4 Feb 2023 17:27:48 +0000 (12:27 -0500)]
agx: Lower uniform sources with a dedicated pass
Move the decision of "can I copyprop this uniform?" from copyprop to a
standalone lowering pass. This is more straightforward and will enable the next
patch. This has the side effect of sinking load_preamble instructions, for a
nice reduction in register pressure. Instruction count increase is from
rematerializing some moves, which should be more than balanced out by the
reduced register pressure.
total instructions in shared programs: 1523285 -> 1523317 (<.01%)
instructions in affected programs: 1148 -> 1180 (2.79%)
helped: 0
HURT: 13
HURT stats (abs) min: 1.0 max: 4.0 x̄: 2.46 x̃: 2
HURT stats (rel) min: 0.69% max: 7.69% x̄: 3.65% x̃: 2.61%
95% mean confidence interval for instructions value: 1.78 3.14
95% mean confidence interval for instructions %-change: 2.16% 5.15%
Instructions are HURT.
total bytes in shared programs:
10444532 ->
10444724 (<.01%)
bytes in affected programs: 7386 -> 7578 (2.60%)
helped: 0
HURT: 13
HURT stats (abs) min: 6.0 max: 24.0 x̄: 14.77 x̃: 12
HURT stats (rel) min: 0.63% max: 7.14% x̄: 3.40% x̃: 2.48%
95% mean confidence interval for bytes value: 10.68 18.85
95% mean confidence interval for bytes %-change: 2.02% 4.78%
Bytes are HURT.
total halfregs in shared programs: 419444 -> 416434 (-0.72%)
halfregs in affected programs: 27080 -> 24070 (-11.12%)
helped: 634
HURT: 0
helped stats (abs) min: 1.0 max: 30.0 x̄: 4.75 x̃: 2
helped stats (rel) min: 2.90% max: 54.55% x̄: 13.13% x̃: 8.51%
95% mean confidence interval for halfregs value: -5.08 -4.41
95% mean confidence interval for halfregs %-change: -14.03% -12.23%
Halfregs are helped.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21122>
Alyssa Rosenzweig [Tue, 20 Dec 2022 03:32:46 +0000 (22:32 -0500)]
agx: Run DCE twice
Needed to combine fsat with vectors due to nir_lower_blend changes.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21122>
Alyssa Rosenzweig [Sat, 4 Feb 2023 18:01:38 +0000 (13:01 -0500)]
agx: Allow uniform sources on phis
The parallel copy lowering has been able to handle uniform sources since
98f0ebf2647 ("agx:
Pass agx_index to agx_copy"), and uniform sources work fine with phis. It's not
super common but there's no need to restrict them. This is a small instruction
count win and will greatly simplify the lowering later in this series.
total instructions in shared programs: 1523806 -> 1523285 (-0.03%)
instructions in affected programs: 17088 -> 16567 (-3.05%)
helped: 38
HURT: 1
helped stats (abs) min: 1.0 max: 44.0 x̄: 13.95 x̃: 7
helped stats (rel) min: 0.42% max: 18.64% x̄: 4.73% x̃: 1.26%
HURT stats (abs) min: 9.0 max: 9.0 x̄: 9.00 x̃: 9
HURT stats (rel) min: 8.57% max: 8.57% x̄: 8.57% x̃: 8.57%
95% mean confidence interval for instructions value: -17.95 -8.77
95% mean confidence interval for instructions %-change: -6.35% -2.43%
Instructions are helped.
total bytes in shared programs:
10447658 ->
10444532 (-0.03%)
bytes in affected programs: 118850 -> 115724 (-2.63%)
helped: 38
HURT: 1
helped stats (abs) min: 6.0 max: 264.0 x̄: 83.68 x̃: 45
helped stats (rel) min: 0.36% max: 16.51% x̄: 4.14% x̃: 1.09%
HURT stats (abs) min: 54.0 max: 54.0 x̄: 54.00 x̃: 54
HURT stats (rel) min: 7.30% max: 7.30% x̄: 7.30% x̃: 7.30%
95% mean confidence interval for bytes value: -107.68 -52.62
95% mean confidence interval for bytes %-change: -5.55% -2.13%
Bytes are helped.
total halfregs in shared programs: 419446 -> 419444 (<.01%)
halfregs in affected programs: 29 -> 27 (-6.90%)
helped: 1
HURT: 0
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21122>
Luc Ma [Thu, 2 Feb 2023 11:29:45 +0000 (19:29 +0800)]
xlib: fix glXDestroyContext in Gallium frontends
when glx is built with -Dglx=xlib, the mishandle in
glXDestroyContext causes glmark2 to exit unexpectedly.
Error: Glmark2 needs OpenGL(ES) version >= 2.0 to run (but version string is: '(null)')!
Error: Failed to add vertex shader from file None:
Error: Failed to create the new program
[build] <default>: Set up failed
Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3985
Signed-off-by: Luc Ma <luc@sietium.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21067>
SoroushIMG [Sat, 4 Feb 2023 17:44:40 +0000 (17:44 +0000)]
zink: fix cap check for arb sparse texture2
arb_sparse_texture2 also enables multisampled sparse textures.
bring back the check for msaa support.
fixes #8229
Fixes:
4f8ba2b9aae ("zink: fix sparse residency query and minLOD feature checks")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21121>
Alyssa Rosenzweig [Fri, 3 Feb 2023 00:44:26 +0000 (19:44 -0500)]
nir/print: Pretty-print color0/1_interp
These are an enum. Furthermore, their 0 state is INTERP_MODE_NONE which we
shouldn't bother printing at all.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21091>
Alyssa Rosenzweig [Fri, 3 Feb 2023 00:33:07 +0000 (19:33 -0500)]
nir/print: Pretty-print I/O semantic locations
Instead of printing the raw location number, which is pretty hard to interpret,
let's print the name of the location. Example output:
vec4 16 ssa_2 = intrinsic load_interpolated_input (ssa_0, ssa_1) (base=0,
component=0, dest_type=float16 /*144*/, io location=VARYING_SLOT_VAR0 slots=1
mediump /*8388768*/)
One of the "regressions" from moving to purely lowered I/O with all variables
removed is a lack of debuggability, since otherwise these location strings don't
show up anywhere in the printed shader! By contrast this should make the lowered
I/O nice to read like the early I/O.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21091>
Alyssa Rosenzweig [Fri, 3 Feb 2023 00:32:25 +0000 (19:32 -0500)]
nir/print: Extract get_location_str
Locations show up in two places: variables and lowered I/O semantics. We want to
reuse the logic in both places, so extract it out. The extracted logic is IMO
easier to read, too.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21091>
Alyssa Rosenzweig [Sat, 3 Dec 2022 19:34:44 +0000 (14:34 -0500)]
agx: Implement barriers
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21062>
Alyssa Rosenzweig [Sat, 3 Dec 2022 02:32:14 +0000 (21:32 -0500)]
agx: Implement compute ID intrinsics
These NIR intrinsics map to vectors of special registers.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21062>
Alyssa Rosenzweig [Sat, 3 Dec 2022 18:18:03 +0000 (13:18 -0500)]
asahi: Identify more compute-related XML
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21062>
Alyssa Rosenzweig [Sat, 3 Dec 2022 02:34:33 +0000 (21:34 -0500)]
asahi: Implement load_ssbo_address/get_ssbo_size
More uniforms that get pushed.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21062>
Alyssa Rosenzweig [Fri, 3 Feb 2023 20:24:05 +0000 (15:24 -0500)]
asahi: Add compute batches
Add a specialized agx_batch for compute commands (queued to the CDM instead of
the VDM for graphics). This uses a sentinel value for the width.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21062>
Alyssa Rosenzweig [Sat, 22 Oct 2022 15:36:38 +0000 (11:36 -0400)]
asahi: Bump PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
Seems arbitrary.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21062>
Alyssa Rosenzweig [Sat, 22 Oct 2022 15:36:23 +0000 (11:36 -0400)]
asahi: Stub out MSAA for dEQP
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21062>
Alyssa Rosenzweig [Mon, 19 Dec 2022 19:28:14 +0000 (14:28 -0500)]
asahi: Advertise seamless cube maps
These are already wired up.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21062>
Alyssa Rosenzweig [Sat, 22 Oct 2022 14:58:45 +0000 (10:58 -0400)]
asahi: Fake more caps for dEQP-GLES31
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21062>
Alyssa Rosenzweig [Sat, 22 Oct 2022 15:15:44 +0000 (11:15 -0400)]
asahi: Add hooks for SSBO and images
Copy paste from Panfrost. This should be close to what we need for Asahi, and
this lets us run dEQP-GLES31 without crashing immediately.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21062>
Alyssa Rosenzweig [Fri, 3 Feb 2023 20:32:19 +0000 (15:32 -0500)]
asahi: Don't leak shader NIR
create_shader_state passes ownership of the NIR to the driver, so we need to
free it when we destroy the shader CSO later. Use ralloc to manage this in a
uniform way between graphics and compute. Strategy from Panfrost.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21062>
Alyssa Rosenzweig [Sat, 22 Oct 2022 15:07:02 +0000 (11:07 -0400)]
asahi: Add compute kernel scaffolding
This adds the basic scaffolding for compute kernels. There's a bit of churn to
make sure we don't need to hang onto the kernel NIR, since it's never used for
anything else except looking up the shader stage.
The compute kernels aren't actually wired up here, but they do get compiled.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21062>
Alyssa Rosenzweig [Fri, 3 Feb 2023 21:21:01 +0000 (16:21 -0500)]
asahi: Fix delete_vs_state implementation
The generic free won't delete the shader variants, leaking them all!
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21062>
Hampus Linander [Sun, 8 Jan 2023 00:18:55 +0000 (01:18 +0100)]
agx: Optimize lower_resinfo for cube maps
We can avoid reading both width and height when the texture is a cube map, and
we do so more simply by relying on CSE+DCE (Alyssa).
Closes: #7541
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20628>
Hampus Linander [Thu, 19 Jan 2023 10:33:26 +0000 (11:33 +0100)]
agx: Use AGX extr for tex lowering
Replaces a number of bit operations by a single extr instruction,
optimizing the extraction of the width from the packed value.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20628>
Hampus Linander [Thu, 12 Jan 2023 23:06:00 +0000 (00:06 +0100)]
agx: Add extr instruction to AGX backend
Encoding is similar to bfeil, in particular the immidiate has the
same encoding as BFI_MASK hence its reuse.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20628>
Hampus Linander [Thu, 12 Jan 2023 17:38:28 +0000 (18:38 +0100)]
nir: Add extr_agx opcode
The AGX extr instruction extracts a bitfield from two 32bit registers.
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20628>
Alyssa Rosenzweig [Sat, 7 Jan 2023 21:49:27 +0000 (16:49 -0500)]
asahi: Implement custom border colours
Implement custom border colours, as required by OpenGL's CLAMP_TO_BORDER and
Vulkan with customBorderColor. This uses an extended sampler descriptor, which
has space for the custom border values. The trouble is that the border must be
packed into an internal interchange format that depends on the original format
in a complex way. That said, we're not solving NP-complete problems here, and it
passes the tests (dEQP-GLES31.functional.texture.border_clamp.* and piglit
texwrap).
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20570>
Alyssa Rosenzweig [Thu, 2 Feb 2023 05:24:11 +0000 (00:24 -0500)]
agx/decode: Handle extended samplers
These include a border colour field.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20570>
Alyssa Rosenzweig [Thu, 2 Feb 2023 05:11:36 +0000 (00:11 -0500)]
agx/decode: Add a data parameter to stateful
So we can handle extended samplers.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20570>
Alyssa Rosenzweig [Sat, 7 Jan 2023 21:48:51 +0000 (16:48 -0500)]
asahi: Add XML for custom border colours
These use extended sampler descriptors.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20570>
Timur Kristóf [Wed, 1 Feb 2023 12:07:42 +0000 (13:07 +0100)]
ac/nir/ngg: Include culled primitives in query.
Vulkan spec 18.8. Primitives Generated Queries:
When a generated primitive query for a vertex stream is active,
the primitives-generated count is incremented every time a
primitive emitted to that stream reaches the transform feedback
stage, whether or not transform feedback is active.
We can see the order of stages in chapter 27 Fixed-Function
Vertex Post-Processing, which shows that the transform feedback
stage is before rasterization (and therefore culling).
Conclusion is that culled primitives should be included
in the primitives generated query.
This commit makes sure to emit the primitives generated query
code before culling and uses the input primitive count passed
to the current wave instead of the exec mask after culling.
Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21037>
Alyssa Rosenzweig [Fri, 3 Feb 2023 21:15:40 +0000 (16:15 -0500)]
agx: Handle constant-offset in address matching
Match iadd(x, #y). The format shift will get constant-folded away and, if y
is sufficiently small, the constant will be inlined by the AGX backend
optimizer. This gets rid of piles of 64-bit arithmetic from lowering UBOs. It
probably doesn't matter for perf since that's happening in preamble shaders but
it *is* noisy.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21108>
Alyssa Rosenzweig [Fri, 3 Feb 2023 03:27:17 +0000 (22:27 -0500)]
agx: Fix storing to varying arrays
The offset is in vec4s, not words (unlike the component). This doesn't matter
right now since we get everything lowered (offset -> 0) but it will come up if
we implement clip distances natively (instead of lowering in FS).
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21097>
Alyssa Rosenzweig [Fri, 3 Feb 2023 03:27:02 +0000 (22:27 -0500)]
docs/asahi: Document clip distance varyings
These implement gl_ClipDistance in hardware, avoiding the fragment shader
lowering. Unfortunately, they can't be disabled on a per-plane basis and they
can't be interpolated, so using them for OpenGL would still require a bunch of
extra lowering steps. Still, we should document the hardware and the caveats.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21097>
Alyssa Rosenzweig [Fri, 3 Feb 2023 21:38:01 +0000 (16:38 -0500)]
asahi: Don't use 16-bit inputs to 32-bit st_tile
The hardware doesn't extend in this case, we need to extend for it. This
fixes 32-bit render target formats with lower_mediump_io.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21082>
Alyssa Rosenzweig [Thu, 2 Feb 2023 20:40:25 +0000 (15:40 -0500)]
agx: Keep varyings forwarded to texture as fp32
This works around bugs in a LOT of applications, since fp16 texture coordinates
are almost never appropriate even though it's a valid implementation of the GLES
spec. It also doesn't seem to matter for perf.
Code from the Bifrost compiler which implements the same workaround for slightly
different reasons.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21082>
Alyssa Rosenzweig [Sat, 7 Jan 2023 04:22:33 +0000 (23:22 -0500)]
asahi: Merge fragment control XML
Same struct specified twice and merged in the hw.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21081>
Alyssa Rosenzweig [Sat, 7 Jan 2023 04:19:45 +0000 (23:19 -0500)]
asahi: Remove redundant tri merge disable bit
Cargoculted from Metal.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21081>
Alyssa Rosenzweig [Sat, 7 Jan 2023 04:17:27 +0000 (23:17 -0500)]
asahi: DRY dirty tracking conditions
Ella did this in agxv and it made a lot more sense than the copypasta I did.
Should get copypropped to similar code.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21081>
Alyssa Rosenzweig [Thu, 22 Dec 2022 03:06:25 +0000 (22:06 -0500)]
asahi: Implement nontrivial rasterizer discard
For vertex shaders with side effects, as seen with transform feedback.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21081>
Alyssa Rosenzweig [Thu, 15 Dec 2022 20:47:41 +0000 (15:47 -0500)]
asahi: Prefer blit-based texture transfer
This speeds up glReadPixels. Instead of reading from the write-combined
framebuffer and converting colours on the CPU, this blits on the GPU to a
writeback staging resource with the colour conversion for free, and memcpies
from the writeback staging resource on the CPU.
In general, due to textures being write combined and tiled/compressed by default
by staging resources being linear writeback, blit-based texture transfer should
win out (you were going to blit anyway), particularly when format conversion is
involved
33% reduction in wall clock time for grim at 4K. No change in deqp-gles2
runtime.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21063>
Alyssa Rosenzweig [Sat, 17 Dec 2022 22:06:24 +0000 (17:06 -0500)]
asahi: Make STAGING resources linear
As intended by the flag.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21063>
Alyssa Rosenzweig [Sat, 17 Dec 2022 21:28:54 +0000 (16:28 -0500)]
asahi: Use writeback when it looks beneficial
When playing the My Little Pony theme song at 1080p on T8103, with mpv's GPU
compositing but software decoding, CPU usage drops from 200% to 50% due to
proper caching of the staging resource.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21063>
Asahi Lina [Fri, 9 Dec 2022 11:16:28 +0000 (20:16 +0900)]
asahi: Refuse to transfer out-of-bounds mip levels
Fixes ail asserts on a pile of dEQP3 tests.
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21063>
Alyssa Rosenzweig [Sat, 21 Jan 2023 17:35:11 +0000 (12:35 -0500)]
agx: Support uniform registers as LODs
This will avoid regressing moves when we lower sampler LOD bias. Corresponding
disassembler change: https://github.com/dougallj/applegpu/pull/22
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20833>
Alyssa Rosenzweig [Sat, 4 Feb 2023 03:02:34 +0000 (22:02 -0500)]
asahi: Correct alignment for USC Uniform packets
We only need 4 byte alignment, not 8 bytes. This isn't a big difference in
practice, but it probably reduces padding in some cases. More importantly, it
corrects our XML to match what the hardware actually does, which is great.
(There is exactly enough room for a 40-bit address with 4 byte alignment.)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21118>
Alyssa Rosenzweig [Sat, 4 Feb 2023 01:58:05 +0000 (20:58 -0500)]
asahi/nir_lower_sysvals: Split large ranges
It is our responsibility to ensure uniform ranges don't exceed 64 uniforms.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21118>
Alyssa Rosenzweig [Sat, 4 Feb 2023 01:54:41 +0000 (20:54 -0500)]
asahi: Strengthen agx_usc_uniform contract
Check the size explicitly, instead of just implicitly in the GenXML pack: it is
the responsibility of the caller to split up larger uploads. While this is
nominally more complicated, agx_usc_uniform is called in the draw hot path
whereas the actual splitting decision can usually be done at compile-time.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21118>
Alyssa Rosenzweig [Sat, 4 Feb 2023 01:53:41 +0000 (20:53 -0500)]
asahi: Fix encoding of uniform size
Only 6-bits, with zero=64 like a groups() encoding.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Suggested-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21118>
Alyssa Rosenzweig [Fri, 3 Feb 2023 23:42:29 +0000 (18:42 -0500)]
asahi: Set layout->mipmapped_z for 3D textures
There's a corner case where 3D textures have extra padding compared to 2D
arrays. We need to communicate that to ail.
Fixes
dEQP-GLES3.functional.texture.specification.texstorage3d.size.3d_32x16x64_4_levels.
That test now uses the same layout as Metal.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21114>
Alyssa Rosenzweig [Fri, 3 Feb 2023 23:54:48 +0000 (18:54 -0500)]
ail: Test 63x63 cube map
This has a subtle interaction with page-aligned layers. Written while debugging
dEQP-GLES3.functional.texture.filtering.cube.combinations.nearest_nearest_repeat_clamp
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21114>
Alyssa Rosenzweig [Fri, 3 Feb 2023 23:47:53 +0000 (18:47 -0500)]
ail: Test mipmapped_z behaviour
The mipmapped_z = true case is checked against Metal, the false case is smoke
testing the old behaviour (which is still used for 2D arrays).
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21114>
Alyssa Rosenzweig [Fri, 3 Feb 2023 23:46:20 +0000 (18:46 -0500)]
ail: Add layout->mipmapped_z input
For 3D images, the full miptree depends on the depth of the image, in contrast
to 2D arrays. We need to account for this to calculate the correct layer
strides.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21114>
Sergi Blanch Torne [Wed, 25 Jan 2023 11:54:57 +0000 (12:54 +0100)]
ci: disable Collabora's LAVA lab for maintance
This is to inform you of some planned downtime in the LAVA lab as follows:
Start: 2023-02-04 06:00 GMT
End: 2023-02-06 12:00 GMT
Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21119>
Ian Romanick [Tue, 22 Feb 2022 18:22:12 +0000 (10:22 -0800)]
nir: Eliminate nir_op_f2b
Builds on the work of !15121. This gets to delete even more code
because many drivers shared a lot of code for i2b and f2b.
No shader-db or fossil-db changes on any Intel platform.
v2: Rebase on
1a35acd8d9006c9.
v3: Update a comment in nir_opcodes_c.py. Suggested by Konstantin.
v4: Another rebase. Remove f2b stuff from Midgard.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20509>
Ian Romanick [Wed, 2 Nov 2022 01:28:46 +0000 (18:28 -0700)]
nir/builder: Handle f2b conversions specially in nir_type_convert
No shader-db or fossil-db changes on any Intel platform.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20509>
Ian Romanick [Tue, 22 Feb 2022 20:07:04 +0000 (12:07 -0800)]
nir/builder: Eliminate nir_f2b helper (and use of nir_f2b32 helper)
There were only two users. Replace each with nir_fneu instead.
This is now a squash of what was two separate commits.
nir_lower_pstipple_block is called after nir_lower_bool_to_int32, so
nir_fneu32 has to be used here or there will be regresssions in stipple
tests on llvmpipe.
v2: Rebase on !20869.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Suggested-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20509>
Mike Blumenkrantz [Fri, 3 Feb 2023 18:09:34 +0000 (13:09 -0500)]
zink: add back VK_DESCRIPTOR_BINDING_PARTIALLY_BOUND_BIT for bindless
this was accidentally lost in refactor
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21100>
Mike Blumenkrantz [Fri, 3 Feb 2023 15:10:36 +0000 (10:10 -0500)]
zink: handle missing line rasterization modes with ds3
it's annoying to validate this at runtime since it has to happen during draw,
but storing the "usable" ds3 mode separately from the pipeline state should
be a reasonable enough compromise for perf here...hopefully
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21100>
Mike Blumenkrantz [Fri, 3 Feb 2023 15:09:03 +0000 (10:09 -0500)]
zink: cache and reuse dummy inputattachment for fbfetch
apparently an actual null descriptor is illegal here, and it's wasted cpu
anyway, so just cache the dummy surface on init and use that data when
fbfetch isn't active but the layout requires it
Fixes:
7ab5c5d36d2 ("zink: use EXT_descriptor_buffer with ZINK_DESCRIPTORS=db")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21100>
Mike Blumenkrantz [Fri, 3 Feb 2023 15:06:32 +0000 (10:06 -0500)]
zink: fix more cases of heap/memtype suballocator mismatch
suballocation must happen based on the memtype, so also add some asserts to
ensure the slab bos are always what the caller expects
Fixes:
f6d3a5755f6 ("zink: zink_heap isn't 1-to-1 with memoryTypeIndex")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21100>
Mike Blumenkrantz [Fri, 3 Feb 2023 13:42:22 +0000 (08:42 -0500)]
zink: free descriptor buffer maps on batch state destroy
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21100>
SoroushIMG [Mon, 30 Jan 2023 18:53:19 +0000 (18:53 +0000)]
zink: fix sparse residency query and minLOD feature checks
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21013>
Yiwei Zhang [Fri, 3 Feb 2023 10:29:16 +0000 (10:29 +0000)]
venus: lazily query and cache gralloc front rendering usage
When skiavk is the default system ui renderer, venus icd gets preloaded
into Zygote. However, Zygote access to render node is normally denied by
selinux except for legacy bootanimation purpose. This change fixes venus
icd loading to avoid invoking cros gralloc driver loading by moving the
perform op outside, so that we still get the memory footprint win.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21107>