Kever Yang [Fri, 19 Jul 2019 10:01:11 +0000 (18:01 +0800)]
rockchip: sdhci: Fix sdhci mmc driver probe abort
This patch fix mmc driver abort caused by below patch:
3d296365e4 mmc: sdhci: Add support for sdhci-caps-mask
After the patch sdhci_setup_cfg() access to host->mmc->dev,
so we have to do init before make the call to the function()
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Chris Webb [Tue, 16 Jul 2019 19:53:26 +0000 (20:53 +0100)]
rockchip: Remove obsolete references to pyelftools
make_fit_atf.py no longer requires pyelftools, and nothing else in the
rockchip build requires it either, so remove references to installing it
from the documentation.
Signed-off-by: Chris Webb <chris@arachsys.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Chris Webb [Tue, 16 Jul 2019 19:52:57 +0000 (20:52 +0100)]
rockchip: make_fit_atf.py: Eliminate pyelftools dependency
make_fit_aft.py depends on the non-standard library pyelftools to pull
out PT_LOAD segments from ELF files. However, this is as easy to do
manually, without imposing the extra dependency on users.
Structures in the ELF file are unpacked into variables named to exactly
match the ELF spec to ensure the destructuring code is reasonably
self-documenting.
Signed-off-by: Chris Webb <chris@arachsys.com>
Reviewed-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Kever Yang [Tue, 16 Jul 2019 12:40:17 +0000 (20:40 +0800)]
rockchip: enable rk322x TPL_BOOTROM_SUPPORT in Kconfig
The TPL_BOOTROM_SUPPORT is needed for boot from bootrom like
other storages.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Niklas Schulze [Sun, 14 Jul 2019 10:40:13 +0000 (10:40 +0000)]
rockchip: video: rk3288_hdmi: Add missing call to dw_hdmi_enable()
The RK3288 HDMI driver's rk3288_hdmi_enable() currently lacks a call to
dw_hdmi_enable(). Thus, the HDMI output never gets enabled.
Signed-off-by: Niklas Schulze <me@jns.io>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Kever Yang [Tue, 9 Jul 2019 14:06:01 +0000 (22:06 +0800)]
rockchip: rk3399: use common TPL board file
Use common tpl.c instead of rk3399-board-tpl.c
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 14:06:00 +0000 (22:06 +0800)]
rockchip: rk3399: remove TPL_BOARD_INIT
RK3399 TPL do not need a dedicate board init, print the firmware
info when debug init instead.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 14:05:59 +0000 (22:05 +0800)]
rockchip: rk3399: use common secure_timer_init() for spl/tpl
SPL/TPL share the same secure_timer_init(), update to use
one copy source code and update to use CONFIG_ROCKCHIP_STIMER_BASE
as base address and rename to function name to rockchip_stimer_init().
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 14:05:58 +0000 (22:05 +0800)]
rockchip: rk3368: use common TPL board file
Use common tpl.c instead of rk3368-board-tpl.c
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 14:05:57 +0000 (22:05 +0800)]
rockchip: rk3288: use common TPL board file
Use Common tpl.c instead of rk3288-board-tpl.c
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 14:05:56 +0000 (22:05 +0800)]
rockchip: rk322x: use common TPL board file
Use Common tpl.c instead of rk322x-board-tpl.c
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 14:05:55 +0000 (22:05 +0800)]
rockchip: add common tpl board file
Rockchip SoCs have similar boot process, prefer to use TPL for DRAM
init and back to bootrom, and SPL as Trust ATF/U-Boot loader. TPL
common board is a basic TPL board init which can be shared for most
of SoCs to avoid copy-pase for different SoCs.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 14:00:33 +0000 (22:00 +0800)]
rockchip: evb-px5: switch to use ARM generic timer
Default to use ARM generic timer in ARM64, switch from
rk timer to generic timer.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 14:00:32 +0000 (22:00 +0800)]
rockchip: rk3368-lion: switch to use ARM generic timer
Default to use ARM generic timer in ARM64, switch from
rk timer to generic timer.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 14:00:31 +0000 (22:00 +0800)]
rockchip: rk3368: enable stimer for rk3368
Add stimer_init() for spl/tpl so that we able to switch
to use arch timer.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 14:00:30 +0000 (22:00 +0800)]
rockchip: rk3368: move sgrf init to spl as arch_cpu_init()
The SoC related init will move to SPL and keep TPL clean,
so that we can reuse the common TPL board file.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 14:00:29 +0000 (22:00 +0800)]
rockchip: remove rk_timer
We have convert all SoC to use DM timer or ARM arch/generic
timer, we can remove this rk_timer now.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 14:00:28 +0000 (22:00 +0800)]
rockchip: remove no use header file in board code
The timer.h is no use any more, remove it from the board files.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 14:00:27 +0000 (22:00 +0800)]
rockchip: rk3128: use ARM arch timer instead of rk_timer
We prefer to use ARM arch timer instead of rockchip timer, so that
we are using the same timer for SPL, U-Boot and Kernel, which will
make things simple and easy to track to boot time.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 14:00:26 +0000 (22:00 +0800)]
rockchip: rk3288: use ARM arch timer instead of rk_timer
We prefer to use ARM arch timer instead of rockchip timer, so that
we are using the same timer for SPL, U-Boot and Kernel, which will
make things simple and easy to track to boot time.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 14:00:25 +0000 (22:00 +0800)]
rockchip: rk3036: use ARM arch timer instead of rk_timer
We prefer to use ARM arch timer instead of rockchip timer, so that
we are using the same timer for SPL, U-Boot and Kernel, which will
make things simple and easy to track the boot time.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 14:00:24 +0000 (22:00 +0800)]
rockchip: rk3036: sdram: use udelay instead of rockchip_udelay
Use system api for udelay instead of vendor defined api,
and rockchip_udelay() will be removed.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 14:00:23 +0000 (22:00 +0800)]
rockchip: rk322x: use ARM arch timer instead of rk_timer
We prefer to use ARM arch timer instead of rockchip timer, so that
we are using the same timer for SPL, U-Boot and Kernel, which will
make things simple and easy to track to boot time.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 14:00:22 +0000 (22:00 +0800)]
rockchip: rk322x: sdram: use udelay instead of rockchip_udelay
Use system api for udelay instead of vendor defined api,
and rockchip_udelay() will be removed.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 13:58:55 +0000 (21:58 +0800)]
rockchip: board: rk3288: remove board_boot_order()
Prefer to use dts config instead, remove all board_boot_order()
for rk3288 boards.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 13:58:54 +0000 (21:58 +0800)]
rockchip: rk3288: dts: enable spl-boot-order
We share the same default SPL boot order for all rk3288 boards,
use dts instead of hard code in board file.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Wed, 17 Jul 2019 10:12:20 +0000 (18:12 +0800)]
rockchip: spl-boot-order: update dependency to OF_LIBFDT
The fdt interfaces are actuall depends on OF_LIBFDT instead
of OF_CONTROL, some boards may enable OF_CONTROL while disable
OF_LIBFDT.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 13:58:53 +0000 (21:58 +0800)]
rockchip: popmetal-rk3288: add -u-boot.dtsi
Move U-Boot relate dts node/property into -u-boot.dtsi
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 13:58:52 +0000 (21:58 +0800)]
rockchip: miqi-rk3288: add -u-boot.dtsi
Move U-Boot relate dts node/property into -u-boot.dtsi
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 13:58:51 +0000 (21:58 +0800)]
rockchip: rk3288-firefly: sync sdmmc pinctrl from mainline
The rk3288-firefly board have different setting for sdmmc
io, sync then from kernel mainline:
6fbc7275c7a9 Linux 5.2-rc7
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 13:58:50 +0000 (21:58 +0800)]
rockchip: firefly-rk3288: add -u-boot.dtsi
Move U-Boot relate dts node/property into -u-boot.dtsi
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 13:58:49 +0000 (21:58 +0800)]
rockchip: rk3288: update u-boot raw image size for all boards
Some rk3288 boards are using raw image of u-boot.bin, and now
it's much bigger than default 200KB, update CONFIG_SYS_MONITOR_LEN
to 600KB.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 13:58:48 +0000 (21:58 +0800)]
rockchip: fennec-rk3288: add -u-boot.dtsi
Move U-Boot relate dts node/property into -u-boot.dtsi
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 13:58:47 +0000 (21:58 +0800)]
rockchip: evb-rk3288: add -u-boot.dtsi
Move U-Boot relate dts node/property into -u-boot.dtsi
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 13:58:46 +0000 (21:58 +0800)]
rockchip: rk3288: enable TPL for evb-rk3288
Enable TPL for evb-rk3288 so that we can have a free size limited
SPL.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 13:58:45 +0000 (21:58 +0800)]
rockchip: rk3288: add default TPL_LDSCRIPT value in Kconfig
We share the same TPL_LDSCRIPT for all rk3288 board, add
default value in Kconfig.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 13:58:44 +0000 (21:58 +0800)]
rockchip: rk3288: move configure_l2ctlr back to rk3288
The configure_l2ctlr() is used only by rk3288, do not need to
locate in sys_proto.h
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 13:58:43 +0000 (21:58 +0800)]
rockchip: rk3288: add arch_cpu_init in spl
Add arch_cpu_init() in SPL for soc related init, and
move configure_l2ctlr() into it.
The arch_cpu_init() only need to run once, so no need
to run in TPL.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 14:14:29 +0000 (22:14 +0800)]
rockchip: rk3368: default enable SPL LIBCOMMON and LIBGENERIC
We needs SPL LIBCOMMON and LIBGENERIC for all boards,
so we can enable them by default and no need to define
in each board.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 14:14:28 +0000 (22:14 +0800)]
rockchip: rk322x: default enable SPL LIBCOMMON and LIBGENERIC
We needs SPL LIBCOMMON and LIBGENERIC for all boards,
so we can enable them by default and no need to define
in each board.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 14:14:27 +0000 (22:14 +0800)]
rockchip: rk3328: default enable SPL LIBCOMMON and LIBGENERIC
We needs SPL LIBCOMMON and LIBGENERIC for all boards,
so we can enable them by default and no need to define
in each board.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 14:14:26 +0000 (22:14 +0800)]
rockchip: rk3399: default enable SPL LIBCOMMON and LIBGENERIC
We needs SPL LIBCOMMON and LIBGENERIC for all boards,
so we can enable them by default and no need to define
in each board.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 14:14:25 +0000 (22:14 +0800)]
rockchip: rk3368: use defaule value for SYS_MALLOC_F_LEN
There is no difference in rk3368 board use for SYS_MALLOC_F_LEN,
so we can use default value.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 14:14:24 +0000 (22:14 +0800)]
rockchip: rk3328: use defaule value for SYS_MALLOC_F_LEN
There is no difference in rk3328 board use for SYS_MALLOC_F_LEN,
so we can use default value.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 14:14:23 +0000 (22:14 +0800)]
rockchip: rk3399: use default value for SYS_MALLOC_F_LEN
There is no difference in rk3399 board use for SYS_MALLOC_F_LEN,
so we can use default value.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 14:14:22 +0000 (22:14 +0800)]
rockchip: rk3288: use default value for SYS_MALLOC_F_LEN
There is no difference in rk3288 board use for SYS_MALLOC_F_LEN,
so we can use default value.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 14:14:21 +0000 (22:14 +0800)]
rockchip: rk322x: use defconfig for SYS_MALLOC_F_LEN
There is no difference in rk322x board use for SYS_MALLOC_F_LEN,
so we can use default value.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 14:14:20 +0000 (22:14 +0800)]
rockchip: Kconfig: move ROCKCHIP_BOOT_MODE_REG to soc Kconfig
Rockchip SoCs have different ROCKCHIP_BOOT_MODE_REG value,
move it to SoC's own Kconfig, and add address for rk3128 and
rk3328 so that all SoCs have available address.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 14:14:19 +0000 (22:14 +0800)]
rockchip: Kconfig: move rk3399 config into its Kconfig
Each SoC have its config setting and its Kconfig, move
the specific setting to its own Kconfig file.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 14:14:18 +0000 (22:14 +0800)]
rockchip: Kconfig: move rk3368 config into its Kconfig
Each SoC have its config setting and its Kconfig, move
the specific setting to its own Kconfig file.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 14:14:17 +0000 (22:14 +0800)]
rockchip: Kconfig: move rk3288 config into its Kconfig
Each SoC have its config setting and its Kconfig, move
the specific setting to its own Kconfig file.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 14:14:16 +0000 (22:14 +0800)]
rockchip: Kconfig: move rk322x config into its Kconfig
Each SoC have its config setting and its Kconfig, move
the specific setting to its own Kconfig file.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 14:14:15 +0000 (22:14 +0800)]
rockchip: fixup board choice in Kconfig
Kconfig for board target select is choice option, fixup for
rk3036, rk3288 and rv1108.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 13:55:30 +0000 (21:55 +0800)]
rockchip: remove redundant pinctrl header including
No code is using this header file, remove it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 13:55:29 +0000 (21:55 +0800)]
rockchip: rk3288: remove pinctrl init in spl_board_init
The pinctrl will default init the io while driver is probe
with new pinctrl driver.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 13:55:28 +0000 (21:55 +0800)]
rockchip: rk3188: remove pinctrl init in spl_board_init
The pinctrl will default init the io while driver is probe
with new pinctrl driver.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 9 Jul 2019 13:55:27 +0000 (21:55 +0800)]
rockchip: rk3399: remove pinctrl init in spl_board_init
The pinctrl will default init the io while driver is probe
with new pinctrl driver.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:45 +0000 (17:27 +0530)]
rockchip: dts: rk3399: rock-pi-4: Use LPDDR4-100 dtsi
Use LPDDR4-100 sdram timings dtsi for RockPI-4 board.
All these timings are processed during TPL stage of rock-pi-4 board,
bootchain. This make TPL would replace rockchip in house rkbin in
current bootchain.
Bootchain after and before this change:
TPL -> SPL -> U-Boot proper
rkbin -> SPL -> U-Boot proper
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Mon, 15 Jul 2019 18:28:56 +0000 (23:58 +0530)]
rockchip: dts: rk3399: nanopi-neo4: Use DDR3-1866 dtsi
Use DDR3-1866 2GB ddr timings dtsi for 1GB NanoPi Neo4 board.
Since sdram rk3399 support dynamic stride and rank detection it
can able to detect 1GB ddr eventough the timings are meant for
dual channel, 2GB size.
Bootchain after and before this change are:
TPL -> SPL -> U-Boot proper
rkbin -> SPL -> U-Boot proper
This certainly fix the second channel data training initialization
since we have dynamic rank, stride where second channel capabilities
are clear or memset to 0.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:44 +0000 (17:27 +0530)]
rockchip: dts: rk3399: rockpro64: Use LPDDR4-100 dtsi
Use LPDDR4-100 sdram timings dtsi for Rockpro64 board.
All these timings are processed during TPL stage of rockpro64 board,
bootchain. This make TPL would replace rockchip in house rkbin in
current bootchain.
Bootchain after and before this change:
TPL -> SPL -> U-Boot proper
rkbin -> SPL -> U-Boot proper
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:43 +0000 (17:27 +0530)]
rockchip: dts: rk3399: Add LPDDR4-100 timings
Add sdram timings for LPDDR4-100 via rk3399-sdram-lpddr4-100.dtsi file.
all timings are dumped from rkbin/bin/rk33/rk3399_ddr_800MHz_v1.20.bin
Associated LPDDR4 board -u-boot.dtsi can include this to make these
timings available during SPL or TPL stages.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:42 +0000 (17:27 +0530)]
configs: rock-pi-4: Enable LPDDR4 support
Due to foot-print issues, we have LPDDR4 code can be
marked as CONFIG_RAM_RK3399_LPDDR4.
So, enable it for Rock-PI-4 board.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:41 +0000 (17:27 +0530)]
configs: rockpro64: Enable LPDDR4 support
Due to foot-print issues, we have LPDDR4 code can be
marked as CONFIG_RAM_RK3399_LPDDR4.
So, enable it for Rockpro64 board.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:40 +0000 (17:27 +0530)]
ram: rk3399: Add lpddr4 set rate support
Unlike rest of dram type chips, LPDDR4 initialization start
with at board selected frequency (say 50MHz) and then it
switches into 400MHz and 800MHz simultaneously to make the
proper sequence work on each channel with associated training.
The lpddr4 set rate sequnce will follow by setting lpddr4
- dq out
- ca odt
- MR3
- MR12
- MR14
registers sets in sequential order.
Here is sameple log about LPDDR4-100 init sequence in Rockpro64:
Channel 0: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
Channel 1: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
256B stride
channel 0 training pass
channel 1 training pass
change freq to 400 MHz 0, 1
channel 0 training pass
channel 1 training pass
change freq to 800 MHz 1, 0
This patch add support to this init sequence via lpddr4 set rate
by taking sdram timing parameters from 400, 800 .inc files.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(Fix travis error, use one ret instead of ret[2] in set_ctrl)
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:39 +0000 (17:27 +0530)]
ram: rk3399: Add set_rate sdram rk3399 ops
DDR set rate can be even required for lpddr4 and we
need to keep the lpddr4 code to compile only for relevant
boards which do support lpddr4.
For this requirement, and for code readability handle
data training via sdram_rk3399_ops with .set_rate and
same will update in future while supporting lpddr4 code.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:38 +0000 (17:27 +0530)]
ram: rk3399: Add LPPDDR4-800 timings inc
LPDDR4 initialization start with at board selected frequency
and then it switches into 400MHz and 800MHz simultaneously to
make the proper sequence work on each channel with associated
training.
So, add LPDDR4-800 timings inc file in driver area so-that
these timings will take during LPDDR4 initialization phase.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:37 +0000 (17:27 +0530)]
ram: rk3399: Add LPPDDR4-400 timings inc
LPDDR4 initialization start with at board selected frequency
and then it switches into 400MHz and 800MHz simultaneously to
make the proper sequence work on each channel with associated
training.
So, add LPDDR4-400 timings inc file in driver area so-that
these timings will take during LPDDR4 initialization phase.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:36 +0000 (17:27 +0530)]
clk: rockchip: rk3399: Set 400MHz ddr clock
Add support for setting 400MHz ddr clock.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:35 +0000 (17:27 +0530)]
clk: rockchip: rk3399: Set 50MHz ddr clock
Add support for setting 50MHz ddr clock.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:34 +0000 (17:27 +0530)]
rockchip: dts: rk3399: Add u-boot, dm-pre-reloc for pmu
Add u-boot,dm-pre-reloc property for pmu in rk3399-u-boot.dtsi
so-that SPL can access pmu.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:33 +0000 (17:27 +0530)]
rockchip: rk3399: syscon: Add pmu support
Add pmu compatible with relevant U_BOOT_DRIVER for rk3399
via syscon rk3399 driver.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:32 +0000 (17:27 +0530)]
arm: include: rockchip: Add rk3399 pmu file
Add pmu header file for rk3399 SoC, this will help
to configure pmu in sdram driver.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:31 +0000 (17:27 +0530)]
ram: rk3399: Add LPPDR4 mr detection
Like data training in other sdram types, mr detection need
to taken care for lpddr4 with looped rank and associated
channel to make sure the proper configuration held.
Once the mr detection successful for active and configured
rank with channel number, the same can later reused during
actual LPDDR4 initialization.
So, add code to support for it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:30 +0000 (17:27 +0530)]
ram: rk3399: Handle data training via ops
data training can be even required for lpddr4 and we
need to keep the lpddr4 code to compile only for relevant
boards which do support lpddr4.
For this requirement, and for code readability handle
data training via sdram_rk3399_ops and same will update
in future while supporting lpddr4 code.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:29 +0000 (17:27 +0530)]
ram: rk3399: Simplify data training first argument
data training is using chan_info as first argument with
channel number as second argument instead of that use
dram_info as first argument so-that we can get the
chan_info at data training definition.
This was the argument handling is meaningful, readable
and it would help to add similar data training for
lpddr4 in future.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:28 +0000 (17:27 +0530)]
ram: rk3399: Update lpddr4 vref_mode_ac
Update vref_mode_ac for lpddr4 based on VDDQ/3/2=16.8%
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:27 +0000 (17:27 +0530)]
ram: rk3399: Update lpddr4 mode_sel based on io settings
The mode_sel on lpddr4 value is depending on IO settings
of rd_vref.
Add support for it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:26 +0000 (17:27 +0530)]
ram: rk3399: Update lpddr4 vref based on io settings
The vref_mode_dq, vref_value_dq on lpddr4 value is depending
on IO settings of rd_vref.
Add support for it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:25 +0000 (17:27 +0530)]
ram: rk3399: Get lpddr4 tsel_rd_en from io settings
For base.odt 1 the lpddr4 tsel_rd_en value is depending
on IO settings of rd_odt_en.
Add support for it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:24 +0000 (17:27 +0530)]
ram: rk3399: Configure soc odt support
CTL 145, 146, 159, 160 registers are used to configure
soc odt on rk3399.
These soc odt values are updated from CS0_MR22_VAL and
CS1_MR22_VAL and for lpddr4 these values ORed with
tsel_rd_select_n.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:23 +0000 (17:27 +0530)]
ram: rk3399: Add tsel control clock drive
tsel contrl clock drives are required to configure PHY
929, 939 controls drive settings.
Add support for these control clock for all dramtype
sdrams.
Thse control clock drives are configure via tsel_ckcs_select_p
and tsel_ckcs_select_n variables.
tsel_ckcs_select_n is PHY_DRV_ODT_34_3 value where as
tsel_ckcs_select_p is retrived from IO settings for lpddr4
and rest uses PHY_DRV_ODT_34_3.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:22 +0000 (17:27 +0530)]
ram: sdram: Configure lpddr4 tsel rd, wr based on IO settings
Now we have IO settings available for all supported sdram
frequencies, so retrieve these IO settings and make used
for LPDDR4 ds odt configuration.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:21 +0000 (17:27 +0530)]
ram: rk3399: Add IO settings
Add IO settings for dram ctl and phy.
IO settings are useful for configuring ctl, phy odt, vref,
mr5, mode select and other needed input output operations
for lpddr4 or any other dramtype sdram.
Right now, this patch added IO setting for all supported
sdram frequencies.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:20 +0000 (17:27 +0530)]
ram: rk3399: Don't disable dfi dram clk for lpddr4, rank 1
The hardware for LPDDR4 with
- CLK0P/N connect to lower 16-bits
- CLK1P/N connect to higher 16-bits
and usually dfi dram clk is configured via CLK1P/N, so
disabling dfi dram clk will disable the CLK1P/N as well.
So, add patch to not to disable dfi dram clk for lpddr4,
with rank 1.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:19 +0000 (17:27 +0530)]
ram: rk3399: Configure tsel write ca for lpddr4
tsel write ca_p and ca_n values need to write on PHY 544, 672
and 800 to configure ds odt.
Configure the same PHY register for lpddr4 would require a mask
value of (300 << 8).
Add support for it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:18 +0000 (17:27 +0530)]
ram: rk3399: Map chipselect for lpddr4
Assign desired cs_map values for lpddr4 during set memory map.
Initial cs_map values is based on the sdram parameters, so
the same will adjusted based dramtype as LPDDR4.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:17 +0000 (17:27 +0530)]
ram: rk3399: Configure PHY RX_CM_INPUT for lpddr4
Configure PHY RX_CM_INPUT for lpddr4 during phy IO config.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:16 +0000 (17:27 +0530)]
ram: rk3399: Configure SLEWP_EN, SLEWN_EN for lpddr4
Configure SLEWP_EN, SLEWN_EN for lpddr4 during phy IO config.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:15 +0000 (17:27 +0530)]
ram: rk3399: Configure BOOSTP_EN, BOOSTN_EN for lpddr4
Configure BOOSTP_EN, BOOSTN_EN for lpddr4 during phy IO config.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:14 +0000 (17:27 +0530)]
ram: rk3399: Configure PHY_898, PHY_919 for lpddr4
PHY_898, PHY_919 would require to configure PHY LP4 boot
pll control and ca for lpddr4.
So, configure the same in pctl_cfg for LPDDR4.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:13 +0000 (17:27 +0530)]
ram: rk3399: Avoid two channel ZQ Cal Start at the same time
It is possible in lpddr4 dram, where both the channels would
start at same time with ZQ Cal Start. If it uses ZQ Call start
then it will use RZQ.
For example LPDDR4 366 Dual-Die, Quad-Channel Package, RZQ maybe
connect to both channel. If ZQ Cal Start at the same time,
it will use the same RZQ.
It is not a problem of using RZQ in both the channels, but can not
use at the same time.
So, to avoid this, we have an option of dram tINIT3 value for
increasing the frequency for channel 1.
This patch increase the available tINIT3 with existing running
dram frequency.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:12 +0000 (17:27 +0530)]
ram: rk3399: Don't wait for PLL lock in lpddr4
lpddr4 has PLL bypass mode during phy initialization phase,
which does all pll configurations.
So no need to wait explicitly during pctl config.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:11 +0000 (17:27 +0530)]
ram: rk3399: Move mode_sel assignment
mode_sel assignment is based on dram type.
In phy_io_config, already have vref setting based
on the dram type, so move this mode_sel assignment
on vref setting area.
No functionality change.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:10 +0000 (17:27 +0530)]
ram: rk3399: Add lpddr4 rank mask for wdql training
Add rank_mask based on the rank number for lpddr4.
This would keep the wdql data training loop based on the
desired rank mask value instead of looping for all values.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:09 +0000 (17:27 +0530)]
ram: rk3399: Add lpddr4 rank mask for ca training
Add rank_mask based on the rank number for lpddr4.
This would keep the ca data training loop based on the
desired rank mask value instead of looping for all values.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:08 +0000 (17:27 +0530)]
ram: rockchip: Kconfig: Add RK3399 LPDDR4 entry
Supporting LPDDR4 code support in RK3399 would increases
the size of SPL/TPL.
So add kconfig entry for RK3399 LPDDR4 code so-that
the boards have LPDDR4 can enable them via defconfig.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:07 +0000 (17:27 +0530)]
ram: rk3399: Configure phy IO in ds odt
Some dramtypes like lpddr4 initialization would required to
configure phy IO even after pctl_cfg and after set_ds_odt.
For those cases the set_ds_odt would be an initial call to
setup the phy.
To satisfy all the cases, trigger phy IO from set_ds_odt.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:06 +0000 (17:27 +0530)]
ram: rk3399: Add DdrMode
Add DdrMode structure with associated bit fields.
These would help to reconfigure sdram capabilities during
lpddr4 setup related configs.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:05 +0000 (17:27 +0530)]
ram: rk3399: Add ddrtimingC0
Add DdrTimingC0 structure with associated bit fields.
These would help to reconfigure sdram capabilities during
lpddr4 setup related configs.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
Jagan Teki [Tue, 16 Jul 2019 11:57:04 +0000 (17:27 +0530)]
ram: rk3399: Add ddr version enc macro
Add dram config macro for handling ddr version number.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
projects / platform / kernel / u-boot.git / log