Douglas Yung [Mon, 9 Sep 2019 20:12:29 +0000 (20:12 +0000)]
Relax opcode checks in test to check for only a number instead of a specific number.
llvm-svn: 371447
Julian Lettner [Mon, 9 Sep 2019 20:07:03 +0000 (20:07 +0000)]
[TSan] Add AnnotateIgnoreReadsBegin declaration to tsan/test.h
Declare the family of AnnotateIgnore[Read,Write][Begin,End] TSan
annotations in compiler-rt/test/tsan/test.h so that we don't have to
declare them separately in every test that needs them. Replace usages.
Leave usages that explicitly test the annotation mechanism:
thread_end_with_ignore.cpp
thread_end_with_ignore3.cpp
llvm-svn: 371446
Philip Reames [Mon, 9 Sep 2019 20:06:19 +0000 (20:06 +0000)]
[SDAG] Add a isSimple cover functon to MemSDNode, just as we have in IR/MI [NFC]
Uses are in reviews D66322 and D66318. Submitted separately to control rebuild times.
llvm-svn: 371445
Pirama Arumuga Nainar [Mon, 9 Sep 2019 19:52:39 +0000 (19:52 +0000)]
[Driver] Handle default case in refactored addOpenMPRuntime
Summary:
Appease failed builds (due to -Werror and -Wswitch) where OMPRT_Unknown
is not handled in the switch statement (even though it's handled by the
early exit).
This fixes -Wswitch triggered by r371442.
Reviewers: srhines, danalbert, jdoerfert
Subscribers: guansong, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D67364
llvm-svn: 371444
Francis Visoiu Mistrih [Mon, 9 Sep 2019 19:47:25 +0000 (19:47 +0000)]
[Remarks] Fix warning for uint8_t < 0 comparison
http://lab.llvm.org:8011/builders/clang-with-thin-lto-ubuntu/builds/19109/steps/build-stage1-compiler/logs/stdio
llvm-svn: 371443
Max Moroz [Mon, 9 Sep 2019 19:30:48 +0000 (19:30 +0000)]
[UBSan] Do not overwrite the default print_summary sanitizer option.
Summary:
This option is true by default in sanitizer common. The default
false value was added a while ago without any reasoning in
https://github.com/llvm-mirror/compiler-rt/commit/
524e934112a593ac081bf2b05aa0d60a67987f05
so, presumably it's safe to remove for consistency.
Reviewers: hctim, samsonov, morehouse, kcc, vitalybuka
Reviewed By: hctim, samsonov, vitalybuka
Subscribers: delcypher, #sanitizers, llvm-commits, kcc
Tags: #llvm, #sanitizers
Differential Revision: https://reviews.llvm.org/D67193
llvm-svn: 371442
Philip Reames [Mon, 9 Sep 2019 19:23:22 +0000 (19:23 +0000)]
Introduce infrastructure for an incremental port of SelectionDAG atomic load/store handling
This is the first patch in a large sequence. The eventual goal is to have unordered atomic loads and stores - and possibly ordered atomics as well - handled through the normal ISEL codepaths for loads and stores. Today, there handled w/instances of AtomicSDNodes. The result of which is that all transforms need to be duplicated to work for unordered atomics. The benefit of the current design is that it's harder to introduce a silent miscompile by adding an transform which forgets about atomicity. See the thread on llvm-dev titled "FYI: proposed changes to atomic load/store in SelectionDAG" for further context.
Note that this patch is NFC unless the experimental flag is set.
The basic strategy I plan on taking is:
introduce infrastructure and a flag for testing (this patch)
Audit uses of isVolatile, and apply isAtomic conservatively*
piecemeal conservative* update generic code and x86 backedge code in individual reviews w/tests for cases which didn't check volatile, but can be found with inspection
flip the flag at the end (with minimal diffs)
Work through todo list identified in (2) and (3) exposing performance ops
(*) The "conservative" bit here is aimed at minimizing the number of diffs involved in (4). Ideally, there'd be none. In practice, getting it down to something reviewable by a human is the actual goal. Note that there are (currently) no paths which produce LoadSDNode or StoreSDNode with atomic MMOs, so we don't need to worry about preserving any behaviour there.
We've taken a very similar strategy twice before with success - once at IR level, and once at the MI level (post ISEL).
Differential Revision: https://reviews.llvm.org/D66309
llvm-svn: 371441
Matt Arsenault [Mon, 9 Sep 2019 18:57:51 +0000 (18:57 +0000)]
AMDGPU/GlobalISel: Legalize G_BUILD_VECTOR v2s16
Handle it the same way as G_BUILD_VECTOR_TRUNC. Arguably only
G_BUILD_VECTOR_TRUNC should be legal for this, but G_BUILD_VECTOR will
probably be more convenient in most cases.
llvm-svn: 371440
Julian Lettner [Mon, 9 Sep 2019 18:57:32 +0000 (18:57 +0000)]
[TSan] Add interceptors for mach_vm_[de]allocate
I verified that the test is red without the interceptors.
rdar://
40334350
Reviewed By: kubamracek, vitalybuka
Differential Revision: https://reviews.llvm.org/D66616
llvm-svn: 371439
Matt Arsenault [Mon, 9 Sep 2019 18:43:29 +0000 (18:43 +0000)]
AMDGPU: Make VReg_1 size be 1
This was getting chosen as the preferred 32-bit register class based
on how TableGen selects subregister classes.
llvm-svn: 371438
Pirama Arumuga Nainar [Mon, 9 Sep 2019 18:31:41 +0000 (18:31 +0000)]
[Driver] Add -static-openmp driver option
Summary:
For Gnu, FreeBSD and NetBSD, this option forces linking with the static
OpenMP host runtime (similar to -static-libgcc and -static-libstdcxx).
Android's NDK will start the shared OpenMP runtime in addition to the static
libomp. In this scenario, the linker will prefer to use the shared library by
default. Add this option to enable linking with the static libomp.
Reviewers: Hahnfeld, danalbert, srhines, joerg, jdoerfert
Subscribers: guansong, cfe-commits
Tags: #clang
Fixes https://github.com/android-ndk/ndk/issues/1028
Differential Revision: https://reviews.llvm.org/D67200
llvm-svn: 371437
Matt Arsenault [Mon, 9 Sep 2019 18:29:45 +0000 (18:29 +0000)]
AMDGPU/GlobalISel: Select llvm.amdgcn.class
Also fixes missing SubtargetPredicate on f16 class instructions.
llvm-svn: 371436
Matt Arsenault [Mon, 9 Sep 2019 18:29:37 +0000 (18:29 +0000)]
AMDGPU/GlobalISel: Select fmed3
llvm-svn: 371435
Eli Friedman [Mon, 9 Sep 2019 18:29:27 +0000 (18:29 +0000)]
[IfConversion] Correctly handle cases where analyzeBranch fails.
If analyzeBranch fails, on some targets, the out parameters point to
some blocks in the function. But we can't use that information, so make
sure to clear it out. (In some places in IfConversion, we assume that
any block with a TrueBB is analyzable.)
The change to the testcase makes it trigger a bug on builds without this
fix: IfConvertDiamond tries to perform a followup "merge" operation,
which isn't legal, and we somehow end up with a branch to a deleted MBB.
I'm not sure how this doesn't crash the compiler.
Differential Revision: https://reviews.llvm.org/D67306
llvm-svn: 371434
Sanjay Patel [Mon, 9 Sep 2019 18:14:10 +0000 (18:14 +0000)]
[x86] add test for false dependency with minsize (PR43239); NFC
llvm-svn: 371433
Matt Arsenault [Mon, 9 Sep 2019 18:10:31 +0000 (18:10 +0000)]
AMDGPU: Use PatFrags to allow selecting custom nodes or intrinsics
This enables GlobalISel to handle various intrinsics. The custom node
pattern will be ignored, and the intrinsic will work. This will also
allow SelectionDAG to directly select the intrinsics, but as they are
all custom lowered to the nodes, this ends up leaving dead code in the
table.
Eventually either GlobalISel should add the equivalent of custom nodes
equivalent, or intrinsics should be directly used. These each have
different tradeoffs.
There are a few more to handle, but these are easy to handle
ones. Some others fail for other reasons.
llvm-svn: 371432
Craig Topper [Mon, 9 Sep 2019 17:54:44 +0000 (17:54 +0000)]
[SelectionDAG] Remove ISD::FP_ROUND_INREG
I don't think anything in tree creates this node. So all of this
code appears to be dead.
Code coverage agrees
http://lab.llvm.org:8080/coverage/coverage-reports/llvm/coverage/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp.html
Differential Revision: https://reviews.llvm.org/D67312
llvm-svn: 371431
Craig Topper [Mon, 9 Sep 2019 17:48:05 +0000 (17:48 +0000)]
[X86] Allow _MM_FROUND_CUR_DIRECTION and _MM_FROUND_NO_EXC to be used together on instructions that only support SAE and not embedded rounding.
Current for SAE instructions we only allow _MM_FROUND_CUR_DIRECTION(bit 2) or _MM_FROUND_NO_EXC(bit 3) to be used as the immediate passed to the inrinsics. But these instructions don't perform rounding so _MM_FROUND_CUR_DIRECTION is just sort of a default placeholder when you don't want to suppress exceptions. Using _MM_FROUND_NO_EXC by itself is really bit equivalent to (_MM_FROUND_NO_EXC | _MM_FROUND_TO_NEAREST_INT) since _MM_FROUND_TO_NEAREST_INT is 0. Since we aren't rounding on these instructions we should also accept (_MM_FROUND_CUR_DIRECTION | _MM_FROUND_NO_EXC) as equivalent to (_MM_FROUND_NO_EXC). icc allows this, but gcc does not.
Differential Revision: https://reviews.llvm.org/D67289
llvm-svn: 371430
Francis Visoiu Mistrih [Mon, 9 Sep 2019 17:43:50 +0000 (17:43 +0000)]
[Remarks] Add parser for bitstream remarks
The bitstream remark serializer landed in r367372.
This adds a bitstream remark parser that parser bitstream remark files
to llvm::remarks::Remark objects through the RemarkParser interface.
A few interesting things to point out:
* There are parsing helpers to parse the different types of blocks
* The main parsing helper allows us to parse remark metadata and open an
external file containing the encoded remarks
* This adds a dependency from the Remarks library to the BitstreamReader
library
* The testing strategy is to create a remark entry through YAML, parse
it, serialize it to bitstream, parse that back and compare the objects.
* There are close to no tests for malformed bitstream remarks, due to
the lack of textual format for the bitstream format.
* This adds a new C API for parsing bitstream remarks:
LLVMRemarkParserCreateBitstream.
* This bumps the REMARKS_API_VERSION to 1.
Differential Revision: https://reviews.llvm.org/D67134
llvm-svn: 371429
Simon Atanasyan [Mon, 9 Sep 2019 17:28:45 +0000 (17:28 +0000)]
[mips] Fix decoding of microMIPS JALX instruction
microMIPS jump and link exchange instruction stores a target in a
26-bits field. Despite other microMIPS JAL instructions these bits
are target address shifted right 2 bits [1]. The patch fixes the
JALX instruction decoding and uses 2-bit shift.
[1] MIPS Architecture for Programmers Volume II-B: The microMIPS32 Instruction Set
Differential Revision: https://reviews.llvm.org/D67320
llvm-svn: 371428
Matt Arsenault [Mon, 9 Sep 2019 17:25:35 +0000 (17:25 +0000)]
AMDGPU: Move MnemonicAlias out of instruction def hierarchy
Unfortunately MnemonicAlias defines a "Predicates" field just like an
instruction or pattern, with a somewhat different interpretation.
This ends up overriding the intended Predicates set by
PredicateControl on the pseudoinstruction defintions with an empty
list. This allowed incorrectly selecting instructions that should have
been rejected due to the SubtargetPredicate from patterns on the
instruction definition.
This does remove the divergent predicate from the 64-bit shift
patterns, which were already not used for the 32-bit shift, so I'm not
sure what the point was. This also removes a second, redundant copy of
the 64-bit divergent patterns.
llvm-svn: 371427
Sanjay Patel [Mon, 9 Sep 2019 17:16:03 +0000 (17:16 +0000)]
[SLP] add test for over-vectorization (PR33958); NFC
llvm-svn: 371426
Jessica Paquette [Mon, 9 Sep 2019 17:15:56 +0000 (17:15 +0000)]
[GlobalISel][AArch64] Handle tail calls with non-void return types
Just return once you emit the call, which is exactly what SelectionDAG does in
this situation.
Update call-translator-tail-call.ll.
Also update dllimport.ll to show that we tail call here in GISel again. Add
-verify-machineinstrs to the GISel line too, to defend against verifier
failures.
Differential revision: https://reviews.llvm.org/D67282
llvm-svn: 371425
Matt Arsenault [Mon, 9 Sep 2019 17:13:44 +0000 (17:13 +0000)]
AMDGPU/GlobalISel: Implement LDS G_GLOBAL_VALUE
Handle the simple case that lowers to a constant.
llvm-svn: 371424
Matt Arsenault [Mon, 9 Sep 2019 17:04:18 +0000 (17:04 +0000)]
AMDGPU/GlobalISel: Legalize G_BUILD_VECTOR_TRUNC
Treat this as legal on gfx9 since it can use S_PACK_* instructions for
this.
This isn't used by anything yet. The same will probably apply to
16-bit G_BUILD_VECTOR without the trunc.
llvm-svn: 371423
Ilya Biryukov [Mon, 9 Sep 2019 17:03:49 +0000 (17:03 +0000)]
[clangd] Attempt to fix failing Windows buildbots.
The assertion is failing on Windows, probably because path separator is different.
For the failure see:
http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-windows10pro-fast/builds/28072/steps/test/logs/stdio
llvm-svn: 371422
Dmitri Gribenko [Mon, 9 Sep 2019 16:46:45 +0000 (16:46 +0000)]
Revert "[MachineCopyPropagation] Remove redundant copies after TailDup via machine-cp"
This reverts commit 371359. I'm suspecting a miscompile, I posted a
reproducer to https://reviews.llvm.org/D65267.
llvm-svn: 371421
Fangrui Song [Mon, 9 Sep 2019 16:45:17 +0000 (16:45 +0000)]
[yaml2obj] Simplify p_filesz/p_memsz computing
This fixes a bug as well. When "FileSize:" (p_filesz) is specified and
different from the actual value, the following code probably should not
use PHeader.p_filesz:
if (SHeader->sh_offset == PHeader.p_offset + PHeader.p_filesz)
PHeader.p_memsz += SHeader->sh_size;
Reviewed By: jhenderson
Differential Revision: https://reviews.llvm.org/D67256
llvm-svn: 371420
David Green [Mon, 9 Sep 2019 16:35:49 +0000 (16:35 +0000)]
[ARM] Fix loads and stores for predicate vectors
These predicate vectors can usually be loaded and stored with a single
instruction, a VSTR_P0. However this instruction will store the entire P0
predicate, 16 bits, zeroextended to 32bits. Each lane of the the
v4i1/v8i1/v16i1 representing 4/2/1 bits.
As far as I understand, when llvm says "store this v4i1", it really does need
to store 4 bits (or 8, that being the size of a byte, with this bottom 4 as the
interesting bits). For example a bitcast from a v8i1 to a i8 is defined as a
store followed by a load, which is how the code is expanded.
So this instead lowers the v4i1/v8i1 load/store through some shuffles to get
the bits into the correct positions. This, as you might imagine, is not as
efficient as a single instruction. But I believe it is needed for correctness.
v16i1 equally should not load/store 32bits, only storing the 16bits of data.
Stack loads/stores are still using the VSTR_P0 (as can be seen by the test not
changing). This is fine as they are self-consistent, it is only "externally
observable loads/stores" (from our point of view) that need to be corrected.
Differential revision: https://reviews.llvm.org/D67085
llvm-svn: 371419
Matt Arsenault [Mon, 9 Sep 2019 16:18:07 +0000 (16:18 +0000)]
AMDGPU/GlobalISel: Select atomic loads
A new check for an explicitly atomic MMO is needed to avoid
incorrectly matching pattern for non-atomic loads
llvm-svn: 371418
David Carlier [Mon, 9 Sep 2019 16:10:14 +0000 (16:10 +0000)]
LLDB - Simplify GetProgramFileSpec
Reviewers: zturner, emaste
Reviewed By: emaste
Differential Revision: https://reviews.llvm.org/D46518
llvm-svn: 371417
Matt Arsenault [Mon, 9 Sep 2019 16:06:37 +0000 (16:06 +0000)]
AMDGPU/GlobalISel: Fix RegBankSelect for unaligned, uniform constant loads
llvm-svn: 371416
Simon Pilgrim [Mon, 9 Sep 2019 16:05:59 +0000 (16:05 +0000)]
Fix typo in comment noticed in D60295. NFCI.
llvm-svn: 371415
Matt Arsenault [Mon, 9 Sep 2019 16:03:45 +0000 (16:03 +0000)]
AMDGPU/GlobalISel: Fix regbankselect for uniform extloads
There are no scalar extloads.
llvm-svn: 371414
Matt Arsenault [Mon, 9 Sep 2019 16:02:07 +0000 (16:02 +0000)]
AMDGPU: Remove code address space predicates
Fixes 8-byte, 8-byte aligned LDS loads. 16-byte case still broken due
to not be reported as legal.
llvm-svn: 371413
Matt Arsenault [Mon, 9 Sep 2019 15:46:13 +0000 (15:46 +0000)]
AMDGPU/GlobalISel: Select G_PTR_MASK
llvm-svn: 371412
Matt Arsenault [Mon, 9 Sep 2019 15:44:16 +0000 (15:44 +0000)]
AMDGPU/GlobalISel: Fix reg bank for uniform LDS loads
The pointer is always a VGPR. Also fix hardcoding the pointer size to
64.
llvm-svn: 371411
Diogo N. Sampaio [Mon, 9 Sep 2019 15:39:45 +0000 (15:39 +0000)]
[NFC] Add aacps bitfields access test
llvm-svn: 371410
Matt Arsenault [Mon, 9 Sep 2019 15:39:32 +0000 (15:39 +0000)]
AMDGPU/GlobalISel: Use known bits for selection
llvm-svn: 371409
Ilya Biryukov [Mon, 9 Sep 2019 15:32:51 +0000 (15:32 +0000)]
[clangd] Use pre-populated mappings for standard symbols
Summary:
This takes ~5% of time when running clangd unit tests.
To achieve this, move mapping of system includes out of CanonicalIncludes
and into a separate class
Reviewers: sammccall, hokein
Reviewed By: sammccall
Subscribers: MaskRay, jkorous, arphaman, kadircet, jfb, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D67172
llvm-svn: 371408
Matt Arsenault [Mon, 9 Sep 2019 15:20:49 +0000 (15:20 +0000)]
AMDGPU/GlobalISel: Legalize wavefrontsize intrinsic
llvm-svn: 371407
Matt Arsenault [Mon, 9 Sep 2019 15:20:44 +0000 (15:20 +0000)]
AMDGPU/GlobalISel: Try generated matcher before add/sub code
This will allow optimization patterns which fold adds away to work.
llvm-svn: 371406
Simon Tatham [Mon, 9 Sep 2019 15:17:26 +0000 (15:17 +0000)]
[ARM] Remove some spurious MVE reduction instructions.
The family of 'dual-accumulating' vector multiply-add instructions
(VMLADAV, VMLALDAV and VRMLALDAVH) can all operate on both signed and
unsigned integer types, and they all have an 'exchange' variant (with
an X in the name) that modifies which pairs of vector lanes in the two
inputs are multiplied together. But there's a clause in the spec that
says that the X variants //don't// operate on unsigned integer types,
only signed. You can have X, or unsigned, or neither, but not both.
We didn't notice that clause when we implemented the MC support for
these instructions, so LLVM believes that things like VMLADAVX.U8 do
exist, contradicting the spec. Here I fix that by conditioning them
out in Tablegen.
In order to do that, I've reversed the nesting order of the Tablegen
multiclasses for those instructions. Previously, the innermost
multiclass generated the X and not-X variants, and the one outside
that generated the A and not-A variants. Now X is done by the outer
multiclass, which allows me to bypass that one when I only want the
two not-X variants.
Changing the multiclass nesting order also changes the names of the
instruction ids unless I make a special effort not to. I decided that
while I was changing them anyway I'd make them look nicer; so now the
instructions have names like MVE_VMLADAVs32 or MVE_VMLADAVaxs32,
instead of cumbersome _noacc_noexch suffixes.
The corresponding multiply-subtract instructions are unaffected. Those
don't accept unsigned types at all, either in the spec or in LLVM.
Reviewers: ostannard, dmgreen
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67214
llvm-svn: 371405
Matt Arsenault [Mon, 9 Sep 2019 15:06:06 +0000 (15:06 +0000)]
AMDGPU/GlobalISel: Remove dead patterns
llvm-svn: 371404
Sven van Haastregt [Mon, 9 Sep 2019 14:39:20 +0000 (14:39 +0000)]
Merge note_ovl_builtin_candidate diagnostics; NFC
There is no difference between the unary and binary case, so
merge them.
llvm-svn: 371403
Ilya Biryukov [Mon, 9 Sep 2019 14:33:10 +0000 (14:33 +0000)]
[clangd] Add a new highlighting kind for typedefs
Summary:
We still attempt to highlight them as underlying types, but fallback to
the generic 'typedef' highlighting kind if the underlying type is too
complicated.
Reviewers: hokein
Reviewed By: hokein
Subscribers: nridge, MaskRay, jkorous, arphaman, kadircet, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D67290
llvm-svn: 371402
Roman Lebedev [Mon, 9 Sep 2019 14:27:39 +0000 (14:27 +0000)]
[NFC][InstCombine] Fixup test i added in rL371352.
llvm-svn: 371401
Ed Maste [Mon, 9 Sep 2019 13:50:20 +0000 (13:50 +0000)]
compiler-rt: use fp_t instead of long double, for consistency
Most builtins accepting or returning long double use the fp_t typedef.
Change the remaining few cases to do so.
Differential Revision: https://reviews.llvm.org/D35034
llvm-svn: 371400
James Molloy [Mon, 9 Sep 2019 13:17:55 +0000 (13:17 +0000)]
[DFAPacketizer] Reapply: Track resources for packetized instructions
Reapply with fix to reduce resources required by the compiler - use
unsigned[2] instead of std::pair. This causes clang and gcc to compile
the generated file multiple times faster, and hopefully will reduce
the resource requirements on Visual Studio also. This fix is a little
ugly but it's clearly the same issue the previous author of
DFAPacketizer faced (the previous tables use unsigned[2] rather uglily
too).
This patch allows the DFAPacketizer to be queried after a packet is formed to work out which
resources were allocated to the packetized instructions.
This is particularly important for targets that do their own bundle packing - it's not
sufficient to know simply that instructions can share a packet; which slots are used is
also required for encoding.
This extends the emitter to emit a side-table containing resource usage diffs for each
state transition. The packetizer maintains a set of all possible resource states in its
current state. After packetization is complete, all remaining resource states are
possible packetization strategies.
The sidetable is only ~500K for Hexagon, but the extra tracking is disabled by default
(most uses of the packetizer like MachinePipeliner don't care and don't need the extra
maintained state).
Differential Revision: https://reviews.llvm.org/D66936
llvm-svn: 371399
Fangrui Song [Mon, 9 Sep 2019 13:08:51 +0000 (13:08 +0000)]
[ELF] nmagic or omagic: don't allocate PT_PHDR or PF_R PT_LOAD for the !hasPhdrsCommands case
```
part.phdrs = script->hasPhdrsCommands() ? script->createPhdrs() : createPhdrs(part);
```
createPhdrs() allocates a PT_PHDR and a PF_R PT_LOAD, which will be
deleted later in LinkerScript::allocateHeaders, but leave a gap between
the program headers and the first section. Don't allocate the segments
to avoid the gap. PT_INTERP is likely not needed as well.
Reviewed By: ruiu
Differential Revision: https://reviews.llvm.org/D67324
llvm-svn: 371398
Clement Courbet [Mon, 9 Sep 2019 13:08:16 +0000 (13:08 +0000)]
[Inliner][NFC] Make test less brittle.
Summary:
This tests inlining size thresholds, but relies on the output of running
the full O2 pipeline, making it brittle against changes in unrelated
passes.
Only run the inlining pass and set thresholds on the test RUN line
instead.
Found while investigating D60318.
Reviewers: RKSimon, qcolombet
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67349
llvm-svn: 371397
Yitzhak Mandelbaum [Mon, 9 Sep 2019 12:59:14 +0000 (12:59 +0000)]
[clang-tidy] Fix bug in bugprone-use-after-move check
Summary:
The bugprone-use-after-move check exhibits false positives for certain uses of
the C++17 if/switch init statements. These false positives are caused by a bug
in the ExprSequence calculations.
This revision adds tests for the false positives and fixes the corresponding
sequence calculation.
Reviewers: gribozavr
Subscribers: xazax.hun, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D67292
llvm-svn: 371396
Sam Parker [Mon, 9 Sep 2019 12:54:47 +0000 (12:54 +0000)]
[ARM][MVE] VCTP instruction selection
Add codegen support for vctp{8,16,32}.
Differential Revision: https://reviews.llvm.org/D67344
llvm-svn: 371395
Fangrui Song [Mon, 9 Sep 2019 12:42:10 +0000 (12:42 +0000)]
[clang-doc] sys::fs::F_None -> OF_None. NFC
F_None, F_Text and F_Append are kept for compatibility.
llvm-svn: 371394
Simon Pilgrim [Mon, 9 Sep 2019 12:33:22 +0000 (12:33 +0000)]
Revert rL371198 from llvm/trunk: [DFAPacketizer] Track resources for packetized instructions
This patch allows the DFAPacketizer to be queried after a packet is formed to work out which
resources were allocated to the packetized instructions.
This is particularly important for targets that do their own bundle packing - it's not
sufficient to know simply that instructions can share a packet; which slots are used is
also required for encoding.
This extends the emitter to emit a side-table containing resource usage diffs for each
state transition. The packetizer maintains a set of all possible resource states in its
current state. After packetization is complete, all remaining resource states are
possible packetization strategies.
The sidetable is only ~500K for Hexagon, but the extra tracking is disabled by default
(most uses of the packetizer like MachinePipeliner don't care and don't need the extra
maintained state).
Differential Revision: https://reviews.llvm.org/D66936
........
Reverted as this is causing "compiler out of heap space" errors on MSVC 2017/19 NDEBUG builds
llvm-svn: 371393
Kadir Cetinkaya [Mon, 9 Sep 2019 12:28:44 +0000 (12:28 +0000)]
[clangd] Support multifile edits as output of Tweaks
Summary:
First patch for propogating multifile changes from tweak outputs to LSP
WorkspaceEdits.
Uses SM to convert tooling::Replacements to TextEdits.
Errors out if there are any inconsistencies between the draft version and the
version generated the edits.
Reviewers: sammccall
Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D66637
llvm-svn: 371392
Sam McCall [Mon, 9 Sep 2019 11:34:01 +0000 (11:34 +0000)]
[clangd] Update clangd-vscode docs to be more user-focused.
Summary: Relegate "updating the extension" docs to a separate file.
Reviewers: hokein, kadircet
Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D67092
llvm-svn: 371390
Fangrui Song [Mon, 9 Sep 2019 11:22:27 +0000 (11:22 +0000)]
[ELF][AArch64] Apply some NFC cleanups to AArch64ErrataFix.cpp
Reviewed By: ruiu
Differential Revision: https://reviews.llvm.org/D67310
llvm-svn: 371389
Cullen Rhodes [Mon, 9 Sep 2019 11:21:14 +0000 (11:21 +0000)]
[AArch64][SVE] Implement abs and neg intrinsics
Summary:
This patch implements two arithmetic intrinsics:
* int_aarch64_sve_abs
* int_aarch64_sve_neg
testing the support for scalable vector types in intrinsics added in D65930.
Reviewed By: greened
Differential Revision: https://reviews.llvm.org/D65931
llvm-svn: 371388
David Green [Mon, 9 Sep 2019 10:46:25 +0000 (10:46 +0000)]
[ARM] Prevent generating NEON stack accesses under MVE.
We should not be generating Neon stack loads/stores even for these large
registers.
No test here because my understanding is we will only generate these QQPR regs
for intrinsics and VLDn's. The tests will follow once those are available.
Differential revision: https://reviews.llvm.org/D67169
llvm-svn: 371386
Tim Northover [Mon, 9 Sep 2019 10:36:58 +0000 (10:36 +0000)]
GlobalISel: fix unused warnings in release builds.
llvm-svn: 371385
Tim Northover [Mon, 9 Sep 2019 10:04:23 +0000 (10:04 +0000)]
GlobalISel: add combiner to form indexed loads.
Loosely based on DAGCombiner version, but this part is slightly simpler in
GlobalIsel because all address calculation is performed by G_GEP. That makes
the inc/dec distinction moot so there's just pre/post to think about.
No targets can handle it yet so testing is via a special flag that overrides
target hooks.
llvm-svn: 371384
George Rimar [Mon, 9 Sep 2019 09:55:56 +0000 (09:55 +0000)]
[yaml2obj] - Fix BB after r371380
Just a fix for an input file name.
llvm-svn: 371383
George Rimar [Mon, 9 Sep 2019 09:43:03 +0000 (09:43 +0000)]
[lib/ObjectYAML] - Improve and cleanup error reporting in ELFState<ELFT> class.
The aim of this patch is to refactor how we handle and report error.
I suggest to use the same approach we use in LLD: delayed error reporting.
For that I introduced 'HasError' flag which triggers when we report an error.
Now we do not exit instantly on any error. The benefits are:
1) There are no more 'exit(1)' calls in the library code.
2) Code was simplified significantly in a few places.
3) It is now possible to print multiple errors instead of only one.
Also, I changed the messages to be lower case and removed a full stop.
Differential revision: https://reviews.llvm.org/D67182
llvm-svn: 371380
Ilya Biryukov [Mon, 9 Sep 2019 09:37:17 +0000 (09:37 +0000)]
[clangd] Highlight typedefs to template parameters as template parameters
Summary:
Template parameters were handled outside `addType`, this led to lack of highlightings for typedefs
to template types.
This was never desirable, we want to highlight our typedefs as their underlying type.
Note that typedefs to more complicated types, like pointers and references are still not highlighted.
Original patch by Johan Vikström.
Reviewers: hokein, jvikstrom
Reviewed By: hokein
Subscribers: nridge, javed.absar, kristof.beyls, MaskRay, jkorous, arphaman, kadircet, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D66516
llvm-svn: 371379
Ilya Biryukov [Mon, 9 Sep 2019 08:57:17 +0000 (08:57 +0000)]
[clangd] Replace HighlightingKind::NumKinds with LastKind. NFC
Summary:
The latter simplifies the client code by avoiding the need to handle it
as a separate case statement.
Reviewers: hokein
Reviewed By: hokein
Subscribers: nridge, MaskRay, jkorous, arphaman, kadircet, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D67277
llvm-svn: 371375
Oliver Stannard [Mon, 9 Sep 2019 08:50:28 +0000 (08:50 +0000)]
[ARM][MVE] Decoding of uqrshl and sqrshl accepts unpredictable encodings
Specify the Unpredictable bits, and return softfails when appropriate.
Patch by Mark Murray!
Differential revision: https://reviews.llvm.org/D66939
llvm-svn: 371374
Ilya Biryukov [Mon, 9 Sep 2019 08:47:05 +0000 (08:47 +0000)]
[clangd] Improve output of semantic highlighting tests in case of failures
Summary:
Instead of matching lists of highlightings, we annotate input code with
resulting highlightings and diff it against the expected annotated input.
In case of failures, this produces much nicer output in form of text-based
diffs.
Reviewers: hokein
Reviewed By: hokein
Subscribers: nridge, MaskRay, jkorous, arphaman, kadircet, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D67274
llvm-svn: 371373
Sam Parker [Mon, 9 Sep 2019 08:39:14 +0000 (08:39 +0000)]
[ARM][ParallelDSP] Fix for sext input
The incoming accumulator value can be discovered through a sext, in
which case there will be a mismatch between the input and the result.
So sign extend the accumulator input if we're performing a 64-bit mac.
Differential Revision: https://reviews.llvm.org/D67220
llvm-svn: 371370
Jonas Paulsson [Mon, 9 Sep 2019 07:58:57 +0000 (07:58 +0000)]
[SystemZ] NFC: use clearRegisterDeads() in SystemZElimCompare.cpp
This is simpler than using findRegisterDefOperandIdx() + setIsDead().
Review: Ulrich Weigand.
llvm-svn: 371369
Craig Topper [Mon, 9 Sep 2019 07:46:11 +0000 (07:46 +0000)]
[X86] Add broadcast load unfolding support for vpcmpeq/vpcmpgt/vpcmp/vpcmpu.
llvm-svn: 371368
Craig Topper [Mon, 9 Sep 2019 07:46:07 +0000 (07:46 +0000)]
[X86] Add broadcast load unfolding tests for vpcmpeq/vpcmpgt/vpcmp/vpcmpu.
llvm-svn: 371367
Craig Topper [Mon, 9 Sep 2019 06:32:24 +0000 (06:32 +0000)]
[X86] Add broadcast load unfold support for smin/umin/smax/umax.
llvm-svn: 371366
Craig Topper [Mon, 9 Sep 2019 06:32:20 +0000 (06:32 +0000)]
[X86] Add broadcast load unfolding tests for smin/umin/smax/smin.
llvm-svn: 371365
Matt Arsenault [Mon, 9 Sep 2019 05:49:52 +0000 (05:49 +0000)]
AMDGPU: Remove pointless wrapper nodes for init.exec intrinsics
llvm-svn: 371364
Craig Topper [Mon, 9 Sep 2019 04:25:01 +0000 (04:25 +0000)]
[X86] Add broadcast load unfolding support for VMAXPS/PD and VMINPS/PD.
llvm-svn: 371363
Craig Topper [Mon, 9 Sep 2019 04:24:57 +0000 (04:24 +0000)]
[X86] Add broadcast load unfolding tests for vmaxps/pd and vminps/pd
llvm-svn: 371362
Fangrui Song [Mon, 9 Sep 2019 03:35:14 +0000 (03:35 +0000)]
[ELF][test] Improve and reorganize another set of tests
Add file-level comments
Replace trivial Input/*.s with echo ... | llvm-mc
Delete insignificant addresses to make them more tolerant to layout changes
Simplify test output
Merge merge-section-types.s into compatible-section-types.s and add a missed case
Merge gnu-ifunc-gotpcrel.s (added in D19517) into gnu-ifunc-dso.s (added in D35119) and add missed cases
Delete typed-undef.s - covered by executable-undefined-ignoreall.s
Delete emit-relocs-shared.s - covered by emit-relocs-merge.s
Replace copy-rel-pie.s and copy-rel-pie2.s with canonical-plt-pcrel.s, canonical-plt-symbolic.s and copy-rel.s:
add -no-pie cases.
add a case that a canonical PLT can be created for STT_GNU_IFUNC. The logic in Symbols.h was untested:
// ctor of SharedSymbol
if (this->type == llvm::ELF::STT_GNU_IFUNC)
this->type = llvm::ELF::STT_FUNC;
llvm-svn: 371361
Craig Topper [Mon, 9 Sep 2019 02:44:46 +0000 (02:44 +0000)]
[X86] Add fp128 test cases for ceil/floor/trunc/nearbyint/rint/round libcalls.
llvm-svn: 371360
Kai Luo [Mon, 9 Sep 2019 02:32:42 +0000 (02:32 +0000)]
[MachineCopyPropagation] Remove redundant copies after TailDup via machine-cp
Summary:
After tailduplication, we have redundant copies. We can remove these
copies in machine-cp if it's safe to, i.e.
```
$reg0 = OP ...
... <<< No read or clobber of $reg0 and $reg1
$reg1 = COPY $reg0 <<< $reg0 is killed
...
<RET>
```
will be transformed to
```
$reg1 = OP ...
...
<RET>
```
Differential Revision: https://reviews.llvm.org/D65267
llvm-svn: 371359
Craig Topper [Mon, 9 Sep 2019 01:35:04 +0000 (01:35 +0000)]
[X86] Add test cases for fptoui/fptosi/sitofp/uitofp between fp128 and i128.
llvm-svn: 371358
Craig Topper [Mon, 9 Sep 2019 01:35:00 +0000 (01:35 +0000)]
[X86] Use xorps to create fp128 +0.0 constants.
This matches what we do for f32/f64. gcc also does this for fp128.
llvm-svn: 371357
Craig Topper [Mon, 9 Sep 2019 01:34:55 +0000 (01:34 +0000)]
[X86] Add avx and avx512f RUN lines to fp128-cast.ll
llvm-svn: 371356
Douglas Yung [Mon, 9 Sep 2019 01:21:33 +0000 (01:21 +0000)]
Relax opcode checks in test to check for only a number instead of a specific number.
llvm-svn: 371355
Kamil Rytarowski [Sun, 8 Sep 2019 23:53:36 +0000 (23:53 +0000)]
Enable LSan for NetBSD/i386 in test/asan/lit.cfg.py
llvm-svn: 371354
Simon Pilgrim [Sun, 8 Sep 2019 21:38:33 +0000 (21:38 +0000)]
[X86][SSE] SimplifyDemandedVectorEltsForTargetNode - add faux shuffle support.
This patch decodes target and faux shuffles with getTargetShuffleInputs - a reduced version of resolveTargetShuffleInputs that doesn't resolve SM_SentinelZero cases, so we can correctly remove zero vectors if they aren't demanded.
llvm-svn: 371353
Roman Lebedev [Sun, 8 Sep 2019 21:30:34 +0000 (21:30 +0000)]
[InstCombine][NFC] Some tests for usub overflow+nonzero check improvement (PR43251)
https://rise4fun.com/Alive/kHq
https://bugs.llvm.org/show_bug.cgi?id=43251
llvm-svn: 371352
Craig Topper [Sun, 8 Sep 2019 20:56:09 +0000 (20:56 +0000)]
[X86] Add a hack to combineVSelectWithAllOnesOrZeros to turn selects with two zero/undef vector inputs into an all zeroes vector.
If the two zero vectors have undefs in different places they
won't get combined by simplifySelect.
This fixes a regression from an earlier commit.
llvm-svn: 371351
Craig Topper [Sun, 8 Sep 2019 20:56:05 +0000 (20:56 +0000)]
[X86] Remove call to getZeroVector from materializeVectorConstant. Add isel patterns for zero vectors with all types.
The change to avx512-vec-cmp.ll is a regression, but should be
easy to fix. It occurs because the getZeroVector call was
canonicalizing both sides to the same node, then SimplifySelect
was able to simplify it. But since only called getZeroVector
on some VTs this isn't a robust way to combine this.
The change to vector-shuffle-combining-ssse3.ll is more
instructions, but removes a constant pool load so its unclear
if its a regression or not.
llvm-svn: 371350
Roman Lebedev [Sun, 8 Sep 2019 20:14:15 +0000 (20:14 +0000)]
[InstSimplify] simplifyUnsignedRangeCheck(): if we know that X != 0, handle more cases (PR43246)
Summary:
This is motivated by D67122 sanitizer check enhancement.
That patch seemingly worsens `-fsanitize=pointer-overflow`
overhead from 25% to 50%, which strongly implies missing folds.
In this particular case, given
```
char* test(char& base, unsigned long offset) {
return &base + offset;
}
```
it will end up producing something like
https://godbolt.org/z/LK5-iH
which after optimizations reduces down to roughly
```
define i1 @t0(i8* nonnull %base, i64 %offset) {
%base_int = ptrtoint i8* %base to i64
%adjusted = add i64 %base_int, %offset
%non_null_after_adjustment = icmp ne i64 %adjusted, 0
%no_overflow_during_adjustment = icmp uge i64 %adjusted, %base_int
%res = and i1 %non_null_after_adjustment, %no_overflow_during_adjustment
ret i1 %res
}
```
Without D67122 there was no `%non_null_after_adjustment`,
and in this particular case we can get rid of the overhead:
Here we add some offset to a non-null pointer,
and check that the result does not overflow and is not a null pointer.
But since the base pointer is already non-null, and we check for overflow,
that overflow check will already catch the null pointer,
so the separate null check is redundant and can be dropped.
Alive proofs:
https://rise4fun.com/Alive/WRzq
There are more patterns of "unsigned-add-with-overflow", they are not handled here,
but this is the main pattern, that we currently consider canonical,
so it makes sense to handle it.
https://bugs.llvm.org/show_bug.cgi?id=43246
Reviewers: spatel, nikic, vsk
Reviewed By: spatel
Subscribers: hiraditya, llvm-commits, reames
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67332
llvm-svn: 371349
Sanjay Patel [Sun, 8 Sep 2019 19:48:47 +0000 (19:48 +0000)]
[InstCombine] add tests for icmp with srem operand; NFC
llvm-svn: 371348
Roman Lebedev [Sun, 8 Sep 2019 19:36:13 +0000 (19:36 +0000)]
[X86] X86DAGToDAGISel::combineIncDecVector(): call getSplatBuildVector() manually
As reported in post-commit review of r370327,
there is some case where the code crashes.
As discussed with Craig Topper, the problem is that getConstant()
internally calls getSplatBuildVector(), so we don't insert
the constant itself.
If we do that manually we're good.
llvm-svn: 371346
Craig Topper [Sun, 8 Sep 2019 19:24:42 +0000 (19:24 +0000)]
[X86] Use DAG.getConstant instead of getZeroVector in combinePMULDQ.
getZeroVector canonicalizes the type to vXi32, but that's a
legalization action. We should use the most correct type if
possible.
llvm-svn: 371345
Craig Topper [Sun, 8 Sep 2019 19:24:39 +0000 (19:24 +0000)]
[DAGCombiner][X86][ARM] Teach visitMULO to fold multiplies with 0 to 0 and no carry.
I modified the ARM test to use two inputs instead of 0 so the
test hopefully still tests what was intended.
llvm-svn: 371344
Craig Topper [Sun, 8 Sep 2019 19:24:29 +0000 (19:24 +0000)]
[X86] Teach materializeVectorConstant to not call getZeroVector/getOnesVector on the types we already have isel patterns for.
llvm-svn: 371343
Gabor Borsik [Sun, 8 Sep 2019 19:23:43 +0000 (19:23 +0000)]
Move prop-sink branch to monorepo.
llvm-svn: 371342
Sanjay Patel [Sun, 8 Sep 2019 19:03:01 +0000 (19:03 +0000)]
[InstCombine] fold extract+insert into identity shuffle
This is similar to the existing fold for splats added with:
rL365379
If we can adjust the shuffle mask to include another element
in an identity mask (if it changes vector length, that's an
extract/insert subvector operation in the backend), then that
can eliminate extractelement/insertelement pairs in IR.
All targets are expected to lower shuffles with identity masks
efficiently.
llvm-svn: 371340
Roman Lebedev [Sun, 8 Sep 2019 17:50:40 +0000 (17:50 +0000)]
[NFC][InstSimplify] Some tests for dropping null check after uadd.with.overflow of non-null (PR43246)
https://rise4fun.com/Alive/WRzq
Name: C <= Y && Y != 0 --> C <= Y iff C != 0
Pre: C != 0
%y_is_nonnull = icmp ne i64 %y, 0
%no_overflow = icmp ule i64 C, %y
%r = and i1 %y_is_nonnull, %no_overflow
=>
%r = %no_overflow
Name: C <= Y || Y != 0 --> Y != 0 iff C != 0
Pre: C != 0
%y_is_nonnull = icmp ne i64 %y, 0
%no_overflow = icmp ule i64 C, %y
%r = or i1 %y_is_nonnull, %no_overflow
=>
%r = %y_is_nonnull
Name: C > Y || Y == 0 --> C > Y iff C != 0
Pre: C != 0
%y_is_null = icmp eq i64 %y, 0
%overflow = icmp ugt i64 C, %y
%r = or i1 %y_is_null, %overflow
=>
%r = %overflow
Name: C > Y && Y == 0 --> Y == 0 iff C != 0
Pre: C != 0
%y_is_null = icmp eq i64 %y, 0
%overflow = icmp ugt i64 C, %y
%r = and i1 %y_is_null, %overflow
=>
%r = %y_is_null
https://bugs.llvm.org/show_bug.cgi?id=43246
llvm-svn: 371339
Kamil Rytarowski [Sun, 8 Sep 2019 17:07:28 +0000 (17:07 +0000)]
Enable LSan tests for NetBSD/i386
llvm-svn: 371338
Kamil Rytarowski [Sun, 8 Sep 2019 16:15:18 +0000 (16:15 +0000)]
Stop marking 5 ASan tests as failing on NetBSD/i386
Unexpected Passing Tests (4):
AddressSanitizer-i386-netbsd :: TestCases/Posix/coverage-reset.cpp
AddressSanitizer-i386-netbsd :: TestCases/Posix/coverage.cpp
AddressSanitizer-i386-netbsd :: TestCases/Posix/interception-in-shared-lib-test.cpp
AddressSanitizer-i386-netbsd :: TestCases/suppressions-library.cpp
llvm-svn: 371337