platform/upstream/mesa.git
6 years agoradeonsi: improve quality of 16 sample locations
Marek Olšák [Wed, 2 May 2018 03:17:07 +0000 (23:17 -0400)]
radeonsi: improve quality of 16 sample locations

This results in better 16x and 8x quality when using these locations.
Verified with the piglit MSAA accuracy test.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoradeonsi: use better sample locations for 4x MSAA
Marek Olšák [Wed, 2 May 2018 02:45:24 +0000 (22:45 -0400)]
radeonsi: use better sample locations for 4x MSAA

Discovered by luck. Verified with the piglit MSAA accuracy test.
It also shows that the worst case EQAA 16s4f results in very good 4x MSAA
in the worst case.

Nine might not like these positions, but they are prettier to the eye and
GL doesn't care.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoradeonsi: reorder sample locations as required by EQAA
Marek Olšák [Sat, 28 Apr 2018 01:35:33 +0000 (21:35 -0400)]
radeonsi: reorder sample locations as required by EQAA

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoradeonsi: simplify si_get_sample_position
Marek Olšák [Sat, 28 Apr 2018 02:02:04 +0000 (22:02 -0400)]
radeonsi: simplify si_get_sample_position

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoradeonsi: simplify arrays of sample locations
Marek Olšák [Fri, 27 Apr 2018 01:53:33 +0000 (21:53 -0400)]
radeonsi: simplify arrays of sample locations

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoradeonsi: set DB_EQAA the same as Vulkan
Marek Olšák [Fri, 27 Apr 2018 03:18:41 +0000 (23:18 -0400)]
radeonsi: set DB_EQAA the same as Vulkan

These never change, but they only affect EQAA, which isn't implemented.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoradeonsi: remove CM_ prefixes
Marek Olšák [Fri, 27 Apr 2018 02:54:54 +0000 (22:54 -0400)]
radeonsi: remove CM_ prefixes

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoradeonsi: don't update clear color registers if they don't change
Marek Olšák [Thu, 26 Apr 2018 20:21:19 +0000 (16:21 -0400)]
radeonsi: don't update clear color registers if they don't change

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoradeonsi: remove r600_fmask_info
Marek Olšák [Tue, 1 May 2018 02:48:00 +0000 (22:48 -0400)]
radeonsi: remove r600_fmask_info

radeon_surf contains almost everything.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoac/surface: unify common legacy and gfx9 fmask fields
Marek Olšák [Tue, 1 May 2018 02:35:51 +0000 (22:35 -0400)]
ac/surface: unify common legacy and gfx9 fmask fields

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoac/surface/gfx6: compute FMASK together with the color surface
Marek Olšák [Tue, 1 May 2018 00:54:06 +0000 (20:54 -0400)]
ac/surface/gfx6: compute FMASK together with the color surface

instead of invoking FMASK computation separately.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoac/surface/gfx9: fix a typo in CMASK RB/pipe alignment
Marek Olšák [Tue, 1 May 2018 00:20:55 +0000 (20:20 -0400)]
ac/surface/gfx9: fix a typo in CMASK RB/pipe alignment

No change in behavior because it's always aligned.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoac: set correct LLVM processor names for Raven & Vega12
Marek Olšák [Mon, 30 Apr 2018 22:10:50 +0000 (18:10 -0400)]
ac: set correct LLVM processor names for Raven & Vega12

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoac: sort raster configs
Marek Olšák [Tue, 1 May 2018 17:44:21 +0000 (13:44 -0400)]
ac: sort raster configs

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoac: remove 1 RB raster config for Iceland
Marek Olšák [Tue, 1 May 2018 17:08:44 +0000 (13:08 -0400)]
ac: remove 1 RB raster config for Iceland

Iceland always reports 2 RBs.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoac: move the Fiji kernel workaround for raster config out of the switch
Marek Olšák [Tue, 1 May 2018 17:08:44 +0000 (13:08 -0400)]
ac: move the Fiji kernel workaround for raster config out of the switch

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoac: enable both RBs on Kaveri
Marek Olšák [Tue, 1 May 2018 16:48:05 +0000 (12:48 -0400)]
ac: enable both RBs on Kaveri

This can result in 2x increase in performance on non-harvested Kaveris.

v2: don't do it on radeon

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoradeonsi/gfx9: work around a GPU hang due to broken indirect indexing in LLVM
Marek Olšák [Wed, 2 May 2018 00:16:19 +0000 (20:16 -0400)]
radeonsi/gfx9: work around a GPU hang due to broken indirect indexing in LLVM

Fixes: 6d19120da85 "radeonsi/gfx9: workaround for INTERP with indirect indexing"
Cc: 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agointel/isl/storage: Don't lower most UNORM formats on gen11+
Jason Ekstrand [Mon, 7 May 2018 21:47:06 +0000 (14:47 -0700)]
intel/isl/storage: Don't lower most UNORM formats on gen11+

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Tested-by: Anuj Phogat <anuj.phogat@gmail.com>
6 years agointel/isl: Several UNORM formats support typed writes on gen11+
Jason Ekstrand [Mon, 7 May 2018 21:44:20 +0000 (14:44 -0700)]
intel/isl: Several UNORM formats support typed writes on gen11+

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Tested-by: Anuj Phogat <anuj.phogat@gmail.com>
6 years agomesa: revert GL_[SECONDARY_]COLOR_ARRAY_SIZE glGet type to TYPE_INT
Brian Paul [Thu, 10 May 2018 15:24:20 +0000 (09:24 -0600)]
mesa: revert GL_[SECONDARY_]COLOR_ARRAY_SIZE glGet type to TYPE_INT

Since size can be 3, 4 or GL_BGRA we need to keep these glGet types
as TYPE_INT, not TYPE_UBYTE.

Fixes: d07466fe18522 ("mesa: fix glGetInteger/Float/etc queries for
vertex arrays attribs")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106462
cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
6 years agoradv: disable DCC for shareable images on GFX9+
Andres Rodriguez [Thu, 10 May 2018 03:40:21 +0000 (23:40 -0400)]
radv: disable DCC for shareable images on GFX9+

This seems to be broken at the moment for opengl interop.

Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
6 years agoconfigure.ac: rework -latomic check
Thomas Petazzoni [Mon, 7 May 2018 11:34:11 +0000 (13:34 +0200)]
configure.ac: rework -latomic check

The configure.ac logic added in commit
2ef7f23820a67e958c2252bd81eb0458903ebf33 ("configure: check if
-latomic is needed for __atomic_*") makes the assumption that if a
64-bit atomic intrinsic test program fails to link without -latomic,
it is because we must use -latomic.

Unfortunately, this is not completely correct: libatomic only appeared
in gcc 4.8, and therefore gcc versions before that will not have
libatomic, and therefore don't provide atomic intrinsics for all
architectures. This issue was for example encountered on PowerPC with
a gcc 4.7 toolchain, where the build fails with:

powerpc-ctng_e500v2-linux-gnuspe/bin/ld: cannot find -latomic

This commit aims at fixing that, by not assuming -latomic is
available. The commit re-organizes the atomic intrinsics detection as
follows:

 (1) Test if a program using 64-bit atomic intrinsics links properly,
     without -latomic. If this is the case, we have atomic intrinsics,
     and we're good to go.

 (2) If (1) has failed, then test to link the same program, but this
     time with -latomic in LDFLAGS. If this is the case, then we have
     atomic intrinsics, provided we link with -latomic.

This has been tested in three situations:

 - On x86-64, where atomic instrinsics are all built-in, with no need
   for libatomic. In this case, config.log contains:

   GCC_ATOMIC_BUILTINS_SUPPORTED_FALSE='#'
   GCC_ATOMIC_BUILTINS_SUPPORTED_TRUE=''
   LIBATOMIC_LIBS=''

   This means: atomic intrinsics are available, and we don't need to
   link with libatomic.

 - On NIOS2, where atomic intrinsics are available, but some of them
   (64-bit ones) require using libatomic. In this case, config.log
   contains:

   GCC_ATOMIC_BUILTINS_SUPPORTED_FALSE='#'
   GCC_ATOMIC_BUILTINS_SUPPORTED_TRUE=''
   LIBATOMIC_LIBS='-latomic'

   This means: atomic intrinsics are available, and we need to link
   with libatomic.

 - On PowerPC with an old gcc 4.7 toolchain, where 32-bit atomic
   instrinsics are available, but not 64-bit atomic instrinsics, and
   there is no libatomic. In this case, config.log contains:

   GCC_ATOMIC_BUILTINS_SUPPORTED_FALSE=''
   GCC_ATOMIC_BUILTINS_SUPPORTED_TRUE='#'

   With means that atomic intrinsics are not usable.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
6 years agomesa: fix glGetInteger/Float/etc queries for vertex arrays attribs
Brian Paul [Thu, 10 May 2018 01:46:32 +0000 (19:46 -0600)]
mesa: fix glGetInteger/Float/etc queries for vertex arrays attribs

The vertex array Size and Stride attributes are now ubyte and short,
respectively.  The glGet code needed to be updated to handle those
types, but wasn't.

Fixes the new piglit test gl-1.5-get-array-attribs test.

v2: fix inadvertant whitespace change, change COLOR_ARRAY_SIZE to UBYTE,
misc fixes suggested by Justin

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106450
Fixes: d5f42f96e16 ("mesa: shrink size of gl_array_attributes (v2)")
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
6 years agowinsys/radeon: Destroy fd_hash table when the last winsys is removed.
Jan Vesely [Tue, 8 May 2018 05:39:04 +0000 (01:39 -0400)]
winsys/radeon: Destroy fd_hash table when the last winsys is removed.

Fixes memory leak on module unload.
v2: Use util_hash_table helper function

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
6 years agogallium/auxiliary: Add helper function to count the number of entries in hash table
Jan Vesely [Wed, 9 May 2018 19:06:33 +0000 (15:06 -0400)]
gallium/auxiliary: Add helper function to count the number of entries in hash table

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
6 years agoradv: move handling nosisched option in a better place
Samuel Pitoiset [Wed, 9 May 2018 21:52:53 +0000 (23:52 +0200)]
radv: move handling nosisched option in a better place

It's a per-application optimization, so it makes more sense
to do that in radv_handle_per_app_options().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
6 years agoradv: assorted typo fixes
Grazvydas Ignotas [Wed, 9 May 2018 21:26:21 +0000 (00:26 +0300)]
radv: assorted typo fixes

Trivial.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
6 years agomesa/vbo/tnl: Move gl_vertex_array related stuff to tnl.
Mathias Fröhlich [Sun, 1 Apr 2018 18:18:36 +0000 (20:18 +0200)]
mesa/vbo/tnl: Move gl_vertex_array related stuff to tnl.

The only remaining users of gl_vertex_array are tnl based
drivers. So move everything related to that into tnl and
rename it accordingly.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
6 years agomesa: Remove Array._DrawArrays.
Mathias Fröhlich [Sun, 1 Apr 2018 18:18:36 +0000 (20:18 +0200)]
mesa: Remove Array._DrawArrays.

Only tnl based drivers still use this array. So remove it
from core mesa and use Array._DrawVAO instead.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
6 years agoi965: Remove the now unused gl_vertex_array.
Mathias Fröhlich [Sun, 1 Apr 2018 18:18:36 +0000 (20:18 +0200)]
i965: Remove the now unused gl_vertex_array.

Was meant to be temporary in i965.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
6 years agoi965: Remove the gl_vertex_array indirection.
Mathias Fröhlich [Sun, 1 Apr 2018 18:18:36 +0000 (20:18 +0200)]
i965: Remove the gl_vertex_array indirection.

For now store binding and attrib in brw_vertex_element.
The i965 driver still provides lots of opportunity to make use
of the unique binding information in the VAO which is currently not
taken from the VAO.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
6 years agoi965: Implement all_varyings_in_vbos in terms of Array._DrawVAO.
Mathias Fröhlich [Sun, 1 Apr 2018 18:18:36 +0000 (20:18 +0200)]
i965: Implement all_varyings_in_vbos in terms of Array._DrawVAO.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
6 years agost/mesa: Remove the now unused gl_vertex_array.
Mathias Fröhlich [Sun, 1 Apr 2018 18:18:36 +0000 (20:18 +0200)]
st/mesa: Remove the now unused gl_vertex_array.

Was meant to be temporary in gallium.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
6 years agost/mesa: Make feedback draw and rasterpos use _DrawVAO.
Mathias Fröhlich [Thu, 26 Apr 2018 21:17:20 +0000 (23:17 +0200)]
st/mesa: Make feedback draw and rasterpos use _DrawVAO.

Instead of playing with Array._DrawArrays, make the feedback draw
path use Array._DrawVAO. Also st_RasterPos needs to use the VAO then.

v2: Use helper methods to get the offset values for array and binding.
    Update comments.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
6 years agost/mesa: Use Array._DrawVAO in st_atom_array.c.
Mathias Fröhlich [Sun, 1 Apr 2018 18:18:36 +0000 (20:18 +0200)]
st/mesa: Use Array._DrawVAO in st_atom_array.c.

Finally make use of the binding information in the VAO when
setting up arrays for draw.

v2: Emit less relocations also for interleaved userspace arrays.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
6 years agost/mesa: Make the input_to_index array available.
Mathias Fröhlich [Sun, 1 Apr 2018 18:18:36 +0000 (20:18 +0200)]
st/mesa: Make the input_to_index array available.

The input_to_index array is already available internally
when preparing vertex programs. Store the map in
struct st_vertex_program.
Also store the bitmask of mesa vertex processing inputs in
struct st_vp_variant.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
6 years agost/mesa: Use _DrawVAO for edgeflag enabled check.
Mathias Fröhlich [Sun, 1 Apr 2018 18:18:36 +0000 (20:18 +0200)]
st/mesa: Use _DrawVAO for edgeflag enabled check.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
6 years agomesa: Compute effective buffer bindings in the vao.
Mathias Fröhlich [Sun, 1 Apr 2018 18:18:36 +0000 (20:18 +0200)]
mesa: Compute effective buffer bindings in the vao.

Compute VAO buffer binding information past the position/generic0 mapping.
Scan for duplicate buffer bindings and collapse them into derived
effective buffer binding index and effective attribute mask variables.
Provide a set of helper functions to access the distilled
information in the VAO. All of them prefixed with _mesa_draw_...
to indicate that they are meant to query draw information.

v2: Also group user space arrays containing interleaved arrays.
    Add _Eff*Offset to be copied on attribute and binding copy.
    Update comments.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
6 years agovirgl: Add support for passing GL_ANY_SAMPLES_PASSED_CONSERVATIVE
Gert Wollny [Wed, 9 May 2018 14:51:49 +0000 (16:51 +0200)]
virgl: Add support for passing GL_ANY_SAMPLES_PASSED_CONSERVATIVE

This is needed for fixing CTS:
   dEQP-GLES3.functional.occlusion_query.conservative*

Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
6 years agor600: fix constant buffer bounds.
Dave Airlie [Wed, 9 May 2018 22:17:09 +0000 (23:17 +0100)]
r600: fix constant buffer bounds.

If you have an indirect access to a constant buffer on r600/eg
use a vertex fetch in the shader. However apps have expected
behaviour on those out of bounds accessess (even if illegal).

If the constants were being uploaded as part of a larger
upload buffer, we'd set the range of allowed access to a lot
larger than required so apps would get values back from
other parts of the upload buffer instead of the expected out
of bounds access.

This fixes rendering bugs in Trine and Witcher 1, thanks
to iive for nagging me effectively until I figured it out :-)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91808
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
6 years agoi965,anv: Set the CS stall bit on the ISP disable PIPE_CONTROL
Jason Ekstrand [Wed, 9 May 2018 22:06:13 +0000 (15:06 -0700)]
i965,anv: Set the CS stall bit on the ISP disable PIPE_CONTROL

From the bspec docs for "Indirect State Pointers Disable":

    "At the completion of the post-sync operation associated with this
    pipe control packet, the indirect state pointers in the hardware are
    considered invalid"

So the ISP disable is a post-sync type of operation which means that it
should be combined with a CS stall.  Without this, the simulator throws
an error.

Fixes: 766d801ca "anv: emit pixel scoreboard stall before ISP disable"
Fixes: f536097f6 "i965: require pixel scoreboard stall prior to ISP disable"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
6 years agoradv: handle arrays in the fmask descriptor.
Dave Airlie [Mon, 19 Mar 2018 07:13:46 +0000 (07:13 +0000)]
radv: handle arrays in the fmask descriptor.

This fixes the fmask descriptor generation to handle 2d ms arrays.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
6 years agogallium/tests: Fix assignment of EXTRA_DIST
Matt Turner [Wed, 9 May 2018 23:36:58 +0000 (16:36 -0700)]
gallium/tests: Fix assignment of EXTRA_DIST

Fixes: 6754c2e83d79 ("autotools: Include new meson files")

6 years agoconfigure.ac: Check for grep with AC_PROG_GREP
Matt Turner [Wed, 9 May 2018 23:32:12 +0000 (16:32 -0700)]
configure.ac: Check for grep with AC_PROG_GREP

Perhaps with a new version of autoconf, I began seeing:

| checking the name lister (/usr/bin/nm -B) interface... ./configure: line 6973: External.*some_variable: command not found
| BSD nm

This is because AC_PROG_NM expands to

...
if $GREP 'External.*some_variable' conftest.out > /dev/null; then
    lt_cv_nm_interface="MS dumpbin"
fi
...

I'm not sure if it's a bug in AC_PROG_NM that it doesn't call
AC_PROG_GREP, but it's easy enough for us to do it.

6 years agomain: fail texture_storage() call if the size is not okay
Xiong, James [Fri, 27 Apr 2018 15:34:47 +0000 (08:34 -0700)]
main: fail texture_storage() call if the size is not okay

Signed-off-by: Xiong, James <james.xiong@intel.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agomain: return 0 length when the queried program object's not linked
Xiong, James [Fri, 27 Apr 2018 01:39:57 +0000 (18:39 -0700)]
main: return 0 length when the queried program object's not linked

Signed-off-by: Xiong, James <james.xiong@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
6 years agoi965: Shut up unused variable warnings.
Kenneth Graunke [Wed, 9 May 2018 23:20:50 +0000 (16:20 -0700)]
i965: Shut up unused variable warnings.

These are only used in assertions.

6 years agosrc/intel/Makefile.vulkan.am: add missing MKDIR_GEN
Ross Burton [Wed, 9 May 2018 20:48:43 +0000 (21:48 +0100)]
src/intel/Makefile.vulkan.am: add missing MKDIR_GEN

Out of tree builds can try to write into a directory that doesn't exist yet:

| Traceback (most recent call last):
|   File "../../../mesa-18.0.2/src/intel/vulkan/anv_icd.py", line 46, in <module>
|     with open(args.out, 'w') as f:
| IOError: [Errno 2] No such file or directory: 'vulkan/intel_icd.x86_64.json'
| Makefile:4882: recipe for target 'vulkan/intel_icd.x86_64.json' failed

Add missing MKDIR_GEN calls to solve this.

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
6 years agomesa: fix error handling in get_framebuffer_parameteriv
Rhys Perry [Fri, 4 May 2018 22:27:51 +0000 (23:27 +0100)]
mesa: fix error handling in get_framebuffer_parameteriv

CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
6 years agoanv: emit pixel scoreboard stall before ISP disable
Lionel Landwerlin [Tue, 8 May 2018 16:25:55 +0000 (17:25 +0100)]
anv: emit pixel scoreboard stall before ISP disable

We want to make sure that all indirect state data has been loaded into
the EUs before disable the pointers.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Fixes: 78c125af3904c ("anv/gen10: Ignore push constant packets during context restore.")

6 years agoi965: require pixel scoreboard stall prior to ISP disable
Lionel Landwerlin [Tue, 1 May 2018 11:32:45 +0000 (12:32 +0100)]
i965: require pixel scoreboard stall prior to ISP disable

Invalidating the indirect state pointers might affect a previously
scheduled & still running 3DPRIMITIVE (causing page fault). So stall
on pixel scoreboard before that.

v2: Fix compile issue :(

v3: Stall on pixel scoreboard

v4: Drop the post sync operation (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Fixes: ca19ee33d7d39 ("i965/gen10: Ignore push constant packets during context restore.")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106243

6 years agointel/isl: Allow CCS_E on 1010102 formats
Jason Ekstrand [Fri, 26 Jan 2018 19:43:24 +0000 (11:43 -0800)]
intel/isl: Allow CCS_E on 1010102 formats

On CNL and above, CCS_E supports 1010102 formats and R11G11B10F.  We had
shut them off during early enabling because blorp_copy couldn't handle
them.  Now it can handle 1010102 formats so we can turn them back on.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agointel/blorp: Allow CCS copies of 1010102 formats
Jason Ekstrand [Fri, 26 Jan 2018 19:42:35 +0000 (11:42 -0800)]
intel/blorp: Allow CCS copies of 1010102 formats

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agointel/blorp: Add support for more format bitcasting
Jason Ekstrand [Fri, 26 Jan 2018 19:41:02 +0000 (11:41 -0800)]
intel/blorp: Add support for more format bitcasting

nir_format_bitcast_uint_vec_unmasked can only be used to cast between
formats with uniform channel sizes.  In particular, it cannot handle
10_10_10_2 formats.  By making use of the NIR helper for uint vector
casts, we should now be able to bitcast between any two uint formats so
long as their channels are in RGBA order (possibly with channels
missing).  In order to do this we need to rework the key a bit to pass
the actual formats instead of just the number of bits in each.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agointel/blorp: Use nir_format_bitcast_uint_vec_unmasked
Jason Ekstrand [Fri, 26 Jan 2018 19:35:04 +0000 (11:35 -0800)]
intel/blorp: Use nir_format_bitcast_uint_vec_unmasked

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agonir/format_convert: Add code for bitcasting vectors
Jason Ekstrand [Fri, 26 Jan 2018 19:34:04 +0000 (11:34 -0800)]
nir/format_convert: Add code for bitcasting vectors

This is a fairly direct port from blorp.  The only real change is that
the nir_format_convert version doesn't assume that everything is a vec4.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agointel/blorp: Use ISL instead of bitcast_color_value_to_uint
Jason Ekstrand [Fri, 26 Jan 2018 18:44:51 +0000 (10:44 -0800)]
intel/blorp: Use ISL instead of bitcast_color_value_to_uint

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agointel/isl: Add format conversion code
Jason Ekstrand [Fri, 23 Jun 2017 01:45:24 +0000 (18:45 -0700)]
intel/isl: Add format conversion code

This adds helpers to ISL to convert an isl_color_value to and from
binary data encoded with a given isl_format.  The conversion is done
using ISL's built-in format introspection so it's fairly slow as format
conversions go but it should be fine for a single pixel value.  In
particular, we can use this to convert clear colors.

As a side-effect, we now rely on the sRGB helpers in libmesautil so we
need to tweak the build system a bit.  All prior uses of src/util in ISL
were header-only.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agointel/isl/format: Get rid of the ALPHA colorspace
Jason Ekstrand [Fri, 23 Jun 2017 06:18:06 +0000 (23:18 -0700)]
intel/isl/format: Get rid of the ALPHA colorspace

Alpha-only formats are just linear.  There's no need to specially
deliminate them as being in their own colorspace.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agointel/isl/format: Add field locations informations to channel_layout
Jason Ekstrand [Fri, 23 Jun 2017 00:12:36 +0000 (17:12 -0700)]
intel/isl/format: Add field locations informations to channel_layout

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agointel/isl/format: Add a column for channel order to the table
Jason Ekstrand [Thu, 22 Jun 2017 23:52:56 +0000 (16:52 -0700)]
intel/isl/format: Add a column for channel order to the table

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agoi965/blorp: Remove a pile of blorp_blit restrictions
Jason Ekstrand [Sat, 21 Jan 2017 06:36:30 +0000 (22:36 -0800)]
i965/blorp: Remove a pile of blorp_blit restrictions

Previously, blorp could only blit into something that was renderable.
Thanks to recent additions to blorp, it can now blit into basically
anything so long as it isn't compressed.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agoi965/blorp: Allow blorp blits for 16x MSAA
Jason Ekstrand [Wed, 9 May 2018 16:48:29 +0000 (09:48 -0700)]
i965/blorp: Allow blorp blits for 16x MSAA

BLORP has supported 16x MSAA for quite a while now, we just never
bothered to enable it for CopyTexSubImage.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agoanv: Allow blitting to/from any supported format
Jason Ekstrand [Sat, 21 Jan 2017 19:30:40 +0000 (11:30 -0800)]
anv: Allow blitting to/from any supported format

Now that blorp handles all the cases, why not?  The only real change we
have to make is to stop using anv_swizzle_for_render() in blorp_blit
because it doesn't work for B4G4R4A4 and blorp now natively handles that.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agointel/blorp: Support the RGB workaround on more formats
Jason Ekstrand [Sat, 21 Jan 2017 18:53:12 +0000 (10:53 -0800)]
intel/blorp: Support the RGB workaround on more formats

Previously we only supported UINT formats because that's what blorp_copy
required.  If we want to use it in blorp_blit, however, we need to
support everything.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agointel/blorp: Silently convert RGBX destination formats to RGBA
Jason Ekstrand [Sat, 21 Jan 2017 17:34:44 +0000 (09:34 -0800)]
intel/blorp: Silently convert RGBX destination formats to RGBA

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agointel/isl: Add some helpers for working with RGBX formats
Jason Ekstrand [Sat, 21 Jan 2017 17:24:26 +0000 (09:24 -0800)]
intel/isl: Add some helpers for working with RGBX formats

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agointel/blorp: Handle more exotic destination formats
Jason Ekstrand [Sat, 21 Jan 2017 06:12:06 +0000 (22:12 -0800)]
intel/blorp: Handle more exotic destination formats

This commit adds support for the following formats as destination
formats even though the hardware does not support rendering to them:

 - ISL_FORMAT_R24_UNORM_X8_TYPELESS
 - ISL_FORMAT_A4B4G4R4_UNORM
 - ISL_FORMAT_L8_UNORM_SRGB
 - ISL_FORMAT_R9G9B9E5_SHAREDEXP

This is done by using a different format and emitting shader code to
fake it the rest of the way.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agointel/blorp: Include nir_format_convert.h in blorp_blit.c
Jason Ekstrand [Fri, 26 Jan 2018 07:01:40 +0000 (23:01 -0800)]
intel/blorp: Include nir_format_convert.h in blorp_blit.c

nir_mask_shift_or is now defined in nir_format_convert.h so we can
delete the copy in blorp_blit.c.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agonir/format_convert: Add a function to pack RGB9_E5 formats
Jason Ekstrand [Fri, 26 Jan 2018 07:06:11 +0000 (23:06 -0800)]
nir/format_convert: Add a function to pack RGB9_E5 formats

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agonir/format_convert: Add pack/unpack for R11F_G11F_B10F
Jason Ekstrand [Fri, 26 Jan 2018 06:32:16 +0000 (22:32 -0800)]
nir/format_convert: Add pack/unpack for R11F_G11F_B10F

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agonir/format_convert: Add linear <-> sRGB helpers
Jason Ekstrand [Fri, 26 Jan 2018 06:52:37 +0000 (22:52 -0800)]
nir/format_convert: Add linear <-> sRGB helpers

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agonir: Add the start of a format conversion helper header
Jason Ekstrand [Fri, 20 Oct 2017 16:35:48 +0000 (09:35 -0700)]
nir: Add the start of a format conversion helper header

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agointel/blorp: Add swizzle support for all hardware
Jason Ekstrand [Thu, 9 Feb 2017 02:00:05 +0000 (18:00 -0800)]
intel/blorp: Add swizzle support for all hardware

This commit makes blorp capable of swizzling anything even on hardware
that doesn't support texture swizzle.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agointel/isl: Add a helper for inverting swizzles
Jason Ekstrand [Thu, 9 Feb 2017 01:59:43 +0000 (17:59 -0800)]
intel/isl: Add a helper for inverting swizzles

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agointel/isl: Add a helper for composing swizzles
Jason Ekstrand [Tue, 7 Feb 2017 17:14:46 +0000 (09:14 -0800)]
intel/isl: Add a helper for composing swizzles

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agointel/isl: Add an isl_swizzle_supports_rendering helper
Jason Ekstrand [Thu, 9 Feb 2017 01:21:54 +0000 (17:21 -0800)]
intel/isl: Add an isl_swizzle_supports_rendering helper

This helper encodes more details, specifically about Haswell, than the
previous asserts in isl_surface_state.c.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agoi965/surface_state: Use an identity swizzle pre-Haswell
Jason Ekstrand [Thu, 9 Feb 2017 22:50:01 +0000 (14:50 -0800)]
i965/surface_state: Use an identity swizzle pre-Haswell

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agoblorp: Handle the RGB workaround more like other workarounds
Jason Ekstrand [Sat, 21 Jan 2017 15:59:56 +0000 (07:59 -0800)]
blorp: Handle the RGB workaround more like other workarounds

The previous version was sort-of strapped on in that it just adjusted
the blit rectangle and trusted in the fact that we would use texelFetch
and round to the nearest integer to ensure that the component positions
matched.  This new version, while slightly more complicated, is more
accurate because all three components end up with exactly the same
dst_pos and so they will get interpolated and sampled at the same
texture coordinate.  This makes the workaround suitable for using with
scaled blits.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agoi965: silence unused variable
Lionel Landwerlin [Wed, 9 May 2018 15:40:37 +0000 (16:40 +0100)]
i965: silence unused variable

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 2dc29e095f9da ("i965: Don't leak blorp on Gen4-5.")
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
6 years agointel: devinfo: silence coverity warning
Lionel Landwerlin [Wed, 9 May 2018 14:08:03 +0000 (15:08 +0100)]
intel: devinfo: silence coverity warning

It's just not possible to have a device with no subslices.

CID: 1433511
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
6 years agodri3: Only update number of back buffers in loader_dri3_get_buffers
Michel Dänzer [Fri, 27 Apr 2018 15:41:48 +0000 (17:41 +0200)]
dri3: Only update number of back buffers in loader_dri3_get_buffers

And only free no longer needed back buffers there as well.

We want to stick to the same back buffer throughout a frame, otherwise
we can run into various issues.

Bugzilla: https://bugs.freedesktop.org/105906
Bugzilla: https://bugs.freedesktop.org/106399
Fixes: 3160cb86aa92 "egl/x11: Re-allocate buffers if format is suboptimal"
Reported-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
Tested-by: Eero Tamminen <eero.t.tamminen@intel.com>
Acked-by: Daniel Stone <daniels@collabora.com>
6 years agoanv: ignore pColorBlendState if all color attachments of the subpass are unused
Samuel Iglesias Gonsálvez [Mon, 7 May 2018 06:42:56 +0000 (08:42 +0200)]
anv: ignore pColorBlendState if all color attachments of the subpass are unused

According to Vulkan spec:

  "pColorBlendState is a pointer to an instance of the
   VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
   pipeline has rasterization disabled or if the subpass of the render pass the
   pipeline is created against does not use any color attachments."

Fixes tests from CL#2505:

   dEQP-VK.renderpass.*.simple.color_unused_omit_blend_state

v2:
- Check that blend is not NULL before usage.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agomesa: remove hard-coded OpenGL 3.2 compat limit
Timothy Arceri [Tue, 8 May 2018 00:35:40 +0000 (10:35 +1000)]
mesa: remove hard-coded OpenGL 3.2 compat limit

Just let validate_context_version() do it instead. This fixes
MESA_GL_VERSION_OVERRIDE for compat, it will also allow us to
enable new compat versions on a per driver bases in future.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
6 years agomesa: add GLSLVersionCompat constant
Timothy Arceri [Tue, 8 May 2018 00:10:39 +0000 (10:10 +1000)]
mesa: add GLSLVersionCompat constant

This allows drivers to define what version of GLSL they support
in compat. This will be needed in order to support compat 3.2
without breaking drivers that wont support it.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
6 years agomesa: dont call _mesa_override_glsl_version() in _mesa_init_constants()
Timothy Arceri [Mon, 7 May 2018 23:22:41 +0000 (09:22 +1000)]
mesa: dont call _mesa_override_glsl_version() in _mesa_init_constants()

All drivers that support GLSL will later set their default GLSL versions
overriding this override call. They currently all call
 _mesa_override_glsl_version() again later in order to support overrides.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
6 years agomesa: dont set GLSLVersion in _mesa_init_constants()
Timothy Arceri [Mon, 7 May 2018 23:19:04 +0000 (09:19 +1000)]
mesa: dont set GLSLVersion in _mesa_init_constants()

Just leave it as 0 and let the drivers set it (as they already do)
to avoid redundantly initialising it.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
6 years agopipe-loader: Free driver_name in error path
Jan Vesely [Tue, 8 May 2018 03:40:47 +0000 (23:40 -0400)]
pipe-loader: Free driver_name in error path

CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
6 years agoglsl: change ast_type_qualifier bitset size to work around GCC 5.4 bug
Brian Paul [Tue, 8 May 2018 14:24:21 +0000 (08:24 -0600)]
glsl: change ast_type_qualifier bitset size to work around GCC 5.4 bug

Change the size of the bitset from 128 bits to 96.  This works around an
apparent GCC 5.4 bug in which bad SSE code is generated, leading to a
crash in ast_type_qualifier::validate_in_qualifier() (ast_type.cpp:654).

This can be repro'd with the Piglit test tests/spec/glsl-1.50/execution/
varying-struct-basic-gs-fs.shader_test

Bugzilla:https://bugs.freedesktop.org/show_bug.cgi?id=105497
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Tested-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
6 years agoi965: Dump validation list on INTEL_DEBUG=bat,submit.
Kenneth Graunke [Tue, 10 Apr 2018 08:19:55 +0000 (01:19 -0700)]
i965: Dump validation list on INTEL_DEBUG=bat,submit.

This is really useful when debugging any sort of buffer management
issues, so just printing it during INTEL_DEBUG=bat,submit seems
reasonable.  With bat, we're already spamming so much output that
it doesn't really hurt.  With submit, it's still easy to grep for
the older information, and the new information is nice too.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
6 years agoi965/miptree: Remove redundant fields from intel_miptree_aux_buffer
Jason Ekstrand [Fri, 4 May 2018 23:49:47 +0000 (16:49 -0700)]
i965/miptree: Remove redundant fields from intel_miptree_aux_buffer

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agoi965: Simplify brw_emit_depthbuffer and brw_emit_depth_stencil_hiz
Jason Ekstrand [Sat, 5 May 2018 05:57:09 +0000 (22:57 -0700)]
i965: Simplify brw_emit_depthbuffer and brw_emit_depth_stencil_hiz

Now that we're using ISL, a good chunk of brw_emit_depthstencil is
pointless checks which ISL will do for us anyway.  Since we only have
one manual depth buffer emit function, move the useful bits into it.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agoi965: Move brw_emit_depth_stencil_hiz higher up in the file
Jason Ekstrand [Sat, 5 May 2018 05:46:49 +0000 (22:46 -0700)]
i965: Move brw_emit_depth_stencil_hiz higher up in the file

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agoi965: Use ISL for emitting depth/stencil/hiz state on gen6+
Jason Ekstrand [Sat, 5 May 2018 05:32:24 +0000 (22:32 -0700)]
i965: Use ISL for emitting depth/stencil/hiz state on gen6+

We leave gen4-5 alone because the ISL code hasn't really been well-
tested on gen4-5 or with combined depth-stencil because we don't use
BLORP for depth operations on gen4-5.  Also, the gen4-5 code has to deal
with intratile offsets for LOD hacks and ISL doesn't handle those yet.
We could make ISL handle gen4-5 capable or we could just not bother.

Among other things, this should make future platform enabling easier
because it means we don't have to update multiple (or hand-rolled!)
depth stencil emit paths.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agoi965: Use the brw_depthbuffer atom on all gens
Jason Ekstrand [Sat, 5 May 2018 05:41:19 +0000 (22:41 -0700)]
i965: Use the brw_depthbuffer atom on all gens

The only reason why we had two atoms was that the one we used for gen7+
depended on _NEW_DEPTH and _NEW_STENCIL as well as _NEW_BUFFERS.  Since
this is no longer true, we can combine them into one atom.  We do add a
dependence on BRW_NEW_AUX_STATE but that should never get set on gen4-5
so adding it is a no-op for those platforms.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agoi965: Always set depth/stencil write enables on gen7+
Jason Ekstrand [Mon, 7 May 2018 17:57:49 +0000 (10:57 -0700)]
i965: Always set depth/stencil write enables on gen7+

The hardware will AND these fields with the corresponding fields in
DEPTH_STENCIL_STATE so there's no real reason to toggle them on and off
based on state bits.  This removes our reliance on the _NEW_DEPTH and
_NEW_STENCIL state bits and better matches what ISL does.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agoi965: Re-order depth/stencil/hiz/clear packets to match ISL
Jason Ekstrand [Sat, 5 May 2018 19:35:01 +0000 (12:35 -0700)]
i965: Re-order depth/stencil/hiz/clear packets to match ISL

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agoi965: Re-emit depth/stencil/hiz on BRW_NEW_AUX_STATE
Jason Ekstrand [Sat, 5 May 2018 19:48:54 +0000 (12:48 -0700)]
i965: Re-emit depth/stencil/hiz on BRW_NEW_AUX_STATE

Certain things can change the aux usage or fast clear color of a depth
surface and we want to re-emit if that happens.  For instance, if you do
a fast depth clear of an already clear depth surface, we will just set
the clear color and not do anything else.  In that case, we could fail
to re-emit 3DSTATE_CLEAR_PARAMS and not get the new fast-clear color.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agointel: devinfo: fix assertion on devices with odd number of EUs
Lionel Landwerlin [Mon, 23 Apr 2018 16:52:37 +0000 (17:52 +0100)]
intel: devinfo: fix assertion on devices with odd number of EUs

I forgot to change the assert in the second helper function in a
previous change.

This hit the assert() on a Broadwell platform with 1 slice, 3
subslices but all EUs disabled in subslice 1 & 2.

Fixes: c1900f5b0fb ("intel: devinfo: add helper functions to fill fusing masks values")
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>