Marek Olšák [Fri, 25 Oct 2019 04:15:37 +0000 (00:15 -0400)]
st/mesa: call nir_lower_flrp only once per shader
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Marek Olšák [Fri, 25 Oct 2019 04:06:34 +0000 (00:06 -0400)]
st/mesa: call nir_opt_access only once
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Leo Liu [Mon, 4 Nov 2019 16:18:46 +0000 (11:18 -0500)]
ac: add missing Arcturus to the info of pc lines
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: Marek Olšák <marek.olsak@amd.com>
Alyssa Rosenzweig [Mon, 4 Nov 2019 20:35:23 +0000 (15:35 -0500)]
panfrost/ci: Update T760 expectations
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Thu, 31 Oct 2019 18:57:54 +0000 (14:57 -0400)]
pan/midgard: Extend default_phys_reg to !32-bit
We can pass through a size.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Thu, 31 Oct 2019 18:56:45 +0000 (14:56 -0400)]
pan/midgard: Extend swizzle packing for vec4/16-bit
We would like to pack not just xyzw swizzles but also efgh swizzles.
This should work for vec4/16-bit. More work will be needed to pack
swizzles for vec8/16-bit and even more work for 8-bit, of course.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Thu, 31 Oct 2019 18:57:35 +0000 (14:57 -0400)]
pan/midgard: Extend offset_swizzle to non-32-bit
We take a size parameter; use it.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Mon, 4 Nov 2019 15:44:54 +0000 (10:44 -0500)]
pan/midgard: offset_swizzle doesn't need dstsize
This argument should be omitted.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Mon, 4 Nov 2019 15:40:37 +0000 (10:40 -0500)]
pan/midgard: Add bizarre corner case
Someone really needs to look into this.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 22 Oct 2019 01:32:35 +0000 (21:32 -0400)]
pan/midgard: Compute bundle interference
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Mon, 4 Nov 2019 15:32:49 +0000 (10:32 -0500)]
pan/midgard: Fix quadword_count handling
Spilling can mess with this considerably.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Mon, 4 Nov 2019 15:09:31 +0000 (10:09 -0500)]
pan/midgard: Validate tags when branching
Midgard prefetches instructions based on tag (ALU, LD/ST, texture *
size). To do so, the shader descriptor specifies the tag of the first
instruction, all instructions specify the tag of the next linear
instruction is, and all branches explicitly specify the tag of the
branch target.
If you mess this up, you get an INSTR_TYPE_MISMATCH, which unambiguously
refers to this problem, but it's still annoying to try to work out all
the branch targets in your head to debug.
Instead, let's track the tags of various blocks over time, so we can
automatically validate tags of branch targets, to make
INSTR_TYPE_MISMATCH issues immediately obvious in a disassembly.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Daniel Schürmann [Thu, 31 Oct 2019 16:33:35 +0000 (17:33 +0100)]
aco: fix accidential reordering of instructions when scheduling
Fixes:
86786999189c43b4a2c8e1c1a18b55cd2f369fff "aco: implement VGPR spilling"
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Daniel Schürmann [Fri, 1 Nov 2019 08:06:26 +0000 (09:06 +0100)]
aco: only use single-dword loads/stores for spilling
Fixes:
86786999189c43b4a2c8e1c1a18b55cd2f369fff "aco: implement VGPR spilling"
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Daniel Schürmann [Thu, 31 Oct 2019 12:25:44 +0000 (13:25 +0100)]
aco: fix immediate offset for spills if scratch is used
Fixes:
86786999189c43b4a2c8e1c1a18b55cd2f369fff "aco: implement VGPR spilling"
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Lionel Landwerlin [Wed, 30 Oct 2019 11:51:08 +0000 (13:51 +0200)]
anv: Properly handle host query reset of performance queries
The host query reset entry point didn't use the availability offset
for performance queries.
To fix this, reorder the availability of performance queries to match
other queries.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
2b5f30b1d9 ("anv: implement VK_INTEL_performance_query")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Paul Gofman [Mon, 4 Nov 2019 12:31:10 +0000 (15:31 +0300)]
state_tracker: Handle texture view min level in st_generate_mipmap()
Signed-off-by: Paul Gofman <gofmanp@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
James Xiong [Thu, 4 Apr 2019 15:27:33 +0000 (08:27 -0700)]
iris: try to set the specified tiling when importing a dmabuf
When importing a dmabuf with a specified tiling, the dmabuf user
should always try to set the tiling mode because: 1) the exporter
can set tiling AFTER exporting/importing. 2) a dmabuf could be
exported from a kernel driver other than i915, in this case the
dmabuf user and exporter need to set tiling separately.
This patch fixes a problem when running vkmark under weston with
iris on ICL, it crashed to console with the following assert. i965
doesn't have this problem as it always tries to set the specified
tiling mode.
weston: ../src/gallium/drivers/iris/iris_resource.c:990: iris_resource_from_handle: Assertion `res->bo->tiling_mode == isl_tiling_to_i915_tiling(res->surf.tiling)' failed.
Signed-off-by: James Xiong <james.xiong@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Kenneth Graunke [Mon, 4 Nov 2019 07:50:38 +0000 (23:50 -0800)]
iris: Fix "Force Zero RTA Index Enable" setting again
In
2ca0d913ea8, we began updating cso_fb->layers to the actual layer
count, rather than 0. This fixed cases where we were setting "Force
Zero RTA Index Enable" even when doing layered rendering. Sadly, it
also broke the check entirely: cso_fb->layers is now 1 for non-layered
cases, but the Force Zero RTA Index check was still comparing for 0.
Fixes:
2ca0d913ea8 ("iris: Fix framebuffer layer count")
Dylan Baker [Fri, 25 Oct 2019 20:48:38 +0000 (13:48 -0700)]
nir: correct use of identity check in python
Python has the identity operator `is`, and the equality operator `==`.
Using `is` with strings sometimes works in CPython due to optimizations
(they have some kind of cache), but it may not always work.
Fixes:
96c4b135e34d0804e41bfbc28fc1b5050c49d71e
("nir/algebraic: Don't put quotes around floating point literals")
Reviewed-by: Matt Turner <mattst88@gmail.com>
Boris Brezillon [Mon, 4 Nov 2019 10:57:22 +0000 (11:57 +0100)]
panfrost: MALI_DEPTH_TEST is actually MALI_DEPTH_WRITEMASK
MALI_DEPTH_TEST should only be set when depth->writemask is true,
not when the depth test is enabled. Let's rename the flag and patch
panfrost_bind_depth_stencil_state() to do the right thing.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Lionel Landwerlin [Mon, 4 Nov 2019 08:21:00 +0000 (10:21 +0200)]
vulkan: bump headers/registry to 1.1.127
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Samuel Pitoiset [Fri, 1 Nov 2019 08:34:12 +0000 (09:34 +0100)]
radv: fix compute pipeline keys when optimizations are disabled
If an app first creates a compute pipeline with
VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT set, then re-compile it
without that flag, the driver should re-compile the compute shader.
Otherwise, it will return the unoptimized one.
Fixes:
ce188813bfe ("radv: add initial support for VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Karol Herbst [Sat, 2 Nov 2019 23:57:28 +0000 (00:57 +0100)]
nv50/ir: fix crash in isUniform for undefined values
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Lionel Landwerlin [Fri, 1 Nov 2019 17:43:00 +0000 (19:43 +0200)]
mesa: check draw buffer completeness on glClearBufferfi/glClearBufferiv
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Vasily Khoruzhick [Sat, 26 Oct 2019 02:08:57 +0000 (19:08 -0700)]
lima: set dithering flag when necessary
Bit 13 in aux1 enables dithering
Reviewed-by: Qiang.Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Marek Olšák [Thu, 31 Oct 2019 00:38:44 +0000 (20:38 -0400)]
glsl: encode struct/interface types better
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Thu, 31 Oct 2019 00:27:08 +0000 (20:27 -0400)]
glsl: encode array types better
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Thu, 31 Oct 2019 00:22:49 +0000 (20:22 -0400)]
glsl: encode explicit_stride for basic types better
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Thu, 31 Oct 2019 00:18:05 +0000 (20:18 -0400)]
glsl: encode vector_elements and matrix_columns better
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Thu, 31 Oct 2019 00:15:36 +0000 (20:15 -0400)]
glsl: encode/decode types using a union with bitfields for readability
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Vasily Khoruzhick [Fri, 25 Oct 2019 05:14:05 +0000 (22:14 -0700)]
lima: ignore flags while looking for BO in cache
Any BO would work, we don't have any BO types yet anyway. Moreover
lima_submit_add_bo() changes BO flags so they won't match allocation
flags.
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Vasily Khoruzhick [Fri, 25 Oct 2019 05:12:30 +0000 (22:12 -0700)]
lima: align size before trying to fetch BO from cache
Otherwise we may be looking in wrong bucket
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Vasily Khoruzhick [Fri, 25 Oct 2019 03:16:06 +0000 (20:16 -0700)]
lima: add debug prints for BO cache
LIMA_DEBUG=bocache now activates debug prints for BO allocation,
destruction and BO cache.
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Alyssa Rosenzweig [Thu, 31 Oct 2019 19:50:45 +0000 (15:50 -0400)]
pan/midgard: Use fp32 blend shaders
Clearly we do want to have fp16 at some point ... but I kind of give up
debugging and it turns out the issues with fp16 support in 'frost are so
deeply rooted that I might as well disable this non-opt and land
LCRA now.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Bas Nieuwenhuizen [Fri, 1 Nov 2019 00:07:02 +0000 (01:07 +0100)]
radv: Close all unnecessary fds in secure compile.
The seccomp filter allows read/write, let us make sure nobody can
do anything with this.
Fixes:
cff53da3748 "radv: enable secure compile support"
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Erik Faye-Lund [Mon, 28 Oct 2019 15:25:10 +0000 (16:25 +0100)]
anv: remove incorrect polygonMode=point early-out
This is incorrect, because polygonMode only applies if the final
primitive type is a polygon; polygonMode doesn't apply to
line-primitives as the comment suggests.
The Vulkan 1.1 spec, section 26.11, "Polygons" defines that polygons are
separate from points and line segments:
" A polygon results from the decomposition of a triangle strip, triangle
fan or a series of independent triangles. Like points and line segments,
polygon rasterization is controlled by several variables in the
VkPipelineRasterizationStateCreateInfo structure. "
Further, section 26.11.2, "Polygon Mode", only define polygonMode to
apply to polygons:
" Possible values of the VkPipelineRasterizationStateCreateInfo::polygonMode
property of the currently active pipeline, specifying the method of
rasterization for polygons, are: "
This seems to clearly define that polygonMode doesn't apply to points
and lines, so let's make sure that we don't early out with the wrong
value.
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Alyssa Rosenzweig [Wed, 30 Oct 2019 20:29:28 +0000 (16:29 -0400)]
pan/midgard: Eliminate blank_alu_src
We don't need it in practice, so this is some more cleanup.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Sat, 26 Oct 2019 18:06:17 +0000 (14:06 -0400)]
pan/midgard: Refactor swizzles
Rather than having hw-specific swizzles encoded directly in the
instructions, have a unified swizzle arary so we can manipulate swizzles
generically.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Sat, 26 Oct 2019 19:50:38 +0000 (15:50 -0400)]
pan/midgard: Add a dummy source for loads
We want symmetry between loads and stores, so we add a dummy source. So
we get, e.g.
st_int4 _, val, arg_1, arg_2
ld_int4 dest, _, arg_1, arg_2
Semantically, this dummy source represents the data itself, as if the
load is simply a move. That means it has a swizzle that acts as a
source.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Sat, 26 Oct 2019 19:50:26 +0000 (15:50 -0400)]
pan/midgard: Remove OP_IS_STORE_VARY
Unused.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Timothy Arceri [Wed, 30 Oct 2019 00:34:27 +0000 (11:34 +1100)]
glsl: disable lower_fragdata_array() for NIR drivers
This function was added in
7e414b58640a to work around a defect in
lower_output_reads(). As of the previous commit no NIR driver calls
lower_output_reads().
This change means we don't need the special GLSL IR style
gl_FragData handling for building the resource list in a NIR based
linker.
No shader-db change on SKL i965.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Timothy Arceri [Wed, 30 Oct 2019 00:24:37 +0000 (11:24 +1100)]
glsl: just use NIR to lower outputs when driver can't read outputs
This will allow us to stop lowering gl_FragData in GLSL IR for NIR
drivers which means we won't need the special GLSL IR type
handling for building the resource list in a NIR based linker.
i965 has been doing this since
b828f7a27b2b.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Icenowy Zheng [Tue, 22 Oct 2019 14:14:56 +0000 (22:14 +0800)]
lima: support indexed draw with bias
When doing an indexed draw with index_bias set to a non-zero value (e.g.
by glDrawElementsBaseVertex), the vertex buffer should be offseted by
index_bias vertices.
Add this offset when setting the vertex buffer address.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Jason Ekstrand [Wed, 30 Oct 2019 20:05:29 +0000 (15:05 -0500)]
anv: Move the RT BTI flush workaround to begin_subpass
Now that we're no longer compacting binding table entries, the only time
they can possibly change is when we actually switch subpasses.
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Jason Ekstrand [Wed, 30 Oct 2019 19:07:47 +0000 (14:07 -0500)]
anv: Stop compacting render targets in the binding table
Instead, always emit one entry for every color attachment in the subpass
or one NULL if there are no color attachments. This will let us adjust
an Ice Lake workaround so we don't get a stall on every draw call.
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Jason Ekstrand [Wed, 30 Oct 2019 20:53:11 +0000 (15:53 -0500)]
anv: Don't claim the null RT as a valid color target
If it's NULL, we can let the compiler go ahead and delete it or flag it
as NULL.
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Jason Ekstrand [Wed, 30 Oct 2019 20:50:51 +0000 (15:50 -0500)]
anv: Don't delete fragment shaders that write sample mask
Also, use color_outputs_valid rather than nr_color_outputs since it
should be a bit more accurate.
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Yevhenii Kolesnikov [Mon, 7 Oct 2019 12:59:52 +0000 (15:59 +0300)]
glsl: Enable textureSize for samplerExternalOES
From OES_EGL_image_external_essl3
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1901
Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Eric Anholt [Mon, 21 Oct 2019 20:36:14 +0000 (13:36 -0700)]
ci: Switch over to an autoscaling GKE cluster for builds.
The GKE pool we're using is 1-3 32-core VMs, preemptible (to keep
costs down), with 8 jobs concurrent per system. We have plenty of
memory (4G/core), so we run make -j8 to try to keep the cores busy even
when one job is in a single-threaded step (docker image download, git
clone, artifacts processing, etc.) When all jobs are generating work
for all the cores, they'll be scheduled fairly.
The nodes in the pool have 300GB boot disks (over-provisioned in space
to provide enough iops and throughput) mounted to /ccache, and
CACHE_DIR set pointing to them. This means that once a new
autoscaled-up node has run some jobs, it should have a hot ccache from
then on (instead of having to rely on the docker container cache
having our ccache laying around and not getting wiped out by some
other fd.o job). Local SSDs would provide higher performance, but
unfortunately are not supported with the cluster autoscaler.
For now, the softpipe/llvmpipe test runs are still on the shared
runners, until I can get them ported onto Bas's runner so they can be
parallelized in a single job.
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Eric Anholt [Mon, 28 Oct 2019 22:21:44 +0000 (15:21 -0700)]
ci: Make lava inherit the ccache setup of the .build script.
It was just duplicating the code.
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Eric Engestrom [Wed, 25 Sep 2019 16:38:49 +0000 (17:38 +0100)]
meson: revert glvnd workaround
This effectively reverts MR !2112.
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Eric Engestrom [Wed, 25 Sep 2019 16:42:18 +0000 (17:42 +0100)]
meson: require glvnd 1.2.0
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Eric Engestrom [Wed, 25 Sep 2019 19:18:27 +0000 (20:18 +0100)]
gitlab-ci: build a recent enough version of GLVND (ie. 1.2.0)
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Eric Engestrom [Thu, 31 Oct 2019 15:35:29 +0000 (15:35 +0000)]
meson: move idep_xmlconfig_headers to xmlpool/
That's where `xmlpool_options_h` is defined, and this way we can make sure
nobody starts making use of it in the future :)
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Jason Ekstrand [Thu, 31 Oct 2019 15:28:05 +0000 (10:28 -0500)]
anv: Use the new BO alloc API for Android
Fixes:
a44f5ee0d8b "anv: Rework the internal BO allocation API"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Erik Faye-Lund [Wed, 30 Oct 2019 12:57:21 +0000 (13:57 +0100)]
zink: emit line-width when using polygon line-mode
When switching this to dynamic state, I forgot that this also needs to
be emitted when we use a polygon-mode set to lines.
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Fixes:
6d30abb4f14 ("zink: use dynamic state for line-width")
Eric Engestrom [Sat, 26 Oct 2019 23:55:52 +0000 (00:55 +0100)]
radeon: replace xmlpool_options_h with idep_xmlconfig_headers
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Eric Engestrom [Sat, 26 Oct 2019 23:55:45 +0000 (00:55 +0100)]
r200: replace xmlpool_options_h with idep_xmlconfig_headers
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Eric Engestrom [Sat, 26 Oct 2019 23:55:37 +0000 (00:55 +0100)]
nouveau: replace xmlpool_options_h with idep_xmlconfig_headers
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Eric Engestrom [Sat, 26 Oct 2019 23:55:30 +0000 (00:55 +0100)]
i915: replace xmlpool_options_h with idep_xmlconfig_headers
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Eric Engestrom [Sat, 26 Oct 2019 23:55:06 +0000 (00:55 +0100)]
dri: replace xmlpool_options_h with idep_xmlconfig_headers
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Eric Engestrom [Sat, 26 Oct 2019 23:54:49 +0000 (00:54 +0100)]
targets/xvmc: replace xmlpool_options_h with idep_xmlconfig_headers
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Eric Engestrom [Sat, 26 Oct 2019 23:54:38 +0000 (00:54 +0100)]
targets/xa: replace xmlpool_options_h with idep_xmlconfig_headers
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Eric Engestrom [Sat, 26 Oct 2019 23:54:28 +0000 (00:54 +0100)]
targets/vdpau: replace xmlpool_options_h with idep_xmlconfig_headers
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Eric Engestrom [Sat, 26 Oct 2019 23:54:19 +0000 (00:54 +0100)]
targets/va: replace xmlpool_options_h with idep_xmlconfig_headers
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Eric Engestrom [Sat, 26 Oct 2019 23:54:10 +0000 (00:54 +0100)]
targets/omx: replace xmlpool_options_h with idep_xmlconfig_headers
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Eric Engestrom [Sat, 26 Oct 2019 23:53:37 +0000 (00:53 +0100)]
loader: replace xmlpool_options_h with idep_xmlconfig_headers
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Eric Engestrom [Sat, 26 Oct 2019 23:51:41 +0000 (00:51 +0100)]
pipe-loader: drop unnecessary xmlpool_options_h
idep_xmlconfig already covers that
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Eric Engestrom [Sat, 26 Oct 2019 23:51:22 +0000 (00:51 +0100)]
radv: drop unnecessary xmlpool_options_h
idep_xmlconfig already covers that
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Eric Engestrom [Sat, 26 Oct 2019 23:04:33 +0000 (00:04 +0100)]
anv: add missing xmlconfig headers dependency
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Eric Engestrom [Sat, 26 Oct 2019 23:48:36 +0000 (00:48 +0100)]
meson: split out idep_xmlconfig_headers from idep_xmlconfig
A bunch of components need the former but not the latter.
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Alyssa Rosenzweig [Sat, 26 Oct 2019 19:10:22 +0000 (15:10 -0400)]
pipe-loader: Build kmsro loader for with all kmsro targets
Build failure reported by i965 CI, triggered by building dynamic
pipeloaders with kmsro drivers (besides 'frost). At this point, there's
no reason to actually do that -- mesa CI didn't mind -- but let's not
break the build.
v2: Simplify script. Add extra dependencies for v3d.
Fixes:
afb0d08cb0f ("pipe-loader: Default to kmsro if probe fails")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reported-by: Clayton Craft <clayton.a.craft@intel.com>
Tested-by: Clayton Craft <clayton.a.craft@intel.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Erik Faye-Lund [Tue, 29 Oct 2019 09:07:53 +0000 (10:07 +0100)]
zink: heap-allocate samplers objects
VkSampler is 64-bit even on 32-bit systems, so casting it to a pointer
is a bad idea there. So let's heap-allocate the sampler-object instead.
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2017
Reviewed-by: Witold Baryluk <witold.baryluk@gmail.com>
Tested-by: Witold Baryluk <witold.baryluk@gmail.com>
Jason Ekstrand [Wed, 30 Oct 2019 17:31:12 +0000 (12:31 -0500)]
anv: Zero released anv_bo structs
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Tue, 29 Oct 2019 19:26:15 +0000 (14:26 -0500)]
anv: Use a bitset for tracking residency
Now that we can conveniently map between GEM handles and struct anv_bo
pointers, we can use a simple bitset for residency tracking instead of
the complex hash set. This shaves about 3% off of a CPU-limited example
running with the Dawn WebGPU implementation.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Wed, 30 Oct 2019 19:37:45 +0000 (14:37 -0500)]
anv: Set the batch allocator for compute pipelines
Otherwise relocations just up and crash.
Fixes:
a3153162a9b "anv: Delay allocation of relocation lists"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Tue, 29 Oct 2019 20:18:16 +0000 (15:18 -0500)]
anv: Add a device parameter to anv_execbuf_add_bo
We're about to start needing to lookup BO pointers by GEM handle so we
need access to the device.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Mon, 28 Oct 2019 23:03:32 +0000 (18:03 -0500)]
anv: Drop anv_bo_init and anv_bo_init_new
BOs are now only ever allocated through the BO cache so there's no need
to have these exposed.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Mon, 28 Oct 2019 22:28:09 +0000 (17:28 -0500)]
anv: Allocate misc BOs from the cache
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Mon, 28 Oct 2019 21:42:02 +0000 (16:42 -0500)]
anv: Allocate scratch BOs from the cache
While we're here, we get rid of the locking and use a lock-free
algorithm. The chances of spilling contention are low and this is
actually a bit simpler in some ways.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Mon, 28 Oct 2019 20:42:20 +0000 (15:42 -0500)]
anv: Allocate batch and fence buffers from the cache
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Mon, 28 Oct 2019 19:49:38 +0000 (14:49 -0500)]
util: Add a free list structure for use with util_sparse_array
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Fri, 25 Oct 2019 22:15:31 +0000 (17:15 -0500)]
anv: Allocate descriptor buffers from the BO cache
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Fri, 25 Oct 2019 22:12:06 +0000 (17:12 -0500)]
anv: Set more flags on descriptor pool buffers
the ASYNC flag, in particular, has the potential to help performance
because it means less sync tracking in the kernel.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Fri, 25 Oct 2019 22:07:36 +0000 (17:07 -0500)]
anv: Allocate query pool BOs from the cache
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Fri, 25 Oct 2019 22:07:02 +0000 (17:07 -0500)]
anv: Use the query_slot helper in vkResetQueryPoolEXT
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Fri, 25 Oct 2019 21:29:29 +0000 (16:29 -0500)]
anv: Allocate block pool BOs from the cache
This commit switches block pools over to being allocated from the BO
cache rather than being allocated manually by the block pool.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Wed, 30 Oct 2019 16:44:12 +0000 (11:44 -0500)]
anv/tests: Initialize the BO cache and device mutex
We're about to start depending on the BO cache in the state and block
pools so we need them properly initialized for the tests to work.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Wed, 30 Oct 2019 16:43:53 +0000 (11:43 -0500)]
anv/tests: Zero-initialize instances
Some of the tests were actually relying on some of those uninitialized
bits to be non-zero. In particular, a couple want use_softpin = true.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Fri, 25 Oct 2019 23:18:52 +0000 (18:18 -0500)]
anv: Choose BO flags internally in anv_block_pool
All block pools are allocated with the same flags. There's no good
reason why it needs to be configurable.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Fri, 25 Oct 2019 22:45:28 +0000 (17:45 -0500)]
anv: Rework the internal BO allocation API
This makes a number of changes to the current API:
1. Everything is renamed to anv_device_* instead of anv_bo_cache_*
because the BO cache is soon going to be the sole BO allocation path
and not some special case to make import/export work.
2. Drop the cache parameter. It's totally redundant with the device
and just annoying to keep typing.
3. Rework flags so that they go the convenient direction for usage in
ANV rather than whichever awkward way the i915 specified it to
maintain backwards compatibility. This also gives us the
opportunity to set some defaults.
4. Add flags for mapping and coherency.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Fri, 25 Oct 2019 21:42:47 +0000 (16:42 -0500)]
anv: Use anv_block_pool_foreach_bo in get_bo_from_pool
While we're at it, use gen_48b_address().
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Fri, 25 Oct 2019 21:10:11 +0000 (16:10 -0500)]
anv: Rework anv_block_pool_expand_range
The growing algorithms for the softpin case and the userptr version are
almost entirely different. Having this weird join doesn't make the code
more comprehensible. This rework does a few things:
1. Move the comment about 48-bit addresses to anv_device_init where we
actually unset the EXEC_OBJECT_SUPPORTS_48B_ADDRESS flag.
2. Separate the paths in anv_block_pool_expand_range so it's easier to
see what happens in the two different cases.
3. Use the anv_block_poo::bos array for storing all allocated BOs in
both paths rather than using the cleanup list in both paths. This
lets us make the cleanups array only used for mmaps of the memfd for
the userptr case.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Fri, 25 Oct 2019 20:42:22 +0000 (15:42 -0500)]
anv: Fix a potential BO handle leak
Fixes:
731c4adcf9b "anv/allocator: Add support for non-userptr"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Fri, 25 Oct 2019 19:52:37 +0000 (14:52 -0500)]
anv: Handle state pool relocations using "wrapper" BOs
Instead of depending on a mutable BO in the state pool for handling
growing state pools, add a concept of "wrapper" BOs which just wrap an
actual BO. This way, the wrapper can exist once for all of time and we
can put it in relocation lists even if the actual BO it references gets
swapped out.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Tue, 29 Oct 2019 01:12:24 +0000 (20:12 -0500)]
anv: Replace ANV_BO_EXTERNAL with anv_bo::is_external
We're not THAT strapped for space that we can't burn one extra bit for
a boolean. If we're really worried about it, we can always shrink the
flags field to 16 bits because the kernel only uses 7 currently.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Fri, 25 Oct 2019 19:51:19 +0000 (14:51 -0500)]
anv: Inline anv_block_pool_get_bo
It has exactly one caller and we're about to change some of the dynamics
which would make this confusing as a separate function.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Fri, 25 Oct 2019 21:33:23 +0000 (16:33 -0500)]
anv: Declare the bo in the anv_block_pool_foreach_bo loop
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Fri, 25 Oct 2019 19:33:48 +0000 (14:33 -0500)]
anv: Stop storing the GEM handle in anv_reloc_list_add
We have to go through and rewrite them all anyway so it doesn't do us
any good to put them in the list in anv_reloc_list_add. Also, for state
pools the handles are likely wrong by the time vkQueueSubmit is called.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>