Simon Pilgrim [Mon, 27 Nov 2017 18:14:18 +0000 (18:14 +0000)]
[X86][AVX512] Tag AVX512 PACKSS/PACKUS/PMADDWD/PMADDUBSW instructions with SSE_PACK/SSE_PMADD schedule classes
llvm-svn: 319065
Krzysztof Parzyszek [Mon, 27 Nov 2017 18:12:16 +0000 (18:12 +0000)]
[Hexagon] Implement HexagonSubtarget::isHVXVectorType
llvm-svn: 319064
Craig Topper [Mon, 27 Nov 2017 18:00:49 +0000 (18:00 +0000)]
[X86] Add avx512bw command lines to vselect-packss.ll
This shows several places where we fail to use masked move or blendm.
llvm-svn: 319063
Alexander Kornienko [Mon, 27 Nov 2017 17:59:26 +0000 (17:59 +0000)]
[clang-tidy] Rename qualified references to check class + support inconsistent names
llvm-svn: 319062
Jonas Hahnfeld [Mon, 27 Nov 2017 17:55:47 +0000 (17:55 +0000)]
Delete obsolete function mergeUseListsImpl
mergeUseLists is implemented iteratively since r243590.
Differential Revision: https://reviews.llvm.org/D40491
llvm-svn: 319061
Kamil Rytarowski [Mon, 27 Nov 2017 17:54:26 +0000 (17:54 +0000)]
Build more sanitizers for NetBSD
Summary:
Enable for NetBSD:
- MSan,
- TSan,
- LSan.
Sponsored by <The NetBSD Foundation>
Reviewers: joerg, eugenis, dvyukov, vitalybuka
Reviewed By: eugenis
Subscribers: srhines, mgorny, llvm-commits, #sanitizers
Tags: #sanitizers
Differential Revision: https://reviews.llvm.org/D40464
llvm-svn: 319060
Craig Topper [Mon, 27 Nov 2017 17:51:55 +0000 (17:51 +0000)]
[X86] Make getSetCCResultType return vXi1 for any vXi32/vXi64 vector over 512 bits long when AVX512 is enabled.
Similar for vXi16/vXi8 with BWI.
Any vector larger than 512 bits will be split to 512 bits during legalization. But without this we will fold sexts with them before that making it difficult to recover leading to scalarization.
llvm-svn: 319059
Artem Dergachev [Mon, 27 Nov 2017 17:37:09 +0000 (17:37 +0000)]
[analyzer] pr34766: Fix a crash on explicit std::initializer_list constructor.
We didn't support the following syntax:
(std::initializer_list<int>){12}
which suddenly produces CompoundLiteralExpr that contains
CXXStdInitializerListExpr.
Lift the assertion and instead pass the value through CompoundLiteralExpr
transparently, as it doesn't add much.
Differential Revision: https://reviews.llvm.org/D39803
llvm-svn: 319058
Ben Hamilton [Mon, 27 Nov 2017 17:34:03 +0000 (17:34 +0000)]
[polly] Set up .arcconfig to point to new Diffusion PLO repository
Summary: We want to automatically copy the appropriate mailing list
for review requests to the polly repository.
For context, see the proposal and discussion here:
http://lists.llvm.org/pipermail/cfe-dev/2017-November/056032.html
Similar to D40179, I set up a new Diffusion repository with callsign
"PLO" for polly:
https://reviews.llvm.org/source/polly/
This explicitly updates polly's .arcconfig to point to the new C
repository in Diffusion, which will let us use Herald rule H270.
llvm-svn: 319056
Artem Dergachev [Mon, 27 Nov 2017 17:31:16 +0000 (17:31 +0000)]
[analyzer] pr34404: Fix a crash on modeling pointers to indirect members.
We were crashing whenever a C++ pointer-to-member was taken, that was pointing
to a member of an anonymous structure field within a class, eg.
struct A {
struct {
int x;
};
};
// ...
&A::x;
Differential Revision: https://reviews.llvm.org/D39800
llvm-svn: 319055
Simon Pilgrim [Mon, 27 Nov 2017 17:29:49 +0000 (17:29 +0000)]
[X86][SSE] Fix roundpd instructions to correctly use IIC_SSE_ROUNDPD_* itineraries
llvm-svn: 319054
Ben Hamilton [Mon, 27 Nov 2017 17:21:24 +0000 (17:21 +0000)]
[clang] Set up .arcconfig to point to new Diffusion C repository
Summary:
We want to automatically copy cfe-commits@ on review requests
to the clang repository.
Similar to D40179, I set up a new Diffusion repository with callsign
"C" for clang:
https://reviews.llvm.org/source/clang/
This explicitly updates clang's .arcconfig to point to the new C
repository in Diffusion, which will let us use Herald rule H268.
Reviewers: klimek, sammccall
Reviewed By: klimek
Subscribers: dlj, bkramer
Differential Revision: https://reviews.llvm.org/D40494
llvm-svn: 319052
Rafael Espindola [Mon, 27 Nov 2017 17:18:09 +0000 (17:18 +0000)]
Add a missing test.
We were not testing that we correctly handled a .o with a weak symbol
after a .so.
llvm-svn: 319051
Dmitry Preobrazhensky [Mon, 27 Nov 2017 17:14:35 +0000 (17:14 +0000)]
[AMDGPU][MC][DISASSEMBLER][GFX9] Corrected decoding of GLOBAL/SCRATCH opcodes
See bug 35433: https://bugs.llvm.org/show_bug.cgi?id=35433
Differential Revision: https://reviews.llvm.org/D40493
Reviewers: artem.tamazov, SamWot, arsenm
llvm-svn: 319050
Zaara Syeda [Mon, 27 Nov 2017 17:11:03 +0000 (17:11 +0000)]
[Power9] Improvements to vector extract with variable index exploitation
This patch extends on to rL307174 to not use the power9 vector extract with
variable index instructions when extracting word element 1. For such cases,
the existing selection of MFVSRWZ provides a better sequence.
Differential Revision: https://reviews.llvm.org/D38287
llvm-svn: 319049
Pavel Labath [Mon, 27 Nov 2017 17:06:42 +0000 (17:06 +0000)]
Remove custom TimePoint-formatting code
This was a temporary thing, until llvm has proper support for formatting
time. That time has come, so we can remove the relevant code. There
should be no change in the format of the time.
llvm-svn: 319048
Fangrui Song [Mon, 27 Nov 2017 16:59:26 +0000 (16:59 +0000)]
[XRay] Fix typo in docs. NFC
Reviewers: dberris
Differential Revision: https://reviews.llvm.org/D40461
llvm-svn: 319047
Alexey Bataev [Mon, 27 Nov 2017 16:54:08 +0000 (16:54 +0000)]
[OPENMP] Improve handling of cancel directives in target-based
constructs, NFC.
Improved handling of cancel|cancellation point directives inside
target-based for directives.
llvm-svn: 319046
Simon Pilgrim [Mon, 27 Nov 2017 16:43:18 +0000 (16:43 +0000)]
[X86][AVX512] Tag AVX512 sqrt instructions with SSE_SQRT schedule classes
llvm-svn: 319045
Jonas Devlieghere [Mon, 27 Nov 2017 16:40:46 +0000 (16:40 +0000)]
[llvm-dwarfdump] Display DW_AT_high_pc as absolute value
DWARF4 relative DW_AT_high_pc values are now displayed as absolute
addresses. The relative value is only shown when explicitly dumping the
forms, i.e. in show-form or verbose mode.
```
DW_AT_low_pc (0x0000000000000049)
DW_AT_high_pc (0x00000019)
```
becomes
```
DW_AT_low_pc (0x0000000000000049)
DW_AT_high_pc (0x0000000000000062)
```
Differential revision: https://reviews.llvm.org/D40317
rdar://
35416943
llvm-svn: 319044
Sanjay Patel [Mon, 27 Nov 2017 16:37:09 +0000 (16:37 +0000)]
[InstSimplify] use m_APFloat to simplify fcmp folds; NFCI
llvm-svn: 319043
Marshall Clow [Mon, 27 Nov 2017 16:17:19 +0000 (16:17 +0000)]
Fix failure on C++03 bots
llvm-svn: 319042
Sanjay Patel [Mon, 27 Nov 2017 16:08:34 +0000 (16:08 +0000)]
[InstSimplify] add fcmp with negative constant tests; NFC
This is a superset of the tests proposed with D40012 to show another potential improvement.
llvm-svn: 319041
Ben Hamilton [Mon, 27 Nov 2017 15:58:26 +0000 (15:58 +0000)]
[clang-tools-extra] Fix small typo in docs/ReleaseNotes.rst
Summary:
This is mainly a test diff to check the new Herald rule I
added in LLVM Phabricator to automatically Cc: cfe-commits on all
clang-tools-extra diffs.
Reviewers: Wizard, hokein, klimek
Reviewed By: Wizard
Subscribers: dlj, bkramer, sammccall
Differential Revision: https://reviews.llvm.org/D40180
llvm-svn: 319040
Ben Hamilton [Mon, 27 Nov 2017 15:58:25 +0000 (15:58 +0000)]
[clang-tools-extra] Set up .arcconfig to point to new Diffusion CTE repository
Summary:
I'm testing out a new Diffusion repository `CTE`:
https://reviews.llvm.org/source/clang-tools-extra/
This explicitly updates clang-tools-extra's `.arcconfig` to point to
the new `CTE` repository in Diffusion, which will let us set up Herald
rules, etc.
Reviewers: klimek, sammccall
Reviewed By: sammccall
Subscribers: bkramer, dlj
Differential Revision: https://reviews.llvm.org/D40179
llvm-svn: 319039
Marshall Clow [Mon, 27 Nov 2017 15:51:36 +0000 (15:51 +0000)]
Implement LWG#2948: unique_ptr does not define operator<< for stream output
llvm-svn: 319038
Vassil Vassilev [Mon, 27 Nov 2017 15:32:00 +0000 (15:32 +0000)]
Constify. NFC.
llvm-svn: 319037
Nirav Dave [Mon, 27 Nov 2017 15:28:15 +0000 (15:28 +0000)]
[DAG] Do MergeConsecutiveStores again before Instruction Selection
Summary:
Now that store-merge is only generates type-safe stores, do a second
pass just before instruction selection to allow lowered intrinsics to
be merged as well.
Reviewers: jyknight, hfinkel, RKSimon, efriedma, rnk, jmolloy
Subscribers: javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D33675
llvm-svn: 319036
Alexander Kornienko [Mon, 27 Nov 2017 15:17:13 +0000 (15:17 +0000)]
[clang-tidy] Fix link error in clang-tidy after the recent check renames.
llvm-svn: 319034
Gabor Horvath [Mon, 27 Nov 2017 15:05:24 +0000 (15:05 +0000)]
[clang-tidy] Misc redundant expressions check updated for overloaded operators
Patch by: Lilla Barancsuk
Differential Revision: https://reviews.llvm.org/D39243
llvm-svn: 319033
Simon Pilgrim [Mon, 27 Nov 2017 14:39:50 +0000 (14:39 +0000)]
[X86] Add INVLPGA to the existing INVLPG scheduling
llvm-svn: 319031
Petar Jovanovic [Mon, 27 Nov 2017 14:25:36 +0000 (14:25 +0000)]
[mips] fix asmstring of Ext and Ins instructions and mips16 JALRC/JRC
Make the print format consistent with other assembler instructions.
Adding a tab character instead of space in asmstring of Ext and Ins
instructions.
Removing space around the tab character for JALRC and replacing space with
tab in JRC.
Patch by Milos Stojanovic.
Differential Revision: https://reviews.llvm.org/D38144
llvm-svn: 319030
Simon Pilgrim [Mon, 27 Nov 2017 14:23:55 +0000 (14:23 +0000)]
[X86] Add scheduling tests for invlpg/invlpga
llvm-svn: 319029
Pavel Labath [Mon, 27 Nov 2017 13:47:14 +0000 (13:47 +0000)]
dotest: Mark more android targets as chatty
New android ndk linker started adding more flags to the produced
binaries, which causes older dynamic linkers display warnings to stderr
about unsupported flags. This interferes with our stderr tests.
Extend the hasChattyStderr function to catch these targets as well.
llvm-svn: 319028
Jan Korous [Mon, 27 Nov 2017 13:42:03 +0000 (13:42 +0000)]
[Support] Fix locking of shared variable in threadpool
llvm-svn: 319027
Fedor Sergeev [Mon, 27 Nov 2017 13:33:19 +0000 (13:33 +0000)]
[lit] Set shlibpath_var on Solaris
Summary:
During make check-all on Solaris, lit complains
llvm-lit: /vol/gcc/src/llvm/llvm/dist/tools/clang/test/Unit/lit.cfg.py:57: warning: unable to inject shared library path on 'SunOS'
The following patch avoids this: Solaris uses LD_LIBRARY_PATH like several other targets.
In theory, one could also handle LD_LIBRARY_PATH_{32,64} which take precedence over
LD_LIBRARY_PATH if set, but let's cross that bridge when we get there.
Patch by Rainer Orth.
Reviewers: rsmith, lichray
Reviewed By: lichray
Differential Revision: https://reviews.llvm.org/D39640
llvm-svn: 319026
Vedran Miletic [Mon, 27 Nov 2017 13:26:38 +0000 (13:26 +0000)]
[AMDGPU] Add custom lowering for llvm.log{,10}.{f16,f32} intrinsics
AMDGPU backend errors with "unsupported call to function" upon
encountering a call to llvm.log{,10}.{f16,f32} intrinsics. This patch
adds custom lowering to avoid that error on both R600 and SI.
Reviewers: arsenm, jvesely
Subscribers: tstellar
Differential Revision: https://reviews.llvm.org/D29942
llvm-svn: 319025
Krasimir Georgiev [Mon, 27 Nov 2017 13:23:45 +0000 (13:23 +0000)]
[clang-format] Add option to group multiple #include blocks when sorting includes
Summary:
This patch allows grouping multiple #include blocks together and sort all includes as one big block.
Additionally, sorted includes can be regrouped after sorting based on configured categories.
Contributed by @KrzysztofKapusta!
Reviewers: krasimir
Reviewed By: krasimir
Subscribers: cfe-commits, klimek
Differential Revision: https://reviews.llvm.org/D40288
llvm-svn: 319024
Alexander Kornienko [Mon, 27 Nov 2017 13:06:28 +0000 (13:06 +0000)]
[clang-tidy] Move checks from misc- to performance-
Summary:
rename_check.py misc-move-constructor-init performance-move-constructor-init
rename_check.py misc-inefficient-algorithm performance-inefficient-algorithm
Reviewers: hokein, aaron.ballman
Reviewed By: hokein, aaron.ballman
Subscribers: aaron.ballman, mgorny, xazax.hun, cfe-commits
Differential Revision: https://reviews.llvm.org/D40487
llvm-svn: 319023
Benjamin Kramer [Mon, 27 Nov 2017 12:48:26 +0000 (12:48 +0000)]
Make helper function static. NFC.
llvm-svn: 319022
Alexander Kornienko [Mon, 27 Nov 2017 12:42:04 +0000 (12:42 +0000)]
[clang-tidy] readability-non-const-parameter fixes should update all declarations
Fixes http://llvm.org/PR34410.
llvm-svn: 319021
Peter Smith [Mon, 27 Nov 2017 11:49:18 +0000 (11:49 +0000)]
[ELF][ARM] Refine check for when undefined weak needs a Thunk
When an undefined weak reference has a PLT entry we must generate a range
extension thunk for any B or BL that can't reach the PLT entry.
This change explicitly looks for whether a PLT entry exists rather than
assuming that weak references never need PLT entries unless Config->Shared
is in operation. This covers the case where we are linking an executable
with dynamic linking, hence a PLT entry will be needed for undefined weak
references. This case comes up in real programs over 32 Mb in size as there
is a B to a weak reference __gmon__start__ in the Arm crti.o for glibc.
Differential Revision: https://reviews.llvm.org/D40248
llvm-svn: 319020
John Brawn [Mon, 27 Nov 2017 11:29:15 +0000 (11:29 +0000)]
[CGP] Fix handling of null pointer values in optimizeMemoryInst
The current way that trivial addressing modes are detected incorrectly thinks
that null pointers are non-trivial, leading to an infinite loop where we keep
duplicating the same select. Fix this by aware of null when deciding if an
addressing mode is trivial.
Differential Revision: https://reviews.llvm.org/D40447
llvm-svn: 319019
Max Kazantsev [Mon, 27 Nov 2017 11:20:58 +0000 (11:20 +0000)]
[NFC] Add missing unit tests for EquivalenceClasses
llvm-svn: 319018
Vedran Miletic [Mon, 27 Nov 2017 11:14:06 +0000 (11:14 +0000)]
configure.py: Add gfx900 (Vega, Raven)
Sort amdgcn-- and amdgcn--amdhsa in a consistent way.
llvm-svn: 319017
Simon Pilgrim [Mon, 27 Nov 2017 10:41:32 +0000 (10:41 +0000)]
[X86][FMA] Tag all FMA/FMA4 instructions with WriteFMA schedule class
As mentioned on PR17367, many instructions are missing scheduling tags preventing us from setting 'CompleteModel = 1' for better instruction analysis. This patch deals with FMA/FMA4 which is one of the bigger offenders (along with AVX512 in general).
Annoyingly all scheduler models need to define WriteFMA (now that its actually used), even for older targets without FMA/FMA4 support, but that is an existing problem shared by other schedule classes.
Differential Revision: https://reviews.llvm.org/D40351
llvm-svn: 319016
Aleksei Sidorin [Mon, 27 Nov 2017 10:30:00 +0000 (10:30 +0000)]
[ASTImporter] Support importing CXXPseudoDestructorExpr
Patch by Peter Szecsi!
Differential Revision: https://reviews.llvm.org/D38843
llvm-svn: 319015
Momchil Velikov [Mon, 27 Nov 2017 10:13:14 +0000 (10:13 +0000)]
[ARM] Fix an off-by-one error when restoring LR for 16-bit Thumb
The commit https://reviews.llvm.org/rL318143 computes incorrectly to offset to
restore LR from.
The number of tPOP operands is 2 (condition) + 2 (implicit def and use of SP) +
count of the popped registers. We need to load LR from just past the last
register, hence the correct offset should be either getNumOperands() - 4 and
getNumExplicitOperands() - 2 (multiplied by 4).
Differential revision: https://reviews.llvm.org/D40305
llvm-svn: 319014
Andrew V. Tischenko [Mon, 27 Nov 2017 09:58:00 +0000 (09:58 +0000)]
Update BTVER2 sched numbers for SSE42 string instructions.
Differential Revision: https://reviews.llvm.org/D39846
llvm-svn: 319013
Ivan A. Kosarev [Mon, 27 Nov 2017 09:39:29 +0000 (09:39 +0000)]
[CodeGen] Collect information about sizes of accesses and access types for TBAA
The information about access and type sizes is necessary for
producing TBAA metadata in the new size-aware format. With this
patch, D39955 and D39956 in place we should be able to change
CodeGenTBAA::createScalarTypeNode() and
CodeGenTBAA::getBaseTypeInfo() to generate metadata in the new
format under the -new-struct-path-tbaa command-line option. For
now, this new information remains unused.
Differential Revision: https://reviews.llvm.org/D40176
llvm-svn: 319012
Alexey Sotkin [Mon, 27 Nov 2017 09:14:17 +0000 (09:14 +0000)]
[OpenCL] Add extensions cl_intel_subgroups and cl_intel_subgroups_short
Reviewers: yaxunl, Anastasia, bader
Reviewed By: Anastasia, bader
Subscribers: cfe-commits
Differential Revision: https://reviews.llvm.org/D39936
llvm-svn: 319011
Craig Topper [Mon, 27 Nov 2017 05:52:54 +0000 (05:52 +0000)]
[SelectionDAG] Teach SplitVecRes_SETCC to call GetSplitVector if the operands have already been split.
llvm-svn: 319010
Craig Topper [Mon, 27 Nov 2017 05:52:52 +0000 (05:52 +0000)]
[SelectionDAG] Fix function name in comment. NFC
llvm-svn: 319009
Igor Kudrin [Mon, 27 Nov 2017 05:51:10 +0000 (05:51 +0000)]
[ELF] Do not keep symbols if they referenced only from discarded sections.
This patch also ensures that in case of "--as-needed" is used,
DT_NEEDED entries are not created if they are required only by
these eliminated symbols.
Differential Revision: https://reviews.llvm.org/D38790
llvm-svn: 319008
Kamil Rytarowski [Sun, 26 Nov 2017 22:24:22 +0000 (22:24 +0000)]
Enable additonal features in NetBSD
Summary:
Enable for x86_64:
- ESan,
- KASan,
- MSan.
Enable for x86_64 and i386:
- Scudo.
These features are under active development and in various level of completeness.
Sponsored by <The NetBSD Foundation>
Reviewers: dvyukov, joerg, vitalybuka, eugenis
Reviewed By: eugenis
Subscribers: llvm-commits, #sanitizers
Tags: #sanitizers
Differential Revision: https://reviews.llvm.org/D40456
llvm-svn: 319007
Craig Topper [Sun, 26 Nov 2017 21:14:48 +0000 (21:14 +0000)]
[X86] Fix an assert that was incorrectly checking for BMI instead of AVX512VBMI.
The check is actually unnecessary since AVX512VBMI implies AVX512BW which is the other part of the assert.
llvm-svn: 319006
Simon Pilgrim [Sun, 26 Nov 2017 20:50:29 +0000 (20:50 +0000)]
[X86][3DNow] Add 3DNow! instruction itinerary and scheduling classes
llvm-svn: 319005
Kamil Rytarowski [Sun, 26 Nov 2017 20:20:42 +0000 (20:20 +0000)]
Prevent Thread Exited/Joined events race
Summary:
Add atomic verification to ensure that Thread is Joined after marking it
Finished.
It is required for NetBSD in order to prevent Thread Exited/Joined race,
that may occur when native system libpthread(3) cannot be reliably traced
in a way to guarantee that the mentioned events happen one after another.
This change fixes at least TSan and LSan on NetBSD.
Sponsored by <The NetBSD Foundation>
Reviewers: joerg, dvyukov, vitalybuka
Reviewed By: dvyukov
Subscribers: llvm-commits, kubamracek, #sanitizers
Tags: #sanitizers
Differential Revision: https://reviews.llvm.org/D40294
llvm-svn: 319004
Simon Pilgrim [Sun, 26 Nov 2017 20:03:53 +0000 (20:03 +0000)]
[X86][SSE] Add SSE42 tests to the clear upper tests
llvm-svn: 319003
Aaron Ballman [Sun, 26 Nov 2017 20:01:12 +0000 (20:01 +0000)]
Determine the attribute subject for diagnostics based on declarative information in DeclNodes.td. This greatly reduces the number of enumerated values used for more complex diagnostics; these are now only required when the "attribute only applies to" diagnostic needs to be generated manually as part of semantic processing.
This also clarifies some terminology used by the diagnostic (methods -> Objective-C methods, fields -> non-static data members, etc).
Many of the tests needed to be updated in multiple places for the diagnostic wording tweaks. The first instance of the diagnostic for that attribute is fully specified and subsequent instances cut off the complete list (to make it easier if additional subjects are added in the future for the attribute).
llvm-svn: 319002
Simon Dardis [Sun, 26 Nov 2017 19:22:44 +0000 (19:22 +0000)]
[utils][mips] Add support for mips for update_llc_checks.py
Add support for mips, particularly skipping the matching of .frame, .(f)mask
and LLVM's usage of the .set no(reorder|at|macro) directives.
Reviewers: spatel
Differential Revision: https://reviews.llvm.org/D40268
llvm-svn: 319001
Simon Pilgrim [Sun, 26 Nov 2017 19:22:37 +0000 (19:22 +0000)]
[X86][3DNow] Remove unused I3DNow_binop_rm/I3DNow_conv_rm templates. NFCI
llvm-svn: 319000
Simon Pilgrim [Sun, 26 Nov 2017 17:56:07 +0000 (17:56 +0000)]
[X86][MMX] Add IIC_MMX_MOVMSK instruction itinerary class
llvm-svn: 318999
Aleksei Sidorin [Sun, 26 Nov 2017 17:04:06 +0000 (17:04 +0000)]
[ASTImporter] Support TypeTraitExpr
Patch by Takafumi Kubota!
Differential Revision: https://reviews.llvm.org/D39722
llvm-svn: 318998
Jatin Bhateja [Sun, 26 Nov 2017 15:08:41 +0000 (15:08 +0000)]
[SCEV] Adding a check on outgoing branches of a terminator instr for SCEVBackedgeConditionFolder, NFC.
Summary:
For a given loop, getLoopLatch returns a non-null value
when a loop has only one latch block. In the modified
context adding an assertion to check that both the outgoing branches of
a terminator instruction (of latch) does not target same header.
+
few minor code reorganization.
Reviewers: jbhateja
Reviewed By: jbhateja
Subscribers: sanjoy
Differential Revision: https://reviews.llvm.org/D40460
llvm-svn: 318997
Oren Ben Simhon [Sun, 26 Nov 2017 13:02:45 +0000 (13:02 +0000)]
Control-Flow Enforcement Technology - Shadow Stack support (LLVM side)
Shadow stack solution introduces a new stack for return addresses only.
The HW has a Shadow Stack Pointer (SSP) that points to the next return address.
If we return to a different address, an exception is triggered.
The shadow stack is managed using a series of intrinsics that are introduced in this patch as well as the new register (SSP).
The intrinsics are mapped to new instruction set that implements CET mechanism.
The patch also includes initial infrastructure support for IBT.
For more information, please see the following:
https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf
Differential Revision: https://reviews.llvm.org/D40223
Change-Id: I4daa1f27e88176be79a4ac3b4cd26a459e88fed4
llvm-svn: 318996
Oren Ben Simhon [Sun, 26 Nov 2017 12:34:54 +0000 (12:34 +0000)]
Control-Flow Enforcement Technology - Shadow Stack and Indirect Branch Tracking support (Clang side)
Shadow stack solution introduces a new stack for return addresses only.
The stack has a Shadow Stack Pointer (SSP) that points to the last address to which we expect to return.
If we return to a different address an exception is triggered.
This patch includes shadow stack intrinsics as well as the corresponding CET header.
It includes CET clang flags for shadow stack and Indirect Branch Tracking.
For more information, please see the following:
https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf
Differential Revision: https://reviews.llvm.org/D40224
Change-Id: I79ad0925a028bbc94c8ecad75f6daa2f214171f1
llvm-svn: 318995
Kamil Rytarowski [Sun, 26 Nov 2017 09:42:01 +0000 (09:42 +0000)]
Detect thread termination in LSan/NetBSD
Summary:
Stop using the Linux solution with pthread_key_create(3).
This approach does not work on NetBSD, because calling
the thread destructor is not the latest operation on a POSIX
thread entity.
Detect _lwp_exit(2) call as it is really the latest operation
called from a detaching POSIX thread.
The pthread_key_create(3) solution also cannot be used
in early libc/libpthread initialization on NetBSD as the
system libraries are not bootstrapped enough.
Sponsored by <The NetBSD Foundation>
Reviewers: joerg, vitalybuka, kcc, dvyukov
Reviewed By: dvyukov
Subscribers: llvm-commits, #sanitizers
Tags: #sanitizers
Differential Revision: https://reviews.llvm.org/D40457
llvm-svn: 318994
Coby Tayree [Sun, 26 Nov 2017 09:36:41 +0000 (09:36 +0000)]
[x86][icelake]GFNI
galois field arithmetic (GF(2^8)) insns:
gf2p8affineinvqb
gf2p8affineqb
gf2p8mulb
Differential Revision: https://reviews.llvm.org/D40373
llvm-svn: 318993
Marshall Clow [Sun, 26 Nov 2017 02:55:38 +0000 (02:55 +0000)]
More of P0600; marking allocation routines as [[nodiscard]]
llvm-svn: 318992
Jatin Bhateja [Sun, 26 Nov 2017 02:01:01 +0000 (02:01 +0000)]
[SCEV] NFC : Removing unnecessary check on outgoing branches of a branch instr.
Summary:
For a given loop, getLoopLatch returns a non-null value
when a loop has only one latch block. In the modified
context a check on both the outgoing branches of a terminator instruction (of latch) to same header is redundant.
Reviewers: jbhateja
Reviewed By: jbhateja
Subscribers: sanjoy
Differential Revision: https://reviews.llvm.org/D40460
llvm-svn: 318991
Marshall Clow [Sun, 26 Nov 2017 00:39:59 +0000 (00:39 +0000)]
Fix copy/paste bug in test where we were putting a '3' into a vector<bool>. NFC.
llvm-svn: 318990
Eric Fiselier [Sat, 25 Nov 2017 23:39:17 +0000 (23:39 +0000)]
Fix installation of cxxabi.h through libc++.
Previously, the install command for the cxxabi headers specified
the wrong component, and therefore they were not being included
in the install-cxx command.
This patch corrects the component name.
llvm-svn: 318989
Davide Italiano [Sat, 25 Nov 2017 23:01:31 +0000 (23:01 +0000)]
[MaximalStaticExpansion] Simplify this code a bit. NFCI.
llvm-svn: 318988
David Blaikie [Sat, 25 Nov 2017 20:06:04 +0000 (20:06 +0000)]
Remove dead code
(this header is not fully implemented (the out of line function
writeTypeRecordKind is called in an inline function but never
implemented - this fails to link under modular code generation) and not
included anywhere)
llvm-svn: 318987
Craig Topper [Sat, 25 Nov 2017 20:00:37 +0000 (20:00 +0000)]
[X86] Remove GCCBuiltin from intrinsics that are no longer used by clang.
llvm-svn: 318986
Craig Topper [Sat, 25 Nov 2017 19:32:12 +0000 (19:32 +0000)]
[X86] Use separate builtins for fma4 scalar intrinsics. Use negations to remove some of the scalar fma3 builtins.
fma4 instructions zero the upper bits of the xmm register. fma3 instructions leave the bits unmodified. This requires separate builtins for the different semantics.
While we're cleaning up the scalar builtins this also removes the fma3 fmsub/fnmadd/fnmsub builtins by using negates in the header file.
llvm-svn: 318985
Craig Topper [Sat, 25 Nov 2017 18:32:43 +0000 (18:32 +0000)]
[X86] Add separate intrinsics for scalar FMA4 instructions.
Summary:
These instructions zero the non-scalar part of the lower 128-bits which makes them different than the FMA3 instructions which pass through the non-scalar part of the lower 128-bits.
I've only added fmadd because we should be able to derive all other variants using operand negation in the intrinsic header like we do for AVX512.
I think there are still some missed negate folding opportunities with the FMA4 instructions in light of this behavior difference that I hadn't noticed before.
I've split the tests so that we can use different intrinsics for scalar testing between the two. I just copied the tests split the RUN lines and changed out the scalar intrinsics.
fma4-fneg-combine.ll is a new test to make sure we negate the fma4 intrinsics correctly though there are a couple TODOs in it.
Reviewers: RKSimon, spatel
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D39851
llvm-svn: 318984
Craig Topper [Sat, 25 Nov 2017 18:09:37 +0000 (18:09 +0000)]
[X86] Don't report gather is legal on Skylake CPUs when AVX2/AVX512 is disabled. Allow gather on SKX/CNL/ICL when AVX512 is disabled by using AVX2 instructions.
Summary:
This adds a new fast gather feature bit to cover all CPUs that support fast gather that we can use independent of whether the AVX512 feature is enabled. I'm only using this new bit to qualify AVX2 codegen. AVX512 is still implicitly assuming fast gather to keep tests working and to match the scatter behavior.
Test command lines have been added for these two cases.
Reviewers: magabari, delena, RKSimon, zvi
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D40282
llvm-svn: 318983
Craig Topper [Sat, 25 Nov 2017 17:59:00 +0000 (17:59 +0000)]
[SelectionDAG] Remove some dead code from vector scalaring
Summary:
Currently ScalarizeVecRes_SETCC checks for the result type being a vector and jumps to ScalarizeVecRes_VSETCC. But if we're scalarizing a vector result, aren't we guaranteed to be looking at a vector type?
This patch deletes the current ScalarizeVecRes_SETCC and renames ScalarizeVecRes_VSETCC to ScalarizeVecRes_SETCC.
Reviewers: RKSimon, arsenm, eladcohen, zvi
Reviewed By: RKSimon
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D40452
llvm-svn: 318982
Jan Kratochvil [Sat, 25 Nov 2017 17:16:56 +0000 (17:16 +0000)]
Due to changes for DWZ I would need to update those such as renaming it to
SetFileOffset.
Differential revision: https://reviews.llvm.org/D40458
llvm-svn: 318981
Kamil Rytarowski [Sat, 25 Nov 2017 16:47:20 +0000 (16:47 +0000)]
Plug dlerror() leak for swift_demangle
Summary:
InitializeSwiftDemangler() attempts to resolve the
swift_demangle symbol. If this is not available, we
observe dlerror message leak.
Caught on NetBSD/amd64 in TSan.
Sponsored by <The NetBSD Foundation>
Reviewers: joerg, kubamracek, vitalybuka, dvyukov, eugenis
Reviewed By: dvyukov
Subscribers: llvm-commits, #sanitizers
Tags: #sanitizers
Differential Revision: https://reviews.llvm.org/D40382
llvm-svn: 318980
Devin Coughlin [Sat, 25 Nov 2017 14:57:42 +0000 (14:57 +0000)]
[analyzer] Teach RetainCountChecker about CoreMedia APIs
Teach the retain-count checker that CoreMedia reference types use
CoreFoundation-style reference counting. This enables the checker
to catch leaks and over releases of those types.
rdar://problem/
33599757
llvm-svn: 318979
Sylvestre Ledru [Sat, 25 Nov 2017 14:12:33 +0000 (14:12 +0000)]
doxygen: disable the html timestamp: this is breaking the reproducible build of openmp
llvm-svn: 318978
Andrew V. Tischenko [Sat, 25 Nov 2017 10:46:53 +0000 (10:46 +0000)]
Add BTVER2 sched support for SHLD/SHRD.
Differential Revision: https://reviews.llvm.org/D40124
llvm-svn: 318977
Martin Probst [Sat, 25 Nov 2017 09:35:33 +0000 (09:35 +0000)]
clang-format: [JS] do not collapse short classes.
Summary:
clang-format does not collapse short records, interfaces, unions, etc.,
but fails to do so if the record is preceded by certain modifiers
(export, default, abstract, declare). This change skips over all
modifiers, and thus handles all record definitions uniformly.
Before:
export class Foo { bar: string; }
class Baz {
bam: string;
}
After:
export class Foo {
bar: string;
}
class Baz {
bam: string;
}
Reviewers: djasper
Subscribers: klimek
Differential Revision: https://reviews.llvm.org/D40430
llvm-svn: 318976
Martin Probst [Sat, 25 Nov 2017 09:33:47 +0000 (09:33 +0000)]
clang-format: [JS] handle semis in generic types.
Summary:
TypeScript generic type arguments can contain object (literal) types,
which in turn can contain semicolons:
const x: Array<{a: number; b: string;} = [];
Previously, clang-format would incorrectly categorize the braced list as
a block and terminate the line at the openening `{`, and then format the
entire expression badly.
With this change, clang-format recognizes `<` preceding a `{` as
introducing a type expression. In JS, `<` comparison with an object
literal can never be true, so the chance of introducing false positives
here is very low.
Reviewers: djasper
Subscribers: klimek, cfe-commits
Differential Revision: https://reviews.llvm.org/D40424
llvm-svn: 318975
Martin Probst [Sat, 25 Nov 2017 09:24:33 +0000 (09:24 +0000)]
clang-format: [JS] handle `for` as object label.
Summary: Previously, clang-format would fail formatting `{for: 1}`.
Reviewers: djasper
Subscribers: klimek
Differential Revision: https://reviews.llvm.org/D40441
llvm-svn: 318974
Martin Probst [Sat, 25 Nov 2017 09:19:42 +0000 (09:19 +0000)]
clang-format: [JS] disable ASI on decorators.
Summary:
Automatic Semicolon Insertion in clang-format tries to guess if a line
wrap should insert an implicit semicolong. The previous heuristic would
not trigger ASI if a token was immediately preceded by an `@` sign:
function foo(@Bar // <-- does not trigger due to preceding @
baz) {}
However decorators can have arbitrary parameters:
function foo(@Bar(param, param, param) // <-- precending @ missed
baz) {}
While it would be possible to precisely find the matching `@`, just
conversatively disabling ASI for the entire line is simpler, while also
not regressing ASI substatially.
Reviewers: djasper
Subscribers: klimek, cfe-commits
Differential Revision: https://reviews.llvm.org/D40410
llvm-svn: 318973
Alexander Kornienko [Sat, 25 Nov 2017 08:52:42 +0000 (08:52 +0000)]
[clang-tidy] Fix link error (llvm.org/PR35417).
llvm-svn: 318972
Alexander Kornienko [Sat, 25 Nov 2017 08:49:04 +0000 (08:49 +0000)]
[clang-tidy] Actually fix header guard handling in scripts
llvm-svn: 318971
Craig Topper [Sat, 25 Nov 2017 07:20:24 +0000 (07:20 +0000)]
[X86] Simplify some code in combineSetCC. NFCI
Make the condition for doing a std::swap simpler so we don't have to repeat the full checks.
llvm-svn: 318970
Craig Topper [Sat, 25 Nov 2017 07:20:23 +0000 (07:20 +0000)]
[X86] Qualify some vector specific code with VT.isVector(). NFCI
Other checks inside require a build_vector, but we this lets us stop earlier and makes the code more clear.
llvm-svn: 318969
Craig Topper [Sat, 25 Nov 2017 07:20:22 +0000 (07:20 +0000)]
[X86] Support folding to andnps with SSE1 only.
With SSE1 only, we emit FAND and FXOR nodes for v4f32.
llvm-svn: 318968
Craig Topper [Sat, 25 Nov 2017 07:20:21 +0000 (07:20 +0000)]
[X86] Add some early DAG combines to turn v4i32 AND/OR/XOR into FAND/FOR/FXOR whe only SSE1 is available.
v4i32 isn't a legal type with sse1 only and would end up getting scalarized otherwise.
This isn't completely ideal as it doesn't handle cases like v8i32 that would get split to v4i32. But it at least helps with code written using the clang intrinsic header.
llvm-svn: 318967
Craig Topper [Fri, 24 Nov 2017 20:29:04 +0000 (20:29 +0000)]
Recommit r318963 "[APInt] Don't print debug messages from the APInt knuth division algorithm by default"
The previous commit had the condition in the do/while backwards.
Debug builds currently print out low level details of the Knuth division algorithm when -debug is used. This information isn't useful in most cases and just adds noise to the log.
This adds a new preprocessor flag to enable the prints in the knuth division code in APInt.
Differential Revision: https://reviews.llvm.org/D40404
llvm-svn: 318966
Craig Topper [Fri, 24 Nov 2017 19:57:48 +0000 (19:57 +0000)]
[X86] Prevent using X * rsqrt(X) to approximate sqrt when only sse1 is enabled.
This optimization can occur after type legalization and emit a vselect with v4i32 type. But that type is not legal with sse1. This ultimately gets scalarized by the second type legalization that runs after vector op legalization, but that's really intended to handle the scalar types that might be introduced by legalizing vector ops.
For now just stop this from happening by disabling the optimization with sse1.
llvm-svn: 318965
Craig Topper [Fri, 24 Nov 2017 19:32:34 +0000 (19:32 +0000)]
Revert 318963 "[APInt] Don't print debug messages from the APInt knuth division algorithm by default"
I seem to have botched the logic when switching to push_macro
llvm-svn: 318964
Craig Topper [Fri, 24 Nov 2017 19:13:24 +0000 (19:13 +0000)]
[APInt] Don't print debug messages from the APInt knuth division algorithm by default
Debug builds currently print out low level details of the Knuth division algorithm when -debug is used. This information isn't useful in most cases and just adds noise to the log.
This adds a new preprocessor flag to enable the prints in the knuth division code in APInt.
Differential Revision: https://reviews.llvm.org/D40404
llvm-svn: 318963
Rafael Espindola [Fri, 24 Nov 2017 19:06:14 +0000 (19:06 +0000)]
Delete dead code.
The parent constructor is already setting the binding.
llvm-svn: 318962