freedreno: Update RB_DBG_ECO_CNTL/RB_DBG_ECO_CNTL_blit.

On blob v512.490, using WRAP_GPU_ID to fake GPU versions, I see 0x41 used
everywhere, except for BLIT_OP_SCALE on a630.  Define the magic number in
dev info so it can be reused in the two places that set the
non-BLIT_OP_SCALE value.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19794>

r600/sfn: sort FS color outputs before all other outputs

The color outputs must be checked against the number of available
color buffers, therefore it is best to sort the color outputs to be
on the driver locations before the other FS outputs.

Fixes: 79ca456b4837b3bc21cf9ef3c03c505c4b4909f6
   r600/sfn: rewrite NIR backend

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7530

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19804>

r600: Print RAT instruction names in disassembly

Also print the swizzle of the address to indicate what
values may be used.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19804>

r600: Update scratch buffer late

For some reason the setup that comes after the scratch buffer
setup calls clobber the PS output configuration. Emitting the
scratch buffer setup as last action before the actual draw commands
seems to fix this.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19804>

freedreno/drm/virtio: Defer flush on BO free

Freeing BOs tends to be bursty (ie. when a submit is retired, or
expiring entries from BO cache).  Sending lots of small SET_IOVA
messages to the host can quickly eat up the available virtqueue
slots, resulting in (eventually) starving the guest waiting for
free virtqueue space.  By batching, we can avoid this and handle
things more efficiently on the host (ie. in a single wakeup rather
than many).

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19832>

freedreno/drm: Support for batched frees

Batch up handles before closing them to give the drm backend a chance to
batch up any extra handling needed (ie. virtio batching up messages to
host to release IOVA).

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19832>

freedreno/drm: Add optimized path for freeing many BOs

Submits tend to hold references to a lot of BOs, which get unref'd when
the submit is destroyed/retired.  For now, all this does is reduce lock
aquire/release, but the next commit will build on it.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19832>

asahi: Add batch tracking logic

We already have the notion of an agx_batch, which encapsulates a render
pass. Extend the logic to allow multiple in-flight batches per context, avoiding
a flush in set_framebuffer_state and improving performance for certain
applications designed for IMRs that ping-pong unnecessarily between FBOs. I
don't have such an application immediately in mind, but I wanted to get this
flag-day out of the way while the driver is still small and flexible.

The driver was written from day 1 with batch tracking in mind, so this is a
relatively small change to actually wire it up, but there are lots of little
details to get right.

The code itself is mostly a copy/paste of panfrost, which in turn draws
inspiration from freedreno and v3d.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19865>

asahi: Use the batch for submission

So we can submit background batches.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19865>

asahi: Use batch_reads for sysvals

Required for proper resource tracking.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19865>

asahi: Use a pipe_framebuffer_state batch key

More convenient for batch tracking.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19865>

asahi: Use batch instead of ctx for pipelines

So we can support multiple batches later.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19865>

asahi: Hide ctx->batch

This will make it easier to support multiple batches.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19865>

asahi: Factor out prepare_for_map

This will be expanded, let's expand in the direction of less spaghetti.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19865>

intel/fs: put scratch surface in the surface state heap

In 4ceaed7839af we made scratch surface state allocations part of the
internal heap (mapped to STATE_BASE_ADDRESS::SurfaceStateBaseAddress)
so that it doesn't uses slots in the application's expected 1M
descriptors (especially with vkd3d-proton).

But all our compiler code relies on BSS
(STATE_BASE_ADDRESS::BindlessSurfaceStateBaseAddress).

The additional issue is that there is only 26bits of surface offset
available in CS instruction (CFE_STATE, 3DSTATE_VS, etc...) for
scratch surfaces. So we need the drivers to put the scratch surfaces
in the first chunk of STATE_BASE_ADDRESS::SurfaceStateBaseAddress
(hence all the driver changes).

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 4ceaed7839af ("anv: split internal surface states from descriptors")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7687
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19727>

iris: move bindless surface state heap inside the surface state heap

We're about to make scratch surface states part of the surface state
heap. Because those are required to be in the low 26bits parts surface
state heap (we're limited in bits handed in the CFE_STATE, 3DSTATE_VS,
etc... instructions), this change splits the 32bit surface state heap
as follow:

   - 8Mb of surface states for scratch
   - 1Gb - 8Mb of binding tables
   - 3Gb of surface states

That way all of the surfaces are located within a 4Gb region visible
from STATE_BASE_ADDRESS::SurfaceStateBaseAddress

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19727>

iris: prevent crash in decoder

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19727>

radv: Convert instance bvh address to node in bvh build.

So we don't have to do it in the traversal loop. Should 2 and
instructions and a 64-bit shift, so 4/8 cycles per instance node
visit.

Totals from 7 (0.01% of 134913) affected shaders:

CodeSize: 208460 -> 208292 (-0.08%)
Instrs: 38276 -> 38248 (-0.07%)
Latency: 803181 -> 803142 (-0.00%)
InvThroughput: 165384 -> 165376 (-0.00%)
Copies: 4912 -> 4905 (-0.14%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19706>

radv: Fiddle with opaque flag positions to reduce instructions.

Totals from 7 (0.01% of 134913) affected shaders:

CodeSize: 209076 -> 208460 (-0.29%)
Instrs: 38374 -> 38276 (-0.26%)
Latency: 803899 -> 803181 (-0.09%)
InvThroughput: 165530 -> 165384 (-0.09%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19706>

radv: Skip and for node_to_addr with bvh_base.

Cause the bvh base is always 64 byte aligned.

Totals from 7 (0.01% of 134913) affected shaders:

CodeSize: 209216 -> 209076 (-0.07%)
Instrs: 38402 -> 38374 (-0.07%)
Latency: 804537 -> 803899 (-0.08%)
InvThroughput: 165663 -> 165530 (-0.08%)
Copies: 4919 -> 4912 (-0.14%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19706>

radv: Move ray flag compares out of the loop.

To save on and+cmp combos with VALU instructions.

Totals from 7 (0.01% of 134913) affected shaders:

CodeSize: 208476 -> 209216 (+0.35%)
Instrs: 38384 -> 38402 (+0.05%)
Latency: 805725 -> 804537 (-0.15%)
InvThroughput: 165906 -> 165663 (-0.15%)
Copies: 4936 -> 4919 (-0.34%)
PreSGPRs: 393 -> 430 (+9.41%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19706>

Revert "nir/lower_shader_calls: put inserted instructions into a dummy block"

This reverts commit 35d82ecf1ee117bef575731100fa6ae532f225fc.

Cc: mesa-stable
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19820>

nir/lower_shader_calls: wrap only jumps rather than entire code blocks

Moving entire chunks of code into a dummy if block is causing issues
in some situations. To work around the issue that we tried to fix in
35d82ecf1e ("nir/lower_shader_calls: put inserted instructions into a
dummy block") which is that we cannot cut and past a block of
instruction that ends with a jump if there are more instruction behind
where we're going to past. We can instead just wraps the jumps into
dummy if blocks.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19820>

nir/lower_shader_calls: update metadata before validation

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19820>

radv/bvh: Adjust sah cost based on depth

Adds a cost field to radv_ir_node and uses it to model the cost of tree
depth. This improves framerates by 2% if my benchmarking is correct.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19756>

nir/range_analysis: Set higher default maximum for max_workgroup_count

Fixes: c2a81ebe19f ("nir: Add default unsigned upper bound configuration.")
Closes: #7676
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19835>

iris: Pass devinfo directly in iris_setup_uniforms

Instead of reaching through brw_compiler.  This will make easy
future changes on brw_compiler side.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19836>

intel/compiler: Require C++17

Fixes: 6c194ddd18f ("intel/compiler: Prepare SIMD selection helpers to handle different prog_datas")

Signed-off-by: Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19833>

asahi: Don't support 16-bit vertex attributes

Currently broken, let vbuf deal with it. "Fixes" sysprof.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>

asahi: Fix logic ops

Need to set colour mask correctly. Fixes spec@!opengl 1.0@gl-1.0-logicop@GL_AND,
at least the non-MSAA portion.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>

asahi: Restrict rendering to what we support

Noticed with Kodi that tries to use rgb10a2.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>

asahi: Don't validate WSI (twiddled) strides

These are made up and won't necessarily be aligned.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>

asahi: Split out agx_usc.h into a common file

So the tilebuffer helpers can build the "shared" USC word. Also because Ella
will probably want to use these O:)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>

asahi: Note some magic bits used with memoryless RTs

Obviously there can't *actually* be memoryless render targets, because
how would partial renders work? The control stream with memoryless looks
like everything would if it went to memory (e.g. full 2D MSAA
attachments for the partial loads/stores even if only a resolved
2D image for the final store). Except the memoryless attachments all
load from the same address 0xeeee0000. Clearly that's not actually what
happens, so what gives? Unclear... but I see the magic bits mentioned
here set, and I assume there are some firmware (or kernel) shenanigans
used to JIT allocate the backing storage for partial renders.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>

asahi: Identify "Sample mask after depth/stencil" bit

Corresponds to Metal [[sample_mask,post_depth_coverage]].

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>

asahi: Identify the pass type enum

Via PowerVR.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>

asahi: Identify PBE sample count

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>

asahi: Identify Dimension for Render Target

Metal uses when rendering to multisampled 2D.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>

asahi: Fix agx_set_framebuffer_state for MRT

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>

asahi: Set data_valid for the correct level

By inspection.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>

asahi: Implement stencil texturing

Stencil texturing is easy: S8_UINT is textured like R8_UINT (with a
little swizzle fixup), and stencil is always S8_UINT thanks to
u_transfer_helper. So we just need to do some fixups to make
u_transfer_helper's seperate_stencil work and everything will work out.

Passes dEQP-GLES31.functional.stencil_texturing.*

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>

asahi: Add internal formats for RGB10A2

We need to use I16 as the interchange format here. Fixes:

   dEQP-GLES3.functional.fragment_out.basic.uint.rgb10_a2ui*

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>

asahi: Implement perf_debug

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>

asahi: Free the scanout resource

Fixes memory leaks with renderonly.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>

agx: Handle collects in backwards isel

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>

agx: Assert more invariants in RA

Was helpful for debugging.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>

agx: Validate part of SSA form

To debug backend pass problems.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>

agx: Split off NIR preprocessing from compiling

So we can specialize after lowering I/O.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>

agx: Handle scalar texture destinations

Fixes dEQP-GLES3.functional.shaders.texture_functions.texturelod.sampler2dshadow_fragment.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>

agx: Don't depend on GenXML

Separation of concerns, unused #include.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>

agx: Lower packs/unpacks and bitfields

Needed for GLES3. These could be optimized.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>

util: Move src/gallium/include/pipe/p_format.h to src/util/format/u_formats.h

Because p_format.h shared between vulkan drivers and opengl drivers

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19629>

ci/freedreno: disable flaking Civilization V

See: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7491

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19862>

util: Rename PIPE_ALIGN_STACK to UTIL_ALIGN_STACK and moved into util/compiler.h

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19676>

llvmpipe: fixes error: ‘enum pipe_blendfactor’ declared  in lp_test_blend.c

error  message:
In file included from ../../src/gallium/drivers/llvmpipe/lp_test_blend.c:44:
../../src/gallium/drivers/llvmpipe/lp_bld_blend.h:47:21: error: ‘enum pipe_blendfactor’ declared inside parameter list will not be visible outside of this definition or declaration [-Werror]
   47 |                enum pipe_blendfactor factor_src,

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19676>

util: convert usage of uint to unsigned in u_format.h

Because uint comes from pipe/p_compiler.h, and that depends will be removed in future

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19676>

util: use void * instead of byte * for util_copy_rect in u_format.h

As ubyte comes from p_compiler.h,  so do not use it,
and the code calles util_copy_rect may use args with type uint8_t*, ubyte* or unsigned char*,
so use the type void* that consistence with memcpy

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19676>

tgsi: fixes error: ‘enum pipe_shader_type’ declared  in tgsi_info.h

error message:
../../src/gallium/auxiliary/tgsi/tgsi_info.h:92:30: error: ‘enum pipe_shader_type’ declared inside parameter list will not be visible outside of this definition or declaration [-Werror]
   92 | tgsi_get_processor_name(enum pipe_shader_type processor);

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19676>

aco: fixes error: 'uint' was not declared in aco_instruction_selection.cpp

uint is from pipe/p_compiler.h

error message:
../../src/amd/compiler/aco_instruction_selection.cpp:11061:4: error: 'uint' was not declared in this scope; did you mean 'rint'?
11061 |    uint en_mask = 1;

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19676>

util: Remove the usage of enum pipe_error in u_hash_table.*

Use 0 instead of PIPE_OK in u_hash_table.c

Because pipe_error and PIPE_OK is comes from pipe/p_defines.h that doesn't belong
to src/util/

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19676>

util: Remove redundant #include "util/u_inlines.h" in u_trace.c

util/u_inlines.h is comes from src/gallium/auxiliary/util/u_inlines.h,
so when possible, do not use it under src/util folder

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19676>

intel/compiler: Remove redundant argument from brw_nir_create_passthrough_tcs

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19831>

intel/perf: fix printf formatting of size_t for 32bit builds

Fixes: bdacd6df5adc ("intel/perf: add a non installable tool to print metrics")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7736
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19856>

ci/dzn: add flake

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19858>

docs: update Python requirement to 3.7

Reported in https://gitlab.freedesktop.org/mesa/mesa/-/issues/7716

Reviewed-by: Eric Engestrom <eric@igalia.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19791>

include: Update the OpenCL headers

This syncs all our headers with their canonical versions from Khronos.
Of particular note, CL headers repo does not have cl.hpp and cl2.hpp has
been depricated all in favor of opencl.hpp which is the new canonical
header.  Fortunately, nothing in Mesa uses any of the C++ headers so
this shouldn't break anything.

Acked-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19816>

clover: Use braces arround a union initializer

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19816>

scripts: Fix khronos-update.py to use main for OpenCL headers

Also, cl.hpp no longer exists in OpenCL-Headers to fix it at the last
commit where it did exist.

Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19816>

Update 00-mesa-defaults.conf

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19619>

nir/lower_explicit_io: fix metadata preserve

This pass can insert if blocks, therefore no dominance/block_index for
you.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19818>

nir/lower_bit_size: lower uadd_sat/iadd_sat/isub_sat to unsaturated alu

The unsaturated arithmetic won't overflow/borrow, and may be faster.

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19473>

nir/lower_bit_size: optimize usub_sat lowering

The result should never be larger than uint_max. This doesn't need a
special path.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19473>

nir/algebraic: optimize open-coded uadd_sat/usub_sat

fossil-db (navi21):
Totals from 19 (0.01% of 135636) affected shaders:
Instrs: 40730 -> 40688 (-0.10%)
CodeSize: 217708 -> 217568 (-0.06%)
Latency: 261466 -> 261373 (-0.04%)
InvThroughput: 74944 -> 74896 (-0.06%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19473>

radv: lower 8/16-bit uadd_carry/usub_borrow

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7615
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19473>

nir/lower_bit_size: lower uadd_carry

8/16-bit uadd_carry can exist in SPIR-V.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7615
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19473>

crocus: Pass devinfo directly in crocus_setup_uniforms

Instead of reaching through brw_compiler.  This will make easy
future changes on brw_compiler side.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19834>

radv: advertise extendedDynamicState3ColorBlendEnable

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19579>

radv: add support for dynamic color blend enable

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19579>

ci/freedreno: temporarily disable godot-trive

Test if this trace impact surrounding traces causing rendering changes.

Ref: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7732

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19838>

ci/panfrost: drop glmark2 traces, useless

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19838>

ci/iris: drop glmark2 traces, useless

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19838>

ci/llvmpipe: drop glmark2 traces, useless

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19838>

ci/virgl: drop glmark2 traces, useless

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19838>

ci/broadcom: drop glmark2 traces, useless

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19838>

ci/freedreno: drop glmark2 traces, useless

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19838>

ci/amd: drop glmark2 traces, useless

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19838>

nir/lower_shader_calls: Get rid of any brw occurences

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19749>

tu: Rewrite inline uniform implementation

Now we always push the inline uniforms, using an indirect CP_LOAD_STATE.
There is just enough space to be able to always push them if we expose
the minimum possible per-stage limits. This aligns us with Qualcomm and
removes the need to setup a uniform descriptor which will be
problematic.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18703>

nir: Fix nir_chase_binding() vecN handling

In the comments we claimed to handle vecN instructions, for the case
where an offset is trimmed from the descriptor, but we didn't ignore the
offset itself and in effect only handled identity vecN's (which copy
propagation would normally remove already!), so the handling of vecN was
useless and this relied on copy propagation cleaning things up. Fix it
to ignore everything except the components in the original source.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18703>

pvr: Minor cleanup around pvr_emit_vdm_index_list()

Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19802>

vulkan/wsi/wayland: Set num_modifier_lists = 0 if num_drm_modifiers == 0

This case was missed in
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18826 ,
resulting in native Wayland apps failing with

 ../src/vulkan/wsi/wsi_common_drm.c:452: wsi_configure_native_image: Assertion `!"Failed to find a supported modifier!  This should never " "happen because LINEAR should always be available"' failed.

if the Wayland compositor advertises only the INVALID modifier.

Fixes: c315e20d6198 ("vulkan/wsi/wayland: Configure images via params passed to wsi_swapchain_init()")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19795>

pvr: Support clear colours with more than 32 bits

The support for this seems to already exist, but was blocked by a
conditional. Replace with an assert to ensure the format can be packed
into 4x32 bit words (true for all currently supported formats).

Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19799>

pvr: Fix clang-format error.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19798>

virgl/video: Check driver supported profiles and entrypoints

Since the support of video by the device and the driver may be
different, it is necessary to check on the driver side as well.

Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18831>

virgl/video: Add support for H.265 encoding

Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Signed-off-by: Weishi Li <liweishi@kylinos.cn>
Signed-off-by: Liming Sun <sunliming@kylinos.cn>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18831>

virgl/video: Add support for H.264 encoding

Implement encoding framework and support H.264 encoding.

Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Signed-off-by: Ming Xie <xieming@kylinos.cn>
Signed-off-by: Liming Sun <sunliming@kylinos.cn>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18831>

virgl/video: Pass "max_references" to backend when creating a video codec

The "max_references" is an important value in sequence parameters,
which will be used when encoding SPS headers.

Signed-off-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18831>

frontends/va/enc: save intra_idr_period in the context

The va frontend loses some information when processing parameter
buffers, but the virgl video encoding driver needs it to work.

Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18831>

virgl/video: Move hardware-related definitions from virgl_video.h to virgl_video_hw.h

Considering the increasing number of hardware-related definitions,
it is better to put them in a separate file.

Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18831>

iris: Increase the maximum grid size

I had simply copied these values from another driver when adding initial
compute support to iris.  The actual hardware limit is UINT32_MAX (see
the GPGPU_WALKER/COMPUTE_WALKER ThreadGroupID{X,Y,Z}Dimension fields).

Thanks to Karol Herbst for noticing the unnecessarily low limit.

References: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7676
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19826>