Andre Vieira [Thu, 16 May 2019 11:05:34 +0000 (12:05 +0100)]
[PATCH 31/57][Arm][GAS] Add support for MVE instructions: vshrn[tb], vrshrn[tb], vqshrn[tb], vqshrun[tb], vqrshrn[tb] and vqrshrun[tb]
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (M_MNEM_vshrnt, M_MNEM_vshrnb, M_MNEM_vrshrnt,
M_MNEM_vqshrnt, M_MNEM_vqshrnb, M_MNEM_vqshrunt, M_MNEM_vqshrunb,
M_MNEM_vrshrnb, M_MNEM_vqrshrnt, M_MNEM_vqrshrnb, M_MNEM_vqrshrunt,
M_MNEM_vqrshrunb): New instruction encodings.
(do_mve_vshrn): New encoding function.
(insns): Add entries for MVE mnemonics.
* testsuite/gas/arm/mve-vqrshrn-bad.d: New test.
* testsuite/gas/arm/mve-vqrshrn-bad.l: New test.
* testsuite/gas/arm/mve-vqrshrn-bad.s: New test.
* testsuite/gas/arm/mve-vshrn-bad.d: New test.
* testsuite/gas/arm/mve-vshrn-bad.l: New test.
* testsuite/gas/arm/mve-vshrn-bad.s: New test.
Andre Vieira [Thu, 16 May 2019 11:04:35 +0000 (12:04 +0100)]
[PATCH 30/57][Arm][GAS] Add support for MVE instructions: vqmovnt, vqmovnb, vqmovunt, vqmovunb, vqrshl and vrshl
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (M_MNEM_vqmovnt, M_MNEM_vqmovnb,
M_MNEM_vqmovunt, M_MNEM_vqmovunb): New instruction encodings.
(do_mve_vqmovn): New encoding function.
(do_neon_rshl): Change to accepte MVE variants.
(insns): Change entries and add new for MVE mnemonics.
* testsuite/gas/arm/mve-vqmovn-bad.d: New test.
* testsuite/gas/arm/mve-vqmovn-bad.l: New test.
* testsuite/gas/arm/mve-vqmovn-bad.s: New test.
* testsuite/gas/arm/mve-vqrshl-bad.d: New test.
* testsuite/gas/arm/mve-vqrshl-bad.l: New test.
* testsuite/gas/arm/mve-vqrshl-bad.s: New test.
* testsuite/gas/arm/mve-vrshl-bad.d: New test.
* testsuite/gas/arm/mve-vrshl-bad.l: New test.
* testsuite/gas/arm/mve-vrshl-bad.s: New test.
Andre Vieira [Thu, 16 May 2019 11:03:30 +0000 (12:03 +0100)]
[PATCH 29/57][Arm][GAS] Add support for MVE instructions: vqdmullt and vqdmullb
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (enum operand_parse_code): Add new operand.
(parse_operands): Handle new operand.
(do_mve_vqdmull): New encoding function.
(insns): Add entry for MVE mnemonics.
* testsuite/gas/arm/mve-vqdmull-bad.d: New test.
* testsuite/gas/arm/mve-vqdmull-bad.l: New test.
* testsuite/gas/arm/mve-vqdmull-bad.s: New test.
Andre Vieira [Thu, 16 May 2019 11:00:54 +0000 (12:00 +0100)]
[PATCH 28/57][Arm][GAS] Add support for MVE instructions: vqdmlah, vqrdmlah, vqdmlash, vqrdmlash, vqdmulh and vqrdmulh
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (enum operand_parse_code): Add new operand.
(parse_operands): Handle new operand.
(mve_encode_qqr): Handle new instructions.
(do_neon_qdmulh): Add support for MVE variants.
(do_neon_qrdmlah): Likewise.
(do_mve_vqdmlah): New encoding function.
(insns): Change entries and add new entries for MVE mnemonics.
* testsuite/gas/arm/mve-vqdmulh-bad.d: New test.
* testsuite/gas/arm/mve-vqdmulh-bad.l: New test.
* testsuite/gas/arm/mve-vqdmulh-bad.s: New test.
Andre Vieira [Thu, 16 May 2019 10:59:36 +0000 (11:59 +0100)]
[PATCH 27/57][Arm][GAS] Add support for MVE instructions: vqdmladh, vqrdmladh, vqdmlsdh and vqrdmlsdh
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_mve_vqdmladh): New encoding function.
(insns): Add entries for MVE mnemonics.
* testsuite/gas/arm/mve-vqdmladh-bad.d: New test.
* testsuite/gas/arm/mve-vqdmladh-bad.l: New test.
* testsuite/gas/arm/mve-vqdmladh-bad.s: New test.
* testsuite/gas/arm/mve-vqdmlsdh-bad.d: New test.
* testsuite/gas/arm/mve-vqdmlsdh-bad.l: New test.
* testsuite/gas/arm/mve-vqdmlsdh-bad.s: New test.
Andre Vieira [Thu, 16 May 2019 10:57:44 +0000 (11:57 +0100)]
[PATCH 26/57][Arm][GAS] Add support for MVE instructions: vpnot and vpsel
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_mve_vpsel): New encoding function.
(do_mve_vpnot): Likewise.
(insns): Add entries for MVE mnemonics.
* testsuite/gas/arm/mve-vpnot-bad.d: New test.
* testsuite/gas/arm/mve-vpnot-bad.l: New test.
* testsuite/gas/arm/mve-vpnot-bad.s: New test.
* testsuite/gas/arm/mve-vpsel-bad.d: New test.
* testsuite/gas/arm/mve-vpsel-bad.l: New test.
* testsuite/gas/arm/mve-vpsel-bad.s: New test.
Andre Vieira [Thu, 16 May 2019 10:52:29 +0000 (11:52 +0100)]
[PATCH 25/57][Arm][GAS] Add support for MVE instruction: vmvn, vqabs and vqneg
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_neon_mvn): Change to accept MVE variants.
(do_neon_sat_abs_neg): Likewise.
(insns): Likewise.
* testsuite/gas/arm/mve-vmvn-bad.d: New test.
* testsuite/gas/arm/mve-vmvn-bad.l: New test.
* testsuite/gas/arm/mve-vmvn-bad.s: New test.
* testsuite/gas/arm/mve-vqabsneg-bad.d: New test.
* testsuite/gas/arm/mve-vqabsneg-bad.l: New test.
* testsuite/gas/arm/mve-vqabsneg-bad.s: New test.
Andre Vieira [Thu, 16 May 2019 10:49:02 +0000 (11:49 +0100)]
[PATCH 24/57][Arm][GAS] Add support for MVE instructions: vmlas, vmulh and vrmulh
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_mve_vmlas): New encoding function.
(do_mve_vmulh): Likewise.
(insns): Add entries for MVE mnemonics.
* testsuite/gas/arm/mve-vmlas-bad.d: New test.
* testsuite/gas/arm/mve-vmlas-bad.l: New test.
* testsuite/gas/arm/mve-vmlas-bad.s: New test.
* testsuite/gas/arm/mve-vmulh-bad.d: New test.
* testsuite/gas/arm/mve-vmulh-bad.l: New test.
* testsuite/gas/arm/mve-vmulh-bad.s: New test.
Andre Vieira [Thu, 16 May 2019 10:46:48 +0000 (11:46 +0100)]
[PATCH 23/57][Arm][GAS] Add support for MVE instructions: vmla, vmul, vqadd and vqsub
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (enum operand_parse_code): New operand.
(parse_operands): Handle new operand.
(mve_encode_qqr): Handle new instructions.
(do_neon_dyadic_i64_su): Accept MVE variants.
(neon_dyadic_misc): Likewise.
(do_neon_mac_maybe_scalar): Likewise.
(do_neon_mul): Likewise.
(insns): Change to accept MVE variants.
* testsuite/gas/arm/mve-vmla-bad.d: New test.
* testsuite/gas/arm/mve-vmla-bad.l: New test.
* testsuite/gas/arm/mve-vmla-bad.s: New test.
* testsuite/gas/arm/mve-vmul-bad-1.d: New test.
* testsuite/gas/arm/mve-vmul-bad-1.l: New test.
* testsuite/gas/arm/mve-vmul-bad-1.s: New test.
* testsuite/gas/arm/mve-vmul-bad-2.d: New test.
* testsuite/gas/arm/mve-vmul-bad-2.l: New test.
* testsuite/gas/arm/mve-vmul-bad-2.s: New test.
* testsuite/gas/arm/mve-vqaddsub-bad.d: New test.
* testsuite/gas/arm/mve-vqaddsub-bad.l: New test.
* testsuite/gas/arm/mve-vqaddsub-bad.s: New test.
Andre Vieira [Thu, 16 May 2019 10:45:46 +0000 (11:45 +0100)]
[PATCH 22/57][Arm][GAS] Add support for MVE instructions: vmlaldav, vmlalv, vmlsldav, vrmlaldavh, vrmlalvh and vrmlsldavh
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (M_MNEM_vmlaldav, M_MNEM_vmlaldava,
M_MNEM_vmlaldavx, M_MNEM_vmlaldavax, M_MNEM_vmlsldav,
M_MNEM_vmlsldava, M_MNEM_vmlsldavx, M_MNEM_vmlsldavax,
M_MNEM_vrmlaldavhx, M_MNEM_vrmlaldavhax, M_MNEM_vrmlsldavh,
M_MNEM_vrmlsldavha, M_MNEM_vrmlsldavhx, M_MNEM_vrmlsldavhax): New
instruction encodings.
(NEON_SHAPE_DEF): New shape
(mve_encode_rrqq): New encoding helper function.
(do_mve_vmlaldav): New encoding function.
(do_mve_vrmlaldavh): New encoding function.
(insns): Add entries for MVE mnemonics.
* testsuite/gas/arm/mve-vmlaldav-bad.d: New test.
* testsuite/gas/arm/mve-vmlaldav-bad.l: New test.
* testsuite/gas/arm/mve-vmlaldav-bad.s: New test.
* testsuite/gas/arm/mve-vmlalv-bad.d: New test.
* testsuite/gas/arm/mve-vmlalv-bad.l: New test.
* testsuite/gas/arm/mve-vmlalv-bad.s: New test.
* testsuite/gas/arm/mve-vmlsldav-bad.d: New test.
* testsuite/gas/arm/mve-vmlsldav-bad.l: New test.
* testsuite/gas/arm/mve-vmlsldav-bad.s: New test.
* testsuite/gas/arm/mve-vrmlaldavh-bad.d: New test.
* testsuite/gas/arm/mve-vrmlaldavh-bad.l: New test.
* testsuite/gas/arm/mve-vrmlaldavh-bad.s: New test.
Andre Vieira [Thu, 16 May 2019 10:44:19 +0000 (11:44 +0100)]
[PATCH 21/57][Arm][GAS] Add support for MVE instructions: vmaxv, vmaxav, vminv and vminav
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (M_MNEM_vmaxv, M_MNEM_vmaxav, M_MNEM_vminv,
M_MNEM_vminav): New instruction encodings.
(do_mve_vmaxv): New encoding function.
(insns): Add entries for new MVE mnemonics.
* testsuite/gas/arm/mve-vmaxv-vminv-bad.d: New test.
* testsuite/gas/arm/mve-vmaxv-vminv-bad.l: New test.
* testsuite/gas/arm/mve-vmaxv-vminv-bad.s: New test.
Andre Vieira [Thu, 16 May 2019 10:42:52 +0000 (11:42 +0100)]
[PATCH 20/57][Arm][GAS] Add support for MVE instructions: vmaxnmv, vmaxnmav, vminnmv and vminnmav
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_mve_vmaxnmv): New encoding function.
(insns): Add entries for new mnemonics.
* testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.d: New test.
* testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.l: New test.
* testsuite/gas/arm/mve-vmaxnmv-vminnmv-bad.s: New test.
Andre Vieira [Thu, 16 May 2019 10:41:52 +0000 (11:41 +0100)]
[PATCH 19/57][Arm][GAS] Add support for MVE instructions: vmax[nm][a] and vmin[nm][a]
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_mve_vmaxa_vmina): New encoding function.
(do_mve_vmaxnma_vminnma): Likewise.
(do_neon_dyadic_if_su): Change to support MVE variants.
(do_vmaxnm): Likewise.
(insns): Change to accept MVE variants and add new.
* testsuite/gas/arm/mve-vmax-vmin-bad.d: New test.
* testsuite/gas/arm/mve-vmax-vmin-bad.l: New test.
* testsuite/gas/arm/mve-vmax-vmin-bad.s: New test.
* testsuite/gas/arm/mve-vmaxa-vmina-bad.d: New test.
* testsuite/gas/arm/mve-vmaxa-vmina-bad.l: New test.
* testsuite/gas/arm/mve-vmaxa-vmina-bad.s: New test.
* testsuite/gas/arm/mve-vmaxnm-vminnm-bad.d: New test.
* testsuite/gas/arm/mve-vmaxnm-vminnm-bad.l: New test.
* testsuite/gas/arm/mve-vmaxnm-vminnm-bad.s: New test.
* testsuite/gas/arm/mve-vmaxnma-vminnma-bad.d: New test.
* testsuite/gas/arm/mve-vmaxnma-vminnma-bad.l: New test.
* testsuite/gas/arm/mve-vmaxnma-vminnma-bad.s: New test.
Andre Vieira [Thu, 16 May 2019 10:40:26 +0000 (11:40 +0100)]
[PATCH 18/57][Arm][GAS] Add support for MVE instructions: vhcadd, vhadd, vhsub and vrhadd
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (enum operand_parse_code): New operand.
(parse_operands): Handle new operand.
(mve_encode_qqr): Change to support new instructions.
(enum vfp_or_neon_is_neon_bits): Moved.
(vfp_or_neon_is_neon): Moved.
(check_simd_pred_availability): Moved.
(do_neon_dyadic_i_su): Changed to support MVE variants.
(neon_dyadic_misc): Changed mve_encode_qqr call.
(do_mve_vbrsr): Likewise.
(do_mve_vhcadd): New encoding function.
(insns): Change existing to accept MVE variants and add new.
* testsuite/gas/arm/mve-vhadd-vhsub-vrhadd-bad.d: New test.
* testsuite/gas/arm/mve-vhadd-vhsub-vrhadd-bad.l: New test.
* testsuite/gas/arm/mve-vhadd-vhsub-vrhadd-bad.s: New test.
* testsuite/gas/arm/mve-vhcadd-bad.d: New test.
* testsuite/gas/arm/mve-vhcadd-bad.l: New test.
* testsuite/gas/arm/mve-vhcadd-bad.s: New test.
Andre Vieira [Thu, 16 May 2019 10:39:24 +0000 (11:39 +0100)]
[PATCH 17/57][Arm][GAS] Add support for MVE instructions: vfma and vfms
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_neon_fmac): Change to support MVE variants.
(insns): Change to accept MVE variants.
* testsuite/gas/arm/mve-vfma-vfms-bad.d: New test.
* testsuite/gas/arm/mve-vfma-vfms-bad.l: New test.
* testsuite/gas/arm/mve-vfma-vfms-bad.s: New test.
Andre Vieira [Wed, 15 May 2019 17:36:48 +0000 (18:36 +0100)]
[PATCH 16/57][Arm][GAS] Add support for MVE instructions: vdup, vddup, vdwdup, vidup and viwdup
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (M_MNEM_vddup, M_MNEM_vdwdup, M_MNEM_vidup,
M_MNEM_viwdup): New instruction encodings.
(NEON_SHAPE_DEF): New shapes.
(do_mve_viddup): New encoding function.
(do_neon_dup): Change to support new MVE variants.
(insns): Change existing to accept MVE variants and add new.
* testsuite/gas/arm/mve-vddup-bad.d: New test.
* testsuite/gas/arm/mve-vddup-bad.l: New test.
* testsuite/gas/arm/mve-vddup-bad.s: New test.
* testsuite/gas/arm/mve-vdup-bad.d: New test.
* testsuite/gas/arm/mve-vdup-bad.l: New test.
* testsuite/gas/arm/mve-vdup-bad.s: New test.
* testsuite/gas/arm/mve-vidup-bad.d: New test.
* testsuite/gas/arm/mve-vidup-bad.l: New test.
* testsuite/gas/arm/mve-vidup-bad.s: New test.
Andre Vieira [Wed, 15 May 2019 17:31:38 +0000 (18:31 +0100)]
[PATCH 15/57][Arm][GAS] Add support for MVE instructions: vcls, vclz and vfmas
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_mve_vfmas): New encoding function.
(do_neon_cls): Change to support MVE variants.
(do_neon_clz): Change to support MVE variants.
(insns): Change to support MVE variants and add new.
* testsuite/gas/arm/mve-vcls-bad.d: New test.
* testsuite/gas/arm/mve-vcls-bad.l: New test.
* testsuite/gas/arm/mve-vcls-bad.s: New test.
* testsuite/gas/arm/mve-vclz-bad.d: New test.
* testsuite/gas/arm/mve-vclz-bad.l: New test.
* testsuite/gas/arm/mve-vclz-bad.s: New test.
* testsuite/gas/arm/mve-vfmas-bad.d: New test.
* testsuite/gas/arm/mve-vfmas-bad.l: New test.
* testsuite/gas/arm/mve-vfmas-bad.s: New test.
Andre Vieira [Wed, 15 May 2019 17:21:32 +0000 (18:21 +0100)]
[PATCH 14/57][Arm][GAS] Add support for MVE instructions: vcadd, vcmla and vcmul
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (enum operand_parse_code): New operands.
(parse_operands): Handle new operands.
(do_mve_vcmul): New encoding function.
(do_vcmla): Change to support MVE variants.
(do_vcadd): Change to support MVE variants.
(insns): Change existing to support MVE variants and add new.
* testsuite/gas/arm/mve-vcadd-bad-1.d: New test.
* testsuite/gas/arm/mve-vcadd-bad-1.l: New test.
* testsuite/gas/arm/mve-vcadd-bad-1.s: New test.
* testsuite/gas/arm/mve-vcadd-bad-2.d: New test.
* testsuite/gas/arm/mve-vcadd-bad-2.l: New test.
* testsuite/gas/arm/mve-vcadd-bad-2.s: New test.
* testsuite/gas/arm/mve-vcmla-bad-1.d: New test.
* testsuite/gas/arm/mve-vcmla-bad-1.l: New test.
* testsuite/gas/arm/mve-vcmla-bad-1.s: New test.
* testsuite/gas/arm/mve-vcmla-bad-2.d: New test.
* testsuite/gas/arm/mve-vcmla-bad-2.l: New test.
* testsuite/gas/arm/mve-vcmla-bad-2.s: New test.
* testsuite/gas/arm/mve-vcmul-bad-1.d: New test.
* testsuite/gas/arm/mve-vcmul-bad-1.l: New test.
* testsuite/gas/arm/mve-vcmul-bad-1.s: New test.
* testsuite/gas/arm/mve-vcmul-bad-2.d: New test.
* testsuite/gas/arm/mve-vcmul-bad-2.l: New test.
* testsuite/gas/arm/mve-vcmul-bad-2.s: New test.
Andre Vieira [Wed, 15 May 2019 16:40:06 +0000 (17:40 +0100)]
[PATCH 13/57][Arm][GAS] Add support for MVE instructions: vand, vbic, vorr, vorn and veor
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (enum operand_parse_code): New operands.
(parse_operands): Handle new operands.
(enum vfp_or_neon_is_neon_bits): Moved
(vfp_or_neon_is_neon): Moved
(check_simd_pred_availability): Moved.
(do_neon_logic): Change to accept MVE variants.
(insns): Changed to accept MVE variants.
* testsuite/gas/arm/mve-vand-bad.d: New test.
* testsuite/gas/arm/mve-vand-bad.l: New test.
* testsuite/gas/arm/mve-vand-bad.s: New test.
* testsuite/gas/arm/mve-vbic-bad.d: New test.
* testsuite/gas/arm/mve-vbic-bad.l: New test.
* testsuite/gas/arm/mve-vbic-bad.s: New test.
* testsuite/gas/arm/mve-veor-bad.d: New test.
* testsuite/gas/arm/mve-veor-bad.l: New test.
* testsuite/gas/arm/mve-veor-bad.s: New test.
* testsuite/gas/arm/mve-vorn-bad.d: New test.
* testsuite/gas/arm/mve-vorn-bad.l: New test.
* testsuite/gas/arm/mve-vorn-bad.s: New test.
* testsuite/gas/arm/mve-vorr-bad.d: New test.
* testsuite/gas/arm/mve-vorr-bad.l: New test.
* testsuite/gas/arm/mve-vorr-bad.s: New test.
Andre Vieira [Wed, 15 May 2019 16:38:12 +0000 (17:38 +0100)]
[PATCH 12/57][Arm][GAS] Add support for MVE instructions: vaddlv and vaddv
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (M_MNEM_vaddlv, M_MNEM_vaddlva, M_MNEM_vaddv,
M_MNEM_vaddva): New instruction encodings.
(mve_encode_rq): New encoding helper function.
(do_mve_vaddlv): New encoding function.
(do_mve_vaddv): New encoding function.
* testsuite/gas/arm/mve-vaddlv-bad.d: New test.
* testsuite/gas/arm/mve-vaddlv-bad.l: New test.
* testsuite/gas/arm/mve-vaddlv-bad.s: New test.
* testsuite/gas/arm/mve-vaddv-bad.d: New test.
* testsuite/gas/arm/mve-vaddv-bad.l: New test.
* testsuite/gas/arm/mve-vaddv-bad.s: New test.
Andre Vieira [Wed, 15 May 2019 16:37:07 +0000 (17:37 +0100)]
[PATCH 11/57][Arm][GAS] Add support for MVE instructions: vadc, vsbc and vbrsr
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (M_MNEM_vadc, M_MNEM_vadci, M_MNEM_vbrsr):
New instruction encodings.
(do_mve_vadc): New encoding instruction.
(do_mve_vbrsr): Likewise.
(do_mve_vsbc): Likewise.
* testsuite/gas/arm/mve-vadc-bad.d: New test.
* testsuite/gas/arm/mve-vadc-bad.l: New test.
* testsuite/gas/arm/mve-vadc-bad.s: New test.
* testsuite/gas/arm/mve-vbrsr-bad.d: New test.
* testsuite/gas/arm/mve-vbrsr-bad.l: New test.
* testsuite/gas/arm/mve-vbrsr-bad.s: New test.
* testsuite/gas/arm/mve-vsbc-bad.d: New test.
* testsuite/gas/arm/mve-vsbc-bad.l: New test.
* testsuite/gas/arm/mve-vsbc-bad.s: New test.
Andre Vieira [Wed, 15 May 2019 16:35:43 +0000 (17:35 +0100)]
[PATCH 10/57][Arm][GAS] Add support for MVE instructions: vcmp and vpt
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (MVE_BAD_QREG): New error message.
(enum operand_parse_code): Define new operand.
(parse_operands): Handle new operand.
(do_mve_vpt): Change for VPT blocks.
(NEON_SHAPE_DEF): New shape.
(neon_logbits): Moved.
(LOW4): Moved
(HI1): Moved
(mve_get_vcmp_vpt_cond): New function to translate vpt conditions.
(do_mve_vcmp): New encoding function.
(do_vfp_nsyn_cmp): Changed to support MVE variants.
(insns): Change to support MVE variants of vcmp and add vpt.
* testsuite/gas/arm/mve-vcmp-bad-1.d: New test.
* testsuite/gas/arm/mve-vcmp-bad-1.l: New test.
* testsuite/gas/arm/mve-vcmp-bad-1.s: New test.
* testsuite/gas/arm/mve-vcmp-bad-2.d: New test.
* testsuite/gas/arm/mve-vcmp-bad-2.l: New test.
* testsuite/gas/arm/mve-vcmp-bad-2.s: New test.
* testsuite/gas/arm/mve-vpt-bad-1.d: New test.
* testsuite/gas/arm/mve-vpt-bad-1.l: New test.
* testsuite/gas/arm/mve-vpt-bad-1.s: New test.
* testsuite/gas/arm/mve-vpt-bad-2.d: New test.
* testsuite/gas/arm/mve-vpt-bad-2.l: New test.
* testsuite/gas/arm/mve-vpt-bad-2.s: New test.
Andre Vieira [Wed, 15 May 2019 16:31:25 +0000 (17:31 +0100)]
[PATCH 9/57][Arm][GAS] Add support for MVE instructions: vmov
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (struct arm_it): Expand isscalar field to be able to
distinguish between types of scalar.
(parse_typed_reg_or_scalar): Change to accept MVE scalar variants.
(parse_scalar): Likewise.
(parse_neon_mov): Accept MVE variant.
(po_scalar_or_goto): Make use reg_type.
(parse_operands): Change uses of po_scalar_or_goto.
(do_vfp_sp_monadic): Change to accept MVE variants.
(do_vfp_reg_from_sp): Likewise.
(do_vfp_sp_from_reg): Likewise.
(do_vfp_dp_rd_rm): Likewise.
(do_vfp_dp_rd_rn_rm): Likewise.
(do_vfp_dp_rm_rd_rn): Likewise.
(M_MNEM_vmovlt, M_MNEM_vmovlb, M_MNEM_vmovnt, M_MNEM_vmovnb): New
instruction encodings.
(NEON_SHAPE_DEF): New shape.
(do_mve_mov): New encoding fuction.
(do_mve_movn): Likewise.
(do_mve_movl): Likewise.
(do_neon_mov): Change to accept MVE variants.
(mcCE): New MACRO.
(insns): Accept new MVE variants and instructions.
* testsuite/gas/arm/mve-vmov-bad-1.d: New test.
* testsuite/gas/arm/mve-vmov-bad-1.l: New test.
* testsuite/gas/arm/mve-vmov-bad-1.s: New test.
* testsuite/gas/arm/mve-vmov-bad-2.d: New test.
* testsuite/gas/arm/mve-vmov-bad-2.l: New test.
* testsuite/gas/arm/mve-vmov-bad-2.s: New test.
Andre Vieira [Wed, 15 May 2019 16:21:53 +0000 (17:21 +0100)]
[PATCH 8/57][Arm][GAS] Add support for MVE instructions: vcvt
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (enum operand_parse_code): Add new operand.
(parse_operands): Handle new operand.
(do_neon_cvt_1): Handle MVE variants.
(do_neon_cvttb_1): Likewise.
(insns): Accept MVE variants.
* testsuite/gas/arm/mve-vcvt-bad-1.d: New test.
* testsuite/gas/arm/mve-vcvt-bad-1.l: New test.
* testsuite/gas/arm/mve-vcvt-bad-1.s: New test.
* testsuite/gas/arm/mve-vcvt-bad-2.d: New test.
* testsuite/gas/arm/mve-vcvt-bad-2.l: New test.
* testsuite/gas/arm/mve-vcvt-bad-2.s: New test.
* testsuite/gas/arm/mve-vcvt-bad-3.d: New test.
* testsuite/gas/arm/mve-vcvt-bad-3.l: New test.
* testsuite/gas/arm/mve-vcvt-bad-3.s: New test.
* testsuite/gas/arm/mve-vcvt-bad-4.d: New test.
* testsuite/gas/arm/mve-vcvt-bad-4.l: New test.
* testsuite/gas/arm/mve-vcvt-bad-4.s: New test.
* testsuite/gas/arm/mve-vcvt-bad.d: New test.
* testsuite/gas/arm/mve-vcvt-bad.l: New test.
* testsuite/gas/arm/mve-vcvt-bad.s: New test.
Andre Vieira [Wed, 15 May 2019 16:20:46 +0000 (17:20 +0100)]
[PATCH 7/57][Arm][GAS] Add support for MVE instructions: vstr/vldr
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (struct arm_it): Make immisreg field larger to hold
type of register.
(enum shift_kind): Add SHIFT_UXTW shift kind.
(enum parse_shift_mode): Add SHIFT_UXTW_IMMEDIATE shift mode.
(parse_shift): Handle new shift type.
(parse_address_main): Accept new addressing modes.
(M_MNEM_vstrb, M_MNEM_vstrh, M_MNEM_vstrw, M_MNEM_vstrd,
M_MNEM_vldrb, M_MNEM_vldrh, M_MNEM_vldrw, M_MNEM_vldrd): New
instruction encodings.
(do_mve_vstr_vldr_QI): New encoding functions.
(do_mve_vstr_vldr_RQ): Likewise.
(do_mve_vstr_vldr_RI): Likewise.
(do_mve_vstr_vldr): Likewise.
* testsuite/gas/arm/mve-vldr-bad-1.d: New test.
* testsuite/gas/arm/mve-vldr-bad-1.l: New test.
* testsuite/gas/arm/mve-vldr-bad-1.s: New test.
* testsuite/gas/arm/mve-vldr-bad-2.d: New test.
* testsuite/gas/arm/mve-vldr-bad-2.l: New test.
* testsuite/gas/arm/mve-vldr-bad-2.s: New test.
* testsuite/gas/arm/mve-vldr-bad-3.d: New test.
* testsuite/gas/arm/mve-vldr-bad-3.l: New test.
* testsuite/gas/arm/mve-vldr-bad-3.s: New test.
* testsuite/gas/arm/mve-vstr-bad-1.d: New test.
* testsuite/gas/arm/mve-vstr-bad-1.l: New test.
* testsuite/gas/arm/mve-vstr-bad-1.s: New test.
* testsuite/gas/arm/mve-vstr-bad-2.d: New test.
* testsuite/gas/arm/mve-vstr-bad-2.l: New test.
* testsuite/gas/arm/mve-vstr-bad-2.s: New test.
* testsuite/gas/arm/mve-vstr-bad-3.d: New test.
* testsuite/gas/arm/mve-vstr-bad-3.l: New test.
* testsuite/gas/arm/mve-vstr-bad-3.s: New test.
Andre Vieira [Wed, 15 May 2019 16:05:58 +0000 (17:05 +0100)]
[PATCH 6/57][Arm][GAS] Add support for MVE instructions: vst/vld{2,4}
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (enum it_instruction_type): Add MVE_UNPREDICABLE_INSN.
(BAD_EL_TYPE): New error message.
(parse_neon_el_struct_list): Adapt to be able to accept MVE variant.
(parse_address_main): Likewise.
(group_reloc_type): Add GROUP_MVE.
(enum operand_parse_code): Add new operands.
(parse_operands): Handle new operands.
(M_MNEM_vst20, M_MNEM_vst21, M_MNEM_vst40, M_MNEM_vst41, M_MNEM_vst42,
M_MNEM_vst43, M_MNEM_vld20, M_MNEM_vld21, M_MNEM_vld40, M_MNEM_vld41,
M_MNEM_vld42, M_MNEM_vld43): New encodings.
(do_mve_vst_vld): New encoding function.
(do_neon_ld_st_interleave): Use BAD_EL_TYPE.
(it_fsm_pre_encode): Handle new it_instruction_type
(handle_pred_state): Likewise.
* testsuite/gas/arm/mve-vstld-bad.d: New test.
* testsuite/gas/arm/mve-vstld-bad.l: New test.
* testsuite/gas/arm/mve-vstld-bad.s: New test.
Andre Vieira [Wed, 15 May 2019 15:56:30 +0000 (16:56 +0100)]
[PATCH 5/57][Arm][GAS] Add support for MVE instructions: vmull{b,t}
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (BAD_MVE_AUTO): New error message.
(BAD_MVE_SRCDEST): Likewise.
(mark_feature_used): Diagnose MVE only instructions when in
auto-detection mode or -march=all.
(enum operand_parse_code): Define new operand.
(parse_operands): Handle new operand.
(M_MNEM_vmullt, M_MNEM_vmullb): New encodings.
(mve_encode_qqq): New encoding helper function.
(do_mve_vmull): New encoding function.
(insns): Handle new instructions.
* testsuite/gas/arm/mve-vmullbt-bad.d: New test.
* testsuite/gas/arm/mve-vmullbt-bad.l: New test.
* testsuite/gas/arm/mve-vmullbt-bad.s: New test.
Andre Vieira [Wed, 15 May 2019 15:54:23 +0000 (16:54 +0100)]
[PATCH 4/57][Arm][GAS] Add support for MVE instructions: vabav, vmladav and vmlsdav
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (struct asm_opcode): Make avalue a full int.
(BAD_ODD, BAD_EVEN, BAD_SIMD_TYPE): New errors.
(enum operand_parse_code): Handle new operands.
(parse_operands): Likewise.
(M_MNEM_vabav, M_MNEM_vmladav, M_MNEM_vmladava, M_MNEM_vmladavx,
M_MNEM_vmladavax, M_MNEM_vmlsdav, M_MNEM_vmlsdava, M_MNEM_vmlsdavx,
M_MNEM_vmlsdavax): Define new encodings.
(NEON_SHAPE_DEF): Add new shape.
(neon_check_type): Use BAD_SIMD_TYPE.
(mve_encode_rqq): New encoding helper function.
(do_mve_vabav, do_mve_vmladav): New encoding functions.
(mCEF): New MACRO.
* testsuite/gas/arm/mve-vabav-bad.d: New test.
* testsuite/gas/arm/mve-vabav-bad.l: New test.
* testsuite/gas/arm/mve-vabav-bad.s: New test.
* testsuite/gas/arm/mve-vmladav-bad.d: New test.
* testsuite/gas/arm/mve-vmladav-bad.l: New test.
* testsuite/gas/arm/mve-vmladav-bad.s: New test.
* testsuite/gas/arm/mve-vmlav-bad.d: New test.
* testsuite/gas/arm/mve-vmlav-bad.l: New test.
* testsuite/gas/arm/mve-vmlav-bad.s: New test.
* testsuite/gas/arm/mve-vmlsdav-bad.d: New test.
* testsuite/gas/arm/mve-vmlsdav-bad.l: New test.
* testsuite/gas/arm/mve-vmlsdav-bad.s: New test.
Andre Vieira [Wed, 15 May 2019 15:52:50 +0000 (16:52 +0100)]
[PATCH 3/57][Arm][GAS] Add support for MVE instructions: vabs and vneg
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (do_neon_abs_neg): Make it accept MVE variant.
(insns): Change vabs and vneg entries to accept MVE variants.
* testsuite/gas/arm/mve-vabsneg-bad-1.d: New test.
* testsuite/gas/arm/mve-vabsneg-bad-1.l: New test.
* testsuite/gas/arm/mve-vabsneg-bad-1.s: New test.
* testsuite/gas/arm/mve-vabsneg-bad-2.d: New test.
* testsuite/gas/arm/mve-vabsneg-bad-2.l: New test.
* testsuite/gas/arm/mve-vabsneg-bad-2.s: New test.
Andre Vieira [Wed, 15 May 2019 15:50:58 +0000 (16:50 +0100)]
[PATCH 2/57][Arm][GAS] Add support for MVE instructions: vpst, vadd, vsub and vabd
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (enum it_instruction_type): Rename to...
(enum pred_instruction_type): ... this. Include VPT types.
(it_insn_type): Rename to ...
(pred_insn_type): .. this.
(arm_it): Change comment.
(enum arm_reg_type): Add new value.
(reg_expected_msgs): New entry.
(asm_opcode): Add mayBeVecPred member.
(BAD_SYNTAX, BAD_NOT_VPT, BAD_OUT_VPT, BAD_VPT_COND, MVE_NOT_IT,
MVE_NOT_VPT, MVE_BAD_PC, MVE_BAD_SP): New diagnostic MACROS.
(arm_vcond_hsh): New table for vector condition codes.
(now_it): Rename to ...
(now_pred): ... this.
(now_it_compatible): Rename to ...
(now_pred_compatible): ... this.
(in_it_block): Rename to ...
(in_pred_block): ... this.
(handle_it_state): Rename to ...
(handle_pred_state): ... this. And change it to accept VPT blocks.
(set_it_insn_type): Rename to ...
(set_pred_insn_type): ... this.
(set_it_insn_type_nonvoid): Rename to ...
(set_pred_insn_type_nonvoid): ... this.
(set_it_insn_type_last): Rename to ...
(set_pred_insn_type_last): ... this.
(record_feature_use): Moved.
(mark_feature_used): Likewise.
(parse_typed_reg_or_scalar): Add new case for REG_TYPE_MQ.
(emit_insn): Use renamed functions and variables.
(enum operand_parse_code): Add new operands.
(parse_operands): Handle new operands.
(do_scalar_fp16_v82_encode): Change predication detection.
(do_it): Use renamed functions and variables.
(do_t_add_sub): Likewise.
(do_t_arit3): Likewise.
(do_t_arit3c): Likewise.
(do_t_blx): Likewise.
(do_t_branch): Likewise.
(do_t_bkpt_hlt1): Likewise.
(do_t_branch23): Likewise.
(do_t_bx): Likewise.
(do_t_bxj): Likewise.
(do_t_cond): Likewise.
(do_t_csdb): Likewise.
(do_t_cps): Likewise.
(do_t_cpsi): Likewise.
(do_t_cbz): Likewise.
(do_t_it): Likewise.
(do_mve_vpt): New function to handle VPT blocks.
(encode_thumb2_multi): Use renamed functions and variables.
(do_t_ldst): Use renamed functions and variables.
(do_t_mov_cmp): Likewise.
(do_t_mvn_tst): Likewise.
(do_t_mul): Likewise.
(do_t_nop): Likewise.
(do_t_neg): Likewise.
(do_t_rsb): Likewise.
(do_t_setend): Likewise.
(do_t_shift): Likewise.
(do_t_smc): Likewise.
(do_t_tb): Likewise.
(do_t_udf): Likewise.
(do_t_loloop): Likewise.
(do_neon_cvt_1): Likewise.
(do_vfp_nsyn_cvt_fpv8): Likewise.
(do_vsel): Likewise.
(do_vmaxnm): Likewise.
(do_vrint_1): Likewise.
(do_crypto_2op_1): Likewise.
(do_crypto_3op_1): Likewise.
(do_crc32_1): Likewise.
(it_fsm_pre_encode): Likewise.
(it_fsm_post_encode): Likewise.
(force_automatic_it_block_close): Likewise.
(check_it_blocks_finished): Likewise.
(check_pred_blocks_finished): Likewise.
(arm_cleanup): Likewise.
(now_it_add_mask): Rename to ...
(now_pred_add_mask): ... this. And use new variables and functions.
(NEON_ENC_TAB): Add entries for vabdl, vaddl and vsubl.
(N_I_MVE, N_F_MVE, N_SU_MVE): New MACROs.
(neon_check_type): Generalize error message.
(mve_encode_qqr): New MVE generic encoding function.
(neon_dyadic_misc): Change to accept MVE variants.
(do_neon_dyadic_if_su): Likewise.
(do_neon_addsub_if_i): Likewise.
(do_neon_dyadic_long): Likewise.
(vfp_or_neon_is_neon): Add extra checks.
(check_simd_pred_availability): Helper function to check SIMD
instruction availability with respect to predication.
(enum opcode_tag): New suffix value.
(opcode_lookup): Change to handle VPT blocks.
(new_automatic_it_block): Rename to ...
(close_automatic_it_block): ...this.
(TxCE, TxC3, TxC3w, TUE, TUEc, TUF, CE, C3, ToC, ToU,
toC, toU, CL, cCE, cCL, C3E, xCM_, UE, UF, NUF, nUF,
NCE_tag, NCE, NCEF, nCE_tag, nCE, nCEF): Add default value for new
field.
(mCEF, mnCEF, mnCE, MNUF, mnUF, mToC, MNCE, MNCEF): New MACROs.
(insns): Redefine vadd, vsub, cabd, vabdl, vaddl, vsubl to accept MVE
variants. Add entries for vscclrm, and vpst.
(md_begin): Add arm_vcond_hsh initialization.
* config/tc-arm.h (enum it_state): Rename to...
(enum pred_state): ...this.
(struct current_it): Rename to...
(struct current_pred): ...this.
(enum pred_type): New enum.
(struct arm_segment_info_type): Use current_pred.
* testsuite/gas/arm/armv8_3-a-fp-bad.l: Update error message.
* testsuite/gas/arm/armv8_3-a-simd-bad.l: Update error message.
* testsuite/gas/arm/dotprod-illegal.l: Update error message.
* testsuite/gas/arm/mve-vaddsubabd-bad-1.d: New test.
* testsuite/gas/arm/mve-vaddsubabd-bad-1.l: New test.
* testsuite/gas/arm/mve-vaddsubabd-bad-1.s: New test.
* testsuite/gas/arm/mve-vaddsubabd-bad-2.d: New test.
* testsuite/gas/arm/mve-vaddsubabd-bad-2.l: New test.
* testsuite/gas/arm/mve-vaddsubabd-bad-2.s: New test.
* testsuite/gas/arm/mve-vpst-bad.d: New test.
* testsuite/gas/arm/mve-vpst-bad.l: New test.
* testsuite/gas/arm/mve-vpst-bad.s: New test.
* testsuite/gas/arm/neon-ldst-es-bad.l: Updated error message.
Andre Vieira [Wed, 15 May 2019 15:44:57 +0000 (16:44 +0100)]
[PATCH 1/57][Arm][GAS]: Add support for +mve and +mve.fp
bfd/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* elf32-arm.c (elf32_arm_merge_eabi_attributes): Add case for Tag_MVE_arch.
binutils/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* readelf.c (arm_attr_tag_MVE_arch): New array for Tag_MVE_arch values.
(arm_attr_public_tag arm_attr_public_tags): Add case for Tag_MVE_arch.
elfcpp/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* arm.h (Tag_MVE_arch): Define new enum value.
gas/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (mve_ext, mve_fp_ext): New features.
(armv8_1m_main_ext_table): Add new extensions.
(aeabi_set_public_attributes): Translate new features to new build attributes.
(arm_convert_symbolic_attribute): Add Tag_MVE_arch.
* doc/c-arm.texi: Document new extensions and new build attribute.
include/ChangeLog:
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* elf/arm.h (Tag_MVE_arch): Define new enum value.
* opcode/arm.h (FPU_MVE, FPU_MVE_FP): New MACROs for new features.
Alan Modra [Thu, 16 May 2019 13:05:25 +0000 (22:35 +0930)]
Revert "ARM STM32L4XX erratum test failure"
This reverts commit
3a1bb98c3c4f983b950fbaf2797ddcd21fcb5211.
GDB Administrator [Thu, 16 May 2019 00:00:20 +0000 (00:00 +0000)]
Automatic date update in version.in
Andrew Burgess [Fri, 1 Mar 2019 11:19:22 +0000 (11:19 +0000)]
gdb/fortran: Add sizeof tests for indexed and sliced arrays
Add tests for calling sizeof on indexed and sliced arrays, and on
pointers to arrays. These are all things that currently work, but
were previously untested.
gdb/testsuite/ChangeLog:
* gdb.fortran/vla-sizeof.exp: Add tests of sizeof applied to
indexed and sliced arrays, and pointers to arrays.
Simon Marchi [Wed, 15 May 2019 15:20:16 +0000 (11:20 -0400)]
linux-thread-db.c: use bool where possible in thread_db code
I happened to be looking at this code and noticed we could replace ints
by bools at a few places.
gdb/ChangeLog:
* linux-thread-db.c (try_thread_db_load_1): Change return type
to bool.
(try_thread_db_load): Likewise.
(try_thread_db_load_from_pdir_1): Likewise.
(try_thread_db_load_from_pdir): Likewise.
(try_thread_db_load_from_sdir): Likewise.
(try_thread_db_load_from_dir): Likewise.
(thread_db_load_search): Likewise.
(has_libpthread): Likewise.
(thread_db_load): Likewise.
John Darrington [Wed, 15 May 2019 12:16:33 +0000 (14:16 +0200)]
S12Z: New option -mreg-prefix
Add a new machine dependent option to set a prefix for register names.
gas/
* config/tc-s12z.c (register_prefix): New variable. (md_show_usage,
md_parse_option): parse the new option.
(lex_reg_name): Scan the prefix if one is set.
* doc/c-s12z.texi (S12Z-Opts): Document the new option.
* testsuite/gas/s12z/reg-prefix.d: New file.
* testsuite/gas/s12z/reg-prefix.s: New file.
* testsuite/gas/s12z/s12z.exp: Add them.
Sergio Durigan Junior [Fri, 10 May 2019 20:57:26 +0000 (16:57 -0400)]
Don't crash if dwarf_decode_macro_bytes's 'body' is NULL
Hi,
Ref.: https://bugzilla.redhat.com/show_bug.cgi?id=1708192
https://bugzilla.redhat.com/show_bug.cgi?id=1708786
During the Fedora RPM build process, gdb-add-index is invoked to
extract the DWARF index from the binary, and GDB will segfault because
dwarf2read.c:parse_definition_macro's 'body' variable is NULL.
The underlying problem is that Fedora's rpm-build's "debugedit"
program will silently corrupt .debug_macro strings when a binary is
compiled with -g3. This is being taken care of by Mark Wielaard,
here:
https://bugzilla.redhat.com/show_bug.cgi?id=1708786
However, I still feel it's important to make GDB more resilient
against invalid DWARF input, so I'm proposing this rather simple patch
to catch the situation when "body == NULL" (i.e., it's probably been
corrupted) and issue a complaint. This is not a real fix to the
problem, of course, but at least GDB is able to finish without
segfaulting.
OK for master?
gdb/ChangeLog:
2019-05-15 Sergio Durigan Junior <sergiodj@redhat.com>
Ref.: https://bugzilla.redhat.com/show_bug.cgi?id=1708192
* dwarf2read.c (dwarf_decode_macro_bytes): Check whether 'body' is
NULL, and complain if that's the case.
John Darrington [Wed, 15 May 2019 12:15:02 +0000 (14:15 +0200)]
GAS (doc): Fix misaligned menu entry.
gas/
* doc/as.texi (Machine Dependencies): Fix misaligned menu entry.
Alan Modra [Wed, 15 May 2019 07:07:18 +0000 (16:37 +0930)]
C-SKY FAIL: jbt - csky
Another failure seen with MALLOC_PERTURB_=1.
* config/tc-csky.c (md_convert_frag): Initialise trailing
padding for COND_JUMP_PIC.
Alan Modra [Wed, 15 May 2019 07:01:28 +0000 (16:31 +0930)]
ARM STM32L4XX erratum test failure
Fixes a failure seen with MALLOC_PERTURB_=1.
* elf32-arm.c (elf32_arm_write_section): Don't leave
error case of STM32L4XX_ERRATUM_BRANCH_TO_VENEER with
unitialised section contents.
Alan Modra [Wed, 15 May 2019 01:54:09 +0000 (11:24 +0930)]
.file file number checking
This adds another test for file numbers given in .file directives,
checking that the value can be represented as an unsigned int and that
a memory allocation expression doesn't overflow. I removed a test
added recently since an earlier test (num < 1) already covers the
(num < 0) case.
* dwarf2dbg.c: Whitespace fixes.
(get_filenum): Don't strdup "file". Adjust error message.
(dwarf2_directive_filename): Use an unsigned type for "num".
Catch truncation of file number and overflow of get_filenum
XRESIZEVEC multiplication. Delete dead code.
Alan Modra [Wed, 15 May 2019 01:45:17 +0000 (11:15 +0930)]
tic54x_start_line_hook
git commit
3076e59490 caused
tic54x-coff +FAIL: c54x subsym assignment/use
PR 24538
* config/tc-tic54x.c (tic54x_start_line_hook): Do skip end of line
chars in setting endp.
John Darrington [Wed, 15 May 2019 04:47:16 +0000 (06:47 +0200)]
GDB (s12z): Improve reliability of the stack unwinder.
Previously, the stack unwinder searched through consecutive bytes for values
which it thought might be the start of a stack mutating operation.
This was error prone, because such bytes could also be the operands of other
instructions. This change uses the opcodes api to interpret the code in each
frame.
gdb/ChangeLog:
* s12z-tdep.c (push_pull_get_stack_adjustment): New function.
(advance, posn, abstract_read_memory): New functions.
[struct mem_read_abstraction]: New struct.
(s12z_frame_cache): Use opcodes API to interpret stack frame code.
GDB Administrator [Wed, 15 May 2019 00:00:15 +0000 (00:00 +0000)]
Automatic date update in version.in
Tom Tromey [Fri, 10 May 2019 16:40:15 +0000 (10:40 -0600)]
Fix assertion failure in coerce_unspec_val_to_type
coerce_unspec_val_to_type does:
set_value_address (result, value_address (val));
However, this is only valid for lval_memory. This patch changes this
code to only set the address for lval_memory values.
This seems like an ordinary oversight in coerce_unspec_val_to_type,
and a test case would be difficult to write, so I'm submitting it
without a test case.
Tested on x86-64 Fedora 29; plus using an Ada program that exhibits
the bug (but which cannot be shared).
gdb/ChangeLog
2019-05-14 Tom Tromey <tromey@adacore.com>
* ada-lang.c (coerce_unspec_val_to_type): Only set address when
value is not lval_memory.
Tom de Vries [Tue, 14 May 2019 15:45:51 +0000 (17:45 +0200)]
[gdb/doc] Mention index cache in concept and command index
The "automatic symbol index cache" entry in the docs is missing entries in the
concept and command indices. Add them.
gdb/doc/ChangeLog:
2019-05-14 Tom de Vries <tdevries@suse.de>
* gdb.texinfo (Automatic symbol index cache): Add concept and command
index entries.
Nick Clifton [Tue, 14 May 2019 15:16:56 +0000 (16:16 +0100)]
Add missing verilogtest.s file.
Tom Tromey [Mon, 13 May 2019 15:35:19 +0000 (09:35 -0600)]
Add file name styling to "info sharedlibrary"
This changes "info sharedlibrary" to add styling to the file name.
Tested on x86-64 Fedora 29.
gdb/ChangeLog
2019-05-14 Tom Tromey <tromey@adacore.com>
* solib.c (info_sharedlibrary_command): Style the file name.
gdb/testsuite/ChangeLog
2019-05-14 Tom Tromey <tromey@adacore.com>
* gdb.base/info-shared.exp (check_info_shared): Add "info shared"
styling test.
Nick Clifton [Tue, 14 May 2019 11:42:02 +0000 (12:42 +0100)]
Fix illegal memory access triggered when attempting to assemble a bogus i386 source file.
PR 24538
* config/tc-i386-intel.c (i386_intel_simplify_register): Reject
illegal register numbers.
Jamey Hicks [Tue, 14 May 2019 09:40:04 +0000 (10:40 +0100)]
Add new option to objcopy: --verilog-data-width. Use this option to set the size of byte bundles generated in verilog format files.
PR 19921
binutils* objcopy.c: Add new option --verilog-data-width. Use it to set
the value of VerilogDataWidth.
* doc/binutils.texi: Document the new option.
* testsuite/binutils-all/objcopy.exp: Run tests of new option.
* testsuite/binutils-all/verilog-1.hex: New file.
* testsuite/binutils-all/verilog-2.hex: New file.
* testsuite/binutils-all/verilog-4.hex: New file.
* testsuite/binutils-all/verilog-8.hex: New file.
* NEWS: Mention the new feature.
bfd * verilog.c: (VerilogDataWidth): New variable.
(verilog_write_record): Emit bytes in VerilogDataWidth bundles.
Nick Clifton [Fri, 10 May 2019 15:57:31 +0000 (16:57 +0100)]
A series of fixes to addres problems detected by compiling the assembler with address sanitization enabled.
PR 24538
gas * macro.c (get_any_string): Increase size of buffer used to hold
decimal value of expression result.
* dw2gencfi.c (get_debugseg_name): Handle an empty name.
* dwarf2dbg.c (get_filenum): Catch integer wraparound when
extending allocate file array.
(dwarf2_directive_filename): Add extra checks of the computed file
number.
* config/tc-arm.c (arm_tc_equal_in_insn): Insert copy of name into
warning hash table.
(s_arm_eabi_attribute): Check for obj_elf_vendor_attribute
returning -1.
* config/tc-i386.c (i386_output_nops): Catch an attempt to
generate nops of negative lengths.
* as.h (MAX_LITTLENUMS): Move definition to here from...
* config/atof-ieee.c: ...here.
* config/tc-aarch64.c: ...here.
* config/tc-arc.c: ...here.
* config/tc-arm.c: ...here.
* config/tc-epiphany.c: ...here.
* config/tc-i386.c: ...here.
* config/tc-ia64.c: ...here. (And correct the value).
* config/tc-m32c.c: ...here.
* config/tc-m32r.c: ...here.
* config/tc-metag.c: ...here.
* config/tc-microblaze.c: ...here.
* config/tc-nds32.c: ...here.
* config/tc-or1k.c: ...here.
* config/tc-score.c: ...here.
* config/tc-score7.c: ...here.
* config/tc-tic4x.c: ...here.
* config/tc-tilegx.c: ...here.
* config/tc-tilepro.c: ...here.
* config/tc-visium.c: ...here.
* config/tc-sh.c (md_assemble): Add check for an instruction with
no opcodes.
* config/tc-mips.c (mips_lookup_insn): Add check for very short
instruction name.
* config/tc-tic54x.c: Use unsigned chars to access is_end_of_line
array.
(tic54x_start_line_hook): Check for an empty line.
(next_line_shows_parallel): Do not walk off the end of the string.
(tic54x_macro_start): Check for too much macro nesting.
(tic54x_start_label): Add label_start parameter. Use this
parameter to check the first character of the label.
* config/tc-tic54x.h (TC_START_LABEL_WITHOUT_COLON): Pass
line_start variable to tic54x_start_label.
PR 24538
opcodes * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
end of the table prematurely.
Alan Hayward [Tue, 14 May 2019 09:09:05 +0000 (10:09 +0100)]
AArch64: Add half float view to V registers
AArch64 can fill the vector registers with half precision floats.
Add a view for this.
Add builtin type ieee half and connect this to the existing
floatformats_ieee_half.
gdb/ChangeLog:
2019-05-14 Alan Hayward <alan.hayward@arm.com>
* aarch64-tdep.c (aarch64_vnh_type): Add half view.
(aarch64_vnv_type): Likewise.
* target-descriptions.c (make_gdb_type): Add TDESC_TYPE_IEEE_HALF.
* common/tdesc.c: Likewise.
* common/tdesc.h (enum tdesc_type_kind): Likewise.
* features/aarch64-fpu.c (create_feature_aarch64_fpu): Regenerate.
* features/aarch64-fpu.xml: Add ieee half view.
* features/aarch64-sve.c (create_feature_aarch64_fpu): Likewise.
* gdbtypes.c (gdbtypes_post_init): Add builtin_half
* gdbtypes.h (struct builtin_type): Likewise.
(struct objfile_type): Likewise.
Tom de Vries [Tue, 14 May 2019 08:10:08 +0000 (10:10 +0200)]
[gdb/testsuite] Fix base address selection entry encoding in dw2-skip-prologue.S
A base address selection entry in a location list consist of two (constant or
relocated) address offsets. The two offsets are the same size as an address
on the target machine.
The test-case gdb.dwarf2/dw2-skip-prologue.S encodes a base address selection
entry using .4byte, which is incorrect for 8-byte pointer size. [ Which
triggers an assert in dwz, see PR dwz/24172. ]
Fix this by using PTRBYTE instead.
Tested on x86_64-linux.
gdb/testsuite/ChangeLog:
2019-05-14 Tom de Vries <tdevries@suse.de>
* gdb.dwarf2/dw2-skip-prologue.S (.debug_loc): Fix base address
selection entry encoding.
Tom de Vries [Tue, 14 May 2019 07:58:12 +0000 (09:58 +0200)]
[gdb/doc] Fix "maint info selftests" command index entry
Currently, the entry for the command "maint info selftests" in the Command,
Variable, and Function Index is listed at '"', rather than next to the other
"maint info" commands.
Fix this by removing the superfluous quoting in the @kindex entry.
gdb/doc/ChangeLog:
2019-05-14 Tom de Vries <tdevries@suse.de>
* gdb.texinfo (Maintenance Commands): Remove superfluous
quoting on command index entry for "maint info selftests".
GDB Administrator [Tue, 14 May 2019 00:00:20 +0000 (00:00 +0000)]
Automatic date update in version.in
GDB Administrator [Mon, 13 May 2019 00:00:23 +0000 (00:00 +0000)]
Automatic date update in version.in
Simon Marchi [Sun, 12 May 2019 15:47:37 +0000 (11:47 -0400)]
Fix two langauge -> language typos
GDB Administrator [Sun, 12 May 2019 00:01:00 +0000 (00:01 +0000)]
Automatic date update in version.in
Joel Brobecker [Sat, 11 May 2019 18:29:24 +0000 (11:29 -0700)]
Document the GDB 8.3 release in gdb/ChangeLog
gdb/ChangeLog:
GDB 8.3 released.
Faraz Shahbazker [Mon, 6 May 2019 16:29:20 +0000 (09:29 -0700)]
Add macro expansions for ADD, SUB, DADD and DSUB for MIPS r6
Release 6 of the MIPS architecture does not have an ADDI instruction.
ADD/SUB instructions with immediate operands can be expanded to load
and immediate value and then perform the operation.
gas/
* config/tc-mips.c (macro) <M_ADD_I, M_SUB_I, M_DADD_I, M_DSUB_I>:
Add expansions for MIPS r6.
* testsuite/gas/mips/add.s: Enable tests for R6.
* testsuite/gas/mips/daddi.s: Annotate to test DADD for R6.
* testsuite/gas/mips/mipsr6@add.d: Likewise.
* gas/testsuite/gas/mips/mipsr6@dadd.d: New test.
* gas/testsuite/gas/mips/mips.exp: Run the new test.
opcodes/
* mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
macros for R6.
Alan Modra [Sat, 11 May 2019 00:12:00 +0000 (09:42 +0930)]
PowerPC objdump -Mraw
* ppc-dis.c (print_insn_powerpc) Don't skip optional operands
when -Mraw is in effect.
GDB Administrator [Sat, 11 May 2019 00:00:19 +0000 (00:00 +0000)]
Automatic date update in version.in
Joshua Oreman [Fri, 10 May 2019 23:27:10 +0000 (07:27 +0800)]
Fix problem with ICF where diffs in EH frame info is ignored.
PR gold/21066
* gc.h (gc_process_relocs): Track relocations in .eh_frame sections
when ICF is enabled, even though the .eh_frame sections themselves
are not foldable.
* icf.cc (get_section_contents): Change arguments to permit operation
on just part of a section. Include extra identity regions in the
referring section's contents recursively.
(match_sections): Lock object here instead of in get_section_contents
so that get_section_contents can operate recursively.
(Icf::add_ehframe_links): New method.
(Icf::find_identical_sections): Pass .eh_frame sections to
add_ehframe_links(). Increase default iteration count from 2 to 3
because handling exception info typically requires one extra iteration.
* icf.h (Icf::extra_identity_list_): New data member with accessor.
(is_section_foldable_candidate): Include .gcc_except_table sections.
* options.h: Update documentation for new default ICF iteration count.
* testsuite/Makefile.am (icf_test_pr21066): New test case.
* testsuite/Makefile.in: Regenerate.
* testsuite/icf_test_pr21066.cc: New source file.
* testsuite/icf_test_pr21066.sh: New test script.
Simon Marchi [Fri, 10 May 2019 21:22:09 +0000 (17:22 -0400)]
Fix GDB build when using --disable-gdbmi
Since commit
b4be1b064860 ("Fix MI output for multi-location breakpoints")
we get this error when building with --disable-gdbmi:
CXXLD gdb
/home/smarchi/src/binutils-gdb/gdb/breakpoint.c:6358: error: undefined reference to 'mi_multi_location_breakpoint_output_fixed(ui_out*)'
This is due to breakpoint.c using a function defined in mi/mi-main.c, even
though mi/mi-main.c isn't included in the build.
To fix it, use the flags feature of ui_out. mi_ui_out has the new
fix_multi_location_breakpoint_output flag set for versions >= 3. Also,
move the global variable fix_multi_location_breakpoint_output to
breakpoint.c, so it can be read there even when we build without MI. I
renamed it to fix_multi_location_breakpoint_output_globally so it
doesn't clash with the new enumerator.
gdb/ChangeLog:
* breakpoint.h (fix_multi_location_breakpoint_output_globally):
New variable declaration.
* breakpoint.c (fix_multi_location_breakpoint_output_globally):
New variable.
(print_one_breakpoint): Use ui_out::test_flags and new global
variable to compute use_fixed_output.
* mi/mi-main.h (mi_multi_location_breakpoint_output_fixed):
Remove.
* mi/mi-main.c (fix_multi_location_breakpoint_output): Remove.
(mi_multi_location_breakpoint_output_fixed): Remove.
(mi_cmd_fix_multi_location_breakpoint_output): Adjust to set the
new variable.
* mi/mi-out.c (mi_ui_out::mi_ui_out): Set
fix_multi_location_breakpoint_output flag if version >= 3.
* ui-out.h (enum ui_out_flag)
<fix_multi_location_breakpoint_output>: New enumerator.
Simon Marchi [Fri, 10 May 2019 20:29:00 +0000 (16:29 -0400)]
cc-with-tweaks: show dwz stderr and verify result
When running the gdb.base/index-cache.exp test case with the
cc-with-dwz-m board, I noticed that the final executable didn't actually
contain a .gnu_debugaltlink section with the name of the external dwz
file:
$ readelf --debug-dump=links testsuite/outputs/gdb.base/index-cache/index-cache
* empty *
Running dwz by hand, I realized it's because dwz complains that the
output .debug_info section is empty and fails:
$ gcc ~/src/binutils-gdb/gdb/testsuite/gdb.base/index-cache.c -g3 -O0 -o a && cp a b
$ dwz -m foo a b
dwz: foo: .debug_info section not present
$ echo $?
1
This is because index-cache.c is trivial (just an empty main) and dwz
doesn't find anything to factor out to the dwz file. [1]
I think that cc-with-tweaks should fail in this scenario: if the user
asks for an external dwz file to be generated (the -m flag), then it
should be an error if cc-with-tweaks doesn't manage to produce an
executable with the proper link to this external dwz file. Otherwise,
the test runs with a regular non-dwzified executable, which gives a
false sense of security about whether the feature under test works with
dwzified executables.
So this patch adds checks for that after invoking dwz. It also removes
the 2>&1 to allow the error message to be printed like so:
Running /home/smarchi/src/binutils-gdb/gdb/testsuite/gdb.base/index-cache.exp ...
gdb compile failed, dwz: /home/smarchi/build/binutils-gdb/gdb/testsuite/outputs/gdb.base/index-cache/index-cache.dwz: .debug_info section not present
- In the -m case (multi-file compression), we check if the expected output file
exists.
- In the -z case (single-file compression), we check if the file
contents has changed. This should catch cases where dwz doesn't modify the
file because it's not worth it.
It was chosen not to check for dwz's exit code, as it is not very
reliable up to dwz 0.12.
With this patch, fewer tests will pass than before with the
cc-with-dwz and cc-with-dwz-m boards, but those were false positives
anyway, as the test ran with regular executables.
[1] Note that dwz has been patched by Tom de Vries to work correctly in
this case, so we can use dwz master to run the test:
https://sourceware.org/git/?p=dwz.git;a=commit;h=
08becc8b33453b6d013a65e7eeae57fc1881e801
gdb/ChangeLog:
* contrib/cc-with-tweaks.sh: Validate dwz's work.
Tom Tromey [Fri, 10 May 2019 14:19:04 +0000 (08:19 -0600)]
Document lazy computation for pretty-printer "children" method
I found out recently that some users didn't know that the Python
pretty-printers "children" method should compute its result lazily.
This has been a good idea since the earliest days, but wasn't
mentioned in the docs. This patch adds some text to this effect.
gdb/doc/ChangeLog
2019-05-10 Tom Tromey <tromey@adacore.com>
* python.texi (Pretty Printing API): Mention lazy computation for
"children".
Tom Tromey [Fri, 3 May 2019 23:03:40 +0000 (17:03 -0600)]
Add completion for Ada catch commands
This patch adds a completion function to the "catch exception"
and "catch handlers" commands.
Tested on x86-64 Fedora 29; reviewed off-list by Joel.
gdb/ChangeLog
2019-05-10 Tom Tromey <tromey@adacore.com>
* ada-lang.c (catch_ada_completer): New function.
(_initialize_ada_language): Use it.
gdb/testsuite/ChangeLog
2019-05-10 Tom Tromey <tromey@adacore.com>
* gdb.ada/info_exc.exp: Add "complete" test.
Tom Tromey [Fri, 10 May 2019 12:59:19 +0000 (06:59 -0600)]
Minor "catch" documentation improvements
This patch makes a few minor improvements to the catchpoint
documentation:
* "catch exception" and "catch handlers" now mention the argument in
the @item.
* "catch exception unhandled" is moved to be closer to "catch
exception", rather than after "catch handlers".
* "catch load" and "catch unload" now wrap the argument in @var.
gdb/doc/ChangeLog
2019-05-10 Tom Tromey <tromey@adacore.com>
* gdb.texinfo (Set Catchpoints): Add text for parameter to "catch
exception" and "catch handlers". Move "catch exception unhandled"
text. Use @var for "catch load" and "catch unload"
Alan Modra [Fri, 10 May 2019 13:47:45 +0000 (23:17 +0930)]
Re: Sign-extend start and stop address inputs to objdump
git commit
2379f9c475 introduced an rx-elf test failure. This fixes it.
* testsuite/binutils-all/objdump.exp (test_objdump_disas_limited),
(test_objdump_content_limited): Add text arg, use in place of .text.
(bintest_signed.o): Call get_standard_section_names for name of
text section.
Tom Tromey [Fri, 10 May 2019 13:17:48 +0000 (07:17 -0600)]
Two minor constifications
I noticed a couple of spots where a "char *" was used where a
"const char *" made more sense. This patch fixes both of them.
Tested by rebuilding.
gdb/ChangeLog
2019-05-10 Tom Tromey <tromey@adacore.com>
* thread.c (print_thread_info): Make "requested_threads" const.
* gdbthread.h (print_thread_info): Make "requested_threads"
const.
* ada-tasks.c (print_ada_task_info): Make "taskno_str" const.
* ada-lang.h (print_ada_task_info): Make "taskno_str" const.
GDB Administrator [Fri, 10 May 2019 00:00:37 +0000 (00:00 +0000)]
Automatic date update in version.in
Peter Bergner [Thu, 9 May 2019 14:09:47 +0000 (09:09 -0500)]
Update printing of optional operands during disassembly.
opcodes/
* ppc-dis.c (skip_optional_operands): Change return type and returns.
(print_insn_powerpc) <skip_optional>: Change type.
Call skip_optional_operands if we have not skipped any operands.
gas/
* testsuite/gas/ppc/476.d: Update expected output.
* testsuite/gas/ppc/power6.d: Likewise.
Matthew Malcomson [Thu, 9 May 2019 13:52:45 +0000 (14:52 +0100)]
[gas][testsuite] Don't specify arch in testsuite output
My testcase matched against a file format of elf64-littleaarch64 in the
objdump output. This was unnecessarily restrictive and causes testcase
failures on aarch64_be.
Here we remove that restriction.
Committed as obvious.
Testing done on aarch64_be-none-elf gas to see the failure goes away.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* testsuite/gas/aarch64/sve2.d: Remove file format restriction.
Tom de Vries [Thu, 9 May 2019 10:24:38 +0000 (12:24 +0200)]
[gdb/testsuite] Fix gdb.arch/amd64-tailcall-self.S
The test-case gdb.arch/amd64-tailcall-self.exp fails here:
...
if ![runto b] {
return -1
}
...
like:
...
(gdb) file build/gdb/testsuite/outputs/gdb.arch/amd64-tailcall-self/\
amd64-tailcall-self
Reading symbols from build/gdb/testsuite/outputs/gdb.arch/\
amd64-tailcall-self/amd64-tailcall-self...
Dwarf Error: Cannot find DIE at 0x1f5 referenced from DIE at 0x107 [in \
module build/gdb/testsuite/outputs/gdb.arch/amd64-tailcall-self/\
amd64-tailcall-self]
...
The problem is that in amd64-tailcall-self.S, CU-relative references are
assigned .debug_info section relative values. [ This is similar to the
problem fixed by "Fix gdb.arch/amd64-entry-value-paramref.S". ]
Fix this by assigning CU-relative references instead.
Tested on x86_64-linux.
gdb/testsuite/ChangeLog:
2019-05-09 Tom de Vries <tdevries@suse.de>
* gdb.arch/amd64-tailcall-self.S: Make DW_FORM_ref4 references
CU-relative.
Matthew Malcomson [Thu, 9 May 2019 09:29:29 +0000 (10:29 +0100)]
[binutils][aarch64] Add SVE2 tests
Add tests that SVE2 instructions are encoded as they should be, and
tests that invalid instructions have their problems reported.
Also check that each sve2 cryptographic extension is required to use the
corresponding cryptographic instructions.
Finally, test to ensure that sve2 instructions using mnemonics that
exist in sve1 still need the sve2 feature to be used.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* testsuite/gas/aarch64/illegal-sve2-aes.d: New test.
* testsuite/gas/aarch64/illegal-sve2-bitperm.d: New test.
* testsuite/gas/aarch64/illegal-sve2-sha3.d: Test new instructions.
* testsuite/gas/aarch64/illegal-sve2-sm4.d: Test new instructions.
* testsuite/gas/aarch64/illegal-sve2-sve1ext.d: Test new instructions.
* testsuite/gas/aarch64/illegal-sve2-sve1ext.l: Test new instructions.
* testsuite/gas/aarch64/illegal-sve2.d: Test new instructions.
* testsuite/gas/aarch64/illegal-sve2.l: Test new instructions.
* testsuite/gas/aarch64/illegal-sve2.s: Test new instructions.
* testsuite/gas/aarch64/sve1-extended-sve2.s: New test.
* testsuite/gas/aarch64/sve2.d: Test new instructions.
* testsuite/gas/aarch64/sve2.s: Test new instructions.
Matthew Malcomson [Thu, 9 May 2019 09:29:28 +0000 (10:29 +0100)]
[binutils][aarch64] Add SVE2 instructions.
This patch adds all the SVE2 instructions and their associated qualifier
sets.
Ok for trunk?
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-dis-2.c: Regenerate.
* aarch64-tbl.h (OP_SVE_BBU): New variant set.
(OP_SVE_BBB): New variant set.
(OP_SVE_DDDD): New variant set.
(OP_SVE_HHH): New variant set.
(OP_SVE_HHHU): New variant set.
(OP_SVE_SSS): New variant set.
(OP_SVE_SSSU): New variant set.
(OP_SVE_SHH): New variant set.
(OP_SVE_SBBU): New variant set.
(OP_SVE_DSS): New variant set.
(OP_SVE_DHHU): New variant set.
(OP_SVE_VMV_HSD_BHS): New variant set.
(OP_SVE_VVU_HSD_BHS): New variant set.
(OP_SVE_VVVU_SD_BH): New variant set.
(OP_SVE_VVVU_BHSD): New variant set.
(OP_SVE_VVV_QHD_DBS): New variant set.
(OP_SVE_VVV_HSD_BHS): New variant set.
(OP_SVE_VVV_HSD_BHS2): New variant set.
(OP_SVE_VVV_BHS_HSD): New variant set.
(OP_SVE_VV_BHS_HSD): New variant set.
(OP_SVE_VVV_SD): New variant set.
(OP_SVE_VVU_BHS_HSD): New variant set.
(OP_SVE_VZVV_SD): New variant set.
(OP_SVE_VZVV_BH): New variant set.
(OP_SVE_VZV_SD): New variant set.
(aarch64_opcode_table): Add sve2 instructions.
Matthew Malcomson [Thu, 9 May 2019 09:29:27 +0000 (10:29 +0100)]
[binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand.
New operand describes a shift-left immediate encoded in bits
22:20-19:18-16 where UInt(bits) - esize == shift.
This operand is useful for instructions like sshllb.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (parse_operands): Handle new SVE_SHLIMM_UNPRED_22
operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_SHLIMM_UNPRED_22
operand.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_SHLIMM_UNPRED_22.
(aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
operand.
Matthew Malcomson [Thu, 9 May 2019 09:29:26 +0000 (10:29 +0100)]
[binutils][aarch64] New sve_size_tsz_bhs iclass.
Add sve_size_tsz_bhs iclass needed for sqxtnb and similar instructions.
This iclass encodes one of three variants by the most significant bit
set in a 3-bit value where only one bit may be set.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_tsz_bhs
iclass.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
sve_size_tsz_bhs iclass encode.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
sve_size_tsz_bhs iclass decode.
Matthew Malcomson [Thu, 9 May 2019 09:29:24 +0000 (10:29 +0100)]
[binutils][aarch64] New SVE_Zm4_11_INDEX operand.
This includes defining a new single bit field SVE_i2h at position 20.
SVE_Zm4_11_INDEX handles indexed Zn registers where the index is encoded
in bits 20:11 and the register is chosed from range z0-z15 in bits 19-16.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (parse_operands): Handle new SVE_Zm4_11_INDEX
operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm4_11_INDEX operand.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_Zm4_11_INDEX.
(aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
(fields): Handle SVE_i2h field.
* aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
Matthew Malcomson [Thu, 9 May 2019 09:29:23 +0000 (10:29 +0100)]
[binutils][aarch64] New sve_shift_tsz_bhsd iclass.
This new iclass encodes the variant by which is the most significant bit
used of bits 23-22:20-19, where those bits are usually part of a
given constant operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_insn_class): Add sve_shift_tsz_bhsd
iclass.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
sve_shift_tsz_bhsd iclass encode.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
sve_shift_tsz_bhsd iclass decode.
Matthew Malcomson [Thu, 9 May 2019 09:29:22 +0000 (10:29 +0100)]
[binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand.
Include a new iclass to extract the variant from the most significant 3
bits of this operand.
Instructions such as rshrnb include a constant shift amount as an
operand, where the most significant three bits of this operand determine
what size elements the instruction is operating on.
The new SVE_SHRIMM_UNPRED_22 operand denotes this constant encoded in
bits 22:20-19:18-16 while the new sve_shift_tsz_hsd iclass denotes that
the SVE qualifier is encoded in bits 22:20-19.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (parse_operands): Handle new SVE_SHRIMM_UNPRED_22
operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_SHRIMM_UNPRED_22
operand.
(enum aarch64_insn_class): Add sve_shift_tsz_hsd iclass.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-asm.c (aarch64_ins_sve_shrimm):
(aarch64_encode_variant_using_iclass): Handle
sve_shift_tsz_hsd iclass encode.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
sve_shift_tsz_hsd iclass decode.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_SHRIMM_UNPRED_22.
(aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
operand.
Matthew Malcomson [Thu, 9 May 2019 09:29:21 +0000 (10:29 +0100)]
[binutils][aarch64] New sve_size_013 iclass.
Add sve_size_013 instruction class
This new iclass handles instructions such as pmullb whose size specifier
can only be encoded as 0, 1, or 3.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_013 iclass.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
sve_size_013 iclass encode.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
sve_size_013 iclass decode.
Matthew Malcomson [Thu, 9 May 2019 09:29:20 +0000 (10:29 +0100)]
[binutils][aarch64] New sve_size_bh iclass.
Add new iclass sve_size_bh to handle instructions that have two variants
encoded with the SVE_sz field.
This iclass behaves the same as the sve_size_sd iclass, but it has a
nicer name for those instructions that choose between variants using the
"B" and "H" size qualifiers.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_bh iclass.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
sve_size_bh iclass encode.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
sve_size_bh iclass decode.
Matthew Malcomson [Thu, 9 May 2019 09:29:19 +0000 (10:29 +0100)]
[binutils][aarch64] New sve_size_sd2 iclass.
Define new sve_size_sd2 iclass to distinguish between the two variants
of ldnt1sb and ldnt1sh.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_sd2 iclass.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
sve_size_sd2 iclass encode.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
sve_size_sd2 iclass decode.
* aarch64-opc.c (fields): Handle SVE_sz2 field.
* aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
Matthew Malcomson [Thu, 9 May 2019 09:29:18 +0000 (10:29 +0100)]
[binutils][aarch64] New SVE_ADDR_ZX operand.
Add AARCH64_OPND_SVE_ADDR_ZX operand that allows a vector of addresses
in a Zn register, offset by an Xm register.
This is used with scatter/gather SVE2 instructions.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (REG_ZR): Macro specifying zero register.
(parse_address_main): Account for new addressing mode [Zn.S, Xm].
(parse_operands): Handle new SVE_ADDR_ZX operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_ADDR_ZX operand.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_ADDR_ZX.
(aarch64_print_operand): Add printing for SVE_ADDR_ZX.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
Matthew Malcomson [Thu, 9 May 2019 09:29:17 +0000 (10:29 +0100)]
[binutils][aarch64] New SVE_Zm3_11_INDEX operand.
Introduce new operand SVE_Zm3_11_INDEX that indicates a register between
z0-z7 stored in bits 18-16 and an index stored in bits 20-19:11.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (parse_operands): Handle new SVE_Zm3_11_INDEX
operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm3_11_INDEX operand.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_Zm3_11_INDEX.
(aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
(fields): Handle SVE_i3l and SVE_i3h2 fields.
* aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
fields.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
Matthew Malcomson [Thu, 9 May 2019 09:29:16 +0000 (10:29 +0100)]
[binutils][aarch64] New iclass sve_size_hsd2.
Add "sve_size_hsd2" iclass decode that uses the new FLD_SVE_size field
value to determine the variant of an instruction.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_hsd2 iclass.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
sve_size_hsd2 iclass encode.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
sve_size_hsd2 iclass decode.
* aarch64-opc.c (fields): Handle SVE_size field.
* aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
Matthew Malcomson [Thu, 9 May 2019 09:29:15 +0000 (10:29 +0100)]
[binutils][aarch64] Introduce SVE_IMM_ROT3 operand.
New operand AARCH64_OPND_SVE_IMM_ROT3 handles a single bit rotate
operand encoded at bit position 10.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (parse_operands): Handle new SVE_IMM_ROT3 operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_IMM_ROT3 operand.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_IMM_ROT3.
(aarch64_print_operand): Add printing for SVE_IMM_ROT3.
(fields): Handle SVE_rot3 field.
* aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
Matthew Malcomson [Thu, 9 May 2019 09:29:13 +0000 (10:29 +0100)]
[binutils][aarch64] Allow movprfx for SVE2 instructions.
SVE2 introduces a number of new instructions that work with the movprfx
instruction. This commit ensures that SVE2 instructions are accounted
for.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-opc.c (verify_constraints): Check for movprfx for sve2
instructions.
Matthew Malcomson [Thu, 9 May 2019 09:29:12 +0000 (10:29 +0100)]
[binutils][aarch64] SVE2 feature extension flags.
Include all feature flag macros.
The "sve2" extension that enables the core sve2 instructions.
This also enables the sve extension, since sve is a requirement of sve2.
Extra optional sve2 features are the bitperm, sm4, aes, and sha3 extensions.
These are all given extra feature flags, "bitperm", "sve2-sm4",
"sve2-aes", and "sve2-sha3" respectively.
The sm4, aes, and sha3 extensions are explicitly marked as sve2
extensions to distinguish them from the corresponding NEON extensions.
Rather than continue extending the current feature flag numbers, I used
some bits that have been skipped.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c: Add command line architecture feature flags
"sve2", "sve2-sm4", "sve2-aes", "sve2-sha3", "bitperm".
* doc/c-aarch64.texi: Document new architecture feature flags.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_SVE2
AARCH64_FEATURE_SVE2_AES, AARCH64_FEATURE_SVE2_BITPERM,
AARCH64_FEATURE_SVE2_SM4, AARCH64_FEATURE_SVE2_SHA3): New
feature macros.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-tbl.h
(aarch64_feature_sve2, aarch64_feature_sve2aes,
aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
aarch64_feature_sve2bitperm): New feature sets.
(SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
for feature set addresses.
(SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
Dimitar Dimitrov [Thu, 9 May 2019 09:26:11 +0000 (10:26 +0100)]
Use the correct names for the init and fini array start symbols in the default Pru linker script.
* scripttempl/pru.sc (__init_array_begin, __init_array_begin):
Rename.
GDB Administrator [Thu, 9 May 2019 00:00:28 +0000 (00:00 +0000)]
Automatic date update in version.in
Tom de Vries [Wed, 8 May 2019 22:41:26 +0000 (00:41 +0200)]
[gdb/testsuite] Fix gdb.arch/amd64-entry-value-paramref.S
The file gdb.arch/amd64-entry-value-paramref.S contains a DIE for function
bar:
...
DIE29: .uleb128 0x2 # (DIE (0x29) DW_TAG_subprogram)
.ascii "bar\0" # DW_AT_name
.byte 0x1 # DW_AT_decl_file (gdb.arch/amd64-entry-value-paramref.cc)
.byte 0x15 # DW_AT_decl_line
.long DIE45 # DW_AT_type
.byte 0x1 # DW_AT_inline
...
which refers to DIE45:
...
DIE45: .uleb128 0x4 # (DIE (0x45) DW_TAG_base_type)
.byte 0x4 # DW_AT_byte_size
.byte 0x5 # DW_AT_encoding
.ascii "int\0" # DW_AT_name
...
using a form DW_FORM_ref4:
...
.uleb128 0x2 # (abbrev code)
.uleb128 0x2e # (TAG: DW_TAG_subprogram)
.byte 0x1 # DW_children_yes
...
.uleb128 0x49 # (DW_AT_type)
.uleb128 0x13 # (DW_FORM_ref4)
...
However, the DW_FORM_ref4 is a CU-relative reference, while using a label for
the value will result in a section-relative value.
So, if linked in object files contain dwarf info and are placed in the
.debug_info section before the compilation units generated from
amd64-entry-value-paramref.S, then the referenced type is at 0x108:
...
<1><108>: Abbrev Number: 4 (DW_TAG_base_type)
<109> DW_AT_byte_size : 4
<10a> DW_AT_encoding : 5 (signed)
<10b> DW_AT_name : int
...
but the reference will point to a non-existing DIE at 0x1cf:
...
<1><f0>: Abbrev Number: 2 (DW_TAG_subprogram)
<f1> DW_AT_name : bar
<f5> DW_AT_decl_file : 1
<f6> DW_AT_decl_line : 21
<f7> DW_AT_type : <0x1cf>
<fb> DW_AT_inline : 1 (inlined)
...
which happens to cause a GDB internal error described in PR23270 - "GDB
internal error: dwarf2read.c:18656: internal-error: could not find partial
DIE 0x1b7 in cache".
Fix the invalid DWARF by making the reference value CU-relative:
...
- .long DIE45 # DW_AT_type
+ .long DIE45 - .Ldebug_info0 # DW_AT_type
...
Tested on x86_64-linux.
gdb/testsuite/ChangeLog:
2019-05-09 Tom de Vries <tdevries@suse.de>
* gdb.arch/amd64-entry-value-paramref.S: Make DW_FORM_ref4 references
CU-relative.
Tom Tromey [Thu, 2 May 2019 22:13:50 +0000 (16:13 -0600)]
Convert gdbtypes.c to type-safe registry API
This changes gdbtypes.c to use the type-safe registry API.
gdb/ChangeLog
2019-05-08 Tom Tromey <tom@tromey.com>
* gdbtypes.c (objfile_type_data): Change type.
(objfile_type, _initialize_gdbtypes): Update.
Tom Tromey [Thu, 2 May 2019 22:11:22 +0000 (16:11 -0600)]
Convert dwarf2-frame.c to type-safe registry API
This changes dwarf2-frame.c to use the type-safe registry API.
gdb/ChangeLog
2019-05-08 Tom Tromey <tom@tromey.com>
* dwarf2-frame.c (dwarf2_frame_objfile_data): Change type.
(dwarf2_frame_find_fde, dwarf2_build_frame_info)
(_initialize_dwarf2_frame): Update.
Tom Tromey [Thu, 2 May 2019 22:08:54 +0000 (16:08 -0600)]
Convert objc-lang.c to type-safe registry API
This changes objc-lang.c to use the type-safe registry API.
gdb/ChangeLog
2019-05-08 Tom Tromey <tom@tromey.com>
* objc-lang.c (objc_objfile_data): Change type.
(find_methods): Update.
(_initialize_objc_lang): Remove.
Tom Tromey [Wed, 1 May 2019 21:50:33 +0000 (15:50 -0600)]
Convert stabsread.c to type-safe registry API
This changes stabsread.c to use the type-safe registry API.
gdb/ChangeLog
2019-05-08 Tom Tromey <tom@tromey.com>
* stabsread.c (rs6000_builtin_type_data): Change type.
(rs6000_builtin_type, _initialize_stabsread): Update.
Tom Tromey [Wed, 1 May 2019 21:46:15 +0000 (15:46 -0600)]
Remove mips_pdr_data
mips_pdr_data is unused, so this patch removes it.
gdb/ChangeLog
2019-05-08 Tom Tromey <tom@tromey.com>
* mips-tdep.c (mips_pdr_data): Remove.
(_initialize_mips_tdep): Update.
Tom Tromey [Wed, 1 May 2019 21:44:00 +0000 (15:44 -0600)]
Convert hppa-tdep.c to type-safe registry API
This changes hppa-tdep.c to use the type-safe registry API.
gdb/ChangeLog
2019-05-08 Tom Tromey <tom@tromey.com>
* hppa-tdep.c (hppa_objfile_priv_data): Change type.
(hppa_init_objfile_priv_data, read_unwind_info)
(find_unwind_entry, _initialize_hppa_tdep): Update.
Tom Tromey [Wed, 1 May 2019 21:41:13 +0000 (15:41 -0600)]
Convert elfread.c to type-safe registry API
This changes elfread.c to use the type-safe registry API. This also
fixes a potential memory leak, by changing the hash table so that it
is no longer allocated on an obstack.
gdb/ChangeLog
2019-05-08 Tom Tromey <tom@tromey.com>
* elfread.c (elf_objfile_gnu_ifunc_cache_data): Change type.
(elf_gnu_ifunc_record_cache): Update. Don't allocate hash table
on obstack.
(elf_gnu_ifunc_resolve_by_cache, _initialize_elfread): Update.
projects / platform / upstream / binutils.git / log