Emma Anholt [Thu, 19 May 2022 20:41:34 +0000 (13:41 -0700)]
freedreno/ir3: Fold 16-bit conversions into image load/store src/dsts.
Shaves 5 instructions off of one manhattan31 shader.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16616>
Emma Anholt [Tue, 31 May 2022 19:49:27 +0000 (12:49 -0700)]
freedreno/ir3: Fix validation of half-precision image store values.
ce1a381e57d2 ("turnip: enable VK_KHR_16bit_storage on A650") determined
that the type of the instr decided the type of the value being stored in
the ".b" case. But it would be surprising if image stores had the type
determine the coordinates' precision instead of the value's, and once we
turned on image instruction precision lowering we ran into asserts.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16616>
Matt Turner [Mon, 22 Feb 2021 20:11:14 +0000 (20:11 +0000)]
freedreno/ir3: Pass 16-bit sampler coordinates when possible.
shader-db highlights from Rob's android shaders:
total instructions in shared programs: 769641 -> 767536 (-0.27%)
instructions in affected programs: 151139 -> 149034 (-1.39%)
total last-baryf in shared programs: 55908 -> 55607 (-0.54%)
last-baryf in affected programs: 35219 -> 34918 (-0.85%)
total sstall in shared programs: 67074 -> 65767 (-1.95%)
total full in shared programs: 36115 -> 36080 (-0.10%)
full in affected programs: 203 -> 168 (-17.24%)
sstall in affected programs: 9510 -> 8203 (-13.74%)
total (ss) in shared programs: 14380 -> 14239 (-0.98%)
(ss) in affected programs: 2965 -> 2824 (-4.76%)
total systall in shared programs: 92425 -> 91522 (-0.98%)
systall in affected programs: 13146 -> 12243 (-6.87%)
total (sy) in shared programs: 4330 -> 4314 (-0.37%)
(sy) in affected programs: 167 -> 151 (-9.58%)
total waves in shared programs: 71580 -> 71584 (<.01%)
waves in affected programs: 12 -> 16 (33.33%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16616>
Emma Anholt [Tue, 31 May 2022 21:35:58 +0000 (14:35 -0700)]
freedreno/ir3: Make the types of tex coord padding match.
Required for lowering of coords to be 16-bit.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16616>
Matt Turner [Fri, 19 Feb 2021 20:30:05 +0000 (20:30 +0000)]
freedreno/ir3: Move the texture array coord fixup to nir
We're going to optimize sampler coordinates to FP16, so we'll need to
add the appropriately typed 0.5. Move this to NIR where that information
is readily available.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16616>
Emma Anholt [Thu, 19 May 2022 19:40:18 +0000 (12:40 -0700)]
freedreno/ir3: Enable load/store vectorization for SSBO access, too.
Saves a few ldib/stib instructions in gfxbench vk-5-normal compute shaders
by grouping vec4 accesses together.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16616>
Emma Anholt [Thu, 19 May 2022 20:26:33 +0000 (13:26 -0700)]
nir_lower_mediump: Drop assertion about not containing movs.
A 1D texture operation may need to do a mov to turn a reference to a
channel of an SSA value into a scalar value to be passed as the texture
coordinate (since texture srcs can't do swizzles). Seen in
amnesia-the-dark-descent/low/46.shader_test() for example, where a 1D
texture is used to remap each of r,g,b from a previous texture result.
Besides, the nir_op_is_vec() case will (perhaps surprisingly) look through
a mov, anyway.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16616>
Emma Anholt [Wed, 1 Jun 2022 22:15:24 +0000 (15:15 -0700)]
ci/turnip: Add missing xfails for a618 full VK run
Fixes:
836ce97f5ea8 ("ci: bump VK-GL-CTS to 1.3.2.0")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16616>
Yiwei Zhang [Fri, 27 May 2022 23:02:49 +0000 (23:02 +0000)]
venus: resolve AHARDWAREBUFFER_FORMAT_Y8Cb8Cr8_420 to external format
This is to work around ANGLE yuv support.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16759>
Alyssa Rosenzweig [Thu, 26 May 2022 16:09:54 +0000 (12:09 -0400)]
pan/bi: Respect swizzles in nir_op_pack_64_2x32_split
Triggered a BIR validation error, which made debugging a breeze. That validation
pass (dimensionality checks) gets a lot of use, it seems :-)
Fixes:
dEQP-VK.ssbo.layout.2_level_array.std430.row_major_mat4x2_comp_access_store_cols
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16724>
Alyssa Rosenzweig [Thu, 26 May 2022 16:29:06 +0000 (12:29 -0400)]
panvk: Use vk_image_subresource_*_count for clears
This handles VK_REMAINING_* for us, instead of underflowing and clearing no
levels/layers.
Fixes dEQP-VK.api.image_clearing.core.clear_color_image.2d.linear.single_layer.*
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16724>
Alyssa Rosenzweig [Tue, 17 May 2022 15:13:59 +0000 (11:13 -0400)]
panfrost: Allow 2D AFBC on Valhall
2D AFBC should be working now, flip the switch. 3D AFBC needs more research to
get right, honestly it's not clear how 3D AFBC on Bifrost is working...
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16800>
Alyssa Rosenzweig [Tue, 17 May 2022 18:27:44 +0000 (14:27 -0400)]
panfrost: Handle texturing from AFBC on Valhall
We need to pack special AFBC-specific plane descriptors instead of the generic
plane descriptor. Nothing too fancy here, though.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16800>
Alyssa Rosenzweig [Tue, 17 May 2022 18:27:09 +0000 (14:27 -0400)]
panfrost: Support rendering to AFBC on Valhall
Add the required handling when packing render target and depth buffer
descriptors on Valhall. This is mostly equivalent to Bifrost.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16800>
Alyssa Rosenzweig [Tue, 17 May 2022 18:25:58 +0000 (14:25 -0400)]
panfrost: Add pan_afbc_compression_mode on Valhall
Map a canonical format (a hardware-independent pipe_format) to a compression
mode (Valhall-specific hardware enum defined in GenXML). To be used for packing
plane descriptors and render target descriptors when AFBC is in use on Valhall.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16800>
Alyssa Rosenzweig [Tue, 17 May 2022 18:22:09 +0000 (14:22 -0400)]
panfrost: Pass arch instead of dev into afbc_format
For callers that have a device object, it's easy to pass dev->arch instead of
dev. But this requires callers to have a reference to the device, which is
tricky for callers that only have the arch via PAN_ARCH. Pass dev->arch instead
of dev to accommodate them.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16800>
Alyssa Rosenzweig [Wed, 1 Jun 2022 18:34:08 +0000 (14:34 -0400)]
panfrost: Fix XML for AFBC header on v9
Misnamed field due to copy/paste fail from Bifrost.
Fixes:
c011ea6c265 ("panfrost: Shuffle render target AFBC for Valhall")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16800>
Alyssa Rosenzweig [Tue, 31 May 2022 13:18:46 +0000 (09:18 -0400)]
pan/mdg: Print outmods when printing IR
In particular, this lets us distinguish mul_high from regular mul.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16798>
Alyssa Rosenzweig [Tue, 31 May 2022 13:08:23 +0000 (09:08 -0400)]
pan/mdg: Distinguish SSA vs reg when printing IR
This makes it easy to match the printed IR with the indices in the NIR.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16798>
Alyssa Rosenzweig [Tue, 31 May 2022 12:43:33 +0000 (08:43 -0400)]
pan/mdg: Only print 1 source for moves
This makes the printed IR easier to read at a glance.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16798>
Alyssa Rosenzweig [Tue, 31 May 2022 12:41:03 +0000 (08:41 -0400)]
pan/mdg: Only print 2 sources for ALU
..and assert the other sources are null. The one place this might fail in the
future is for real FMA, but we don't support that for GL.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16798>
Alyssa Rosenzweig [Tue, 31 May 2022 12:37:33 +0000 (08:37 -0400)]
pan/mdg: Only print masked components of swizzle
This matches the IR printer with the disassembler, making the output of the IR
printer much easier to parse at a glance.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16798>
Alyssa Rosenzweig [Thu, 19 May 2022 16:11:32 +0000 (12:11 -0400)]
pan/mdg: Use "<<" instead of "lsl"
Easier to read and consistent with C code.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16798>
Alyssa Rosenzweig [Thu, 19 May 2022 16:08:46 +0000 (12:08 -0400)]
pan/mdg: Remove uppercase write masks
These do not convey any additional information, and fail to account for
shrinking. In particular, a 64-bit writemask with .keephi would fail to
disassemble and instead trip the assertion, since that would be the ZW
components. Just delete the broken code.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16798>
Alyssa Rosenzweig [Thu, 19 May 2022 16:29:01 +0000 (12:29 -0400)]
pan/mdg: Scalarize with 64-bit sources
Otherwise, we can get vec3 with u2u32 with 64-bit sources which we need lowered.
Since our current approach is "scalarize all 64-bit ops", we need to check for
conversions too.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16798>
Georg Lehmann [Thu, 20 Jan 2022 19:50:15 +0000 (20:50 +0100)]
radv, aco: Packed usub_sat/isub_sat.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
Georg Lehmann [Sat, 20 Nov 2021 16:18:28 +0000 (17:18 +0100)]
radv: Enable VK_INTEL_shader_integer_functions2.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
Georg Lehmann [Sat, 20 Nov 2021 13:33:20 +0000 (14:33 +0100)]
radv: Lower 8bit isub_sat/usub_sat.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
Georg Lehmann [Fri, 19 Nov 2021 13:56:07 +0000 (14:56 +0100)]
radv: Lower hadd/hradd.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
Georg Lehmann [Fri, 19 Nov 2021 21:58:41 +0000 (22:58 +0100)]
radv: Lower mul_32x16.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
Georg Lehmann [Fri, 19 Nov 2021 21:38:30 +0000 (22:38 +0100)]
nir: Add optional lowering for mul_32x16.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
Georg Lehmann [Sat, 20 Nov 2021 20:11:57 +0000 (21:11 +0100)]
ac/llvm: Implement uclz.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
Georg Lehmann [Sat, 20 Nov 2021 19:45:57 +0000 (20:45 +0100)]
ac/llvm: Implement usub_sat and isub_sat.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
Georg Lehmann [Fri, 19 Nov 2021 15:43:31 +0000 (16:43 +0100)]
aco: Implement isub_sat.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
Georg Lehmann [Fri, 19 Nov 2021 15:28:52 +0000 (16:28 +0100)]
aco: Implement usub_sat.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
Georg Lehmann [Fri, 19 Nov 2021 13:27:06 +0000 (14:27 +0100)]
aco: Implement uclz.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>
Danylo Piliaiev [Wed, 1 Jun 2022 15:32:27 +0000 (18:32 +0300)]
ir3: Force late-z if FS has global store/atomic
No known tests are fixed.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16816>
Alyssa Rosenzweig [Thu, 19 May 2022 20:10:44 +0000 (16:10 -0400)]
pan/bi: Use flow control lowering on Valhall
Logically at the same part of the compile pipeline as clause scheduling on
Bifrost. Lots of similarities, too. Now that we generate flow control only as a
late pass, various hacks in the compiler are no longer necessary and are
dropped.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>
Alyssa Rosenzweig [Fri, 20 May 2022 16:30:59 +0000 (12:30 -0400)]
pan/va: Unit test flow control merging
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>
Alyssa Rosenzweig [Thu, 19 May 2022 20:58:36 +0000 (16:58 -0400)]
pan/va: Unit test flow control insertion
Test that we correctly track the scoreboard, helper invocations, reconvergence,
and ends and insert NOPs to effect this expected flow control.
As the pass inserts NOPs but does not otherwise modify the shader, this is easy
to test with well-defined behaviour of the pass.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>
Alyssa Rosenzweig [Wed, 25 May 2022 13:40:02 +0000 (09:40 -0400)]
pan/va: Respect assigned slots
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>
Alyssa Rosenzweig [Wed, 25 May 2022 13:39:44 +0000 (09:39 -0400)]
pan/va: Assign slots roundrobin
This should reduce false dependencies with asynchronous instructions.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>
Alyssa Rosenzweig [Fri, 20 May 2022 16:31:12 +0000 (12:31 -0400)]
pan/va: Add flow control merging pass
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>
Alyssa Rosenzweig [Tue, 31 May 2022 19:12:13 +0000 (15:12 -0400)]
pan/va: Terminate helper threads
On Bifrost, to terminate helper threads we set the td bit on the clause. On
Valhall, we need to use the .discard flow control. Extend the flow control NOP
insertion to insert NOP.discard where necessary to terminate helper threads.
This should reduce wasted work in fragment shaders.
This requires fairly involved data flow analysis, but the handling here should
be optimal.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>
Alyssa Rosenzweig [Thu, 19 May 2022 23:08:23 +0000 (19:08 -0400)]
pan/va: Do scoreboard analysis
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>
Alyssa Rosenzweig [Thu, 19 May 2022 20:57:31 +0000 (16:57 -0400)]
pan/va: Add pass to insert flow control
To set flow control modifiers correctly and efficiently, we need a pass that
runs after register allocation and scheduling, but before packing. Add such a
pass.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>
Alyssa Rosenzweig [Wed, 1 Jun 2022 15:37:48 +0000 (11:37 -0400)]
pan/bi: Print flow control on instructions
This helps debug the flow control lowering passes on Valhall.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>
Alyssa Rosenzweig [Fri, 20 May 2022 13:31:29 +0000 (09:31 -0400)]
pan/bi: Export helper termination analysis
The current helper termination analysis code is hardwired for clauses, so it
won't work for Valhall. However, the bulk of it is dataflow analysis which is
portable between Bifrost and Valhall. Export the interesting bits so we can
reuse them on Valhall.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>
Alyssa Rosenzweig [Fri, 20 May 2022 15:10:11 +0000 (11:10 -0400)]
pan/bi: Export bi_block_add_successor
For use in unit tests that need to create blocks.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>
Alyssa Rosenzweig [Fri, 20 May 2022 15:09:43 +0000 (11:09 -0400)]
pan/bi: Extract bit_block helper
Convenience for unit tests which need to create multiple blocks, to test global
passes.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>
Alyssa Rosenzweig [Thu, 19 May 2022 20:58:51 +0000 (16:58 -0400)]
pan/bi: Add a trivial ctx->inputs for unit tests
So we can unit test the flow control insertion which needs to gate some
behaviour on not being in a blend shader.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>
Alyssa Rosenzweig [Thu, 19 May 2022 20:11:24 +0000 (16:11 -0400)]
pan/bi: Add ASSERT_SHADER_EQUAL macro
Useful for whole-program unit tests.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>
Alyssa Rosenzweig [Fri, 20 May 2022 19:46:54 +0000 (15:46 -0400)]
pan/bi: Preserve flow control for non-psiz variant
Otherwise we will get INSTR_INVALID_ENC faults when deleting the final STORE.end
instruction, after we rework our flow control code.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>
Alyssa Rosenzweig [Wed, 25 May 2022 13:38:48 +0000 (09:38 -0400)]
pan/bi: Add slot to bi_instr
For better handling of message-passing instructions.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>
Alyssa Rosenzweig [Fri, 27 May 2022 16:02:37 +0000 (12:02 -0400)]
pan/bi: Extend bi_scoreboard_state for finer tracking
We need to insert dependencies for varyings and memory access. Currently, the
Bifrost scoreboarding pass just treats these as barriers, but this is too heavy
handed. Extend the scoreboard data structure so we can do better.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16804>
Connor Abbott [Wed, 1 Jun 2022 03:56:06 +0000 (05:56 +0200)]
tu: Implement VK_EXT_image_2d_view_of_3d
This is already allowed by the gallium driver, which uses the same code
for image layout and image views, so everything Just Works and the tests
pass. radv doesn't enable the sampler feature, but I don't see any
reason it wouldn't work and the tests pass.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16806>
Marcin Ślusarz [Wed, 1 Jun 2022 13:48:45 +0000 (15:48 +0200)]
anv: mask out not applicable state flags when setting up mesh pipeline
Fixes tests matching:
dEQP-VK.pipeline.extended_dynamic_state.cmd_buffer_start.*unused_ms
These tests bind mesh pipeline, immediately after that bind non-mesh
pipeline and expect that binding mesh pipeline was a no-op.
v2: do it in one place & add comment (Lionel)
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16811>
Martin Roukala (né Peres) [Tue, 31 May 2022 06:19:56 +0000 (09:19 +0300)]
radv/ci: allow polaris10 to retry more times
The Polaris10 in CI has been getting insta-hangs when starting dEQP.
Let's give it 5 attempts to get its act together, as it won't affect
the run time dramatically (max 5 minutes), but will provide more
reliable results for developers.
Tracking of hangs (and many other issues) is done through scrapping the
execution logs, processing them to find these issues, then pushing the
data to influxdb. This allows us to plot the failure rate over time,
and see if the situation is getting better or worse.
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16793>
Daniel Schürmann [Tue, 6 Jul 2021 17:08:04 +0000 (19:08 +0200)]
nir: introduce new nir_alu_alu_width() with nir_vectorize_cb callback
This function allows to only scalarize instructions down to a desired
vectorization width. nir_lower_alu_to_scalar() was changed to use the
new function with a width of 1.
Swizzles outside vectorization width are considered and reduce
the target width.
This prevents ending up with code like
vec2 16 ssa_2 = iadd ssa_0.xz, ssa_1.xz
which requires to emit shuffle code in backends
and usually is not beneficial.
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13080>
Daniel Schürmann [Fri, 18 Dec 2020 18:05:47 +0000 (19:05 +0100)]
nir/opt_vectorize: add callback for max vectorization width
The callback allows to request different vectorization factors
per instruction depending on e.g. bitsize or opcode.
This patch also removes using the vectorize_vec2_16bit option
from nir_opt_vectorize().
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13080>
Emma Anholt [Tue, 10 May 2022 18:32:40 +0000 (11:32 -0700)]
panfrost: always print the bad ALU op if we're failing to translate.
CI failure could have told me what needed fixing, but no...
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16437>
Emma Anholt [Tue, 10 May 2022 17:31:07 +0000 (10:31 -0700)]
glsl,nir: Move i/umulExtended lowering to NIR.
NIR already has the necessary lowering, and the GLSL lowering violates
GLSL IR validation rules. Once quadop lowering was turned off, the IR
validation at the end of the compile path on DEBUG builds caught the
problem.
In order to move the lowering to NIR, though, we need to make sure that
drivers supporting these functions actually have the lowering flag set.
xfails added for t860, where apparently this tickles a variety of existing
64-bit bugs in the backend.
Fixes: #6461
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16437>
Emma Anholt [Tue, 10 May 2022 19:13:17 +0000 (12:13 -0700)]
mesa/st: Only scalarize for doubles lowering if we're lowering doubles.
lower_int64 doesn't need it, and the scalarizing ended up tickling some
bug in virgl once I started using lower_int64.
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16437>
Sagar Ghuge [Thu, 4 Nov 2021 01:20:58 +0000 (18:20 -0700)]
anv: Disable storage image compression for possible atomic ops
It looks like atomics are slow on compressed surfaces so when enabling
compression for storage images that can be possibly used for atomic
operation hinders performance. Lets just disable compression in this
scenario.
v2: Reword comment (Ken)
Allow mutable with 16/32/64 bits (Ken)
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14712>
Kenneth Graunke [Tue, 13 Oct 2020 20:58:20 +0000 (13:58 -0700)]
isl: Add an isl_format_supports_typed_atomics() helper.
v2: Add a fields in isl_format with per gen support (Lionel)
v3: Fixup R32_FLOAT from 80 to 90
Fixup R32_[SU]INT from 80 to 70 (Ken)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14712>
Daniel Schürmann [Wed, 25 May 2022 14:12:19 +0000 (16:12 +0200)]
aco: fix spilling of phis without temp operands
These were spilled unconditionally.
Cc: mesa-stable
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16708>
Erik Faye-Lund [Tue, 31 May 2022 05:20:55 +0000 (07:20 +0200)]
editorconfig: remove pl-rule
Fixes:
721b880e4cf ("script: drop get_reviewer.pl")
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16786>
Erik Faye-Lund [Tue, 31 May 2022 05:19:27 +0000 (07:19 +0200)]
editorconfig: remove m4-rule
Fixes:
95aefc94a94 ("Delete autotools")
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16786>
Erik Faye-Lund [Tue, 31 May 2022 05:17:20 +0000 (07:17 +0200)]
editorconfig: remove html-rule
Fixes:
44a4e34d52e ("docs: remove doxygen support")
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16786>
Erik Faye-Lund [Tue, 31 May 2022 05:15:37 +0000 (07:15 +0200)]
editorconfig: remove scons-ism
Fixes:
6e6cd7d93cc ("scons: Remove.")
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16786>
Erik Faye-Lund [Thu, 19 May 2022 12:47:31 +0000 (14:47 +0200)]
dzn: add debug option to redirect stdout/stderr
For applications that doesn't have a terminal, it's useful to get output
like nir_log etc output somewhere.
This outputs these to stderr.txt and stdout.txt in the current user's
home directory, typically in C:\Users\my-user\.
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16640>
Erik Faye-Lund [Thu, 19 May 2022 12:06:42 +0000 (14:06 +0200)]
dzn: add a debug-flag to wait for the debugger
It's geneunely useful to wait for the debugger to attach in some cases.
So let's add a debug-flag and staill untik the debugger has attached.
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16640>
Erik Faye-Lund [Tue, 31 May 2022 07:28:21 +0000 (09:28 +0200)]
tests/graw: rename shaders from .sh to .txt
The vertex and fragment shaders are named foo.sh, while the geometry
shaders are named foo.txt. Since .sh can easily be confused with shell
scripts, let's rename the vertex and fragment shaders to .txt to match
the geometry shaders.
These tests aren't hooked up to run automatically, so there's no need to
update references to the file names.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16791>
Samuel Pitoiset [Mon, 30 May 2022 14:14:20 +0000 (16:14 +0200)]
radv: reduce radv_discard_rectangle_info::count to 8-bit
DiscardRectangleCount must be less than or equal to
maxDiscardRectangles which is limited to 4.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16778>
Samuel Pitoiset [Mon, 30 May 2022 14:12:39 +0000 (16:12 +0200)]
radv: reduce radv_rasterization_info::polygon_mode to 8-bit
It's large enough.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16778>
Samuel Pitoiset [Mon, 30 May 2022 14:10:08 +0000 (16:10 +0200)]
radv: reduce radv_input_assembly_info::primitive_topology to 8-bit
It's large enough.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16778>
Samuel Pitoiset [Mon, 30 May 2022 14:06:42 +0000 (16:06 +0200)]
radv: reduce radv_tessellation_info::patch_control_points to 8-bit
The value must be less than or equal to maxTessellationPatchSize which
is limited to 32 with RADV.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16778>
Samuel Pitoiset [Mon, 30 May 2022 20:23:01 +0000 (22:23 +0200)]
radv: ignore DYNAMIC_STENCIL_OP if stencil test isn't enabled
Like compare/write masks and reference.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16783>
Iago Toral Quiroga [Tue, 31 May 2022 09:16:35 +0000 (11:16 +0200)]
v3dv: use the global RCL EZ disable if we don't have any EZ draws in the job
Until now we would only disable EZ globally if we had a depth or stencil
load operation or if we had no draw calls at all, but even if we have draw
calls if all of them disable EZ we should also us the global disable.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16794>
Iago Toral Quiroga [Mon, 30 May 2022 09:28:50 +0000 (11:28 +0200)]
v3dv: don't be too aggressive disabling early Z
When we have a draw call that is incompatible with EZ we should only
disable EZ for the remaining of the job in the case that both of the
following conditions are met:
1. The cause for the incompatibility is an incompatible depth test
direction.
2. The pipeline does Z writes.
Otherwise it is enough to disable EZ temporarily only for draw calls
with the incompatible pipeline.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16794>
Martin Roukala (né Peres) [Fri, 13 May 2022 09:51:07 +0000 (12:51 +0300)]
radv/ci: update the list of flakes
This commit has been created by aggregating all the flakes found in the
last 2 weeks, excluding the ones seen once.
v2 (Martin Roukala):
- stop trying to hardcode all the flakes, use a wildcard
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16777>
Lionel Landwerlin [Mon, 30 May 2022 10:53:34 +0000 (13:53 +0300)]
nir/divergence: handle load_ray_num_dss_rt_stacks_intel
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16797>
Lionel Landwerlin [Mon, 2 May 2022 13:32:07 +0000 (16:32 +0300)]
nir/divergence: handle load_scratch_base_ptr
v2: divergent (Jason)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16797>
Vinson Lee [Wed, 25 May 2022 23:49:31 +0000 (16:49 -0700)]
d3d12: Remove unnecessary NULL check.
Fix defect reported by Coverity Scan.
Dereference before null check (REVERSE_INULL)
check_after_deref: Null-checking pD3D12VideoBuffer suggests that it may
be null, but it has already been dereferenced on all paths leading to
the check.
Fixes:
d8206f62865 ("d3d12: Add video decode implementation of pipe_video_codec")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16714>
Connor Abbott [Tue, 3 May 2022 01:37:47 +0000 (03:37 +0200)]
tu: Expose VK_KHR_synchronization2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16374>
Connor Abbott [Tue, 5 Apr 2022 15:25:42 +0000 (17:25 +0200)]
tu: Convert to sync2 entrypoints
Use the common Vulkan fallbacks to implement the now-deprecated original
entrypoints.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16374>
Timothy Arceri [Tue, 31 May 2022 03:36:34 +0000 (13:36 +1000)]
ci: uprev piglit 2022-05-31
Also document additional piglit failures and passes.
Multiple changes, mostly notable:
- few new tests
- fixed test for upcoming mesa MR
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16785>
Mike Blumenkrantz [Fri, 13 May 2022 19:29:24 +0000 (15:29 -0400)]
st/texture: allow compute blits for (some) non-finalized textures
this yields sizable perf improvements in some cases
KHR-GL46.copy_image.functional timing (zink+anv-icl):
before
MESA_LOADER_DRIVER_OVERRIDE=zink ./glcts -n 74.77s user 76.44s system 33% cpu 7:32.38 total
after
MESA_LOADER_DRIVER_OVERRIDE=zink ./glcts -n 69.95s user 68.84s system 33% cpu 6:51.54 total
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16545>
Mike Blumenkrantz [Fri, 13 May 2022 19:30:11 +0000 (15:30 -0400)]
st/texture: use base teximage for compute blits
this matches behavior of st_texture_image_map
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16545>
Mike Blumenkrantz [Mon, 30 May 2022 13:13:17 +0000 (09:13 -0400)]
zink: make swapchain kill message more descriptive
cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16776>
Mike Blumenkrantz [Fri, 27 May 2022 19:57:25 +0000 (15:57 -0400)]
zink: add a #define for descriptor compaction
make those 2s a little less random
fixes #6556
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16755>
Mike Blumenkrantz [Fri, 27 May 2022 19:37:20 +0000 (15:37 -0400)]
zink: flag all cached descriptors as needing update on program change
programs have different usages of descriptors, so forcing a recalc on program
change ensures that the right hash values are always set, especially for compact
sets where there's more descriptors going into each hash value
this can (ideally) be optimized later to check for matching interfaces between old
program and new program to avoid recalc if both programs have identical descriptor
usage for a given set
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16755>
Mike Blumenkrantz [Fri, 27 May 2022 19:02:38 +0000 (15:02 -0400)]
zink: fix change flagging for compact descriptor cache
using pool existence alone is broken since the pools are compacted,
so instead flag based on whether usage exists
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16755>
Mike Blumenkrantz [Fri, 27 May 2022 19:01:52 +0000 (15:01 -0400)]
zink: store the real (non-compact) binding usage for programs
this is useful for quickly determining whether a program has a certain
type of descriptor usage
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16755>
Mike Blumenkrantz [Fri, 27 May 2022 18:46:30 +0000 (14:46 -0400)]
zink: drop requirement for 6 descriptorsets to use bindless
compact mode takes care of this
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16755>
Mike Blumenkrantz [Thu, 26 May 2022 13:17:44 +0000 (09:17 -0400)]
zink: only infer modifiers if winsys handle has a stride
if no stride is passed, the image creation will fail, so avoid this case
fixes:
spec@ext_external_objects@vk-image-overwrite
Fixes:
d79c716331f ("zink: create images with modifiers any time there is an import handle")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16722>
Jason Ekstrand [Fri, 27 May 2022 18:36:50 +0000 (13:36 -0500)]
st,nir: Use nir_shader::xfb_info in nir_lower_io_passes
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16750>
Jason Ekstrand [Fri, 27 May 2022 18:55:18 +0000 (13:55 -0500)]
glsl/nir: Stash the xfb_info in the nir_shader when linking XFB
This pass is used for shaders coming in from SPIR-V.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16750>
Jason Ekstrand [Fri, 27 May 2022 18:53:07 +0000 (13:53 -0500)]
glsl/nir: Stop leaking varyings_info
Fixes:
34b3b92bbee1 ("nir/xfb: move varyings info out of nir_xfb_info")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16750>
Jason Ekstrand [Fri, 27 May 2022 17:52:25 +0000 (12:52 -0500)]
glsl/nir: Populate nir_shader::xfb_info after linking varyings
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16750>
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