ir3: Reduce the maximum allowed imm offset for shared var load/store

STL/LDL have 13 bits to store imm offset. However the most significant
bit in the offset is a sign bit, so the positive offset is limited by
12 bits.

nir_opt_offsets only has the upper limit and doesn't deal with
negative offsets, so shared_max should be changed to `(1 << 12) - 1`.

The issue was found in "Monster Hunter: World".

Fixes: 0b2da9d795610df15346a594384c39a096be338f
("ir3: Limit the maximum imm offset in nir_opt_offset for shared vars")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20100>
(cherry picked from commit 8f0177b3345f8bcc3673b8a2a7c36ea36cbaa029)

ci: Rebalance radv/grunt testing

We've recently rebalanced our lab devices to get a fewer number of
grunts. Switch to scheduling only on the newer shinier ones, running
fewer tests. We'll evaluate the runtime, and if they're quick enough
then we can increase the amount of testing we do.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20081>
(cherry picked from commit 921cfcf4c4f5cb6f82ef978587e0462218093542)

v3dv: fix job serialization for single sync path

The idea in the single sync path is that we serialize any job that
needs to wait, however, our ANY queue syncobj only tracks the last job
submitted to any hardware queue, so in practice when we wait on this
we are only serializing against the queue to which we have submitted
the last job, which is not correct.

Fix that by accumulating the last job sync into the ANY queue synbcobj
to ensure that waiting on this syncobj effectively waits on all
hardware queues.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20078>
(cherry picked from commit 4276ec9f2af33da270ca9cf6a6a9a62b2a4d060a)

v3dv: make single-sync paths more explicit

Instead of having functions that return early in multi-sync mode
let's only call them when we are in single-sync mode. I think this
makes the code more explicit.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20078>
(cherry picked from commit 95b9293eeb02f3b43fb7de5afc6f7c89ffffe92f)

intel/compiler: user payload starts after TUE header & its padding

All data written by the user are offset by TUE header size.
Without this patch we copy the correct amount of user data, but both
"from" and "to" offsets are wrong.

Fixes: 37e78803d7b ("intel/compiler: use nir_lower_task_shader pass")

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19409>
(cherry picked from commit db0e6f9a07b49a95d99c2b2c25fd8a008466c4e8)

nir/lower_task_shader: allow offsetting of the start of payload

We need this, because on Intel task payload starts with private header,
followed by user-accessible data.

Fixes: 37e78803d7b ("intel/compiler: use nir_lower_task_shader pass")

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19409>
(cherry picked from commit f6adfd6278301aa772d3d44fc64ade21c9860574)

intel/compiler: adjust [store|load]_task_payload.base too

Base also needs to be converted from bytes to words.

Fixes: c36ae42e4cc ("intel/compiler: Use nir_var_mem_task_payload")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19409>
(cherry picked from commit 7aaafaa8ae26ee1086a51089c12e4fa9e9645c2e)

freedreno/fdl: Set sRGB bit for storage images

This probably wasn't noticed earlier because tests using sRGB storage
images didn't exist, and we didn't know whether this works, but this
fixes dEQP-VK.image.store.without_format.2d.*_srgb which also proves
that the bit works.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20060>
(cherry picked from commit ccef6d1f5fdae95ee8aa5a68e83662e02645b64a)

radv: Handle nodes with 2 invalid children in internal node converter.

Fixes: 682dc5c28e4 ("radv: Add conversion shader for internal nodes")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19891>
(cherry picked from commit f531f671ef64acc8ea56a473c05aeb5ea9f4c1f0)

aco: Use wave size specific opcode for s_or in cube map coord code.

Cc: mesa-stable
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20041>
(cherry picked from commit a3beb82cf6bcf84425431ec17c046a80b2b7fc79)

pan/mdg: Emulate 8-bit with the 16-bit pipe

We don't care to support i8vec16, we just need a bit of 8-bit support to
implement format packing/unpacking in blend shaders. We're already doing
this by using the 16-bit pipe, we just need to commit to it all the way
-- reporting the correct sizes in max_bitsize_for_alu so the mask
packing logic works as intended -- and dropping the imov-specific hack
that was introduced to workaround a similar class of bugs.

With the previous patch, fixes:

   dEQP-GLES31.functional.draw_buffers_indexed.random.max_required_draw_buffers.1

Fixes: 39e4b7279dc ("pan/midg: Fix swizzling on 8-bit sources")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19763>
(cherry picked from commit 976405907e35629b42501a9f86b067986599cb28)

.pick_status.json: Update to 264a0cabd1dd2a619f24e34f21f767c6bf36fe76

iris: move bindless surface state heap inside the surface state heap

We're about to make scratch surface states part of the surface state
heap. Because those are required to be in the low 26bits parts surface
state heap (we're limited in bits handed in the CFE_STATE, 3DSTATE_VS,
etc... instructions), this change splits the 32bit surface state heap
as follow:

   - 8Mb of surface states for scratch
   - 1Gb - 8Mb of binding tables
   - 3Gb of surface states

That way all of the surfaces are located within a 4Gb region visible
from STATE_BASE_ADDRESS::SurfaceStateBaseAddress

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19727>
(cherry picked from commit daab161535747cf5aef443e4cee46c5415662848)

docs: add release notes for 22.3.0

VERSION: bump for 22.3.0

commit_in_branch.py: add support for checking staging branches

Or any branch that contains a `/` slash.

Cc: mesa-stable
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19988>
(cherry picked from commit 707015891fc65dcf5b0b2601aa78f1fb33a01f39)

ir3: Don't save/restore disasm string pointer

It's not in the key, so it randomly may or may not be present, and if it
is present then we don't actually save/restore the contents, so we will
save/restore random pointer values from the last run. Turnip already
disables searching the shader cache when assembly is requested, but
still wrote the final ir3_shader_variant which resulted in trying to
save random stale pointers when saving off the executable if a
subsequent compile hit that cache entry.

This fixes flakes in
dEQP-VK.pipeline.pipeline_library.shader_module_identifier.pipeline_from_id.*
for me.

Fixes: 56909868cd1 ("turnip: implement VK_KHR_pipeline_executable_properties")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20056>
(cherry picked from commit 8ba2d612d51497b274ff9c4213e1c373b9bb1ca5)

tu: Fix binding NULL descriptor sets

This fixes the new test
dEQP-VK.pipeline.pipeline_library.graphics_library.misc.other.null_descriptor_set_in_monolithic_pipeline.

Fixes: e9f5de11d40 ("tu: Initial implementation of VK_EXT_graphics_pipeline_library")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20057>
(cherry picked from commit 515c9a2e0754bd8a12b0d0b708ce4b0dba29102e)

radv: disable VRS entirely on GFX11

Based on registers, VRS changed a lot and it's unclear how to program
it. This disable VK_KHR_fragment_shading_rate, VRS flat shading and
RADV_FORCE_VRS.

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20054>
(cherry picked from commit 80072df8246f580a4c7d31fb82a9f746c3e1ba8d)

radv: do not enable NGG culling on GFX11

RadeonSI disables it as well. It's really unclear if it will help or
not (eg. NGG culling never helped on GFX10).

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20054>
(cherry picked from commit 5d552b4f6cbfcb4bf14e3a0bdce01cc00eb61073)

radv: do not enable DCC for MSAA images without FMASK

I don't know how this is supposed to work, especially for fast clears
because CMASK should be cleared to 0xC but FMASK implies CMASK.
This fixes a bunch of MSAA test failures on GFX10.3 with
RADV_DEBUG=nofmask.

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20054>
(cherry picked from commit 84a7138d3cfca05fbd623707525b9d4479a27e94)

radv: set INTERPOLATE_COMP_Z to 0 on GFX11

Ported from RadeonSI to fix a EQAA bug.

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20054>
(cherry picked from commit 9b637aa9a17fd14c63b821629fb30d5fc4875df0)

radv: set missing SPI_SHADER_PGM_xxx registers on GFX11

Found by inspection.

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20054>
(cherry picked from commit 62715a6d039a7f2499ceca78476ebd42a5a03068)

radv: introduce RADV_DEBUG=nofmask

To disable MSAA compression on MSAA images. This will also allow us to
emulate GFX11 (FMASK has been removed) and to experiment 32 byte
descriptor sizes.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19613>
(cherry picked from commit cf7b96a83f66f150bca5df2f510ed6951497d9c6)

panfrost/blend: Fix invalid const values leading to NIR validation errors

Using a designated initializer like this leaves padding bits, which form
part of the aliasing u64/f64 member of the union, uninitialised, but a
nir_const_value must always have the unused bits zeroed out. Thus, use
the nir_const_value_for_float helper instead like everywhere else which
will do a memset 0 for us first.

Without this, using the pan_blend shader in a build with validation
enabled fails with:

  NIR validation failed after nir_lower_vars_to_ssa
  ...
            vec4 32 ssa_58 = load_const (0x3f7cfcfd /* 0.988235 */, 0x3f7cfcfd /* 0.988235 */, 0x3f7cfcfd /* 0.988235 */, 0x3f800000 /* 1.000000 */)
  error: memcmp(val, &cmp_val, sizeof(cmp_val)) == 0 (../src/compiler/nir/nir_validate.c:976)

Fixes: 1378c67bcf9e ("panfrost/blend: Inline blend constants")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20071>
(cherry picked from commit 750325730bb84981f68d78b205fb0cec1e165100)

venus: fix android wsi with global fencing disabled

Fixes: b21e4a7990c ("venus: put android wsi on the sub-optimal path")

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20049>
(cherry picked from commit 6148ccef6372e634ea4875b75419bfdc64e6b219)

radeonsi/vcn: set current pic index correctly

video corruption observed while running decode test for av1
content in chromeos.

solution is when target buffer is found in render pic list and when
target codec is null, set curr_pic_indx as index to the
pic in render pic list.

Cc: mesa-stable
Signed-off-by: Sajeesh Sidharthan <sajeesh.sidharthan@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20000>
(cherry picked from commit 8b99e96dc8b44a747824b9d227a72e68012ec520)

nir/lower_int64: fix shift lowering

Starting with !19748 lowered 64 bit shifts were showing wrong results for
shifts with insignificant bits set.

nir shifts are defined to only look at the least significant bits. The
lowering has take this into account.

So there are two things going on:
1. the `ieq` and `uge` further down depend on `y` being masked.
2. the calculation of `reverse_count` actually depends on a masked `y` as
   well, due to the `(iabs (iadd y -32))` giving a different result for
   shifts > 31;

Fixes: 41f3e9e5f5d ("nir: Implement lowering of 64-bit shift operations")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19995>
(cherry picked from commit 5398dd04bf62db100639d96c84a8c41041f4ad01)

tu: Use right enum for compute active_shader_stages

This is VkShaderStageFlags, not VkPipelineStageFlags. Fixes preloading
descriptors for compute dispatches.

Fixes: d862a2ebcbf ("turnip: Only emit descriptor loads for active stages in the pipeline.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20059>
(cherry picked from commit 0a0a04bdaa6faf1dd3e937f7087ae1c4f240c916)

meson: Enable system_has_kms_drm for android

This allows to build libgbm when  system = 'android'  is set in
the cross_file.

Cc: "22.3" "22.2" mesa-stable
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Acked-by: Mauro Rossi <issor.oruam@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20033>
(cherry picked from commit 09ac29cca9bf7978911f81bcfce12ce71c260a97)

d3d12: fix max-array-layers

We used to need this, because we incorrectly multiplied the cube array
sizes by 6. Now that this has been fixed, we can actually support the
OpenGL 4.1 limit for this.

Fixes: 7118b2136e9 ("d3d12: Don't multiply cube array sizes by 6")
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19780>
(cherry picked from commit acc0039aecec661e55e2dd90554a1d08a39d677c)

AOSP: Add intel_hasvk vulkan library suffix

Required to correctly install vulkan.intel_hasvk.so module
after commit 50013ca9 ("intel: add a hasvk vulkan driver")

In order to set property ro.hardware.vulkan as 'intel_hasvk' for the correct iGPU parts at init stage,
i915 'graphics version' can only be detected by means of /sys/kernel/debug/dri/0/i915_capabilities
and debugfs needs to be mounted at early-init stage

https://review.lineageos.org/c/LineageOS/android_device_lge_g3-common/+/19875

Cc: "22.3" mesa-stable
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Mauro Rossi <issor.oruam@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20048>
(cherry picked from commit ea10b0fc7add2ad9dd486e69b5b5e7aca3c422f7)

r600/sfn: always use four slots for Cayman trans ops

This is a partial revert of
  ed6204eb0 (r600/sfn: only use 3 channels on Cayman for trans ops)

The scheduler and/or optimizer passes generate faulty code when
we use only three slots as decribed in the spec. So for now disable
this optimization.

Fixes: ed6204eb0 (r600/sfn: only use 3 channels on Cayman for trans ops)
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7774

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20034>
(cherry picked from commit 28c7684eb9a898089844376193d8332b5f58f3d8)

radv/rt: Check space before emitting descriptors

Found by inspection.

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20020>
(cherry picked from commit c5d91ab254e59bedfc0faf71cfc46531d9be4ea8)

radv/ray_queries: Fix AABB handling

AABB intersections always have to be committed manually.
-> We don't have to copy opaque ones to closest.

It's also invalid to query t for candidate AABBs.

Totals from 7 (14.29% of 49) affected shaders:
CodeSize: 171008 -> 169672 (-0.78%)
Instrs: 32499 -> 32250 (-0.77%); split: -0.78%, +0.01%
Latency: 418859 -> 414759 (-0.98%); split: -0.98%, +0.00%
InvThroughput: 89182 -> 88251 (-1.04%); split: -1.05%, +0.00%
VClause: 602 -> 599 (-0.50%)
SClause: 837 -> 835 (-0.24%)
Copies: 4804 -> 4802 (-0.04%); split: -0.35%, +0.31%
Branches: 1593 -> 1585 (-0.50%)
PreSGPRs: 567 -> 566 (-0.18%)

Fixes: 3f72061 ("radv/rq: Use the common traversal helper")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19698>
(cherry picked from commit 0966fb2c10025398fc048361a9898ba2d56b4f9b)

radv: reserve space for the scissor in vkCmdBeginRendering.

Fixes: c7d0d328d56 ("radv: Set the window scissor to the render area, not framebuffer")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20014>
(cherry picked from commit a97a6d0f0e78c637f7aa4d907e608043efb51528)

etnaviv: fix wrong surface TS clear size

Clearing ts_size - ts_offset bytes in a level means we are clearing the
TS region of all layers in the level starting from the surface layer, so
clearing one surface might corrupt all other layers of a resource level.
Use the correct size to clear only the requested TS region.

Cc: mesa-stable
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19814>
(cherry picked from commit b6fa3cdb0e693f49cdc278ed5923bb9dc048ccbb)

etnaviv: blt: use correct TS offset in clear operations

Using the ts_offset from the level means we are always clearing the
TS region of layer 0 of the level. Use the correct offset which takes
into account the layer offset.

Cc: mesa-stable
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19814>
(cherry picked from commit d9e2a7d6adace0a794c7147f0a5bab43277e5fa6)

Revert "glx/dri: Fix DRI drawable release at MakeCurrent time"

This reverts commit 31b04e420b0eb080084c6323066ea0b83929d59e which
is also breaking KDE in some ways.

Fixes: #7674
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19972>
(cherry picked from commit ea3f73ba85be46dcb9712b43fef52b09cfae643b)

Revert "glx: Fix drawable refcounting for naked Windows"

This reverts commit 768238fdc06eed3dce36da3baf811cb70db42b5c which
is not only leading to memory leaks, but also reportedly breaks KDE
pretty badly.

Fixes: #7674, #7435
Acked-by: Michel Dänzer <mdaenzer@redhat.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19972>
(cherry picked from commit 0cee008fee1dc0365cfb767ff7acf03f2127a03b)

etnaviv: rs: fix blits with insufficient alignment for dual pipe operation

Up-aligning the blit height does not always work, as some blit targets
have a smaller padded height. Fall back to single pipe operation if
increasing the height alignment fails. Still try to do it opportunistically
as it improves performance when resolving MSAA targets.

Fixes: 0ff96aaef3b1 ("etnaviv: rs: fix MSAA alignment adjustment")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19991>
(cherry picked from commit 797454edfcc4d2a6d0c21db451e9a0ea6e0a8023)

etnaviv: always use RS align when GPU has TEXTURE_HALIGN feature

Due to a logic bug we didn't always up-align the resource when the GPU
has the TEXTURE_HALIGN feature, which broke the RS blit when we need
to blit into a sampler shadow from a multi-tiled render target.

Fixes: 735718ed33b2 ("etnaviv: move etna_layout_multiple into etnaviv_resource.c")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19991>
(cherry picked from commit fd06b313b010adb6c6e9a7c30ab55163397f4d47)

driconf/intel: Use fake vendor to WA bad detection in Source engine games

Source engine uses flawed device detection in Linux native OpenGL backend,
which causes it to use bad configurations for Intel devices and thus
not always render correctly. Workaround this by using vendor string that
does not include "Intel" in it.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7725
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19828>
(cherry picked from commit 478ffe712765b5746482d37df32fff36e12192ef)

vulkan: Remove asserts that weren't valid for RADV ETC2 emulation.

Wasn't caught when radv was modified to use these helpers ...

Tried to move the aspects assert so it still checks application inputs.

Fixes: d9048e31a0d ("radv: Use vk_image_view as the base for radv_image_view")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19914>
(cherry picked from commit 13d755441c7b648e4f6671d833a6d58ada9ae32d)

radv: Fix sampler types in ETC2 decode.

Otherwise we'd have a type mismatch vs texture fetches, which
is asserted upon these days.

Fixes: 1153db23f58 ("radv: Add ETC2 decode shader.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19914>
(cherry picked from commit eab61863c0bd6b08bfc7c28d96cd99f49856e449)

radv: Use correct init order for ETC2 image views

Fixes: d9048e31a0d ("radv: Use vk_image_view as the base for radv_image_view")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19914>
(cherry picked from commit c6ec4925c0688cef557beb65c280b28ef3185132)

radv: make sure to mark DCC as compressed on GFX11

The bit has moved to FDCC_ENABLE on GFX11.
Found by inspection.

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20005>
(cherry picked from commit ccac91db7bbf3b428ad4138e0982c54636b4b96c)

ac/nir: mask shift operands

NIR shifts are defined to truncate the shift amount to the number of bits
needed to represent the bit-size of the value shifted. LLVM treats large
shifts as poison. This fix achieves NIR semantics for shifts.

As an example, a|(b << 32), where "a" is 32bits, should produce a|b
according to NIR (because 32&31 == 0).

This caused LLVM to incorrectly optimize "(a >> c) | (b << (32 - c))" to a
u2u32(pack_64_2x32(a, b) >> c) (v_alignbit_b32), when the original NIR
should have returned "a | b" if c==0.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19966>
(cherry picked from commit 064336d35977abd0d5b6ed37784c6cc42cf4f66f)

virgl: Fix injection of double from const mov instruction

We only copy two components, we have to use the complete original source,
and we should rewrite the new source from scratch to avoid incorrect
dimension and indirect handling.

Fixes: 036d7172c (virgl: Move double operands to a temp to avoid double-swizzling bugs)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19975>
(cherry picked from commit d5217b024eac4e725a671b1c3992ab282c9c50f1)

.pick_status.json: Mark 470fbb35efe1935242b346427ec0fa22b40fff2b as denominated

radv: re-emit dynamic depth clamp enable if depth clip enable changed

The depth clamp mode depends on depth clip enable/disable.

Fixes: e48c0fbd8f7 ("radv: add support for dynamic depth clamp enable")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19843>
(cherry picked from commit de4de09a56c421ec1194dea016c3b9ef80abbb83)

mesa: treat unsupported queries as dummies

It's legal in OpenGL to start a query even if the result will have zero
valid bits. It's not enough to just report zero bits, We need to also
prevent calling down into the driver with these invalid queries.

Because ARB_ES3_compatibility adds ANY_SAMPLES_PASSED and
ANY_SAMPLES_PASSED_CONSERVATIVE to the set of queries that support zero
bits, we also need to check for the corresponding indices.

Fixes: 0186e9e1c51 ("mesa: always support occlusion queries")
Reviewed-by: Soroush Kashani <soroush.kashani@imgtec.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19750>
(cherry picked from commit 1b1e8873fe90e878f014140b3b6bd1e5dbfb5a4c)

st/vdpau: fix interop with GL

Fixes: e00bb6cb98b - mesa/st: use tracked samplerview swizzle values
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7751

Tested-By: Veerabadhran.Gopalakrishnan@amd.com
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19961>
(cherry picked from commit c70eec86efd9ca2faa1f66fcaf42cc37360dcb5e)

panfrost: Revert "Require 64-byte alignment on imports"

This reverts commit 811f8a19469722bea32f3c539b8cf0939fe3b057. As Alpine put it
-- this is causing more problems than it's fixing. Hotfix to revert the
offending commit until a more measured fix can be implemented.

Closes: #7731
Cc: mesa-stable
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reported-by: Jan Palus
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19993>
(cherry picked from commit 4b19725ee525f6f0b5785436680cea63a21445a1)

venus: enable VK_KHR_push_descriptor

Signed-off-by: Dawn Han <dawnhan@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18988>
(cherry picked from commit 505a5bc79fa051781878df32603a505356c389bd)

venus: implement vkCmdPushDescriptorSetWithTemplateKHR

Signed-off-by: Dawn Han <dawnhan@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18988>
(cherry picked from commit 933ca11f1a48b19fea088edfcf5177779083d7b5)

venus: extend VkPipelineLayout lifetime for batched VkCmdPushConstants()

Signed-off-by: Dawn Han <dawnhan@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18988>
(cherry picked from commit 19f2b9d0bbd71ba218962a26434507e70f6cde98)

venus: extend lifetime of push descriptor set layout

Signed-off-by: Dawn Han <dawnhan@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18988>
(cherry picked from commit 91966f2eff17cc7c95ca8a89ac40d5d211e5b407)

docs/zink: add missing required device-feature

Seems I forgot to add this to the list of required features.

Fixes: eb0195358c4 ("zink: only inspect dual-src limit if feature enabled")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19779>
(cherry picked from commit a2a0ac21e4f5a7c873e1bab05dee02a61171e378)

zink: update textureCompressionBC requirement

The mesa state-tracker can now emulate all formats indicated by this
feature-flag, so we don't require this for OpenGL 4.2 any more.

It's however a good idea to support for power-usage and performance
reasons, saving on memory bandwidth. So let's move it to the
gl46_optimal block instead.

Fixes: e4ff42684b9 ("mesa/st: enable bptc extension with fallback")
Fixes: 2ea481b2f0a ("Zink: add Zink profiles file")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19779>
(cherry picked from commit 13bccac5a7d930c809927e69ba7305330fb8a9be)

zink: fix incorrect requirements

These were in the wrong list all along.

Fixes: a466c2a7839 ("zink: check for stores and atomics features")
Fixes: 2644835f039 ("zink: add missing required feature")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19779>
(cherry picked from commit 754353c4170918f592e499a370dc90c60c271cff)

zink: remove needless requirements

We never required the uniform texel buffer bit for more than
bufferFeatures for a bunch of these formats.

Similarly, we *don't* need the uniform texel buffer bit for sampled
image access.

For the image-dimensions, the Mesa frontend doesn't validate the max 1D,
3D or Cube sizes, nor the max texture layers. So we'll expose GL 4.1
without these, even if that's not conformant.

Finally, we don't require robustImageAccess2 for OpenGL 4.3 at all. All
we need is the robustBufferAccess feature.

Fixes: 2ea481b2f0a ("Zink: add Zink profiles file")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19779>
(cherry picked from commit b60bc5299253f8e3bbab7c3e44b0f91a91e8dba3)

zink: fix json-errors in profile-file

There's some stray commas here, let's get rid of them.

Fixes: 2ea481b2f0a ("Zink: add Zink profiles file")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19779>
(cherry picked from commit b707cf24a3b4f446e45738f031598eeb6c0a5b6b)

gallivm: use valid LLVM_VERSION_MAJOR instead of LLVM_VERSION

Partial of: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7680
Fixes: 203920d4c69 ("gallivm: add atomic 32-bit float support")

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19926>
(cherry picked from commit b461921ed80abe357cb90f63db3dfc0a1390423c)

etnaviv: Hide MSAA support behind debug flag

With the current level of MSAA support we have some real world rendering
problems in Chromium/Skia (issue #7678). Convert the MSAA support to an
explicit opt-in by settings ETNA_MESA_DEBUG=msaa.

Cc: 22.3 mesa-stable
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19870>
(cherry picked from commit 4f5e59d1146a6d14f57d4f215a08a149bb8bf40c)

pan/mdg: Fix out-of-order execution

We can go up to 15 instructions out of order (performance fix) but we
can't go past a branch (bug fix).

Fixes: 30a393f4581 ("pan/mdg: Enable out-of-order execution after texture ops")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19762>
(cherry picked from commit 044428211c99be2ce362cc28e4596929958a5de6)

.pick_status.json: Update to 22be0d09a005b4b955a46b65a919cfd786d6814f

VERSION: bump for 22.3.0-rc4

vk/runtime: Fix narrowing of timeline signal and wait value to u32.

They are u64. Fixes deadlock in
dEQP-VK.wsi.xcb.present_id_wait.wait.past_no_timeout.

Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Fixes: 9bffd81f1cb7 ("vulkan: Add common implementations of vkQueueSubmit
and vkQueueWaitIdle")

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19951>
(cherry picked from commit f2e535e4fed5bdc13e11a443316a4b77cd5eb81a)

nir/divergence: add missing btd_shader_type_intel

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 6d9ae6ec1eaa ("intel: add a new intrinsic to get the shader stage from bindless shaders")
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19948>
(cherry picked from commit 99dcdf4d648f337c6421050cb5f31025f69665ae)

anv: generate correct addresses for state pool offsets

Fixes a number of CTS patterns on DG2 :

   - dEQP-VK.dynamic_rendering.primary_cmd_buff.random*
   - dEQP-VK.draw.*secondary_cmd*
   - dEQP-VK.dynamic_rendering.*secondary_cmd*
   - dEQP-VK.geometry.*secondary_cmd_buffer
   - dEQP-VK.multiview.*secondary_cmd*

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 9c1c1888d989 ("intel/fs: put scratch surface in the surface state heap")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19946>
(cherry picked from commit 9bb055ff5d7ae90764619d3f85ebba82081937e3)

blorp: support negative offsets in addresses

Similar to anv_address

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 9c1c1888d989 ("intel/fs: put scratch surface in the surface state heap")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19946>
(cherry picked from commit 20e8e1eb0658e68f44316e9ab27ddfa06096d66f)

intel/fs: improve Wa_22013689345 workaround

The initial implementation is a pretty big hammer. Implement the HW
recommendation to minimize cases in which we need a fence.

This improves by 10FPS on some of the Sascha Willems RT demos.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 6031ad4bf690 ("intel/fs: Add Wa_22013689345")
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19322>
(cherry picked from commit 945637514e6e970fcc37745f509eec11ff3b5129)

r600/sfn: allow building with clang 6 (Android 9)

static constexpr const 'value' is replaced by static function
in all type_char template specializations
to avoid the following building errors happening with clang 6

/home/utente/pie-x86_kernel/prebuilts/clang/host/linux-x86/clang-4691093/bin/ld.lld: error: undefined symbol: r600::type_char<r600::ExportInstr>::value
>>> referenced by sfn_scheduler.cpp
>>>               sfn_sfn_scheduler.cpp.o:(bool r600::BlockSheduler::collect_ready_type<r600::ExportInstr>(std::__1::list<r600::ExportInstr*, std::__1::allocator<r600::ExportInstr*> >&, std::__1::list<r600::ExportInstr*, std::__1::allocator<r600::ExportInstr*> >&)) in archive src/gallium/drivers/r600/libr600.a
...
/home/utente/pie-x86_kernel/prebuilts/clang/host/linux-x86/clang-4691093/bin/ld.lld: error: undefined symbol: r600::type_char<r600::RatInstr>::value
>>> referenced by sfn_scheduler.cpp
>>>               sfn_sfn_scheduler.cpp.o:(bool r600::BlockSheduler::collect_ready_type<r600::RatInstr>(std::__1::list<r600::RatInstr*, std::__1::allocator<r600::RatInstr*> >&, std::__1::list<r600::RatInstr*, std::__1::allocator<r600::RatInstr*> >&)) in archive src/gallium/drivers/r600/libr600.a
clang-6.0: error: linker command failed with exit code 1 (use -v to see invocation)

Cc: "22.2" "22.3" mesa-stable
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19873>
(cherry picked from commit e74d989a6935ce11d06970a3c98b474b7773c905)

aco: fix emitting DEALLOC_VGPRS in the discard block

It should be emitted right before s_endpgm.

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19931>
(cherry picked from commit ce11c064294540ed5ea09e71c477b2d481b4d3a6)

radv: fix possible hangs with NGG streamout and secondary cmdbuf

This was missing but it might hang if streamout is used only in
secondary command buffers.
Found by inspection.

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19801>
(cherry picked from commit c9f0b7b0421bcf1591e5aad2f7292c841ade6d87)

radv: fix NGG streamout when it's never enabled in runtime

If a shader has XFB outputs but the application never enables
streamout in runtime (no buffers bound and no begin/end pair), we
have to disable it in the shader by emitting buffer size as 0. It's
also still needed to remember that the cmdbuf needs GDS/GDS OA BOs,
so move this at pipeline bind time instead.

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19801>
(cherry picked from commit 3189be249d4489f7943da6c90ee521bde8624041)

radv: re-mit streamout buffers to unbind them when NGG streamout is disabled

A buffer size as 0 acts like if streamout is disabled with NGG.

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19801>
(cherry picked from commit 6a2bcce8824d1b726eb9a588c8ab2c92aaa041b3)

radv: enable NGG XFB queries only if streamout is enabled

Otherwise, it's possible to increase counters if a shader has XFB but
the application paused it.

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19801>
(cherry picked from commit 5b60949155869f15a9f62a329422bb57b168ee7f)

radv: fix computing the pervertex LDS size with NGG streamout

The NGG streamout lowering pass allocates space for all outputs which
means we have to align our computation. Otherwise, the maximum number
of vertices is incorrect and we end up by reaching the maximum allowed
LDS size. This code could be shared instead of being duplicated but
that's for later.

Fixes some transform feedback tests with Zink and
RADV_PERFTEST=ngg_streamout on GFX10.3.

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19801>
(cherry picked from commit ba81dcf9715e8422b403fa79de4d8726a71eddbb)

radv: stop overallocating LDS for VS/TES when NGG streamout is enabled

The number of shader outputs should only be considered when the
shader has XFB, otherwise we are overallocating LDS.

fossils-db (GFX1100):
Totals from 16602 (12.31% of 134913) affected shaders:
LDS: 17000448 -> 8500224 (-50.00%)

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19801>
(cherry picked from commit 499abeba605da7f7395c84b0a75c917656c19949)

etnaviv: nir: lower extract byte/word

Fixes e.g. 'Unhandled ALU op: extract_u16' seen with deqp on gc7000.

Cc: 22.3 mesa-stable
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19776>
(cherry picked from commit e244b0f8b20a136182cfbd9f4360d90882c14799)

etnaviv: Support negative float inline immediates

Closes: #7652
Fixes: 45a111c21c2 ("nir/opt_algebraic: Fuse c - a * b to FMA")
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19776>
(cherry picked from commit 7d78fe4a8691d3bdd37961f305220500729fcd92)

st/mesa: suppress async glthread flushing for GLX_EXT_texture_from_pixmap

This might fix some window system issues.

Fixes: 3da170faaec - glthread: change when glFlush flushes asynchronously

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19809>
(cherry picked from commit d871958702ebcd46213cd09b91b9b05685f9be62)

etnaviv: fix tile status interaction with write mappings

This fixes a longstanding bug in the interaction between TS and a write
mapping. The write does not update TS regardless of the way the update
is done. Update via etna_copy_resource would just set the target ts_valid
to false without actually writing back any dirty TS to the resource.
Writes via the CPU would update the resource, but keep ts_valid at true
even if the tile status may now not match the actually written tiles of
the resource anymore.

Fix this by writing back a dirty TS to the target resource if needed
before updating the level with the write data. Always invalidate TS,
even when the update is done by the CPU.

Cc: mesa-stable
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19846>
(cherry picked from commit 0fb813526e3b3be6cf8a866b084db044ccd0e103)

anv: fixup context initialization on DG2

Fixing a typo :(

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 507a86e131d6 ("anv: ensure CPS is initialized when KHR_fragment_shading_rate is disabled")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19922>
(cherry picked from commit f7d6c6e1ed9919d37ceb05cbe5ed75b377253a3a)

vulkan: Add a dummy vk_common_CmdSetColorBlendAdvancedEXT()

The entrypoint needs to exist but we don't need to do anything with it.

Fixes: 13c422e1b2ed ("anv: toggle on EXT_extended_dynamic_state3")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19817>
(cherry picked from commit 9cec1ed51d16e62950aceec161511a28ec799f21)

vulkan: Add a common implementation of CmdSetSampleLocationsEnableEXT

Fixes: 13c422e1b2ed ("anv: toggle on EXT_extended_dynamic_state3")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19817>
(cherry picked from commit 182aa9eb15e2740f08b869ea81ccb7697e83cfdf)

vulkan: Add state for extraPrimitiveOverestimationSize

Fixes: 13c422e1b2ed ("anv: toggle on EXT_extended_dynamic_state3")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19817>
(cherry picked from commit b172fd62f51bba16970c413604053a64f7eda244)

anv: ensure CPS is initialized when KHR_fragment_shading_rate is disabled

We need to set CPS_MODE_NONE when no per coarse pixel dispatch.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 231651fd89fb ("anv: implement VK_KHR_fragment_shading_rate")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19867>
(cherry picked from commit 507a86e131d648ecc85dc833f4821da6ac995cfe)

anv: fix 3d state initialization

We missed a couple of restriction leading to inconsistent 3d pipeline
state. It is mostly noticeable when doing a multiple sample dispatch
as the verify first 3d operation.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7531
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19867>
(cherry picked from commit 62f12c2dadc2c9eac34a946450b2d4c615f96f75)

nir/loop_analyze: Fix get_iteration for nir_op_fneu

Consider the loop:

    float i = 0.0;
    while (true) {
       if (i != 0.0)
          break;

       i = i + 1.0;
    }

This loop clearly executes exactly one time.

Some trickery is necessary to handle cases where the initial loop value
is very large and the increment is, by comparison, very small.  From the
fenu_once test case,

    float i = -604462909807314587353088.0;
    while (true) {
       if (i != -604462909807314587353088.0)
          break;

       i = i + 36028797018963968.0;
    }

This loop should also execute exactly once, but this is much more
challenging to calculate due to precision issues.

Going towards smaller magnitude (i.e., adding a small positive value to
a large negative value) requires a smaller delta to make a difference
than going towards a larger magnitude. For this reason,
-604462909807314587353088.0 + 36028797018963968.0 !=
-604462909807314587353088.0, but -604462909807314587353088.0 +
-36028797018963968.0 == -604462909807314587353088.0. Math class is
tough.

No changes in shader-db or fossil-db.

v2: Fix major bug in checking result of the eval_const_binop(nir_op_feq,
...) discovered while developing fneu_once_easy unit test. Fix a typo in
the comment just above that. Add fneu_once_easy test.

v3: Skip the iteration count adjustment tests for nir_op_fenu and
nir_op_ine. Since the iteration count is either 1 or unknown, all this
function can do is add numerical error. Add fenu_once tests.

v4: Change the initial value in the fneu_once test from large positive
to large negative. Change check in get_iteration from nir_op_fsub to
nir_op_fadd. Both changes from discussion with M Henning. Also add some
more explanation in fneu_once.

v5: Rename test cases.

Fixes: 6772a17acc8 ("nir: Add a loop analysis pass")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19732>
(cherry picked from commit f75c83c4aae2b01013f3740a7414cf207f60b0ab)

nir/loop_analyze: Fix get_iteration for nir_op_ine

I discovered this problem because adding an algebraic transformation to
convert some uge and ult to ieq or ine caused a couple loops to stop
unrolling. Consider the loop:

    uint i = 0;
    while (true) {
       if (i >= 1)
          break;

       i++;
    }

This loop clearly executes exactly one time. Note that uge(x, 1) is
equivalent to ine(x, 0). Changing the condition to 'if (i != 0)' will
also execute exactly one time.

In the added test cases, uge_once correctly get an exact loop trip count
of 1. Without the changes to nir_loop_analyze.c, the ine_once case
detects a maximum loop trip count of zero and does not get an exact loop
trip count.

No changes in shader-db or fossil-db.

v2: Move nir_op_fneu changes to a separate commit.

v3: Rename test cases.

Fixes: 6772a17acc8 ("nir: Add a loop analysis pass")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19732>
(cherry picked from commit d9f014401bf842bbc0f57987570e34c9ce080cc4)

rusticl/device: put space at the end of CL_DEVICE_VERSION

Apparently some software relies on that and the spec kind of says it's
there.

Fixes: 20c90fed5a0 ("rusticl: added")
Reported-by: sobkas
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19872>
(cherry picked from commit b51eb98cf65566f0f177031a34603ba8068521f8)

virgl: don't a use staging when a resources created with the shared flag

There seems to be a problem with running firefox by using Xwayland that
results in a shared resources being not always tagged as using staging.

As a result one process tries to map the resource that was allocated as
one that uses staging without actually using the staging resource, and
hence the mapped range only accounts for the small region that we have
to allocated because a zero-allocation doesn't work, but the application
mapping the resource assumes that a properly sized range is mapped, and
consequently this results in invalid memory access.

To work around this issue disable creating staging for resources that
are created by using shared binding. It is not clear to me whether this
is the best fix, but it seems to quell the issue.

Fixes: c9d99b7eec7ec14d6d71d381a424b6280d75a882
    virgl: Fix texture transfers by using a staging resource

Related: https://gitlab.freedesktop.org/virgl/virglrenderer/-/issues/291
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19655>
(cherry picked from commit e496d24cb2d5339566c08c79a8aa7809c240613c)

intel/fs: put scratch surface in the surface state heap

In 4ceaed7839af we made scratch surface state allocations part of the
internal heap (mapped to STATE_BASE_ADDRESS::SurfaceStateBaseAddress)
so that it doesn't uses slots in the application's expected 1M
descriptors (especially with vkd3d-proton).

But all our compiler code relies on BSS
(STATE_BASE_ADDRESS::BindlessSurfaceStateBaseAddress).

The additional issue is that there is only 26bits of surface offset
available in CS instruction (CFE_STATE, 3DSTATE_VS, etc...) for
scratch surfaces. So we need the drivers to put the scratch surfaces
in the first chunk of STATE_BASE_ADDRESS::SurfaceStateBaseAddress
(hence all the driver changes).

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 4ceaed7839af ("anv: split internal surface states from descriptors")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7687
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19727>
(cherry picked from commit 9c1c1888d9895d05246005620953ee307d1a17f1)

.pick_status.json: Mark 56bd81ee21cb42e4a5afa2939514b570a1283754 as denominated

aco: ensure MRT0 is written with dual source blending

Fixes crucible test func.shader.dualsrc_mrt0_undef on polaris10.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: 22.3 mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19806>
(cherry picked from commit 3061bc792d3d0252854a38bff956c15c51b06643)

radv: disable MRT compaction with dual-source blending

Fixes crucible tests func.shader.dualsrc_mrt0_undef on navi21 and
func.shader.dualsrc_mrt1_undef on polaris10.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: 22.3 mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19806>
(cherry picked from commit ea0ae17fc453401223918b27e0610352fe67e66d)

radv: Fix custom build id with C90 compilation.

Seems some build configurations have problems with VLAs still.

Fixes: 97641e5c942 ("radv: Add ability to override the build id for the cache.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19869>
(cherry picked from commit 8d37ab6bfa0321674fe74cc4c76c21aa94d36840)