Bin Meng [Thu, 20 Aug 2015 13:40:20 +0000 (06:40 -0700)]
x86: fsp: Add comments about U-Boot entering start.S twice
Add some comments in start.S for the fact that with FSP U-Boot
actually enters the code twice. Also change to use fsp_init()
and fsp_continue for accuracy.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Thu, 20 Aug 2015 13:40:19 +0000 (06:40 -0700)]
x86: fsp: Enlarge the size of malloc() pool before relocation
After fsp_init() returns, the stack has already been switched to a
place within system memory as defined by CONFIG_FSP_TEMP_RAM_ADDR.
Enlarge the size of malloc() pool before relocation since we have
plenty of memory now.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Thu, 20 Aug 2015 13:40:18 +0000 (06:40 -0700)]
x86: fsp: Delay x86_fsp_init() call a little bit
Move x86_fsp_init() call after initf_malloc() so that we can fix up
the gd->malloc_limit later.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Thu, 20 Aug 2015 13:40:17 +0000 (06:40 -0700)]
dm: pci: Support selected device/driver binding before relocation
On some platforms pci devices behind bridge need to be probed (eg:
a pci uart on recent x86 chipset) before relocation. But we won't
bind all devices found during the enumeration. Only devices whose
driver with DM_FLAG_PRE_RELOC set will be bound. Any other generic
devices except bridges won't be bound.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 15 Aug 2015 20:37:54 +0000 (14:37 -0600)]
x86: ifdtool: Drop microcode from the device tree when collating
When ifdtool collates the microcode into one place it effectively creates
a copy of the 'data' properties in the device tree microcode nodes. This
is wasteful since we now have two copies of the microcode in the ROM.
To avoid this, remove the microcode data from the device tree and shrink it
down. This means that there is only one copy and the overall ROM space used
by the microcode does not increase.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 15 Aug 2015 20:37:53 +0000 (14:37 -0600)]
x86: ifdtool: Support collating microcode into one place
The Intel Firmware Support Package (FSP) requires that microcode be provided
very early before the device tree can be scanned. We already support adding
a pointer to the microcode data in a place where early init code can access.
However this just points into the device tree and can only point to a single
lot of microcode. For boards which may have different CPU types we must
support multiple microcodes and pass all of them to the FSP in one place.
Enhance ifdtool to scan all the microcode, place it together in the ROM and
update the microcode pointer to point there. This allows us to pass multiple
microcode blocks to the FSP using its existing API.
Enable the flag in the Makefile so that this feature is used by default for
all boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 15 Aug 2015 20:37:52 +0000 (14:37 -0600)]
x86: ifdtool: Split microcode linking into its own function
The code to set up the microcode pointer in the ROM shares almost nothing
with the write_uboot() function.
Move it into its own function so it will be easier to extend.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 15 Aug 2015 20:37:51 +0000 (14:37 -0600)]
x86: ifdtool: Check that U-Boot does not overlap other regions
Since U-Boot and its device tree can grow we should check that it does not
overlap the regions above it. Track the ROM offset that U-Boot reaches and
check that other regions (written after U-Boot) do not interfere.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng [Sat, 15 Aug 2015 20:37:50 +0000 (14:37 -0600)]
x86: baytrail: Support multiple microcode copies
Intel FSP has the capability to walk through the microcode blocks
which are passed as the TempRamInit() parameter from U-Boot and
finds the most appropriate microcode which is suitable for the cpu
on which it is running. Now we've seen several steppings for Intel
BayTrail series processors, adding those microcodes to the Intel
BayleyBay and MinnowMax board device tree files.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Bin Meng [Sat, 15 Aug 2015 20:37:49 +0000 (14:37 -0600)]
x86: baytrail: Add microcode for BayTrail-I D0 stepping
This commit adds the microcode blob for BayTrail-I D0 stepping,
CPUID signature 30679h.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 15 Aug 2015 20:37:48 +0000 (14:37 -0600)]
x86: Correct microcode documentation
This is incorrect since we require the -m parameter to the microcode tool.
Update the two examples to show this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng [Tue, 18 Aug 2015 03:34:47 +0000 (20:34 -0700)]
efi: Update README.efi to clarify build and test instructions
The doc has a misleading 'make menuconfig' when building the EFI
application and payload. Clarify this and also update information
on test with QEMU.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Thu, 13 Aug 2015 07:29:17 +0000 (00:29 -0700)]
x86: Set up video framebuffer for coreboot before loading kernel
Currenlty we only set up video framebuffer when VIDEO_VESA driver is
used. With coreboot, VIDEO_COREBOOT driver is used instead. Since we
already saved VESA mode in the VIDEO_COREBOOT driver, now we can also
set up video framebuffer for coreboot before loading Linux kernel.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng [Thu, 13 Aug 2015 07:29:16 +0000 (00:29 -0700)]
video: coreboot: Save VESA mode for future use
When booting as a coreboot payload, the framebuffer details are
passed from coreboot via configuration tables. We save these
information into vesa_mode_info structure for future use.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng [Thu, 13 Aug 2015 07:29:15 +0000 (00:29 -0700)]
x86: Enable CONFIG_PCI_CONFIG_HOST_BRIDGE for all boards
It looks that x86 chipset always contains a host bridge at pci
b.d.f 0.0.0, so enable this for all boards.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng [Thu, 13 Aug 2015 07:29:14 +0000 (00:29 -0700)]
x86: Only include cbfs command for coreboot
When running U-Boot bare-metal, the cbfs command is useless.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng [Thu, 13 Aug 2015 07:29:13 +0000 (00:29 -0700)]
x86: kconfig: Hide "System tables" for coreboot
When booting as a coreboot payload, we don't need write any
configuration tables as coreboot does that for us.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng [Thu, 13 Aug 2015 07:29:12 +0000 (00:29 -0700)]
x86: kconfig: Hide "System tables" for EFI
Instead of hiding each menu entries under "System tables" for EFI,
hide the main menu completely.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng [Thu, 13 Aug 2015 07:29:11 +0000 (00:29 -0700)]
x86: coreboot: Allow >=4GiB memory bank size
Some platforms may have >=4GiB memory, so we need make U-Boot report
such configuration correctly when booting as the coreboot payload.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng [Thu, 13 Aug 2015 07:29:10 +0000 (00:29 -0700)]
x86: Remove calculate_relocation_address()
Now that we have generic routine to calculate relocation address,
remove the x86 specific one which is now only used by coreboot.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng [Thu, 13 Aug 2015 07:29:09 +0000 (00:29 -0700)]
x86: coreboot: Correctly report E820 types
coreboot has some extensions (type 6 & 16) to the E820 types.
When we detect this, mark it as E820_RESERVED.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng [Thu, 13 Aug 2015 07:29:08 +0000 (00:29 -0700)]
x86: coreboot: Increase memrange entry number to 32
Increase lib_sysinfo memrange entry number to 32 to sync with coreboot.
This allows a complete E820 table to be reported to the kernel, as on
some platforms (eg: Bayley Bay) having only 16 entires does not cover
all the memory ranges.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng [Thu, 13 Aug 2015 07:29:07 +0000 (00:29 -0700)]
x86: doc: Update coreboot payload entry point address
With recent EFI support, the entry point address of coreboot payload
was changed. Now we update the address to use _x86boot_start, which
is the same one for EFI.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng [Wed, 26 Aug 2015 13:17:27 +0000 (06:17 -0700)]
net: e1000: Fix build warnings for 32-bit
commit 6497e37 "net: e1000: Support 64-bit physical address" causes
compiler warnings on 32-bit U-Boot build below.
drivers/net/e1000.c: In function 'e1000_configure_tx':
drivers/net/e1000.c:4982:2: warning: right shift count >= width of type [enabled by default]
drivers/net/e1000.c: In function 'e1000_configure_rx':
drivers/net/e1000.c:5126:2: warning: right shift count >= width of type [enabled by default]
This commit fixes the build warnings.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tom Rini [Mon, 24 Aug 2015 20:06:03 +0000 (16:06 -0400)]
Merge git://git.denx.de/u-boot-pxa
Marcel Ziswiler [Sun, 16 Aug 2015 02:16:36 +0000 (04:16 +0200)]
arm: pxa: colibri_pxa270: add optional i2c support
This is useful once Andrew's PXA I2C driver gets merged.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Marcel Ziswiler [Sun, 16 Aug 2015 02:16:35 +0000 (04:16 +0200)]
arm: pxa: colibri_pxa270: add optional lcd support
Add optional LCD support. Note that depending on the toolchain used
one might have to drop some other features to stay within the 0x40000
size limit.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Marcel Ziswiler [Sun, 16 Aug 2015 02:16:34 +0000 (04:16 +0200)]
arm: pxa: colibri_pxa270: add some more nor flash details
Add some more NOR flash details like size, bus width and lock/unlock
time outs.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Marcel Ziswiler [Sun, 16 Aug 2015 02:16:33 +0000 (04:16 +0200)]
arm: pxa: palmtreo680: get rid of obsolete CONFIG_SYS_LCD_PXA_NO_L_BIAS
Looks like the define CONFIG_SYS_LCD_PXA_NO_L_BIAS is not used anywhere
else throughout the U-Boot sources any more. Drop it.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Marcel Ziswiler [Sun, 16 Aug 2015 02:16:31 +0000 (04:16 +0200)]
lcd: pxa: clean-up include file order
Cleaning up order of include files by sorting them alphabetically
keeping in mind to leave common.h on top.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Marcel Ziswiler [Sun, 16 Aug 2015 02:16:30 +0000 (04:16 +0200)]
usb: pxa27x_udc: clean-up include file order
Cleaning up order of include files by sorting them alphabetically
keeping in mind to leave common.h on top.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Marcel Ziswiler [Sun, 16 Aug 2015 02:16:29 +0000 (04:16 +0200)]
serial: pxa: clean-up include file order
Cleaning up order of include files by sorting them alphabetically
keeping in mind to leave common.h on top.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Marcel Ziswiler [Sun, 16 Aug 2015 02:16:27 +0000 (04:16 +0200)]
arm: pxa: mmc: clean-up include file order
Cleaning up order of include files by sorting them alphabetically
keeping in mind to leave common.h on top.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Marcel Ziswiler [Sun, 16 Aug 2015 02:16:26 +0000 (04:16 +0200)]
arm: pxa: clean-up include file order
Cleaning up order of include files by sorting them alphabetically
keeping in mind to leave common.h on top.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Andrew Ruder [Wed, 12 Aug 2015 18:18:31 +0000 (13:18 -0500)]
arm: pxa: use common timer functions
This patch moves pxa to the common timer functions added in commit
8dfafdd - Introduce common timer functions <Rob Herring>
The (removed) pxa timer code (specifically __udelay()) could deadlock at
the 32-bit boundary of get_ticks(). get_ticks() returned a 32-bit value
cast up to a 64-bit value. If get_ticks() + tmo in __udelay() crossed
the 32-bit boundary, the while condition became unconditionally true and
locked the processor. Rather than patch the specific pxa issues, simply
move everything over to the common code.
Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsuiko.com>
Andrew Ruder [Wed, 12 Aug 2015 17:55:47 +0000 (12:55 -0500)]
pxa: Fix boot hang by avoiding vector relocation
Since commit
3ff46cc42b9d73d0 ("arm: relocate the exception vectors")
pxa does not boot anymore.
Add a specific relocate_vectors macro that skips the vector relocation,
as the pxa SoC does not provide RAM at the high vectors address
(0xFFFF0000), and (0x00000000) maps to ROM.
This allows pxa to boot again.
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
Tom Rini [Mon, 24 Aug 2015 15:57:03 +0000 (11:57 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-mips
Tom Rini [Mon, 24 Aug 2015 00:44:25 +0000 (20:44 -0400)]
Merge git://git.denx.de/u-boot-socfpga
Conflicts:
configs/socfpga_arria5_defconfig
configs/socfpga_cyclone5_defconfig
configs/socfpga_socrates_defconfig
Merged these by hand and re-ran savedefconfig on them.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 24 Aug 2015 00:41:04 +0000 (20:41 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-net
Marek Vasut [Wed, 19 Aug 2015 05:46:49 +0000 (07:46 +0200)]
arm: socfpga: Fix ArriaV SoCDK PLL config
Pull out the ArriaV SoCDK clock config from ancient Altera U-Boot
"rel_socfpga_v2013.01.01_15.05.01_pr" and implant those values into
mainline to get a booting ArriaV SoCDK.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Wed, 19 Aug 2015 05:44:39 +0000 (07:44 +0200)]
arm: socfpga: Enable ethernet on ArriaV SoCDK
Synchronise the config options with Cyclone V SoCDK and other boards.
This enables ethernet on the ArriaV SoCDK.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Wed, 19 Aug 2015 05:43:19 +0000 (07:43 +0200)]
arm: socfpga: Fix SD/MMC boot on ArriaV SoCDK
Add the missing DT nodes, so that ArriaV SoCDK can boot from SD
card. The SD card must be in slot J5 and BSEL must be 0x5.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Wed, 19 Aug 2015 20:25:44 +0000 (22:25 +0200)]
arm: socfpga: Fix MAINTAINERS entry for CV/AV SoCDK
Repair the maintainer entries so they match the current state of code.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Tue, 23 Jun 2015 14:01:28 +0000 (16:01 +0200)]
arm: socfpga: Enable DWAPB GPIO driver
Enable the DWAPB GPIO driver for SoCFPGA Cyclone V and Arria V.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Marek Vasut [Mon, 10 Aug 2015 15:20:23 +0000 (17:20 +0200)]
arm: socfpga: dts: Add bank-name property to each GPIO bank
Add "bank-name" property to each GPIO bank to give it unique name.
The approach here is exactly the same as with the "regulator-name"
property for regulators.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Tue, 23 Jun 2015 13:54:19 +0000 (15:54 +0200)]
gpio: Add DW APB GPIO driver
Add driver for the DesignWare APB GPIO IP block.
This driver is DM capable and probes from DT.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Marek Vasut [Mon, 10 Aug 2015 20:17:46 +0000 (22:17 +0200)]
arm: socfpga: Make the pinmux table const u8
Now that we're actually converting the QTS-generated header files,
we can even adjust their data types. A good candidate for this is
the pinmux table, where each entry can have value in the range of
0..3, but each element is declared as unsigned long. By changing
the type to u8, we can save over 600 Bytes from the SPL, so do it.
This patch also constifies the array.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Mon, 10 Aug 2015 19:21:07 +0000 (21:21 +0200)]
arm: socfpga: Switch to filtered QTS files
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Mon, 10 Aug 2015 18:48:07 +0000 (20:48 +0200)]
arm: socfpga: Add qts-filter.sh script
Add script which loads the QTS-generated sources and headers and converts
them into sensible format which can be used with much more easy in mainline
U-Boot. The script also filters out macros which makes no sense anymore, so
they don't pollute namespace and waste space.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Mon, 10 Aug 2015 19:39:52 +0000 (21:39 +0200)]
arm: socfpga: Remove AV-specific parts from CV-SoCDK
Just remove the ArriaV specific parts from the CycloneV SoCDK board
and they are no longer needed now.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Mon, 10 Aug 2015 19:37:14 +0000 (21:37 +0200)]
arm: socfpga: Remove CV-specific parts from AV-SoCDK
Just remove the CycloneV specific parts from the ArriaV SoCDK board
and they are no longer needed now.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Mon, 10 Aug 2015 19:24:53 +0000 (21:24 +0200)]
arm: socfpga: Split Altera socfpga into AV and CV SoCDK
The board/altera/socfpga directory is not a generic SoCFPGA machine
anymore, but instead it represents the Altera SoCDK board. To make
matters more complicated, it represents both CycloneV and ArriaV
variant.
On the other hand, nowadays, the content of this board directory is
mostly comprised of QTS-generated header files, while all the generic
code is in arch/arm/mach-socfpga already.
Thus, this patch splits the board/altera/socfpga into a separate
board directory for ArriaV SoCDK and CycloneV SoCDK, so that each
can be populated with the correct QTS-generated header files for
that particular board.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Sun, 2 Aug 2015 19:57:57 +0000 (21:57 +0200)]
arm: socfpga: Unbind CPU type from board type
The CONFIG_TARGET_SOCFPGA_CYCLONE5 and CONFIG_TARGET_SOCFPGA_ARRIA5
selected both a board and a CPU. This is not correct as these macros
are supposed to select only board.
All would be good, if QTS-generated header files didn't check for
these macros exactly to determine if the platform is Cyclone V or
Arria V. Thus, for the sake of compatibility with not well fleshed
out header file generator, this patch makes these two macros into
a stub config option and introduces new CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK
and CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK targets, which select the
previous stub config option.
The result is that compatibility with QTS is preserved and the new
CONFIG_TARGET_* select actual target boards.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Sun, 2 Aug 2015 19:12:09 +0000 (21:12 +0200)]
arm: socfpga: Move wrappers into platform directory
Move the wrappers for QTS-generated files into platform directory
out of the board directory. The trick here is to add -I to CFLAGS
such that it points to the board directory in source tree and thus
the qts/ directory there is still reachable.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Mon, 3 Aug 2015 13:32:37 +0000 (15:32 +0200)]
arm: socfpga: Do not enable gmac1 in Cyclone V dtsi
The GMAC which is enabled is purely board property, so do not enable
arbitrary GMAC in DT include files. Same goes for PHY mode, which is
again a board property. The CycloneV SoCDK does this correctly, but
SoCrates doesn't. This bug never manifested itself though, since all
the boards ever used the GMAC1 . This bug manifests itself only on
boards that utilise GMAC0.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Sun, 2 Aug 2015 20:55:24 +0000 (22:55 +0200)]
arm: socfpga: Make the DT mmc node consistent
The socfpga_cyclone5.dtsi has an mmc0 node, socrates has mmc node.
This makes aliases not very usable, so make everything into mmc0.
Moreover, zap the useless mmc alias while at this.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Mon, 10 Aug 2015 22:54:12 +0000 (00:54 +0200)]
arm: socfpga: Fix delay in clock manager
This code claims it needs to wait 7us, yet it uses get_timer() function
which operates with millisecond granularity. Use timer_get_us() instead,
which operates with microsecond granularity.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Mon, 10 Aug 2015 22:49:09 +0000 (00:49 +0200)]
arm: socfpga: Fix delay in freeze controller
Based on observation, this udelay(20) was apparently too high and caused
subsequent failure to calibrate DDR when U-Boot was compiled with certain
toolchains. Lowering this delay fixed the problem.
Instead of permanently lowering the delay, calculate the correct delay
based on the original comment, that is, obtain EOSC1 frequency and use
it to calculate the precise delay.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Mon, 10 Aug 2015 21:01:43 +0000 (23:01 +0200)]
ddr: altera: Repair uninited variable
Fix the following problem:
drivers/ddr/altera/sequencer.c: In function 'sdram_calibration_full':
drivers/ddr/altera/sequencer.c:1943:25: warning: 'found_failing_read' may be used uninitialized in this function [-Wmaybe-uninitialized]
if (found_passing_read && found_failing_read)
^
drivers/ddr/altera/sequencer.c:1803:26: note: 'found_failing_read' was declared here
u32 found_passing_read, found_failing_read, initial_failing_dtap;
^
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Mon, 10 Aug 2015 20:50:11 +0000 (22:50 +0200)]
ddr: altera: Replace float multiplication with integer one
This gem is really really rare, there was an actual float used in
the Altera DDR init code, which pulled in floating point ops from
the libgcc, just wow.
Since we don't support floating point operations the same way Linux
does not support them, replace this with an integer multiplication
and division combo. This removes some 2kiB of size from the SPL as
the floating point ops are no longer pulled in from libgcc.
This was detected by enabling CONFIG_USE_PRIVATE_LIBGCC=y , which
does not contain the floating point bits.
Signed-off-by: Marek Vasut <marex@denx.de>
Simon Glass [Wed, 19 Aug 2015 15:33:43 +0000 (09:33 -0600)]
net: Move CONFIG_E1000 options to Kconfig
Move config for the E1000 Ethernet driver to Kconfig and tidy up affected
boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Simon Glass [Wed, 19 Aug 2015 15:33:42 +0000 (09:33 -0600)]
Tidy up some defconfig files
Several files are out of order. This means that when the moveconfig tool
moves CONFIG options to Kconfig it generates a large diff. To avoid this,
reorder the files first.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Wed, 19 Aug 2015 15:33:41 +0000 (09:33 -0600)]
net: e1000: Add Kconfig options
Add Kconfig options in preparation for moving boards to use Kconfig.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Simon Glass [Wed, 19 Aug 2015 15:33:40 +0000 (09:33 -0600)]
net: e1000: Convert to driver model
Update this driver to support driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Apalis T30 2GB on Apalis Evaluation Board
Simon Glass [Wed, 19 Aug 2015 15:33:39 +0000 (09:33 -0600)]
net: e1000: Prepare for driver model conversion
Since struct eth_device does not exist with CONFIG_DM_ETH defined, avoid
using it in the driver unless necessary. Most of the time it is better to
pass the private driver pointer anyway.
Also refactor the code so that code that the driver model implementation
will share are available in functions that can be called. Add stubs where
necessary.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Apalis T30 2GB on Apalis Evaluation Board
Simon Glass [Wed, 19 Aug 2015 15:33:38 +0000 (09:33 -0600)]
net: e1000: Move #include of common.h to the C files
We cannot currently include any header files in the C files since common.h
needs to be included first, and it is in the header file. Move it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Apalis T30 2GB on Apalis Evaluation Board
Michal Simek [Fri, 21 Aug 2015 06:49:48 +0000 (08:49 +0200)]
net: Return -EINTR when ctrl+c is pressed
Current behavior is that if CTRL+C is pressed command returns 0 that was
successful which is not correct behavior.
The easiest test case is "tftpboot 80000 uImage && echo yes"
and press CTRL+C. Then the second command is called which is incorrect.
Error log:
zynq-uboot> tftpb 80000 uImage && echo yes
Gem.
e000b000:7 is connected to Gem.
e000b000. Reconnecting to
Gem.
e000b000
Gem.
e000b000 Waiting for PHY auto negotiation to complete....... done
Using Gem.
e000b000 device
TFTP from server 192.168.0.102; our IP address is 192.168.0.101
Filename 'uImage'.
Load address: 0x80000
Loading: ################
Abort
yes
zynq-uboot>
This patch adds -EINTR return value when CTRL+C is pressed.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Mingkai Hu [Tue, 18 Aug 2015 21:06:26 +0000 (14:06 -0700)]
net: e1000: Support 64-bit physical address
High 32-bit address is needed when u-boot runs in 64-bit space.
Tested on armv8-based LS2085ARDB.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Pavel Machek [Tue, 18 Aug 2015 12:34:26 +0000 (14:34 +0200)]
tftp: adjust settings to be suitable for 100Mbit ethernet
Adjust timouts and retry counts to be suitable for loaded ethernet
network. With 5 seconds timeout, 10 retries maximum, tftp is
impossible even on local network with single full-speed TCP
connection.
100msec timeout should be suitable for most networks tftp is used on,
that is local ethernets. Timeout count really needs to be way higher,
as lost packets are normal when TCP is running over the same network.
Enforce 10msec minimum.
Signed-off-by: Pavel Machek <pavel@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Wu, Josh [Wed, 19 Aug 2015 11:11:21 +0000 (19:11 +0800)]
ARM: at91: sama5: update the spi flash mapping
Also move the spi flash configurations to the at91-sama5_common.h.
Current at91 zImage size is about 3.3M, the old mapping is not
suitable. So update the spi flash map as following:
0x0 ~ 0x004000: at91bootstrap(16k)
0x04000 ~ 0x008000: u-boot env(16k)
0x08000 ~ 0x060000: u-boot(352k)
0x60000 ~ 0x06c000: dtb (48k)
0x6c000 ~ 0x400000: kernel (3M+592k)
In AT91Bootstrap, the U-Boot in spi flash also update to 0x8000, refer
to following commit in AT91Bootstrap:
3e91e54 Kconfig: fix spi flash address
So also update SPL's u-boot load address to 0x8000 in spi flash.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Wu, Josh [Wed, 19 Aug 2015 11:11:20 +0000 (19:11 +0800)]
ARM: at91: sama5: move the nandflash env config to at91-sama5_common.h
As all sama5 nandflash env configurations are same, so move them to
at91-sama5_common.h.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Wu, Josh [Wed, 19 Aug 2015 11:11:19 +0000 (19:11 +0800)]
ARM: at91: sama5d3xek: use a $dtb_name to load dtb
Since sama5d3xek boards has different type of dtb blobs, so we need to detect
the cpu type in runtime.
So we add a new variable $dtb_name. if $dtb_name is not defined, we just use
at91-${board_name}.dtb
as the $dtb_name. Otherwise, we will just load the dtb with
$dtb_name.
For sama5d3xek, we will detect cpu type and make up $dtb_name in
runtime.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Wu, Josh [Wed, 19 Aug 2015 11:11:18 +0000 (19:11 +0800)]
ARM: at91: sama5: move the sd/mmc env config to at91-sama5_common.h
As almost all sama5 sd/mmc env configurations are same, so move them to
at91-sama5_common.h.
Also define CONFIG_ENV_VARS_UBOOT_CONFIG to have the varaible: $board_name.
Then we can use 'at91-${board_name}.dtb' as the dtb name.
TODO: since sama5d3xek has different dtb name, we need to some extra
stuff to make it work on sama5d3xek boards.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Erik van Luijk [Mon, 17 Aug 2015 10:47:34 +0000 (12:47 +0200)]
arm: at91: add support for mini-box picosam9g45 board
Bootlog:
U-Boot SPL 2015.10-rc1-00452-g96a7ed1 (Aug 17 2015 - 10:32:21)
mci: setting clock 258000 Hz, block size 512
mci: setting clock 258000 Hz, block size 512
mci: setting clock 258000 Hz, block size 512
mci: setting clock
33024000 Hz, block size 512
reading u-boot.img
reading u-boot.img
U-Boot 2015.10-rc1-00452-g96a7ed1 (Aug 17 2015 - 10:32:21 +0000)
CPU: AT91SAM9G45
Crystal frequency: 12 MHz
CPU clock : 400 MHz
Master clock : 133.333 MHz
Watchdog enabled
DRAM: 256 MiB
WARNING: Caches not enabled
MMC: mci: 0
mci: setting clock 260416 Hz, block size 512
mci: setting clock 260416 Hz, block size 512
mci: setting clock 260416 Hz, block size 512
mci: setting clock
33333333 Hz, block size 512
reading uboot.env
In: serial
Out: serial
Err: serial
Net: macb0
Error: macb0 address not set.
Hit any key to stop autoboot: 0
U-Boot>
Signed-off-by: Erik van Luijk <evanluijk@interact.nl>
[add 'picosam9g45_defconfig' to MAINTAINERS]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Erik van Luijk [Thu, 13 Aug 2015 13:43:20 +0000 (15:43 +0200)]
arm: at91: pmc: replace the constant with a define in at91_pmc.h
To enable the clocks on the at91 boards a constant (0x4) is used.
This is replaced with a define in at91_pmc.h (1 << 2).
Signed-off-by: Erik van Luijk <evanluijk@interact.nl>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Erik van Luijk [Thu, 13 Aug 2015 13:43:19 +0000 (15:43 +0200)]
arm: at91: at91sam9m10g45ek/corvus remove useless chip select 1 init
On these boards the DDR is connected to a dedicated controller and not
to chip select 1 of the EBI.
Signed-off-by: Erik van Luijk <evanluijk@interact.nl>
Tested-by: Erik van Luijk <evanluijk@interact.nl>
Erik van Luijk [Thu, 13 Aug 2015 13:43:18 +0000 (15:43 +0200)]
arm: at91: mpddr: allow multiple DDR controllers
The mpddr.c depends on ATMEL_BASE_MPDDRC for the base address to configure the controller.
This cannot be used when there is more than one controller (i.e. AT91SAM9G45, AT91SAM9M10).
Signed-off-by: Erik van Luijk <evanluijk@interact.nl>
[remove 'new blank line at EOF']
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Govindraj Raja [Wed, 19 Aug 2015 18:19:15 +0000 (19:19 +0100)]
MIPS: fix syntax for fdt_chosen/initrd.
The syntax for the fdt_chosen/initrd
functions seem to deprecated in usage
from MIPS bootm implementation.
Third parameter is no more used in these api's
Refer to : include/fdt_support.h
Signed-off-by: Govindraj Raja <govindraj.raja@imgtec.com>
Chris Packham [Tue, 14 Jul 2015 10:54:41 +0000 (22:54 +1200)]
mips: Use unsigned int when reading c0 registers
In commit a18a477 (MIPS: use common code from lib/time.c) MIPS platforms
started using common the common timer functions which are based around
the fact that many platforms have a 32-bit free running counter register
that can be used see commit 8dfafdd (Introduce common timer functions).
Even MIPS64 has such a 32-bit register (some have an additional 64-bit free
running counter, but that's something for another time).
The problem is that in __read_32bit_c0_register() we read the value from
this register into an _signed_ int and as it's returned up the call
chain to timer_read_counter() it gets assigned to an unsigned long. On a
32-bit system there is no problem. On a 64-bit system odd things happen,
sign extension seems to kick in and all of a sudden if the counter
register happens to have the MSb (i.e. the sign bit) set the negative
int gets sign extended into a very large unsigned long value. This in
turn throws out things from get_ticks() up.
Update __read_32bit_c0_register() and __read_32bit_c0_ctrl_register() to
use "unsigned int res;" instead of "int res;". There seems to be little
reason to treat these register values as signed. They are either
counters (which by definition are unsigned) or are made up of various
bit fields to be interpreted as per the CPU datasheet.
Reported-by: Sachin Surendran <sachin.surendran@alliedtelesis.co.nz>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Masahiro Yamada [Thu, 20 Aug 2015 01:20:55 +0000 (10:20 +0900)]
ARM: davinci: remove support for cam_enc_4xx
This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Heiko Schocher <hs@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Tom Rini [Wed, 19 Aug 2015 22:04:48 +0000 (18:04 -0400)]
Merge git://git.denx.de/u-boot-usb
Marek Vasut [Wed, 12 Aug 2015 20:19:15 +0000 (22:19 +0200)]
usb: dwc2: Rename to dwc2_usb
This driver is not used only on exynos, but also on Altera SoCFPGA,
HiSilicon SoCs, RPi etc, so rename it accordingly to prevent confusion.
Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Wed, 12 Aug 2015 20:19:14 +0000 (22:19 +0200)]
usb: dwc2: Add original Synopsys compat string
Add the Synopsys compatible string. This is used in SoCFPGA DT files.
Signed-off-by: Marek Vasut <marex@denx.de>
Kishon Vijay Abraham I [Wed, 19 Aug 2015 08:19:48 +0000 (13:49 +0530)]
usb: gadget: ether: populate _reset_ callback
populate _reset_ callback to the USB ethernet gadget since UDC core
expects every gadget driver to have the reset callback. This shouldn't
be needed once the ethernet gadget driver is adapted to use the
composite driver.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Kishon Vijay Abraham I [Wed, 19 Aug 2015 08:19:47 +0000 (13:49 +0530)]
usb: host: xhci-omap: invoke board_usb_cleanup in xhci_hcd_stop
xhci omap driver has board_usb_init in xhci_hcd_init but doesn't have
the corresponding cleanup function in xhci_hcd_stop.
Fix it here by invoking board_usb_cleanup() in xhci_hcd_stop().
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Kishon Vijay Abraham I [Wed, 19 Aug 2015 08:19:46 +0000 (13:49 +0530)]
usb: gadget: ether: Perform board initialization from ethernet gadget driver
Ethernet gadget driver can be used both by both SPL and u-boot. Since
usb_eth_init() is the entry point for ethernet gadget driver, perform
board initialization there. Also perform the cleanup in usb_eth_halt.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Sergey Temerkhanov [Mon, 17 Aug 2015 12:38:07 +0000 (15:38 +0300)]
usb: xhci: Fix a potential NULL pointer dereference
This patch fixes a potential NULL pointer dereference arising on
non-present/non-initialized xHCI controllers and adds some error
handling to xHCI code
Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com>
Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
Stefan Roese [Tue, 18 Aug 2015 07:27:18 +0000 (09:27 +0200)]
usb: spear: Add support for both SPEAr600 EHCI controllers
USB EHCI on SPEAr600 has not been tested for a while. The base controller
addresses are missing. This patch adds the defines to the header. And adds
the missing code.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Vipin Kumar <vk.vipin@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Adrian Alonso [Thu, 6 Aug 2015 20:46:03 +0000 (15:46 -0500)]
imx: usb: ehci-mx6: wait_for_bit to check reg status
Add wait_for_bit to check reg bit status and replace unbounded
loops to check usb command status
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Adrian Alonso [Thu, 6 Aug 2015 20:43:17 +0000 (15:43 -0500)]
imx: usb: ehci-mx6: add usb support for imx7d soc
Extend ehci-mx6 usb driver to support imx7d usb
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Adrian Alonso [Thu, 6 Aug 2015 20:43:16 +0000 (15:43 -0500)]
imx: usb: ehci-mx6: document board specific functions
Document target board specific functions
board_ehci_hcd_init - override usb phy mode
board_ehci_hcd_init - set usb vbus voltage
board_ehci_power - enables/disables usb vbus voltage
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Adrian Alonso [Thu, 6 Aug 2015 20:43:15 +0000 (15:43 -0500)]
imx: usb: ehci-mx6: reg accessor cleanups
Cleanup read/write register access, use clr/set bits_le32
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Michal Simek [Wed, 12 Aug 2015 10:58:54 +0000 (12:58 +0200)]
zynqmp: enable CONFIG_NET_RANDOM_ETHADDR
We have to set a MAC address to use network.
Otherwise, the tftpboot command fails with the following message:
Gem.
e000b000 Waiting for PHY auto negotiation to complete........ done
*** ERROR: `ethaddr' not set
Since commit
92ac52082140 ("net: Remove all references to
CONFIG_ETHADDR and friends"), we can not use CONFIG_ETHADDR.
The easiest way to set a MAC address is to enable
CONFIG_NET_RANDOM_ETHADDR.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 12 Aug 2015 09:25:05 +0000 (11:25 +0200)]
ARM: dts: Rename memory@0 to memory
zynq-7000.dtsi include skeleton.dtsi which contains memory node with
base address and size zero. If you add memory@0 node to the platform DTS
in final DTB there are two memory nodes and U-Boot works with the first
one (with zeros) which end up in failing in dram_init because size is
zero.
Platform memory node should rewrite default memory node setup from
skeleton.dtsi that's why platfroms needs to also use memory as node name
instead of memory@0.
Reported-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Masahiro Yamada [Fri, 17 Jul 2015 11:26:06 +0000 (20:26 +0900)]
zynq: enable CONFIG_NET_RANDOM_ETHADDR
We have to set a MAC address to use network.
Otherwise, the tftpboot command fails with the following message:
Gem.
e000b000 Waiting for PHY auto negotiation to complete........ done
*** ERROR: `ethaddr' not set
Since commit
92ac52082140 ("net: Remove all references to
CONFIG_ETHADDR and friends"), we can not use CONFIG_ETHADDR.
The easiest way to set a MAC address is to enable
CONFIG_NET_RANDOM_ETHADDR.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 3 Aug 2015 12:21:25 +0000 (14:21 +0200)]
zynq: Make CONFIG_OF_EMBED default case
Use embedded DTB to let users use u-boot instead of u-boot-dtb.bin.
And fix SPL to use this target.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Tue, 4 Aug 2015 07:33:26 +0000 (13:03 +0530)]
zynqmp: usb: Add usb dwc3 driver support for zynqmp
Added usb dwc3 driver support for zynqmp
this also supports the DFU and LTHOR to download
the linux images on to RAM and cen be booted from
those linux images.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Masahiro Yamada [Sat, 1 Aug 2015 07:39:54 +0000 (16:39 +0900)]
ARM: zynq: drop "optional" from board select in favor of ZC702
One disadvantage of commit
a26cd04920dc (arch: Make board selection
choices optional) is that Kconfig could create such an insane
.config file that no board is selected.
Rip off the "optional" again in favor of ZC702 as the default
target.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Tue, 4 Aug 2015 07:31:05 +0000 (13:01 +0530)]
board: Xilinx: zynqmp: Define checkboard() function
Define checkboard() function for zynqMP
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 3 Aug 2015 11:19:39 +0000 (13:19 +0200)]
configs: zynqmp: Enable networking by default for EP108
Enable networking for EP108 by default.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>