Mike Blumenkrantz [Thu, 12 Jan 2023 15:15:59 +0000 (10:15 -0500)]
zink: set textures_used in analyze_io
this is otherwise not usable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20674>
Mike Blumenkrantz [Thu, 12 Jan 2023 15:13:56 +0000 (10:13 -0500)]
zink: break out implicit feedback loop detection into separate function
no functional changes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20674>
Rob Clark [Tue, 17 Jan 2023 21:30:58 +0000 (13:30 -0800)]
freedreno: Restore GL_VENDOR string
We cannot change this, as it has already been communicated to app
partners. Also this breaks chrome's GPU quirk matching (which in some
cases is non-gpu-related, but when all you have is a hammer, everything
looks like a nail).
Fixes:
9c1fbc076af ("Return 'Mesa' for GL_VENDOR for community drivers")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20757>
Dave Airlie [Wed, 14 Dec 2022 04:20:28 +0000 (14:20 +1000)]
vulkan/format: add a 10-bit video format
This adds support to the generic vulkan format code for
VK_FORMAT_G10X6_B10X6R10X6_2PLANE_420_UNORM_3PACK16
which is used for 10-bit H265.
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
(Updated version acked by Lynne on irc)
v2: disable these for freedreno
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20389>
Dave Airlie [Mon, 8 Nov 2021 20:48:52 +0000 (06:48 +1000)]
vulkan/video: add common h264/h265 parameter set management code.
The video session and video session parameters objects can have a common
base class the drivers can inherit from if needed.
This creates code to parse the h264/h265 parameter sets into common
structs.
v2: add h265 VPS, add a macro for FIND/ADD generations, changes the API
to make generation easier.
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20389>
Rob Clark [Mon, 2 Jan 2023 17:21:32 +0000 (09:21 -0800)]
freedreno/a6xx: Expose SSBO/image for all shader stages
Now that we've removed the limitation of a single bindful IBO state, we
can expose IBO support on all shader stages.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20687>
Rob Clark [Sun, 1 Jan 2023 23:46:48 +0000 (15:46 -0800)]
freedreno/a6xx: Move tex state building
Now that it is only called from fd6_texture, move it there where it more
rightly belongs.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20687>
Rob Clark [Sun, 1 Jan 2023 23:44:42 +0000 (15:44 -0800)]
freedreno/a6xx: Move compute to tex state group
This lets compute shaders hit the shader state cache as well, and
unifies 3d and cs state emit allowing for more code sharing.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20687>
Rob Clark [Sun, 1 Jan 2023 23:11:20 +0000 (15:11 -0800)]
freedreno/a6xx: Remove tex fb_read state
Now that fb_read is using a bindless descriptor slot, we can remove the
dependency of the TEX state on the PROG state.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20687>
Rob Clark [Sun, 1 Jan 2023 23:00:41 +0000 (15:00 -0800)]
freedreno/a6xx: Removing munging of tex state for IBO
Now that we use bindless descriptors for SSBO/image, lowering to isam
means we can use the existing descriptor. Avoiding the need to smash in
extra bindful sampler state.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20687>
Rob Clark [Sat, 7 Jan 2023 20:30:49 +0000 (12:30 -0800)]
freedreno/a6xx: Remove bindfull IBO state
Now that it is unused.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20687>
Rob Clark [Sun, 1 Jan 2023 21:35:47 +0000 (13:35 -0800)]
freedreno/a6xx: Switch over to bindless IBO
This allows support for SSBOs/images in all shader stages. And also,
unlike the bindful IBO state, does not introduce a dependency on the
program state. With bindless descriptors, SSBO and image fetch lowered
to isam can re-use the same descriptor. This will let us remove the
TEX state dependency on PROG state (in a following cleanup commit).
Note, this does not yet switch the pipe caps to reflect that we can
support SSBOs/images in other shader stages.. because ir3 still tells us
nibo>0 even though we are using bindless and that triggers an assert in
the build_ibo() path. Probably we want ir3 to be more clever.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20687>
Rob Clark [Sun, 1 Jan 2023 20:09:06 +0000 (12:09 -0800)]
freedreno/a6xx: Add bindless state
This will be used when we switch over to lowering image/SSBO to
bindless.
Note that it also starts using CP_SET_DRAW_STATE in the compute path.
Subsequent cleanup will switch texture and eventually other state over
as well (which will make more sense when we get more clever than
emitting all state for every compute grid, but for now simplifies
re-using the same code between 3d and compute).
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20687>
Rob Clark [Sat, 31 Dec 2022 18:36:53 +0000 (10:36 -0800)]
freedreno/a6xx: Pre-bake IBO descriptor sets
Pre-bake IBO descriptor sets at the time that images/SSBOs are bound,
and re-use the pre-baked descriptors at draw time when we emit state.
This starts putting in place the state tracking we'll use when switching
over to bindless IBO state, without yet changing the shaders (lowering
to bindless) or changing the actual state emitted (other than switching
to use the storage descriptor for image reads via isam, like tu does).
Note that this even pre-bakes the iova into the descriptor, rather than
relying on OUT_RELOC() to do the bo tracking, so we need to manually
attach the bo to the ring. But we already require FD_BO_NO_HARDPIN for
a6xx. This makes the state emit a straight memcpy, and will simplify
things when it comes to generating the bindless descriptor set (which
due to the desc_size field in the low bits of the BINDLESS_BASE regs
would be awkward to construct as a ring rather than a bo).
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20687>
Rob Clark [Sat, 31 Dec 2022 19:35:15 +0000 (11:35 -0800)]
freedreno/ir3: Add descriptor set lowering
Add support to lower IBO (image/SSBO) and fb-read to use bindless
descriptors. This will be used by a6xx to avoid having to merge image
and SSBO state into a single compact IBO descriptor, and also simplify
enabling image and SSBO support for additional shader stages (since each
stage can use it's own descriptor set).
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20687>
Rob Clark [Thu, 5 Jan 2023 15:28:17 +0000 (07:28 -0800)]
freedreno: Track image/SSBO usage for all stages
Once a6xx enables image/SSBO for all shader stages, we have to care
about more than just frag shader in the 3d path.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20687>
Rob Clark [Wed, 4 Jan 2023 20:51:25 +0000 (12:51 -0800)]
freedreno/ir3: Let driver specify fb-read descriptor
Let the driver control where the shader should look for fb-read
descriptor.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20687>
Rob Clark [Wed, 4 Jan 2023 20:05:23 +0000 (12:05 -0800)]
freedreno/ir3: Stop copying options
Just copy the entire ir3_compiler_options into ir3_compiler, to make it
easier to add new options.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20687>
Qiang Yu [Sun, 4 Dec 2022 13:47:16 +0000 (21:47 +0800)]
radeonsi: update nir xfb info after medium io lowering
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19489>
Qiang Yu [Sun, 4 Dec 2022 13:42:08 +0000 (21:42 +0800)]
nir/xfb_info: nir_gather_xfb_info_from_intrinsics update nir xfb_info
Use this function to update nir_shader->xfb_info.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19489>
Qiang Yu [Sun, 4 Dec 2022 08:51:15 +0000 (16:51 +0800)]
gallium/aux: remove nir_helpers
Not used by anyone.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19489>
Qiang Yu [Wed, 19 Oct 2022 02:26:14 +0000 (10:26 +0800)]
radeonsi: move gfx10_ngg_export_vertex to si_shader_llvm.c
It's now also used by non-ngg pipeline and older GPUs.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19489>
Qiang Yu [Thu, 1 Dec 2022 01:55:57 +0000 (09:55 +0800)]
radeonsi: replace llvm legacy gs code with nir lowering
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19489>
Qiang Yu [Sun, 4 Dec 2022 05:38:53 +0000 (13:38 +0800)]
radeonsi: remove llvm gs copy shader generate
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19489>
Qiang Yu [Sun, 4 Dec 2022 05:29:29 +0000 (13:29 +0800)]
radeonsi: replace llvm gs copy shader generation with nir
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19489>
Qiang Yu [Sun, 4 Dec 2022 04:33:55 +0000 (12:33 +0800)]
radeonsi: build legacy gs output info when shader compile
To be used by both legacy gs lowering and gs copy shader
generation.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19489>
Qiang Yu [Sun, 4 Dec 2022 03:29:18 +0000 (11:29 +0800)]
radeonsi: add nir implementation of gs copy shader generation
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19489>
Qiang Yu [Tue, 18 Oct 2022 06:04:12 +0000 (14:04 +0800)]
radeonsi: use ac_nir_lower_legacy_vs to replace si_llvm_vs_build_end
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19489>
Qiang Yu [Fri, 25 Nov 2022 02:01:57 +0000 (10:01 +0800)]
radeonsi: use nir_print_xfb_info to replace si_dump_streamout
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19489>
Qiang Yu [Mon, 17 Oct 2022 09:16:40 +0000 (17:16 +0800)]
radeonsi: lower nir streamout intrinsics in abi
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19489>
Qiang Yu [Thu, 1 Dec 2022 01:27:26 +0000 (09:27 +0800)]
radeonsi: implement nir_load_ring_gs2vs_offset_amd
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19489>
Qiang Yu [Mon, 17 Oct 2022 09:01:35 +0000 (17:01 +0800)]
radeonsi: implement nir_load_ring_gsvs_amd
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19489>
Emma Anholt [Thu, 12 Jan 2023 00:07:05 +0000 (16:07 -0800)]
ci: Enable building the testing drivers with perfetto.
We've talked about being able to capture perfetto traces from CI jobs for
a while, and this would be a step toward that. Mostly it's that we
occasionally break the perfetto build, so let's make sure we don't do
that.
Acked-by: Rob Clark <robdclark@chromium.org>
Acked-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20660>
Emma Anholt [Thu, 12 Jan 2023 00:32:00 +0000 (16:32 -0800)]
freedreno/pps: Fix a signed/unsigned complaint.
../src/freedreno/ds/fd_pps_driver.cc:656:44: error: comparison of integer expressions of different signedness: '__gnu_cxx::__alloc_traits<std::allocator<int>, int>::value_type' {aka 'int'} and 'const unsigned int' [-Werror=sign-compare]
656 | assert(d->assigned_counters[i] < g->num_counters);
cc1plus: all warnings being treated as errors
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20660>
Emma Anholt [Tue, 17 Jan 2023 23:51:36 +0000 (15:51 -0800)]
ci/freedreno: Add glx-swap-event-async as a flake.
It's only happened a few times in the last year (used to be more popular),
but it just took out a merge.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20660>
Emma Anholt [Wed, 18 Jan 2023 00:07:28 +0000 (16:07 -0800)]
freedreno: Skip CPU/GPU timestamp sync when not supported.
Fixes immediate segfaults in perfetto-enabled builds on pre-a6xx.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20660>
Emma Anholt [Tue, 17 Jan 2023 22:01:18 +0000 (14:01 -0800)]
ci/zink: Add more blit conversion xfails for a618.
Popular cases in this group recently:
1 dEQP-GLES3.functional.fbo.blit.conversion.r16ui_to_r16ui
1 dEQP-GLES3.functional.fbo.blit.conversion.r16ui_to_rgb10_a2ui
1 dEQP-GLES3.functional.fbo.blit.conversion.rgb5_a1_to_rgb5_a1
3 dEQP-GLES3.functional.fbo.blit.conversion.rgba4_to_r32f
4 dEQP-GLES3.functional.fbo.blit.conversion.rgb565_to_rgba8
5 dEQP-GLES3.functional.fbo.blit.conversion.rgba4_to_rg16f
There's pretty clearly something common with blitting from 16-bit.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20759>
Emma Anholt [Tue, 17 Jan 2023 21:51:55 +0000 (13:51 -0800)]
ci/iris: Generalize the 8888_pbuffer EGL known flakes and share with GLK.
It seems to be this whole group of tests, on both boards that run EGL
tests by default (aml-y is manual-only). Make them a regex until someone
comes up with a fix.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20759>
Emma Anholt [Tue, 17 Jan 2023 21:51:27 +0000 (13:51 -0800)]
ci/iris: Add known flakes for skqp.
We've had a lot more jobs run since I landed the CI, and these seem to be
the common flakes.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20759>
Emma Anholt [Tue, 17 Jan 2023 21:43:02 +0000 (13:43 -0800)]
ci/llvmpipe: Drop dEQP-EGL.functional.sharing.*.link.7 flakes.
These appear to have been resolved by !20458 -- went from typically
multiple per day to none since then. The link.19 fails to seem to still
happen, though.
Closes: #7759
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20759>
Jason Ekstrand [Mon, 16 Jan 2023 22:03:11 +0000 (16:03 -0600)]
gallium,util: Pull u_indices and u_primconvert back into gallium
This was moved in !13741 but doing so created a link-time dependency
between util and gallium which causes problems for Vulkan drivers.
Meanwhile, having mesa/main depend on gallium is fine now that we don't
have any classic drivers. It's a bit circular but should be harmless.
Fixes:
97ba2f2fd486 ("move util/indices to core util")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8098
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20734>
Ikshwaku Chauhan [Thu, 5 Jan 2023 15:55:00 +0000 (21:25 +0530)]
radeonsi: Fix distortion for yuv422 format for GFX10.
For yuv422 format camera show blur output for GFX10.
Signed-off-by: Ikshwaku Chauhan <ikshwaku.chauhan@amd.com>
Reviewed-by: Marek Olšák marek.olsak@amd.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20610>
Corentin Noël [Tue, 17 Jan 2023 09:33:37 +0000 (10:33 +0100)]
ci/venus: Remove failure now passing
It has been fixed either in the CTS or in llvmpipe itself but this now passes when running
in CI.
We haven't seen it in CI yet as we are only running a subset of the Vulkan CTS.
Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20743>
Mike Blumenkrantz [Mon, 9 Jan 2023 18:51:16 +0000 (13:51 -0500)]
zink: prune old swapchains on present
pruning old swapchains is challenging because there's no way to definitively
know when to destroy them without VK_EXT_swapchain_maintenance1 which isn't
supported yet
initially, I handled it by only pruning on shutdown and whenever a new swapchain
was created since those are both safe points, but this leads to scenarios where
a dead swapchain can exist for the entire lifetime of an application
if the swapinterval is changed
to avoid such ballooning, check whether the current swapchain has ever presented
on each present queue and then prune based on this
fixes #7529
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20588>
Emma Anholt [Thu, 12 Jan 2023 18:43:06 +0000 (10:43 -0800)]
dri2: Fix exposing robustness with swkms.
In the original change I noticed that missing robustness on swkms seemed
to be an oversight, since it was enabled on sw-non-kms, so I exposed the
ext based on the underlying pipe query. However it turns out that there
is a dri_screen flag for allowing robust contexts that exists to do error
checking for GLX, which was under an !swkms check. So we would expose the
ext, but then throw an error if you tried to create one.
Fixes:
e6285ea55fb2 ("egl: Replace the robustness DRI2 ext check with a pipe cap query.")
Closes: #8066
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20679>
Jesse Natalie [Tue, 10 Jan 2023 17:19:50 +0000 (09:19 -0800)]
dzn: Remove cmdbuf query 'wait' list
From the Vulkan spec, the WAIT flag on vkCmdCopyQueryPoolResults only
serves to increase the first synchronization scope to include query end
commands, but either way, the synchronization scope only includes
commands that occur earlier in submission order. In other words, we
don't need to enforce queue ordering, a pipeline barrier is all that's
needed.
Fixes deadlocks in the timestamp.misc_tests.two_cmd_buffers_primary test.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20617>
Jesse Natalie [Tue, 10 Jan 2023 16:15:12 +0000 (08:15 -0800)]
dzn: Fix format support checks for storage/uniform texel buffers
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20617>
Jesse Natalie [Tue, 10 Jan 2023 00:46:14 +0000 (16:46 -0800)]
dzn: Disable depth when the rasterizer is disabled due to no position output
D3D considers the rasterizer enabled if there's a pixel shader *or* if
depth is enabled, since you can do depth-only rendering. After parsing
shaders, if we find that there was supposed to be a pixel shader, but
we removed it because there was no output position, disable depth too.
Also, store this info in the cache, since we might not even load the
nir shaders if we'd seen this pipeline before.
Fixes dEQP-VK.synchronization.internally_synchronized_objects.pipeline_cache_graphics
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20617>
Jesse Natalie [Tue, 10 Jan 2023 00:45:45 +0000 (16:45 -0800)]
dzn: Add a zeroed zsa state when depth or raster is disabled
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20617>
Jesse Natalie [Tue, 10 Jan 2023 00:44:02 +0000 (16:44 -0800)]
dzn: Always align cached pipeline header size to input element align
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20617>
Jesse Natalie [Mon, 9 Jan 2023 20:43:46 +0000 (12:43 -0800)]
dzn: Support unnormalized coordinate samplers
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20617>
Jesse Natalie [Mon, 9 Jan 2023 20:43:16 +0000 (12:43 -0800)]
dzn: Support root signature 1.2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20617>
Jesse Natalie [Mon, 9 Jan 2023 20:41:46 +0000 (12:41 -0800)]
dzn: Define a symbol that was present in older D3D headers
D3D12_BARRIER_SYNC_INPUT_ASSEMBLER was renamed to D3D12_BARRIER_SYNC_INDEX_INPUT,
so conditionally define the old name based on the version of the headers that are
being used.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20617>
EmperorPenguin18 [Mon, 16 Jan 2023 01:48:03 +0000 (20:48 -0500)]
v3d: expose more drm formats with SAND128 modifier
Adds four more PIPE_FORMATs that expose BROADCOM_SAND128. This allows mpv
to do hardware decoding on the Raspberry Pi 4.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7944
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20510>
Rob Clark [Sat, 7 Jan 2023 16:01:27 +0000 (08:01 -0800)]
freedreno/a6xx: Rework barrier handling
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20575>
Rob Clark [Sat, 7 Jan 2023 19:28:20 +0000 (11:28 -0800)]
freedreno: Don't re-install a flushed batch
The compute path does this save/restore dance with the current batch, so
various things called to emit state can assume ctx->batch is the current
thing. But during resource tracking, which could have flushed what was
previously the current batch. Fixes a problem that surfaces in the next
patch when we stop just flushing batches for all the barriers.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20575>
Rob Clark [Fri, 6 Jan 2023 15:37:37 +0000 (07:37 -0800)]
freedreno/a6xx: Workaround for no pos/psize
The hw seems unhappy if there are zero outputs from the last geometry
stage. So add a dummy varying as a workaround. Turnip got a similar
workaround in commit
d6d75fcd915 ("tu: Fix hangs for DS with no output")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20575>
Rob Clark [Tue, 3 Jan 2023 22:23:28 +0000 (14:23 -0800)]
freedreno: Fix tracking of enabled SSBOs
Clearing all of the modified bits an relying on OR'ing the needed bits
back in the loop below doesn't quite work out, Because of early continue
if the SSBO has not changed.
Fixes:
0ed053f03d9 ("freedreno: simplify fd_set_shader_buffers(..)")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20575>
Rob Clark [Fri, 6 Jan 2023 19:51:32 +0000 (11:51 -0800)]
freedreno/drm: Remove assert
We can hit this scenario if there is a GPU hang before the userspace
fence writeback happens. Since we have asserts enabled in CI, just
remove this assert.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20575>
Gert Wollny [Tue, 17 Jan 2023 08:31:16 +0000 (09:31 +0100)]
r600/sfn: Do a bit of cleanup with the secondary read port validation
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20739>
Gert Wollny [Tue, 17 Jan 2023 08:03:26 +0000 (09:03 +0100)]
r600/sfn: Fix readport check
We have to take multi-slot instructions into account, and we don't fail
when there are still possible bank swizzle values to be checked.
For clarity also rename the bank swizzle iterator iterator.
Fixes:
79ca456b4837b3bc21cf9ef3c03c505c4b4909f6
r600/sfn: rewrite NIR backend
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20739>
Rhys Perry [Wed, 16 Nov 2022 20:08:22 +0000 (20:08 +0000)]
radv/gfx11: expose shaderBufferFloat32AtomicAdd
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19810>
Rhys Perry [Tue, 17 Jan 2023 16:19:58 +0000 (16:19 +0000)]
radv: load ssbo_atomic_fadd descriptor
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19810>
Rhys Perry [Wed, 16 Nov 2022 20:08:07 +0000 (20:08 +0000)]
aco: add support for fp32 addition atomics
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19810>
Rhys Perry [Wed, 16 Nov 2022 20:07:53 +0000 (20:07 +0000)]
ac/llvm: add support for fp32 addition atomics
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19810>
José Roberto de Souza [Mon, 22 Aug 2022 21:12:46 +0000 (14:12 -0700)]
anv: Move anv_device_check_status() code to i915/anv_device.c
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Acked-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20428>
José Roberto de Souza [Fri, 2 Sep 2022 13:55:22 +0000 (06:55 -0700)]
anv: Split i915 code from anv_batch_chain.c
There is no change in behavior here.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Acked-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20428>
José Roberto de Souza [Mon, 21 Nov 2022 19:45:21 +0000 (11:45 -0800)]
anv: Export anv_exec_batch_debug() and chain_command_buffers()
This functions will be used by i915 and Xe KMD.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Acked-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20428>
José Roberto de Souza [Wed, 5 Oct 2022 18:01:32 +0000 (11:01 -0700)]
anv: Start to move i915 specific code from anv_device to i915/anv_device
More code re-organization to separate i915_drm.h specific code from
the rest.
No behavior changes here.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Acked-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20428>
Gert Wollny [Tue, 17 Jan 2023 11:27:57 +0000 (12:27 +0100)]
virgl: drop the separable flag for cases that can't be handled
The host can't assign more than 32 locations explicitly, and we
exhaust this already when we handle patches and generics. So
drop the separable flag in cases when we have other IO that
uses generated names that will have to be matched by name.
v2: skip tests for VS input and FS outputs
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20738>
Rob Clark [Tue, 17 Jan 2023 16:00:54 +0000 (08:00 -0800)]
freedreno/ci: Add an a618 flake
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20749>
Rob Clark [Tue, 17 Jan 2023 15:28:11 +0000 (07:28 -0800)]
Revert "freedreno/ci: Switch a630 jobs over to manual"
This reverts commit
0cc3701338178bf45f4e6d2d496646b6dec7b297.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20749>
Rob Clark [Tue, 17 Jan 2023 15:27:51 +0000 (07:27 -0800)]
Revert "freedreno/ci: Switch also performance a630 job to manual"
This reverts commit
3be7a28b24256e4bdc4fe4ba6428ef767c7bd287.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20749>
Lionel Landwerlin [Wed, 21 Dec 2022 17:22:46 +0000 (19:22 +0200)]
intel: use a shared UUID with other drivers
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20408>
Tapani Pälli [Mon, 16 Jan 2023 11:09:23 +0000 (13:09 +0200)]
intel/compiler: add cpp_std=c++17 when building tests
Otherwise build fails:
"../src/intel/compiler/brw_private.h:40:4: note:
‘std::variant’ is only available from C++17 onwards"
Fixes:
6c194ddd18f ("intel/compiler: Prepare SIMD selection helpers to handle different prog_datas")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20725>
Gert Wollny [Thu, 24 Nov 2022 16:09:42 +0000 (17:09 +0100)]
virgl: Request setting the atomic offset in the range_base
With that NTT can encode the array base of atomic arrays separately
so that the host driver can address the arrays correctly.
Fixes GL-CTS: KHR-Single-GL43.arrays_of_arrays_gl.AtomicUsage
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19980>
Gert Wollny [Thu, 24 Nov 2022 12:26:17 +0000 (13:26 +0100)]
virgl: lower image variable offsets into the intrinsic range_base value
With that we get the correct base offset when accessing image arrays.
This is required if there a various images with different access
specifiers, because only with the correct base offset the host driver is
able to pick the right array.
Fixes GL-CTS: KHR-GL43.shading_language_420pack.binding_image_array
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19980>
Gert Wollny [Thu, 24 Nov 2022 16:08:18 +0000 (17:08 +0100)]
ntt: Make use of the range_base offset when translating atomics in NTT
v2: Unconditionally add teh range base, it is properly initialized.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19980>
Gert Wollny [Thu, 24 Nov 2022 12:23:50 +0000 (13:23 +0100)]
ntt: handle the image intrinsic range_base when translating to TGSI
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19980>
Gert Wollny [Thu, 24 Nov 2022 16:03:38 +0000 (17:03 +0100)]
nir: Add range_base to atomic_counter and an option to use it
Some drivers may encode constant offsets in the instruction, so
make it possible for the drivers to request lowering the atomic
uniform offset into the range_base variable of the intrinsic.
v2: drop patch to use build-in array offset evaluation, it makes
problems with zink, and update the code accordingly
v3: always initialize range base
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19980>
Gert Wollny [Thu, 24 Nov 2022 12:23:06 +0000 (13:23 +0100)]
nir: Add possibility to store image var offset in range_base
Add the intrinsic range_base value to the image intrinsics and add
the option to store the image array offset into range_base instead
of adding it to the image array index if the driver requests it.
v2: Always initialize range_base
v3: fix for bindless intrinsics
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19980>
Jesse Natalie [Sat, 7 Jan 2023 00:37:38 +0000 (16:37 -0800)]
dzn: Use typeless format for creation of depth-only or stencil-only D24S8
When querying capabilities or creating views using a scoped aspect
mask, we want to return the format for the correct single-channel
format, but when actually creating the resource (aspect mask 0),
we want to use the typeless format, since the single-channel formats
don't report multisampling support.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
Jesse Natalie [Fri, 6 Jan 2023 22:45:34 +0000 (14:45 -0800)]
dzn: Set MultisampleEnable to enable MSAA lines
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
Jesse Natalie [Fri, 6 Jan 2023 21:17:10 +0000 (13:17 -0800)]
dzn: Storage buffer sizes need to be 4-byte-aligned
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
Jesse Natalie [Thu, 5 Jan 2023 23:39:16 +0000 (15:39 -0800)]
dzn: Support int border colors
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
Jesse Natalie [Thu, 5 Jan 2023 17:49:25 +0000 (09:49 -0800)]
dzn: Use R24G8_TYPELESS for 24/8 depth resources
This is the same that was already being done for R32G8X24, not sure
why it was missed for R24G8.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
Jesse Natalie [Thu, 5 Jan 2023 17:22:21 +0000 (09:22 -0800)]
dzn: When changing root signature, dirty descriptors too
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
Jesse Natalie [Wed, 4 Jan 2023 21:22:18 +0000 (13:22 -0800)]
dzn: Support alpha blend factor
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
Jesse Natalie [Wed, 4 Jan 2023 21:22:10 +0000 (13:22 -0800)]
dzn: Get options13
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
Jesse Natalie [Thu, 5 Jan 2023 19:30:33 +0000 (11:30 -0800)]
spirv2dxil: Replace not-provided inputs with zero instead of undef
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
Jesse Natalie [Thu, 5 Jan 2023 19:30:29 +0000 (11:30 -0800)]
spirv2dxil: Allow killing position as an undef varying
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
Jesse Natalie [Thu, 5 Jan 2023 17:38:17 +0000 (09:38 -0800)]
spirv2dxil: When removing unused inputs, make sure they're actually inputs
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
Jesse Natalie [Thu, 5 Jan 2023 00:01:49 +0000 (16:01 -0800)]
spirv2dxil: For removing unused vars, consider the whole I/O var size
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
Jesse Natalie [Thu, 5 Jan 2023 19:02:57 +0000 (11:02 -0800)]
microsoft/compiler: Set num_components to 4 when updating pos write instructions
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
Jesse Natalie [Thu, 5 Jan 2023 18:36:27 +0000 (10:36 -0800)]
microsoft/compiler: Use nir info.fs.uses_sample_shading to force sample-rate
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
Jesse Natalie [Thu, 5 Jan 2023 18:19:29 +0000 (10:19 -0800)]
microsoft/compiler: Re-work the logic for adding SV_SampleIndex to force sample-rate
Only add SV_SampleIndex if there exists a sample-rate var that has either flat
interpolation or centroid (and therefore can't force sample rate implicitly),
unless there is also a sample-rate var that doesn't have those properties.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
Jesse Natalie [Thu, 5 Jan 2023 00:01:12 +0000 (16:01 -0800)]
microsoft/compiler: Always emit float types in the I/O signature for structs
There's VK tests that have mismatching interpolation specifiers between FS
and the previous stage. For structs, that resulted in different types, which
breaks DXIL validation.
We could link the shaders and have that overwrite the interpolation field from
the previous shader, but we could also just not care and always use float.
I don't see any regressions from that.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
Jesse Natalie [Thu, 5 Jan 2023 00:00:44 +0000 (16:00 -0800)]
microsoft/compiler: Remove arrays when testing for structs in I/O
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
Jesse Natalie [Wed, 4 Jan 2023 23:06:54 +0000 (15:06 -0800)]
microsoft/compiler: Implement texture sample count query
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
Jesse Natalie [Wed, 4 Jan 2023 22:52:35 +0000 (14:52 -0800)]
microsoft/compiler: Lower pack_[u/s]norm_2x16
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>