Evan Quan [Tue, 2 Jun 2020 09:48:11 +0000 (17:48 +0800)]
drm/amd/powerplay: update how to use metrics table on Arcturus
Retrieve only those interested metrics data instead of the whole
metrics table. By this, the memory copy can be dropped.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Flora Cui [Fri, 5 Jun 2020 07:12:24 +0000 (15:12 +0800)]
drm/amd/display: drop duplicated .dsc_pg_control for dcn30
There're 2 .dsc_pg_control, drop the first one.
.dsc_pg_control = NULL,
.dsc_pg_control = dcn20_dsc_pg_control,
Signed-off-by: Flora Cui <flora.cui@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Flora Cui [Fri, 5 Jun 2020 06:13:26 +0000 (14:13 +0800)]
drm/amd/display: drop duplicated structure
struct gpu_info_voltage_scaling_v1_0 & gpu_info_soc_bounding_box_v1_0 is
defined in amdgpu_socbb.h
Signed-off-by: Flora Cui <flora.cui@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Wed, 3 Jun 2020 04:33:18 +0000 (12:33 +0800)]
drm/amd/powerplay: update driver if file for sienna_cichlid
Update sienna_cichlid driver if header file to match pptable changes.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Tue, 2 Jun 2020 09:15:20 +0000 (17:15 +0800)]
drm/amd/powerplay: update powerplay table for sienna_cichlid
Update powerplay table for sienna_cichlid, add set_thermal_range and
get_max_power_limit function for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Tue, 2 Jun 2020 09:11:58 +0000 (17:11 +0800)]
drm/amd/powerplay: add smu v11_0_7 pptable
Add smu_v11_0_7_pptable.h for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Tue, 2 Jun 2020 08:29:08 +0000 (16:29 +0800)]
drm/amd/powerplay: move powerplay table operation out of smu_v11_0.c
move smu_v11_0_get_max_power_limit and smu_v11_0_set_thermal_range
function from smu_v11_0.c to asic specific _ppt.c to avoid powerplay
table conflict with different ASIC with smu11.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Stanley.Yang [Thu, 14 May 2020 08:44:42 +0000 (16:44 +0800)]
drm/amdgpu: support reserve bad page for virt (v3)
v1: rename some functions name, only init ras error handler data for
supported asic.
v2: fix potential memory leak.
Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 3 Jun 2020 03:45:49 +0000 (11:45 +0800)]
drm/amd/powerplay: use work queue to perform throttling logging
As IO operations(access to SMU internals) and possible sleep are
involved in throttling logging. Workqueue can handle them well.
Otherwise we may hit "scheduling while atomic" error.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Nirmoy Das <nirmoy.das@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 1 Jun 2020 10:31:20 +0000 (18:31 +0800)]
drm/amd/powerplay: skip BACO feature on DPMs disablement
Instead of disabling and reenabling it later.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 1 Jun 2020 06:03:57 +0000 (14:03 +0800)]
drm/amd/powerplay: add firmware cleanup on sw_fini
To avoid possible memory leak.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 1 Jun 2020 05:08:56 +0000 (13:08 +0800)]
drm/amd/powerplay: move amdgpu_irq_src to the smu structure allocation
Rather than allocating it dynamically at runtime considering it is only
several bytes in size.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 4 Jun 2020 04:00:11 +0000 (12:00 +0800)]
drm/amd/powerplay: maximize code sharing between .hw_fini and .suspend
Thus redundant code can be dropped.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 4 Jun 2020 03:50:39 +0000 (11:50 +0800)]
drm/amd/powerplay: better namings
And some minor changes as dropping unused parameter and label
internal used API as static.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 4 Jun 2020 03:42:08 +0000 (11:42 +0800)]
drm/amd/powerplay: sort those operations performed in hw setup
Those common operations(for all ASICs) are placed first and followed
by ASIC specific ones. While the display related are placed at the last.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 4 Jun 2020 03:35:45 +0000 (11:35 +0800)]
drm/amd/powerplay: maximize code sharing between .hw_init and .resume
Then redundant code can be dropped.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 4 Jun 2020 03:25:28 +0000 (11:25 +0800)]
drm/amd/powerplay: move those operations not needed for resume out
Since smu_smc_table_hw_init() is needed for both .hw_init and .resume.
By doing this, we can drop unnecessary operations on resume.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 4 Jun 2020 03:15:12 +0000 (11:15 +0800)]
drm/amd/powerplay: postpone operations not required for hw setup to late_init
So that we do not need to perform those unnecessary operations again on
resume.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 29 May 2020 06:07:41 +0000 (14:07 +0800)]
drm/amd/powerplay: clean up the overdrive settings
Eliminate the buffer allocation and drop the unnecessary
overdrive table uploading.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 28 May 2020 10:50:00 +0000 (18:50 +0800)]
drm/amd/powerplay: clean up the APIs for pptable setup
Combine and simplify the logics for setup pptable.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 28 May 2020 10:41:28 +0000 (18:41 +0800)]
drm/amd/powerplay: clean up the APIs for bootup clocks
Combine and simplify the logics for retrieving bootup
clocks.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 28 May 2020 08:55:08 +0000 (16:55 +0800)]
drm/amd/powerplay: centralize all buffer allocation in sw_init phase
To fit common design. And this can simplify the buffer deallocation.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 3 Jun 2020 10:09:01 +0000 (18:09 +0800)]
drm/amd/powerplay: implement a common API for dpms disablement
So that code can be shared between .hw_fini and .suspend.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 3 Jun 2020 10:06:02 +0000 (18:06 +0800)]
drm/amd/powerplay: drop unused APIs and unnecessary checks
Minor code cleanups.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 8 Jun 2020 22:05:34 +0000 (18:05 -0400)]
drm/amd/powerplay: eliminate asic type check
The macros check if the asic has the callback.
So no need to explicitly check.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Colin Ian King [Thu, 4 Jun 2020 10:35:44 +0000 (11:35 +0100)]
drm/amd/display: fix spelling mistake: "propogation" -> "propagation"
There is a spelling mistake in a dml_print message. Fix it.
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 2 Jun 2020 21:22:48 +0000 (17:22 -0400)]
drm/amdgpu/display: use blanked rather than plane state for sync groups
We may end up with no planes set yet, depending on the ordering, but we
should have the proper blanking state which is either handled by either
DPG or TG depending on the hardware generation. Check both to determine
the proper blanked state.
Bug: https://gitlab.freedesktop.org/drm/amd/issues/781
Fixes:
5fc0cbfad45648 ("drm/amd/display: determine if a pipe is synced by plane state")
Cc: nicholas.kazlauskas@amd.com
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Wed, 3 Jun 2020 00:42:33 +0000 (20:42 -0400)]
drm/amd/display: Revalidate bandwidth before commiting DC updates
[Why]
Whenever we switch between tiled formats without also switching pixel
formats or doing anything else that recreates the DC plane state we
can run into underflow or hangs since we're not updating the
DML parameters before committing to the hardware.
[How]
If the update type is FULL then call validate_bandwidth again to update
the DML parmeters before committing the state.
This is basically just a workaround and protective measure against
update types being added DC where we could run into this issue in
the future.
We can only fully validate the state in advance before applying it to
the hardware if we recreate all the plane and stream states since
we can't modify what's currently in use.
The next step is to update DM to ensure that we're creating the plane
and stream states for whatever could potentially be a full update in
DC to pre-emptively recreate the state for DC global validation.
The workaround can stay until this has been fixed in DM.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 2 Jun 2020 18:51:36 +0000 (14:51 -0400)]
drm/amdgpu/fence: use the no_scheduler flag
Rather than checking the ring type manually. We already set
this for MES and KIQ (and a few other special cases).
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 2 Jun 2020 19:08:39 +0000 (15:08 -0400)]
Revert "drm/[radeon|amdgpu]: Replace one-element array and use struct_size() helper"
This reverts commit
4541ea81edde6ce9a1d9be082489aca7e8e7e1dc.
This changes structs used by the hardware and breaks dpm on some cards.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Wed, 3 Jun 2020 13:32:10 +0000 (09:32 -0400)]
drm/amd/display: Only actually breakpoint if DEBUG_KERNEL_DC is enabled
To match previous behavior and to not hang the kernel if someone
accidentally builds with KGDB enabled.
Fixes:
1aad7078191116f ("drm/amd/display: Make BREAK_TO_DEBUGGER() a debug print")
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Mon, 1 Jun 2020 02:51:34 +0000 (10:51 +0800)]
drm/amd/powerplay: use existed smu_dpm_set* interfaces to implement powergate functions
Abstract powergate_vcn/jpeg functions, using smu_dpm_set* to implement it.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tianci.Yin [Wed, 3 Jun 2020 02:05:22 +0000 (10:05 +0800)]
drm/amdgpu: temporarily read bounding box from gpu_info fw for navi12
The bounding box is still needed by Navi12, temporarily read it from gpu_info
firmware. Should be droped when DAL no longer needs it.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Thu, 21 May 2020 16:57:54 +0000 (12:57 -0400)]
drm/amd/display: Add DCN3 to Kconfig
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Mon, 25 May 2020 17:18:16 +0000 (13:18 -0400)]
drm/amd/display: Add DCN3 blocks to Makefile
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 3 Jun 2020 17:59:16 +0000 (13:59 -0400)]
drm/amdgpu/display: fix build without CONFIG_DRM_AMD_DC_DCN3_0
Need to guard some new DCN3.0 stuff.
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dmytro Laktyushkin [Mon, 27 Apr 2020 18:55:08 +0000 (14:55 -0400)]
drm/amd/display: fix and simplify pipe split logic for DCN3
This was done already done for other DCN blocks.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Thu, 21 May 2020 16:57:27 +0000 (12:57 -0400)]
drm/amdgpu: Enable DM block for DCN3
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Thu, 21 May 2020 19:35:27 +0000 (15:35 -0400)]
drm/amd/display: Remove Unused Registers
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Thu, 21 May 2020 17:00:08 +0000 (13:00 -0400)]
drm/amd/display: Handle RGBE_ALPHA Pixel Format
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Mon, 25 May 2020 16:44:21 +0000 (12:44 -0400)]
drm/amd/display: Init function tables for DCN3
Initilize function tables for hw programing
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Mon, 25 May 2020 17:15:04 +0000 (13:15 -0400)]
drm/amd/display: Add DCN3 VPG
Video Package generator.
used to prepare avi info, DP info etc
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Thu, 21 May 2020 16:56:17 +0000 (12:56 -0400)]
drm/amd/display: Add DCN3 AFMT
Audio formating
Audio related code for setup/control
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Thu, 21 May 2020 16:58:56 +0000 (12:58 -0400)]
drm/amd/display: Add DCN3 Command Table Helpers
-Handle DCN3 cases for bios parser and command tables
-Add command function tables for DCN3
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Thu, 21 May 2020 16:51:51 +0000 (12:51 -0400)]
drm/amd/display: Add DCN3 Resource
Add support for managing resources for DCN3
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Thu, 21 May 2020 16:48:41 +0000 (12:48 -0400)]
drm/amd/display: Add DCN3 Support in DM (v2)
Handle DCN3 in amdgpu_dm
v2: fix num_pkrs handling
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Thu, 21 May 2020 16:45:45 +0000 (12:45 -0400)]
drm/amd/display: Add DCN3 HWSEQ
Add HW sequence programing for DCN3
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Fri, 29 May 2020 19:06:16 +0000 (15:06 -0400)]
drm/amd/display: Add DCN3 DMUB
DMUB (Display Micro-Controller Unit)
Used to read/write regs
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Thu, 21 May 2020 16:31:21 +0000 (12:31 -0400)]
drm/amd/display: Add DCN3 GPIO
Add support to program GPIO HW block
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Thu, 21 May 2020 16:30:35 +0000 (12:30 -0400)]
drm/amd/display: Add DCN3 IRQ
Add IWQ services for DCN3,
This allows us to create/init and manage irqs for DCN3
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Thu, 21 May 2020 16:29:44 +0000 (12:29 -0400)]
drm/amd/display: Add DCN3 DML
Add support for DML(Display mode library) for bandwidth calculations
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Thu, 21 May 2020 16:42:30 +0000 (12:42 -0400)]
drm/amd/display: Add DCN3 DWB
Add support to program the DCN3 DWB (Display Writeback)
HW Blocks:
+--------++------+ +----------+
| HUBBUB || HUBP | <-- | MMHUBBUB |
+--------++------+ +----------+
| ^
v |
+--------+ +--------+
| DPP | | DWB |
+--------+ +--------+
|
v ^
+--------+ |
| MPC | |
+--------+ |
| |
v |
+-------+ |
| OPP | |
+-------+ |
| |
v |
+--------+ /
| OPTC | --------------
+--------+
|
v
+--------+ +--------+
| DIO | | DCCG |
+--------+ +--------+
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Thu, 21 May 2020 16:36:30 +0000 (12:36 -0400)]
drm/amd/display: Add DCN3 MMHUBHUB
Add support to program the DCN3 MMHUBBUB (Multimedia HUB interface)
HW Blocks:
+--------++------+ +----------+
| HUBBUB || HUBP | <-- | MMHUBBUB |
+--------++------+ +----------+
|
v
+--------+
| DPP |
+--------+
|
v
+--------+
| MPC |
+--------+
|
v
+-------+
| OPP |
+-------+
|
v
+--------+
| OPTC |
+--------+
|
v
+--------+ +--------+
| DIO | | DCCG |
+--------+ +--------+
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Thu, 21 May 2020 16:44:03 +0000 (12:44 -0400)]
drm/amd/display: Add DCN3 HUBP
Add support to program the DCN3 HUBP (Display to data fabric interface
pipe)
HW Blocks:
+--------++------+
| HUBBUB || HUBP |
+--------++------+
|
v
+--------+
| DPP |
+--------+
|
v
+--------+
| MPC |
+--------+
|
v
+-------+
| OPP |
+-------+
|
v
+--------+
| OPTC |
+--------+
|
v
+--------+ +--------+
| DIO | | DCCG |
+--------+ +--------+
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Thu, 21 May 2020 16:37:22 +0000 (12:37 -0400)]
drm/amd/display: Add DCN3 HUBHUB
Add support to program the HUBBUB (DCN memory HUB interface)
HW Blocks:
+--------+
| HUBBUB |
+--------+
|
v
+--------+
| DPP |
+--------+
|
v
+--------+
| MPC |
+--------+
|
v
+-------+
| OPP |
+-------+
|
v
+--------+
| OPTC |
+--------+
|
v
+--------+ +--------+
| DIO | | DCCG |
+--------+ +--------+
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Thu, 21 May 2020 16:35:22 +0000 (12:35 -0400)]
drm/amd/display: Add DCN3 DPP
Add support to program the DCN3 DPP (Multiple pipe and plane combine)
HW Blocks:
+--------+
| DPP |
+--------+
|
v
+--------+
| MPC |
+--------+
|
v
+-------+
| OPP |
+-------+
|
v
+--------+
| OPTC |
+--------+
|
v
+--------+ +--------+
| DIO | | DCCG |
+--------+ +--------+
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Thu, 21 May 2020 16:38:55 +0000 (12:38 -0400)]
drm/amd/display: Add DCN3 MPC
Add support to program the DCN3 MPC (Multiple pipe and plane combine)
HW Blocks:
+--------+
| MPC |
+--------+
|
v
+-------+
| OPP |
+-------+
|
v
+--------+
| OPTC |
+--------+
|
v
+--------+ +--------+
| DIO | | DCCG |
+--------+ +--------+
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Fri, 22 May 2020 21:22:00 +0000 (17:22 -0400)]
drm/amd/display: Add DCN3 OPP header
Add support to program the DCN3 OPP (Output Plane Processing)
HW Blocks:
+-------+
| OPP |
+-------+
|
v
+--------+
| OPTC |
+--------+
|
v
+--------+ +--------+
| DIO | | DCCG |
+--------+ +--------+
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Thu, 21 May 2020 16:43:28 +0000 (12:43 -0400)]
drm/amd/display: Add DCN3 OPTC
Add support for programming the DCN3 OPTC (Output Timing Controller)
HW Blocks:
+--------+
| OPTC |
+--------+
|
v
+--------+ +--------+
| DIO | | DCCG |
+--------+ +--------+
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Thu, 21 May 2020 16:38:30 +0000 (12:38 -0400)]
drm/amd/display: Add DCN3 DCCG
Add programming of the DCCG (Display Controller Clock Generator)
block:
HW Blocks:
+--------+ +--------+
| DIO | | DCCG |
+--------+ +--------+
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Thu, 21 May 2020 16:32:53 +0000 (12:32 -0400)]
drm/amd/display: Add DCN3 CLK_MGR
Adds support for handling of clocking relevant to the DCN3 block
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Fri, 22 May 2020 18:38:38 +0000 (14:38 -0400)]
drm/amd/display: Add DCN3 DIO
Add support for the DIO (Display IO) block of DCN3, which entails our
stream and link encoders.
HW Blocks:
+--------+
| DIO |
+--------+
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Thu, 21 May 2020 16:28:39 +0000 (12:28 -0400)]
drm/amd/display: Add DCN3 chip ids
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Tue, 26 May 2020 08:54:44 +0000 (16:54 +0800)]
drm/amdgpu: bypass tmr when reserve c2p memory
C2P memory reserved should not in tmr memory range.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Fri, 22 May 2020 06:42:35 +0000 (14:42 +0800)]
drm/amdgpu: remove unnecessary check for mem train
a.Check whether mem train support when try to reserve related memory.
b.Remove ASIC check and atom firmware table version check as the check
of firmware capability is enough to achieve that purpose.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Thu, 21 May 2020 07:35:46 +0000 (15:35 +0800)]
drm/amdgpu: support memory training for sienna_cichlid
Add memory training support for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Thu, 21 May 2020 02:33:15 +0000 (10:33 +0800)]
drm/amdgpu: reserve fb according to return value from vbios
Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards
for all the use cases (IP discovery/G6 memory
training/profiling/diagnostic data.etc), otherwise, fallback to legacy
approach to check and reserve tmr block for ip discovery data and G6
memory training data respectively
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 29 May 2020 18:38:53 +0000 (14:38 -0400)]
drm/amd/powerplay: let PMFW to handle the features disablement on BACO in V2
For Sienna_Cichlid, PMFW will handle the features disablement on BACO in. No
need to have driver stepped in.
V2: limit this for baco really
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Mon, 18 May 2020 10:44:10 +0000 (18:44 +0800)]
drm/amd/powerplay: drop sienna_cichlid hardcode of using pptable
Drop the hardcode of sienna_cichlid which will force to use softpptable,
so that it can use pptable on vbios once the value of pp_table_id get
from vbios is 0.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Wed, 13 May 2020 12:24:53 +0000 (20:24 +0800)]
drm/amd/powerplay: update smu function for sienna_cichlid
Add function to check whether baco is support for sienna cichlid.
Remove fucntion of get clock by type with latency as it will not be
called.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Fri, 8 May 2020 06:39:27 +0000 (14:39 +0800)]
drm/amdgpu: update golden setting for sienna_cichlid
Update golden setting for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Wed, 6 May 2020 08:19:41 +0000 (16:19 +0800)]
drm/amdgpu/psp: support for loading PSP SPL fw
Add support for loading SPL firmware.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Wed, 6 May 2020 08:16:08 +0000 (16:16 +0800)]
drm/amdgpu/psp: initialization PSP SPL fw
Support for psp firmware header version v1_3 initialization and
information print.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Wed, 6 May 2020 06:57:13 +0000 (14:57 +0800)]
drm/amdgpu/psp: add structure to support PSP SPL
Add support for PSP SPL (Security patch level) table to support
anti-rollback of FW loaded by Trusted OS.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kenneth Feng [Thu, 7 May 2020 06:33:06 +0000 (14:33 +0800)]
drm/amd/powerplay: show gfxclk=0 in gfxoff state
The instant retrieved gfxclk value should be 0 in gfxoff state.
This can be fetched with gfxoff enabled.
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Fri, 29 May 2020 18:34:15 +0000 (14:34 -0400)]
drm/amdgpu: enable gfxoff for sienna_cichlid
Enable GFXOFF for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Mon, 20 Apr 2020 15:37:07 +0000 (23:37 +0800)]
drm/amd/amdgpu: disable gfxoff to retrieve gfxclk
For Sienna_Cichlid, GFXOFF state puts gfx dpm into standby mode, then the
gfxclk can't be retireved.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Tue, 28 Apr 2020 08:42:30 +0000 (16:42 +0800)]
drm/amd/powerplay: support mclk socclk limit value set for sienna_cichlid.
Add support to force and unforce MCLK or SOCCLK to dpm limit value.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
shaoyunl [Mon, 27 Apr 2020 15:53:00 +0000 (11:53 -0400)]
drm/amdgpu/sriov : Add sriov detection for sienna_cichlid
This is a regression due to the rebase , add sienna_cichlid sriov detection back
Signed-off-by: shaoyunl <shaoyun.liu@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Fri, 17 Apr 2020 09:33:35 +0000 (17:33 +0800)]
drm/amdgpu: only use one gfx pipe for Sienna_Cichlid
Only enable one gfx pipe for sienna_cichlid currently.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Tue, 21 Apr 2020 02:39:12 +0000 (10:39 +0800)]
drm/amd/powerplay: drop jpeg instance1 dpm setup
VCN removed JPEG for instance 1, so drop jpeg instance1 dpm setup.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Thu, 16 Apr 2020 06:53:08 +0000 (14:53 +0800)]
drm/amdgpu: disable runtime pm for sienna_cichlid temporarily
Disable runtime pm for sienna_cichlid temporarily as BACO regression issue.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kenneth Feng [Thu, 16 Apr 2020 03:56:50 +0000 (11:56 +0800)]
drm/amd/powerplay: enable fw ctf
fw ctf can be triggered if the temperature can't be throttled below the limit.
then the gpu will be powered off and the whole system will hang.
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Wed, 15 Apr 2020 03:33:15 +0000 (11:33 +0800)]
drm/amdgpu: skip GPU scheduler setup for KIQ and MES ring
Fix the coding error to skip GPU scheduler setup for KIQ and MES ring.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Mon, 13 Apr 2020 05:00:56 +0000 (13:00 +0800)]
drm/amd/powerplay: enable VDDCI and MVDD for sienna_cichlid
Enable VDDCI and MVDD if PP_MCLK_DPM_MASK was enable for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Mon, 13 Apr 2020 06:10:17 +0000 (14:10 +0800)]
drm/amd/powerplay: append pptable for sienna_cichlid (v2)
Add function to append powerplay table from vbios for sienna_cichlid.
v2: squash in warning fix
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Fri, 17 Apr 2020 18:03:19 +0000 (14:03 -0400)]
drm/amd/powerplay: and smc dpm info struct for sienna_cichlid
And atom_smc_dpm_info_v4_9 struct for sienna_cichlid use.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
shaoyunl [Thu, 9 Apr 2020 19:53:17 +0000 (15:53 -0400)]
drm/amdgpu/sriov : Use kiq to do tlb invalidation for gfx10 on sriov
On SRIOV run time, driver shouldn't directly access invalidation registers through MMIO.
Use kiq to submit wait_reg_mem package for the invalidation
Signed-off-by: shaoyunl <shaoyun.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Thu, 9 Apr 2020 07:33:53 +0000 (15:33 +0800)]
drm/amd/powerplay: enable ULCK DS for sienna_cichlid
Enable uclk deep sleep for sienna_cichlid.
Df cstate kicks in first, then df triggers uclk ds with the sideband.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 9 Apr 2020 20:08:55 +0000 (16:08 -0400)]
drm/amdgpu/vcn3.0: schedule instance 0 for decode and 1 for encode
VCN3 has 2 unsymmetrical instances, i.e there're less codecs
on instance 1, we use 0 for decode and 1 for encode for now
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 9 Apr 2020 20:03:10 +0000 (16:03 -0400)]
drm/amdgpu/mes10.1: add no scheduler flag for mes
We don't want a gpu scheduler for mes.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Boyuan Zhang [Thu, 2 Apr 2020 17:28:07 +0000 (13:28 -0400)]
drm/amdgpu: enable DPG mode for VCN3.0
Enable DPG mode for VCN3.0 by updating related flag.
V2: update description.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: James Zhu <james.zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Boyuan Zhang [Fri, 27 Mar 2020 17:49:11 +0000 (13:49 -0400)]
drm/amdgpu: add workaround for issue in DPG for VCN3.0
To workaround an issue in DPG
V2: update description.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: James Zhu <james.zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Boyuan Zhang [Mon, 30 Mar 2020 15:05:02 +0000 (11:05 -0400)]
drm/amdgpu: rename macro for VCN2.0 2.5 and 3.0
Rename SOC15_DPG_MODE_OFFSET_2_0, RREG32_SOC15_DPG_MODE_2_0 and
WREG32_SOC15_DPG_MODE_2_0 for VCN2.0, VCN2.5 and VCN3.0.
These three macros are used VCN2.0, VCN2.5 and VCN3.0, therefore rename
it to be a general name.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: James Zhu <james.zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Boyuan Zhang [Fri, 27 Mar 2020 18:11:59 +0000 (14:11 -0400)]
drm/amdgpu: rename macro for VCN1.0
Rename RREG32_SOC15_DPG_MODE and WREG32_SOC15_DPG_MODE for VCN1.0
These two macros are used specifically for VCN1.0, therefore rename
it from general name to VCN1.0 specific name.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: James Zhu <james.zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Boyuan Zhang [Thu, 26 Mar 2020 23:16:43 +0000 (19:16 -0400)]
drm/amdgpu: add internal reg offset translation for VCN inst 1
Add range for vcn instance 1 for translation for internal register offset, which
is needed for VCN3.0
V2: update description.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: James Zhu <james.zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Boyuan Zhang [Thu, 26 Mar 2020 23:11:56 +0000 (19:11 -0400)]
drm/amdgpu: set indirect sram mode for VCN3.0
Use indirect sram for secure DPG mode
V2: update description.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: James Zhu <james.zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Boyuan Zhang [Fri, 27 Mar 2020 17:41:54 +0000 (13:41 -0400)]
drm/amdgpu: add pause DPG mode for VCN3.0
Add vcn_v3_0_pause_dpg_mode to pause/unpause DPG mode for VCN3.0
V2: update description.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: James Zhu <james.zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Boyuan Zhang [Fri, 27 Mar 2020 17:38:54 +0000 (13:38 -0400)]
drm/amdgpu: add stop DPG mode for VCN3.0
Add vcn_v3_0_stop_dpg_mode to power off in DPG mode for VCN3.0
V2: update description.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: James Zhu <james.zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Boyuan Zhang [Fri, 27 Mar 2020 17:30:53 +0000 (13:30 -0400)]
drm/amdgpu: add start DPG mode for VCN3.0
Add vcn_v3_0_start_dpg_mode to setup and start VCN block in DPG mode for VCN3.0
V2: Separate from previous patch-0002, and update description.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: James Zhu <james.zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>