Tom Rini [Fri, 22 Nov 2019 15:41:46 +0000 (10:41 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
- Assorted fixes
Tom Rini [Fri, 22 Nov 2019 15:24:14 +0000 (10:24 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-sh
- Assorted Gen3 fixes
Tom Rini [Fri, 22 Nov 2019 15:20:56 +0000 (10:20 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-usb
- Fix some possible alignment issues
Ooi, Joyce [Thu, 21 Nov 2019 14:06:12 +0000 (06:06 -0800)]
arm: socfpga: stratix10: Add alias for gmac0 in S10 dts
Add 'ethernet0' as alias for 'gmac0' in S10 device tree.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Ooi, Joyce <joyce.ooi@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Ooi, Joyce [Thu, 21 Nov 2019 14:48:56 +0000 (06:48 -0800)]
arm: dts: Stratix10: change pad skew values for EMAC0 PHY driver
The HPS EMAC0 drive strength is changed to 4mA because the initial 8mA
drive strength has caused CE test to fail. This requires changes on the
pad skew for EMAC0 PHY driver. Based on several measurements done, Tx
clock does not require the extra 0.96ns delay which was needed in
Arria10.
Signed-off-by: Ooi, Joyce <joyce.ooi@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Simon Goldschmidt [Thu, 21 Nov 2019 21:15:23 +0000 (22:15 +0100)]
usb: dwc2: fix possible alignment issues
Since upgrading to gcc9, warnings are issued:
"taking address of packed member of ‘...’ may result in an unaligned
pointer value"
Fix this by converting dwc2_fifo_read to use unaligned access since packed
structures may be on an unaligned address, depending on USB hardware.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Simon Goldschmidt [Thu, 21 Nov 2019 21:15:22 +0000 (22:15 +0100)]
usb: composite: fix possible alignment issues
Since upgrading to gcc9, warnings are issued:
"taking address of packed member of ‘...’ may result in an unaligned
pointer value"
Fix this by converting two functions to use unaligned access since packed
structures may be on an unaligned address, depending on USB hardware.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Joe Hershberger [Wed, 20 Nov 2019 22:09:05 +0000 (16:09 -0600)]
Update MAINTAINERS to include environment files
To be maintained by me (Joe) and reviewed by Wolfgang Denk when
available.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Tom Rini [Thu, 21 Nov 2019 13:30:45 +0000 (08:30 -0500)]
configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Thu, 21 Nov 2019 13:25:53 +0000 (08:25 -0500)]
Merge branch '2019-11-20-env-migration'
- Migrate a number of common environment related options to Kconfig
Tom Rini [Tue, 19 Nov 2019 01:02:10 +0000 (20:02 -0500)]
env: Finish migration of common ENV options
- In ARMv8 NXP Layerscape platforms we also need to make use of
CONFIG_SYS_RELOC_GD_ENV_ADDR now, do so.
- On ENV_IS_IN_REMOTE, CONFIG_ENV_OFFSET is never used, drop the define
to 0.
- Add Kconfig entry for ENV_ADDR.
- Make ENV_ADDR / ENV_OFFSET depend on the env locations that use it.
- Add ENV_xxx_REDUND options that depend on their primary option and
SYS_REDUNDAND_ENVIRONMENT
- On a number of PowerPC platforms, use SPL_ENV_ADDR not CONFIG_ENV_ADDR
for the pre-main-U-Boot environment location.
- On ENV_IS_IN_SPI_FLASH, check not for CONFIG_ENV_ADDR being set but
rather it being non-zero, as it will now be zero by default.
- Rework the env_offset absolute in env/embedded.o to not use
CONFIG_ENV_OFFSET as it was the only use of ENV_OFFSET within
ENV_IS_IN_FLASH.
- Migrate all platforms.
Cc: Wolfgang Denk <wd@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: uboot-stm32@st-md-mailman.stormreply.com
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tom Rini [Tue, 19 Nov 2019 01:02:09 +0000 (20:02 -0500)]
T1042RDB_PI_NAND_SECURE_BOOT: Guard t104xrdb SPL env code
We can only configure and set the environment in SPL when we have a
particular environment location set that is not "nowhere" like it is in
SECURE_BOOT designs. Update the code to reflect that.
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Tom Rini [Tue, 19 Nov 2019 01:02:08 +0000 (20:02 -0500)]
fsl: layerscape: guard *env_sf_get_env_addr() on CONFIG_ENV_IS_IN_SPI_FLASH
These functions can only be built and used when we have
ENV_IS_IN_SPI_FLASH, use that as a guard.
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Tue, 19 Nov 2019 01:02:07 +0000 (20:02 -0500)]
env: Remove useless CONFIG_ENV_SIZE_REDUND and fix ENV_IS_REDUND check
We have CONFIG_ENV_SIZE_IS_REDUND but don't really use it. We have one
board where we can simply multiple CONFIG_ENV_SIZE by two for the same
result. The other place where we could but were not previously using
this is for where env_internal.h checks for if we should set
ENV_IS_EMBEDDED. This seems like the most likely use, historically, of
the variable, but it was not used. Add logic to check for this now.
Cc: Wolfgang Denk <wd@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tom Rini [Tue, 19 Nov 2019 01:02:06 +0000 (20:02 -0500)]
smart-gateway-mt7688: Rework build time check for overwriting factory data
The board file has a build time check to ensure that we do not have the
redundant environment overwriting the factory data. However, using the
symbol CONFIG_ENV_SIZE_REDUND isn't strictly needed as that is always
the same as CONFIG_ENV_SIZE. Use CONFIG_ENV_SIZE instead so that we can
later drop CONFIG_ENV_SIZE_REDUND.
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Marek Vasut [Wed, 2 Oct 2019 16:54:45 +0000 (18:54 +0200)]
ARM: socfpga: Fix default mtdparts
The default mtdparts value grew a trailing zero during the Kconfig
conversion. This is because the mtdparts value in the header file
had a \0 at the end, which got misconverted into plain 0 instead of
being dropped.
Signed-off-by: Marek Vasut <marex@denx.de>
Fixes:
43ede0bca7fc ("Kconfig: Migrate MTDIDS_DEFAULT / MTDPARTS_DEFAULT")
Reviewed-by: Tom Rini <trini@konsulko.com>
Simon Goldschmidt [Wed, 20 Nov 2019 21:27:31 +0000 (22:27 +0100)]
spi: cadence_qspi: support DM_CLK
Support loading clk speed via DM instead of requiring ad-hoc code.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Simon Goldschmidt [Wed, 23 Oct 2019 20:23:12 +0000 (22:23 +0200)]
timer: dw-apb: add reset handling
To use this DM timer on socfpga as system tick, it needs to take itself
out of reset.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Simon Goldschmidt [Wed, 23 Oct 2019 20:32:30 +0000 (22:32 +0200)]
socfpga: fix include guard in misc.h (arch vs. global)
The file arch/arm/mach-socfpga/include/mach/misc.h used the same include
guard as the global include/misc.h.
Fix this by giving the arch file an arch prefix.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Simon Goldschmidt [Wed, 23 Oct 2019 20:19:37 +0000 (22:19 +0200)]
ddr: socfpga: gen5: constify altera_gen5_sdram_ops
Make the function pointer struct const, as it does not need to be
writable. This doesn't really change anything other than moving this
variable to a different section. No functional change.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Ley Foon Tan [Fri, 8 Nov 2019 02:58:12 +0000 (10:58 +0800)]
configs: Stratix10: Disable CONFIG_SPL_USE_TINY_PRINTF
Commit
2a51e16bd57a ("configs: Make USE_TINY_PRINTF depend on SPL||TPL and be default")
enable USE_TINY_PRINTF by default, disable it for Stratix10.
Resync with savedefconfig.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Ley Foon Tan [Fri, 8 Nov 2019 02:56:26 +0000 (10:56 +0800)]
arm: dts: Stratix10: Fix memory node address and size cells
Add #address-cells and #size-cells to memory node to fix incorrect memory
size decoding in recent Uboot version.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Tom Rini [Wed, 20 Nov 2019 20:38:51 +0000 (15:38 -0500)]
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx
- Fix CONFIG_AHCI related build warning for P2041, P3041, P5040, T102x,
T104x, T4240 platforms
Tom Rini [Wed, 13 Nov 2019 03:46:36 +0000 (22:46 -0500)]
env: Add CONFIG_SYS_RELOC_GD_ENV_ADDR symbol
Today in initr_reloc_global_data() we use some non-obvious tests to
determine if we need to relocate the env_addr within gd or not. In
order to facilitate migration of other symbols to Kconfig we need to
introduce a new symbol for this particular use case.
Cc: Wolfgang Denk <wd@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sun, 17 Nov 2019 00:48:39 +0000 (19:48 -0500)]
input: Move input.o to be built only in some cases
We only need to build and link input.o when we have any of
CONFIG_KEYBOARD, CONFIG_DM_KEYBOARD (and SPL/TPL variants) or
CONFIG_TEGRA_KEYBOARD set.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Tue, 19 Nov 2019 22:42:46 +0000 (17:42 -0500)]
Merge tag 'efi-2020-01-rc4' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2020-01-rc4
Fix errors due to unaligned memory access:
* disable UEFI except for ARMv8, ARMv7, ARM11
* enable unaligned access support on ARM11
Remove an unused function.
Vignesh Raghavendra [Mon, 18 Nov 2019 13:46:33 +0000 (19:16 +0530)]
usb: cdns3: Fix include file path
xhci.h has now been moved to include/usb/ directory. Therefore, update the
path in the Cadence USB drivers.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Heinrich Schuchardt [Tue, 19 Nov 2019 03:19:09 +0000 (04:19 +0100)]
efi_loader: enable EFI_LOADER on arm1136 and arm1176
With an implementation for allow_unaligned() available for arm1136 and
arm1176 UEFI can be supported on these architectures.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Tue, 19 Nov 2019 03:02:10 +0000 (04:02 +0100)]
arm: arm11: allow unaligned memory access
The UEFI spec mandates that unaligned memory access should be enabled if
supported by the CPU architecture.
This patch implements the function unaligned_access() to set the enable
unaligned data support flag and to clear the aligned flag in the system
control register (SCTLR). It is called when UEFI related commands like
bootefi are invoked.
Reported-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Tested-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Tested-by: Guillaume Gardet <Guillaume.Gardet@arm.com>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Sun, 17 Nov 2019 09:44:16 +0000 (10:44 +0100)]
efi_loader: restrict EFI_LOADER to armv7 and armv8 on ARM
fatload USB was reported to fail on the Sheevaplug. Debugging showed that
this was caused by an incorrect unaligned write to memory in
path_to_uefi().
UEFI on ARM requires that unaligned memory access is enabled.
* ARMv5 does not support unaligned access at all.
* ARMv6 supports unaligned access when we clear the A flag and set the
U flag.
* On ARMv7 unaligned access is possible when clearing the aligned flag,
which we do in function allow_unaligned() (arch/arm/cpu/armv7/sctlr.S).
For none of the other cpus in arch/arm/cpu/ we have implemented a
similar function.
* ARMv8 allows unaligned access.
Let EFI_LOADER on ARM depend on SYS_CPU=armv7 or SYS_CPU=armv8.
Once we have implemented allow_unaligned() for other ARM CPUs we can add
these to Kconfig.
Reported-by: Gray Remlin <gryrmln@gmail.com>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Sun, 10 Nov 2019 01:16:33 +0000 (02:16 +0100)]
efi_loader: remove unused function efi_dp_from_dev()
Function efi_dp_from_dev() is not used anywhere. Remove it.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Peng Ma [Wed, 23 Oct 2019 11:07:13 +0000 (11:07 +0000)]
powerpc: t4240: dts: Add Sata DT nodes
This patch is to add sata node for T4240 platform
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Peng Ma [Wed, 23 Oct 2019 11:07:12 +0000 (11:07 +0000)]
powerpc: t104x: dts: Add Sata DT nodes
This patch is to add sata node for T104x platform
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Peng Ma [Wed, 23 Oct 2019 11:07:11 +0000 (11:07 +0000)]
powerpc: t102x: dts: Add Sata DT nodes
This patch is to add sata node for T102x platform
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Peng Ma [Wed, 23 Oct 2019 11:07:10 +0000 (11:07 +0000)]
powerpc: p5040: dts: Add Sata DT nodes
This patch is to add sata node for P5040 platform
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Peng Ma [Wed, 23 Oct 2019 11:07:09 +0000 (11:07 +0000)]
powerpc: p3041: dts: Add Sata DT nodes
This patch is to add sata node for P3041 platform
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Peng Ma [Wed, 23 Oct 2019 11:07:08 +0000 (11:07 +0000)]
powerpc: p2041: dts: Add Sata DT nodes
This patch is to add sata node for P2041 platform
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Peng Ma [Tue, 19 Nov 2019 06:17:40 +0000 (06:17 +0000)]
ata: sata_sil: Add DM support for Silicon sata driver
Add DM support for Silicon(SIL3131 / SIL3132 / SIL3124) sata driver as
few of the PowerPC platforms such as P series based boards need to
use SATA_SIL with DM,
Also fix below warning while PowerPC P series boards compilation,
===================== WARNING ======================"
This board does use CONFIG_LIBATA but has CONFIG_AHCI not"
enabled. Please update the storage controller driver to use"
CONFIG_AHCI before the v2019.07 release."
Failure to update by the deadline may result in board removal."
See doc/driver-model/MIGRATION.txt for more info."
===================================================="
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Peng Ma [Tue, 19 Nov 2019 06:17:36 +0000 (06:17 +0000)]
ata: fsl_sata: Add DM support for Freescale PowerPC SATA driver
Add DM support for Freescale PowerPC sata driver used for PowerPC T series
SoCs,
CONFIG_BLK needs to be enabled on these platforms. It adds the SATA
controller as AHCI device, which is strictly speaking not correct,
as the controller is not AHCI compatible, But the U-Boot AHCI uclass
interface enables the usage of this DM driver,
Also fix below warning while PowerPC T series boards compilation,
===================== WARNING ======================"
This board does use CONFIG_LIBATA but has CONFIG_AHCI not"
enabled. Please update the storage controller driver to use"
CONFIG_AHCI before the v2019.07 release."
Failure to update by the deadline may result in board removal."
See doc/driver-model/MIGRATION.txt for more info."
===================================================="
Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Tom Rini [Tue, 19 Nov 2019 02:31:49 +0000 (21:31 -0500)]
Prepare v2020.01-rc3
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 18 Nov 2019 15:48:29 +0000 (10:48 -0500)]
Merge tag 'video-for-v2020.01-rc2' of https://gitlab.denx.de/u-boot/custodians/u-boot-video
- fix i.MX6ULL evk black screen observed while reboot stress tests
- remove "synopsys,dw-mipi-dsi" compatible to reduce the device tree
differences between Linux and U-Boot for stm32mp1 platform
Tom Rini [Mon, 18 Nov 2019 02:15:57 +0000 (21:15 -0500)]
Merge tag 'u-boot-rockchip-
20191118' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- Add support for rockchip SoC: PX30, RK3308
- Add and migrate to use common dram driver: PX30, RK3328, RK3399
- Add rk3399 board Tinker-s support
- Board config update for Rock960, Rockpro64
Tom Rini [Mon, 18 Nov 2019 02:15:23 +0000 (21:15 -0500)]
Merge tag 'dm-pull-14nov19' of git://git.denx.de/u-boot-dm
Add OP-TEE test swuit
Fix patman cc_file output
Minor sandbox/pinctrl changes
Michael Trimarchi [Fri, 15 Nov 2019 21:07:24 +0000 (22:07 +0100)]
rockchip: dts: tinker: Add tinker-s board support
Support tinker-s board. The board is equivalent of tinker board
except of emmc.
TODO:
- support of usb current burst when the board is powered from pc
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Michael Trimarchi [Fri, 15 Nov 2019 21:07:23 +0000 (22:07 +0100)]
rockchip: dts: tinker: Move u-boot dmc initialization to specific section
dmc is used to initialize the memory controller. It's needed by
u-boot. Move it in the specific section
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thomas Hebb [Fri, 15 Nov 2019 16:48:57 +0000 (08:48 -0800)]
rockchip: imply instead of selecting SPL_SYS_MALLOC_SIMPLE
We shouldn't force which allocator the SPL uses, since there's no
platform requirement for one over the other: in fact, we currently allow
selection of the TPL allocator but not the SPL one!
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thomas Hebb [Fri, 15 Nov 2019 16:48:56 +0000 (08:48 -0800)]
rockchip: allow DRAM init in SPL
The common SPL removed SoC-specific code for RK3399's SPL and in the
process caused the previously-unconditional DRAM initialization in
board_init_f() to only happen when compiling a configuration that does not
support TPL, meaning DRAM never gets initialized if TPL is supported but
disabled.
Fix this by omitting the DRAM init in SPL only when we are configured to
also build a TPL. This fixes custom configurations that have disabled
TPL, and it should also unbreak the "ficus-rk3399", "rock960-rk3399",
and "chromebook_bob" defconfigs, although since I don't have any of
those devices I can't confirm they're broken now.
Fixes:
b7abef2ecbcc ("rockchip: rk3399: Migrate to use common spl board file")
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thomas Hebb [Fri, 15 Nov 2019 16:48:55 +0000 (08:48 -0800)]
rockchip: SPL: fix ordering of DRAM init
The common SPL code reordered the DRAM initialization before
rockchip_stimer_init(), which as far as I can tell causes the RK3399 to
lock up completely.
Fix this issue in the common code by putting the DRAM init back after
timer init. I have only tested this on the RK3399, but it wouldn't make
any sense for the timer init to require DRAM be set up on any system.
Fixes:
b7abef2ecbcc ("rockchip: rk3399: Migrate to use common spl board file")
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Andy Yan [Thu, 14 Nov 2019 03:23:17 +0000 (11:23 +0800)]
doc: rockchip: Add documentation for rk3308 based boards
Add build documentation for rk3308 based boards.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Andy Yan [Thu, 14 Nov 2019 03:23:02 +0000 (11:23 +0800)]
rockchip: rk3308: Add support for ROC-RK3308-CC board
ROC-RK3308-CC is a rk3308 based board designed by
Firelfy, with eMMC and 256MB DDR3 and RTL8188 Wifi
on board.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Andy Yan [Thu, 14 Nov 2019 03:22:47 +0000 (11:22 +0800)]
rockchip: rk3308: Add dts for ROC-RK3308-CC
Add dts file for ROC-RK3308-CC from firefly.
Sync form linux rockchip for v5.5-armsoc/dts64:
"arm64: dts: rockchip: Add devicetree for board roc-rk3308-cc"
(sha1:
4403e1237be3af0977aa23ef399e3496316317a0)
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Andy Yan [Thu, 14 Nov 2019 03:22:34 +0000 (11:22 +0800)]
rockchip: mkimage: add support for RK3308
Usage:
(1) tools/mkimage -n rk3308 -T rksd -d tpl/u-boot-tpl.bin idbloader.img
(2) cat spl/u-boot-spl.bin >> idbloader.img
(3) upgrade_tool wl 0x40 idbloader.img
Note:
When use ddr binary from rkbin as tpl, use it replace u-boot-tpl.bin in(1)
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Andy Yan [Thu, 14 Nov 2019 03:22:18 +0000 (11:22 +0800)]
rockchip: rk3308: Add sdram driver
A dm based dram driver for rk3308 u-boot
to get capacity.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Andy Yan [Thu, 14 Nov 2019 03:21:15 +0000 (11:21 +0800)]
board: rockchip: Add rk3308 evb support
Add support for rk3308 evaluation board.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Andy Yan [Thu, 14 Nov 2019 03:21:14 +0000 (11:21 +0800)]
arm: dts: rockchip: Add dts for rk3308 evb
Add dts for rk3308 evb, sync from the linux kernel
upstream list [0].
[0]https://patchwork.kernel.org/patch/
11201555/
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Finley Xiao [Thu, 14 Nov 2019 03:21:13 +0000 (11:21 +0800)]
rockchip: clk: Add clk driver for rk3308
Add clk controller driver for RK3308 SOC.
This patch depends on Elaine's pll patch[0].
[0]http://patchwork.ozlabs.org/patch/1183718/
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Andy Yan [Thu, 14 Nov 2019 03:21:12 +0000 (11:21 +0800)]
arm: rockchip: Add RK3308 SOC support
RK3308 is a quad Cortex A35 based SOC with rich audio
interfaces(I2S/PCM/TDM/PDM/SPDIF/VAD/HDMI ARC), which
designed for intelligent voice interaction and audio
input/output processing.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Elaine Zhang [Fri, 25 Oct 2019 01:42:17 +0000 (09:42 +0800)]
rockchip: clk: pll: add common pll setting funcs
Common PLL setup function, compatible with different SOC.
Mainly for the subsequent new SOC use.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Wed, 13 Nov 2019 03:14:12 +0000 (11:14 +0800)]
rockchip: rk3399: orangepi: Add init value for vdd_log
We should set the init value when vdd_log is enabled, or else the
vdd_log output voltage may not in soc required range.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Wed, 13 Nov 2019 03:14:11 +0000 (11:14 +0800)]
rockchip: rk3399: khadas-edge: Add init value for vdd_log
We should set the init value when vdd_log is enabled, or else the
vdd_log output voltage may not in soc required range.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Wed, 13 Nov 2019 03:14:10 +0000 (11:14 +0800)]
rockchip: rk3399: rock-pi4: Add init value for vdd_log
We should set the init value when vdd_log is enabled, or else the
vdd_log output voltage may not in soc required range.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Wed, 13 Nov 2019 03:14:09 +0000 (11:14 +0800)]
arm64: dts: rk3399-rock960: add vdd_log and its init value
Add vdd_log node according to rock960 schematic V13.
This patch affect two boards:
- Rock960 Model A
- Ficus
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Peter Robinson [Sat, 9 Nov 2019 20:30:07 +0000 (20:30 +0000)]
rockchip: dts: rk3399-firefly: move u-boot, spl-boot-order to to the u-boot.dtsi
The u-boot specific device tree directives should be in u-boot.dtsi
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Peter Robinson [Sat, 9 Nov 2019 20:30:06 +0000 (20:30 +0000)]
rockchip: dts: rk3399-evb: move u-boot, spl-boot-order to to the u-boot.dtsi
The u-boot specific device tree directives should be in u-boot.dtsi
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Peter Robinson [Sat, 9 Nov 2019 20:30:05 +0000 (20:30 +0000)]
rockchip: dts: rk3399: move the u-boot, dm-pre-reloc to the u-boot.dtsi
The u-boot specific pieces in the dts files should be in u-boot.dtsi
not the main files, this allows easier sync with upstream. The
rk3399.dtsi has a mix of both so move them all for consistency.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(Fix with missing pmugrf)
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Vasily Khoruzhick [Sat, 9 Nov 2019 19:24:50 +0000 (11:24 -0800)]
rockchip: rk3399: split rockpro64 out of evb_rk3399
rockpro64 needs to setup I/O domains in order for USB to work in u-boot.
Since we currently don't have a driver to do that, split it into its own
board file and initialize I/O domains here.
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stuebner [Fri, 8 Nov 2019 23:06:30 +0000 (00:06 +0100)]
rockchip: clk: fix wrong CONFIG_IS_ENABLED handling
CONFIG_IS_ENABLED() needs the config name like used in Kconfig, so
without the leading CONFIG_. The clock drivers all wrongly check for
CONFIG_RESET_ROCKCHIP, fix that
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stuebner [Fri, 8 Nov 2019 23:06:29 +0000 (00:06 +0100)]
rockchip: clk: rv1108: remove duplicate reset init
rockchip_reset_bind() already does the needed init for the reset
registers, only referenced the wrong cru structure.
So we can get rid of the open-coded reset init and just fix
the correct cru reference.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Soeren Moch [Thu, 7 Nov 2019 11:11:22 +0000 (12:11 +0100)]
arm: dts: rk3399-rockpro64: slightly increase center voltage
The rk3399 VD_CENTER voltage domain is not subject to dynamic voltage
scaling. So the regulator reset voltage of 0.9V is used on this board.
Let u-boot initialize the center voltage to 0.95V as it is done for the
VD_LOGIC domain. This avoids instability and occasional linux kernel
Opses on this board.
Signed-off-by: Soeren Moch <smoch@web.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Soeren Moch [Thu, 7 Nov 2019 11:11:21 +0000 (12:11 +0100)]
arm: dts: rk3399-rockpro64: sync dts from linux kernel
The most important change for u-boot is the fix for the vdd-log pwm
voltage regulator to avoid overvoltage for the VD_LOGIC power domain.
Signed-off-by: Soeren Moch <smoch@web.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Peter Robinson [Wed, 6 Nov 2019 11:43:05 +0000 (11:43 +0000)]
rockchip: rk3399: rock960: Update config for TPL
Enable TPL for rock960 like other rk3399 boards.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Sat, 2 Nov 2019 04:49:02 +0000 (10:19 +0530)]
configs: Rename roc-rk3399-pc -> roc-pc-rk3399 defconfig
roc-rk3399-pc_defconfig is committed in below
commit <
8a681f4c5aa15db51ad0209734859c9fe7c29cfd> ("rockchip: rk3399:
Add ROC-RK3399-PC support")
which doesn't follow the existing defconfigs on rk3399.
So, rename as followed with other rk3399 defconfigs.
Cc: Levin Du <djw@t-chip.com.cn>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Wed, 16 Oct 2019 15:19:40 +0000 (20:49 +0530)]
arm: dts: rk3399-roc-pc: Sync latest dts changes from Linux
Few important regulator power rails fixes are available in
linux-next, so sync them same.
Here is the last commit details:
commit <
9f7f9b610e1b7d2dc86c543ab0dfcf781bd42326> ("arm64: dts:
rockchip: Fix roc-rk3399-pc regulator input rails")
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Levin Du <djw@t-chip.com.cn>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Wed, 16 Oct 2019 09:13:32 +0000 (17:13 +0800)]
rockchip: Init driver otg_data for rk3288 usb phy
RK3288 needs to init the otg_data in board level to make the phy driver
work.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Wed, 16 Oct 2019 09:13:31 +0000 (17:13 +0800)]
rockchip: usb: Migrate to use ofnode
Migrate to use ofnode_* instead of fdt_* so that we may able to use live
dt for usb udc driver.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stuebner [Tue, 16 Jul 2019 20:19:43 +0000 (22:19 +0200)]
rockchip: add px30-evb board
The px30 evb is an evaluation board for the px30 together with a dsi-
connected display. This adds board and config files for it.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stuebner [Tue, 16 Jul 2019 20:18:21 +0000 (22:18 +0200)]
rockchip: add px30 architecture core
Add core architecture code to support the px30 soc.
This includes a separate tpl board file due to very limited
sram size as well as a non-dm sdram driver, as this also has
to fit into the tiny sram.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stuebner [Tue, 16 Jul 2019 20:12:07 +0000 (22:12 +0200)]
rockchip: add px30 devicetrees
Add px30 related devicetrees synced from the Linux kernel.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stuebner [Wed, 25 Sep 2019 18:21:21 +0000 (20:21 +0200)]
rockchip: misc: read cpuid either from efuse or otp
Newer Rockchip socs use a different ip block to handle one-time-
programmable memory, so depending on what got enabled get the cpuid
from either source.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Finley Xiao [Wed, 25 Sep 2019 15:57:49 +0000 (17:57 +0200)]
misc: add driver for the Rockchip otp controller
Newer Rockchip socs like the px30 use a different ip block to handle
one-time-programmable memory, so add a misc driver for it as well.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Fri, 12 Jul 2019 09:43:34 +0000 (11:43 +0200)]
rockchip: mkimage: add support for px30
Add the table entry for px30 socs.
The px30 has 10K of sram available.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stuebner [Tue, 23 Jul 2019 23:20:29 +0000 (01:20 +0200)]
net: gmac_rockchip: add support for px30
Add the glue code to allow the px30 variant of the Rockchip gmac
to provide network functionality.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Thu, 11 Jul 2019 08:42:16 +0000 (10:42 +0200)]
rockchip: clk: add px30 clock driver
The px30 contains 2 separate clock controllers, pmucru and cru.
Add drivers for them.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
David Wu [Thu, 11 Jul 2019 08:37:14 +0000 (10:37 +0200)]
pinctrl: rockchip: add px30 pinctrl driver
Add the necessary glue code to allow pinctrl setting on px30 socs.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stuebner [Tue, 16 Jul 2019 20:17:13 +0000 (22:17 +0200)]
rockchip: add core px30 headers
Add headers needed by the upcoming px30 support, including two
new dt-binding headers taken from the Linux kernel.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Stuebner [Tue, 16 Jul 2019 08:12:02 +0000 (10:12 +0200)]
spl: separate SPL_FRAMEWORK config for spl and tpl
Right now enabling SPL_FRAMEWORK will also enable it for the TPL in all
cases, making the TPL bigger. There may be cases where the TPL is really
size constrained due to its underlying ram size.
Therefore introduce a new TPL_FRAMEWORK option and make the relevant
conditionals check for both. The default is set to "y if SPL_FRAMEWORK"
to mimic the previous behaviour where the TPL would always get the
SPL framework if it was enabled in SPL.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
YouMin Chen [Fri, 15 Nov 2019 03:04:53 +0000 (11:04 +0800)]
ram: rk3399: Fix dram setting to make dram more stable
There are some code different with rockchip vendor code which may lead
to different bugs, including:
1) Fix setting error about LPDDR3 dram size ODT.
2) Set phy io speed to 0x2.
3) Fix setting error about phy_pad_fdbk_drive.
4) Fix setting error about PI_WDQLVL_VREF_EN
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Fri, 15 Nov 2019 03:04:52 +0000 (11:04 +0800)]
ram: rk3399: update calculate_stride
Update the calculation of the stride to support all the DRAM case.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Fri, 15 Nov 2019 03:04:51 +0000 (11:04 +0800)]
ram: rk3399: Sync the io setting from Rockchip vendor code
The io setting are updated after some bugfix in different rk3399 boards,
sync the code from vendor.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Fri, 15 Nov 2019 03:04:50 +0000 (11:04 +0800)]
ram: rockchip: update lpddr4 timing for rk3399
Update lpddr timing in lpddr4-400 and lpddr4-800 file from rockchip
vendor code;
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
YouMin Chen [Fri, 15 Nov 2019 03:04:49 +0000 (11:04 +0800)]
ram: rk3399: add support detect capacity
Add capacity detect for rk3399 so that the driver able to detect the
capacity automatically.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
YouMin Chen [Fri, 15 Nov 2019 03:04:48 +0000 (11:04 +0800)]
ram: rk3399: update the function of sdram_init
Clean up the sdram_init to keep sync with rockchip source code.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
YouMin Chen [Fri, 15 Nov 2019 03:04:47 +0000 (11:04 +0800)]
ram: rk3399: fix error about get_ddrc0_con reg addr
Correct the register to its correct name.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
YouMin Chen [Fri, 15 Nov 2019 03:04:46 +0000 (11:04 +0800)]
ram: rk3399: Clean up code
Clean up rk3399 dram driver source code for more readable.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
YouMin Chen [Fri, 15 Nov 2019 03:04:45 +0000 (11:04 +0800)]
ram: rk3399: migrate to use common code
For there are some structures and functions are common for all rockchip SoCs,
migrate to use the common code so that we can clean up reduandent codes.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
YouMin Chen [Fri, 15 Nov 2019 03:04:44 +0000 (11:04 +0800)]
ram: rk3328: use common sdram driver
RK3328 has a similar controller and phy with PX30, so we can use the
common driver for it and remove the duplicate codes.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
YouMin Chen [Fri, 15 Nov 2019 03:04:43 +0000 (11:04 +0800)]
ram: px30: add sdram driver
Add the sdram driver for PX30 to support ddr3, ddr4, lpddr2 and lpddr3.
For TPL_BUILD, the driver implement full dram init and without DM
support due to the limit of internal SRAM size.
For SPL and U-Boot proper, it's a simple driver with dm for get
dram_info like other SoCs.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Fri, 15 Nov 2019 03:04:42 +0000 (11:04 +0800)]
ram: rockchip: add common msch reg definition
The noc register bit definition may be the same for different SoC while
the offset of the register may be different, add the struction
definition as common code.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Fri, 15 Nov 2019 03:04:41 +0000 (11:04 +0800)]
ram: rockchip: add phy driver code for PX30
This sdram_phy_px30.c is based on PX30 SoC, the functions are common
for phy, other SoCs with similar hardware could re-use it.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Fri, 15 Nov 2019 03:04:40 +0000 (11:04 +0800)]
ram: rockchip: add controller code for PX30
This sdram_pctl_px30.c is based on PX30 SoC, the functions are common
for controller, other SoCs with similar hardware could re-use it.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>