Merge branches 'clk-kirkwood', 'clk-imx', 'clk-doc', 'clk-zynq' and 'clk-ralink' into clk-next

* clk-kirkwood:
  clk: kirkwood: Fix a clocking boot regression

* clk-imx:
  clk: imx8mn: Add M7 core clock
  clk: imx8m: fix clock tree update of TF-A managed clocks
  clk: imx: clk-divider-gate: Switch to clk_divider.determine_rate
  clk: imx8mn: use correct mux type for clkout path
  clk: imx8mm: use correct mux type for clkout path

* clk-doc:
  dt-bindings: clock: samsung: fix header path in example
  MAINTAINERS: clock: include S3C and S5P in Samsung SoC clock entry
  dt-bindings: clock: samsung: convert S5Pv210 AudSS to dtschema
  dt-bindings: clock: samsung: convert Exynos AudSS to dtschema
  dt-bindings: clock: samsung: convert Exynos4 to dtschema
  dt-bindings: clock: samsung: convert Exynos3250 to dtschema
  dt-bindings: clock: samsung: convert Exynos542x to dtschema
  dt-bindings: clock: samsung: add bindings for Exynos external clock
  dt-bindings: clock: samsung: convert Exynos5250 to dtschema
  dt-bindings: clock: brcm,iproc-clocks: fix armpll properties
  clk: zynqmp: Fix kernel-doc format
  clk: at91: sama7g5: remove all kernel-doc & kernel-doc warnings
  clk: zynqmp: fix kernel doc

* clk-zynq:
  clk: zynqmp: Fix a memory leak
  clk: zynqmp: Check the return type

* clk-ralink:
  clk: ralink: avoid to set 'CLK_IS_CRITICAL' flag for gates

Merge branches 'clk-nvidia', 'clk-rockchip', 'clk-at91' and 'clk-vc5' into clk-next

 - Support the SD/OE pin on IDT VersaClock 5 and 6 clock generators

* clk-nvidia:
  clk: tegra: fix old-style declaration
  clk: tegra: Remove CLK_IS_CRITICAL flag from fuse clock
  soc/tegra: fuse: Enable fuse clock on suspend for Tegra124
  soc/tegra: fuse: Add runtime PM support
  soc/tegra: fuse: Clear fuse->clk on driver probe failure
  soc/tegra: pmc: Prevent racing with cpuilde driver
  soc/tegra: bpmp: Remove unused including <linux/version.h>

* clk-rockchip:
  clk: rockchip: make rk3308 ddrphy4x clock critical
  clk: rockchip: drop GRF dependency for rk3328/rk3036 pll types
  dt-bindings: clk: Convert rockchip,rk3399-cru to DT schema
  clk: rockchip: Add support for hclk_sfc on rk3036
  clk: rockchip: rk3036: fix up the sclk_sfc parent error
  clk: rockchip: add dt-binding clkid for hclk_sfc on rk3036

* clk-at91:
  clk: at91: clk-generated: Limit the requested rate to our range

* clk-vc5:
  clk: vc5: Add properties for configuring SD/OE behavior
  clk: vc5: Use dev_err_probe
  dt-bindings: clk: vc5: Add properties for configuring the SD/OE pin

Merge branch 'clk-frac-divider' into clk-next

 - Add power of two flag to fractional divider clk type

* clk-frac-divider:
  clk: fractional-divider: Document the arithmetics used behind the code
  clk: fractional-divider: Introduce POWER_OF_TWO_PS flag
  clk: fractional-divider: Hide clk_fractional_divider_ops from wide audience
  clk: fractional-divider: Export approximation algorithm to the CCF users

Merge branches 'clk-renesas', 'clk-cleanup' and 'clk-determine-divider' into clk-next

 - Migrate some clk drivers to clk_divider_ops.determine_rate

* clk-renesas:
  clk: renesas: Make CLK_R9A06G032 invisible
  clk: renesas: r9a07g044: Add entry for fixed clock P0_DIV2
  dt-bindings: clock: r9a07g044-cpg: Add entry for P0_DIV2 core clock
  clk: renesas: r9a07g044: Add clock and reset entries for ADC
  clk: renesas: r9a07g044: Add clock and reset entries for CANFD
  clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch]
  clk: renesas: r9a07g044: Add GPIO clock and reset entries
  clk: renesas: r9a07g044: Add SSIF-2 clock and reset entries
  clk: renesas: r9a07g044: Add USB clocks/resets
  clk: renesas: r9a07g044: Add DMAC clocks/resets
  clk: renesas: r9a07g044: Add I2C clocks/resets
  clk: renesas: r8a779a0: Add the DSI clocks
  clk: renesas: r8a779a0: Add the DU clock
  clk: renesas: rzg2: Rename i2c-dvfs to iic-pmic
  clk: renesas: rzg2l: Fix off-by-one check in rzg2l_cpg_clk_src_twocell_get()
  clk: renesas: rzg2l: Avoid mixing error pointers and NULL
  clk: renesas: rzg2l: Fix a double free on error
  clk: renesas: rzg2l: Fix return value and unused assignment
  clk: renesas: rzg2l: Remove unneeded semicolon

* clk-cleanup:
  clk: palmas: Add a missing SPDX license header
  clk: Align provider-specific CLK_* bit definitions

* clk-determine-divider:
  clk: stm32mp1: Switch to clk_divider.determine_rate
  clk: stm32h7: Switch to clk_divider.determine_rate
  clk: stm32f4: Switch to clk_divider.determine_rate
  clk: bcm2835: Switch to clk_divider.determine_rate
  clk: divider: Implement and wire up .determine_rate by default

Merge branches 'clk-qcom', 'clk-socfpga', 'clk-mediatek', 'clk-lmk' and 'clk-x86' into clk-next

 - Support video, gpu, display clks on qcom sc7280 SoCs
 - GCC clks on qcom MSM8953, SM4250/6115, and SM6350 SoCs
 - Multimedia clks (MMCC) on qcom MSM8994/MSM8992
 - Migrate to clk_parent_data in gcc-sdm660
 - RPMh clks on qcom SM6350 SoCs
 - Support for Mediatek MT8192 SoCs

* clk-qcom: (38 commits)
  clk: qcom: Add SM6350 GCC driver
  dt-bindings: clock: Add SM6350 GCC clock bindings
  clk: qcom: rpmh: Add support for RPMH clocks on SM6350
  dt-bindings: clock: Add RPMHCC bindings for SM6350
  clk: qcom: adjust selects for SM_VIDEOCC_8150 and SM_VIDEOCC_8250
  clk: qcom: Add Global Clock controller (GCC) driver for SM6115
  dt-bindings: clk: qcom: gcc-sm6115: Document SM6115 GCC
  clk: qcom: mmcc-msm8994: Add MSM8992 support
  clk: qcom: Add msm8994 MMCC driver
  dt-bindings: clock: Add support for MSM8992/4 MMCC
  clk: qcom: Add Global Clock Controller driver for MSM8953
  dt-bindings: clock: add Qualcomm MSM8953 GCC driver bindings
  clk: qcom: gcc-sdm660: Replace usage of parent_names
  clk: qcom: gcc-sdm660: Move parent tables after PLLs
  clk: qcom: use devm_pm_runtime_enable and devm_pm_clk_create
  PM: runtime: add devm_pm_clk_create helper
  PM: runtime: add devm_pm_runtime_enable helper
  clk: qcom: a53-pll: Add MSM8939 a53pll support
  dt-bindings: clock: Update qcom,a53pll bindings for MSM8939 support
  clk: qcom: a53pll/mux: Use unique clock name
  ...

* clk-socfpga:
  clk: socfpga: agilex: add the bypass register for s2f_usr0 clock
  clk: socfpga: agilex: fix up s2f_user0_clk representation
  clk: socfpga: agilex: fix the parents of the psi_ref_clk

* clk-mediatek: (22 commits)
  clk: mediatek: make COMMON_CLK_MT8167* depend on COMMON_CLK_MT8167
  clk: mediatek: Add MT8192 vencsys clock support
  clk: mediatek: Add MT8192 vdecsys clock support
  clk: mediatek: Add MT8192 scp adsp clock support
  clk: mediatek: Add MT8192 msdc clock support
  clk: mediatek: Add MT8192 mmsys clock support
  clk: mediatek: Add MT8192 mfgcfg clock support
  clk: mediatek: Add MT8192 mdpsys clock support
  clk: mediatek: Add MT8192 ipesys clock support
  clk: mediatek: Add MT8192 imp i2c wrapper clock support
  clk: mediatek: Add MT8192 imgsys clock support
  clk: mediatek: Add MT8192 camsys clock support
  clk: mediatek: Add MT8192 audio clock support
  clk: mediatek: Add MT8192 basic clocks support
  clk: mediatek: Add mtk_clk_simple_probe() to simplify clock providers
  clk: mediatek: Add configurable enable control to mtk_pll_data
  clk: mediatek: Fix asymmetrical PLL enable and disable control
  clk: mediatek: Get regmap without syscon compatible check
  clk: mediatek: Add dt-bindings of MT8192 clocks
  dt-bindings: ARM: Mediatek: Add audsys document binding for MT8192
  ...

* clk-lmk:
  clk: lmk04832: drop redundant fallthrough statements

* clk-x86:
  clk: x86: Rename clk-lpt to more specific clk-lpss-atom

dt-bindings: clock: samsung: fix header path in example

The proper header is exynos4.h:

    samsung,exynos4412-isp-clock.example.dts:19:18: fatal error: dt-bindings/clock/exynos4412.h: No such file or directory

Fixes: 7ac615780926 ("dt-bindings: clock: samsung: convert Exynos4 to dtschema")
Reported-by: Stephen Boyd <sboyd@kernel.org>
Reported-by: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20210831130643.83249-1-krzysztof.kozlowski@canonical.com
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: tegra: fix old-style declaration

With extra warnings enabled, gcc complains about a slightly odd
prototype:

drivers/clk/tegra/clk-dfll.c:1380:1: error: 'inline' is not at beginning of declaration [-Werror=old-style-declaration]
 1380 | static void inline dfll_debug_init(struct tegra_dfll *td) { }

Move the 'inline' keyword to the start of the line.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20210322215047.1062540-1-arnd@kernel.org
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: qcom: Add SM6350 GCC driver

This adds Global Clock controller (GCC) driver for SM6350 SoC

Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210820203624.232268-3-konrad.dybcio@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

MAINTAINERS: clock: include S3C and S5P in Samsung SoC clock entry

Cover the S3C and S5Pv210 clock controller binding headers by Samsung
SoC clock controller drivers maintainer entry.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20210825134251.220098-3-krzysztof.kozlowski@canonical.com
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

dt-bindings: clock: samsung: convert S5Pv210 AudSS to dtschema

Convert Samsung S5Pv210 Audio SubSystem clock controller bindings to DT
schema format using json-schema.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20210825134251.220098-2-krzysztof.kozlowski@canonical.com
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

dt-bindings: clock: samsung: convert Exynos AudSS to dtschema

Convert Samsung Exynos Audio SubSystem clock controller bindings to DT
schema format using json-schema.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20210825134251.220098-1-krzysztof.kozlowski@canonical.com
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

dt-bindings: clock: samsung: convert Exynos4 to dtschema

Merge Exynos4210 and Exynos4412 clock controller bindings to existing DT
schema.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20210825134056.219884-6-krzysztof.kozlowski@canonical.com
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

dt-bindings: clock: samsung: convert Exynos3250 to dtschema

Merge Exynos3250 clock controller bindings to existing DT schema.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210825134056.219884-5-krzysztof.kozlowski@canonical.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

dt-bindings: clock: samsung: convert Exynos542x to dtschema

Merge Exynos542x clock controller bindings to existing DT schema.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20210825134056.219884-4-krzysztof.kozlowski@canonical.com
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

dt-bindings: clock: samsung: add bindings for Exynos external clock

Document the bindings for Samsung Exynos external to SoC
(oscclk/XXTI/XusbXTI) clock provided on boards.  The bindings are
already implemented in most of the Exynos clock drivers and DTS files.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210825134056.219884-3-krzysztof.kozlowski@canonical.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

dt-bindings: clock: samsung: convert Exynos5250 to dtschema

Convert Samsung Exynos5250 clock controller bindings to DT schema format
using json-schema.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20210825134056.219884-2-krzysztof.kozlowski@canonical.com
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: vc5: Add properties for configuring SD/OE behavior

The SD/OE pin may be configured to enable output when high or low, and
to shutdown the device when high. This behavior is controller by the SH
and SP bits of the Primary Source and Shutdown Register (and to a lesser
extent the OS and OE bits). By default, both bits are 0 (unless set by
OTP memory), but they may need to be configured differently, depending
on the external circuitry controlling the SD/OE pin.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Link: https://lore.kernel.org/r/20210809223813.3766204-3-sean.anderson@seco.com
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: vc5: Use dev_err_probe

Convert uses of dev_err (+ return) to dev_err_probe.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
Link: https://lore.kernel.org/r/20210809223813.3766204-2-sean.anderson@seco.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

dt-bindings: clk: vc5: Add properties for configuring the SD/OE pin

These properties allow configuring the SD/OE pin as described in the
datasheet.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
Link: https://lore.kernel.org/r/20210809223813.3766204-1-sean.anderson@seco.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

dt-bindings: clock: brcm,iproc-clocks: fix armpll properties

armpll clocks (available on Cygnus and Northstar Plus) are simple clocks
with no cells. Adjust binding props #clock-cells and clock-output-names
to handle them.

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Link: https://lore.kernel.org/r/20210819052918.6753-1-zajec5@gmail.com
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: zynqmp: Fix kernel-doc format

Align structure and function names with definitions.

Issues are reported by kernel-doc script as:
drivers/clk/zynqmp/clk-gate-zynqmp.c:24: warning: expecting prototype for
struct clk_gate. Prototype was for struct zynqmp_clk_gate instead
drivers/clk/zynqmp/clk-gate-zynqmp.c:75: warning: expecting prototype for
zynqmp_clk_gate_is_enable(). Prototype was for zynqmp_clk_gate_is_enabled()
instead

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/26526e144296373b2c75e75865dd023158f9bfc7.1629718424.git.michal.simek@xilinx.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: at91: clk-generated: Limit the requested rate to our range

On clk_generated_determine_rate(), the requested rate could be outside
of clk's range. Limit the rate to the clock's range to not return an
error.

Fixes: df70aeef6083 ("clk: at91: add generated clock driver")
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
Link: https://lore.kernel.org/r/20210707131213.3283509-1-codrin.ciubotariu@microchip.com
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: ralink: avoid to set 'CLK_IS_CRITICAL' flag for gates

'clk_init_data' for gates is setting up 'CLK_IS_CRITICAL'
flag for all of them. This was being doing because some
drivers of this SoC might not be ready to use the clock
and we don't wanted the kernel to disable them since default
behaviour without clock driver was to set all gate bits to
enabled state. After a bit more testing and checking driver
code it is safe to remove this flag and just let the kernel
to disable those gates that are not in use. No regressions
seems to appear.

Fixes: 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210727055537.11785-1-sergio.paracuellos@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: zynqmp: Fix a memory leak

Fix a memory leak of mux.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Link: https://lore.kernel.org/r/20210818065929.12835-3-shubhrajyoti.datta@xilinx.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: zynqmp: Check the return type

Currently the return value of of_clk_add_hw_provider is ignored.
lets check and return value.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Link: https://lore.kernel.org/r/20210818065929.12835-2-shubhrajyoti.datta@xilinx.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: at91: sama7g5: remove all kernel-doc & kernel-doc warnings

Remove all "/**" kernel-doc markers from sama7g5.c since they are
all internal to this driver source file only.
This eliminates 14 warnings that were reported by the kernel test robot.

Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Reported-by: kernel test robot <lkp@intel.com>
Cc: Claudiu Beznea <claudiu.beznea@microchip.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: linux-clk@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lore.kernel.org/r/20210819223237.20115-1-rdunlap@infradead.org
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: zynqmp: fix kernel doc

Add missing description of 'custom_type_flag' structure member.

Fixes: e605fa9c4a0c ("clk: zynqmp: Add support for custom type flags")
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Link: https://lore.kernel.org/r/1629720433-19019-1-git-send-email-rajan.vaja@xilinx.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

Merge tag 'clk-imx-5.15' of git://git./linux/kernel/git/abelvesa/linux into clk-imx

Pull i.MX clock driver updates from Abel Vesa

 - Fix CLKOUT clocks on i.MX8MM and i.MX8MN by using imx_clk_hw_mux2
 - Switch from .round_rate to .determine_rate in clk-divider-gate
 - Fix clock tree update for TF-A controlled clocks for all i.MX8M
 - Add missing M7 core clock for i.MX8MN

* tag 'clk-imx-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux:
  clk: imx8mn: Add M7 core clock
  clk: imx8m: fix clock tree update of TF-A managed clocks
  clk: imx: clk-divider-gate: Switch to clk_divider.determine_rate
  clk: imx8mn: use correct mux type for clkout path
  clk: imx8mm: use correct mux type for clkout path

clk: kirkwood: Fix a clocking boot regression

Since a few kernel releases the Pogoplug 4 has crashed like this
during boot:

Unable to handle kernel NULL pointer dereference at virtual address 00000002
(...)
[<c04116ec>] (strlen) from [<c00ead80>] (kstrdup+0x1c/0x4c)
[<c00ead80>] (kstrdup) from [<c04591d8>] (__clk_register+0x44/0x37c)
[<c04591d8>] (__clk_register) from [<c04595ec>] (clk_hw_register+0x20/0x44)
[<c04595ec>] (clk_hw_register) from [<c045bfa8>] (__clk_hw_register_mux+0x198/0x1e4)
[<c045bfa8>] (__clk_hw_register_mux) from [<c045c050>] (clk_register_mux_table+0x5c/0x6c)
[<c045c050>] (clk_register_mux_table) from [<c0acf3e0>] (kirkwood_clk_muxing_setup.constprop.0+0x13c/0x1ac)
[<c0acf3e0>] (kirkwood_clk_muxing_setup.constprop.0) from [<c0aceae0>] (of_clk_init+0x12c/0x214)
[<c0aceae0>] (of_clk_init) from [<c0ab576c>] (time_init+0x20/0x2c)
[<c0ab576c>] (time_init) from [<c0ab3d18>] (start_kernel+0x3dc/0x56c)
[<c0ab3d18>] (start_kernel) from [<00000000>] (0x0)
Code: e3130020 1afffffb e12fff1e c08a1078 (e5d03000)

This is because the "powersave" mux clock 0 was provided in an unterminated
array, which is required by the loop in the driver:

        /* Count, allocate, and register clock muxes */
        for (n = 0; desc[n].name;)
                n++;

Here n will go out of bounds and then call clk_register_mux() on random
memory contents after the mux clock.

Fix this by terminating the array with a blank entry.

Fixes: 105299381d87 ("cpufreq: kirkwood: use the powersave multiplexer")
Cc: stable@vger.kernel.org
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Gregory CLEMENT <gregory.clement@bootlin.com>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20210814235514.403426-1-linus.walleij@linaro.org
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

dt-bindings: clock: Add SM6350 GCC clock bindings

Add device tree bindings for global clock controller on SM6350 SoC.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210820203624.232268-2-konrad.dybcio@somainline.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: qcom: rpmh: Add support for RPMH clocks on SM6350

Add support for RPMH clocks on SM6350 SoCs.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210820203243.230157-3-konrad.dybcio@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

dt-bindings: clock: Add RPMHCC bindings for SM6350

Add bindings and update documentation for clock rpmh driver on SM6350.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210820203243.230157-2-konrad.dybcio@somainline.org
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: qcom: adjust selects for SM_VIDEOCC_8150 and SM_VIDEOCC_8250

Commit 5658e8cf1a8a ("clk: qcom: add video clock controller driver for
SM8150") and commit 0e94711a1f29 ("clk: qcom: add video clock controller
driver for SM8250") add config SM_VIDEOCC_8150 and config SM_VIDEOCC_8250,
which select the non-existing configs SDM_GCC_8150 and SDM_GCC_8250,
respectively.

Hence, ./scripts/checkkconfigsymbols.py warns:

SDM_GCC_8150
Referencing files: drivers/clk/qcom/Kconfig

SDM_GCC_8250
Referencing files: drivers/clk/qcom/Kconfig

It is probably just a typo (or naming confusion of using SM_GCC_xxx and
SDM_GCC_xxx for various Qualcomm clock drivers) in the config definitions
for config SM_VIDEOCC_8150 and SM_VIDEOCC_8250, and intends to select the
existing SM_GCC_8150 and SM_GCC_8250, respectively.

Adjust the selects to the existing configs.

Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Link: https://lore.kernel.org/r/20210816135930.11810-1-lukas.bulwahn@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: qcom: Add Global Clock controller (GCC) driver for SM6115

Add support for the global clock controller found on SM6115
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.

Based on CAF implementation. GDSCs ported from downstream DT.

Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
Link: https://lore.kernel.org/r/20210805161107.1194521-3-iskren.chernev@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

dt-bindings: clk: qcom: gcc-sm6115: Document SM6115 GCC

Add device tree bindings for global clock controller on SM6115 and
SM4250 SoCs (pin and software compatible).

Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
Link: https://lore.kernel.org/r/20210805161107.1194521-2-iskren.chernev@gmail.com
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: qcom: mmcc-msm8994: Add MSM8992 support

MSM8992 features less clocks & GDSCS and has different
freq tables for some of them.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210618111435.595689-3-konrad.dybcio@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: qcom: Add msm8994 MMCC driver

Add a driver for managing MultiMedia SubSystem clocks on msm8994
and its derivatives.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210618111435.595689-2-konrad.dybcio@somainline.org
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

dt-bindings: clock: Add support for MSM8992/4 MMCC

Document the multimedia clock controller found on MSM8992/4.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210618111435.595689-1-konrad.dybcio@somainline.org
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: qcom: Add Global Clock Controller driver for MSM8953

This driver provides clocks, resets and power domains for MSM8953
and compatible SoCs: APQ8053, SDM450, SDA450, SDM632, SDA632.

Signed-off-by: Vladimir Lypak <junak.pub@gmail.com>
Signed-off-by: Adam Skladowski <a_skl39@protonmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Sireesh Kodali <sireeshkodali@protonmail.com>
Link: https://lore.kernel.org/r/IPvVnyRWbHuQFswiFz0W08Kj1dKoH55ddQVyIIPhMJw@cp7-web-043.plabs.ch
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

dt-bindings: clock: add Qualcomm MSM8953 GCC driver bindings

Add bindings and compatible to document MSM8953 GCC (Global Clock
Controller) driver.

Signed-off-by: Vladimir Lypak <junak.pub@gmail.com>
Signed-off-by: Adam Skladowski <a_skl39@protonmail.com>
Signed-off-by: Sireesh Kodali <sireeshkodali@protonmail.com>
Link: https://lore.kernel.org/r/Q6uB3NRxqtD8Prsmliv8ZdsTXGeviv7lb2jQ743jr1E@cp4-web-036.plabs.ch
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: qcom: gcc-sdm660: Replace usage of parent_names

Using parent_data and parent_hws, instead of parent_names, does protect
against some cases of incompletely defined clock trees. While it turns
out that the bug being chased this time was totally unrelated, this
patch converts the SDM660 GCC driver to avoid such issues.

The "xo" fixed_factor clock is unused within the gcc driver, but
referenced from the DSI PHY. So it's left in place until the DSI driver
is updated.

Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210825204517.1278130-1-bjorn.andersson@linaro.org
[sboyd@kernel.org: Reduce diff by moving enum and tables back to
original position in previous patch]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: qcom: gcc-sdm660: Move parent tables after PLLs

In the next patch we're going to change these tables to reference the
PLL structures directly. Let's move them here so the diff is easier to
read. No functional change in this patch.

Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: qcom: use devm_pm_runtime_enable and devm_pm_clk_create

Use two new helpers instead of pm_runtime_enable() and pm_clk_create(),
removing the need for calling pm_runtime_disable and pm_clk_destroy().

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210731195034.979084-4-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

PM: runtime: add devm_pm_clk_create helper

A typical code pattern for pm_clk_create() call is to call it in the
_probe function and to call pm_clk_destroy() both from _probe error path
and from _remove function. For some drivers the whole remove function
would consist of the call to pm_remove_disable().

Add helper function to replace this bolierplate piece of code. Calling
devm_pm_clk_create() removes the need for calling pm_clk_destroy() both
in the probe()'s error path and in the remove() function.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210731195034.979084-3-dmitry.baryshkov@linaro.org
Acked-by: Rafael J. Wysocki <rafael@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

PM: runtime: add devm_pm_runtime_enable helper

A typical code pattern for pm_runtime_enable() call is to call it in the
_probe function and to call pm_runtime_disable() both from _probe error
path and from _remove function. For some drivers the whole remove
function would consist of the call to pm_remove_disable().

Add helper function to replace this bolierplate piece of code. Calling
devm_pm_runtime_enable() removes the need for calling
pm_runtime_disable() both in the probe()'s error path and in the
remove() function.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210731195034.979084-2-dmitry.baryshkov@linaro.org
Acked-by: Rafael J. Wysocki <rafael@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

Merge tag 'v5.15-rockchip-clk1' of git://git./linux/kernel/git/mmind/linux-rockchip into clk-rockchip

Pull Rockchip clk driver updates from Heiko Stuebner:

 - YAML conversion of rk3399 clock controller binding
 - Removal of GRF dependency for the rk3328/rk3036 pll types
 - some clock tree fixes

* tag 'v5.15-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: make rk3308 ddrphy4x clock critical
  clk: rockchip: drop GRF dependency for rk3328/rk3036 pll types
  dt-bindings: clk: Convert rockchip,rk3399-cru to DT schema
  clk: rockchip: Add support for hclk_sfc on rk3036
  clk: rockchip: rk3036: fix up the sclk_sfc parent error
  clk: rockchip: add dt-binding clkid for hclk_sfc on rk3036

Merge tag 'for-5.15-clk' of git://git./linux/kernel/git/tegra/linux into clk-nvidia

Pull a Tegra clk driver cleanup from Thierry Reding:

The FUSE driver has been updated to take manual control of the FUSE
clock over suspend/resume cycles, so the CLK_IS_CRITICAL flag can now be
dropped.

* tag 'for-5.15-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  clk: tegra: Remove CLK_IS_CRITICAL flag from fuse clock
  soc/tegra: fuse: Enable fuse clock on suspend for Tegra124
  soc/tegra: fuse: Add runtime PM support
  soc/tegra: fuse: Clear fuse->clk on driver probe failure
  soc/tegra: pmc: Prevent racing with cpuilde driver
  soc/tegra: bpmp: Remove unused including <linux/version.h>

Merge tag 'renesas-clk-for-v5.15-tag2' of git://git./linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull more Renesas clk driver updates from Geert Uytterhoeven:

 - Make CLK_R9A06G032 invisible

* tag 'renesas-clk-for-v5.15-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: Make CLK_R9A06G032 invisible

clk: imx8mn: Add M7 core clock

Add missing M7 core clock entry to the iMX8MN clock driver.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Cc: Abel Vesa <abel.vesa@nxp.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Link: https://lore.kernel.org/r/20210819202036.2084782-1-marex@denx.de
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>

clk: imx8m: fix clock tree update of TF-A managed clocks

On the i.MX8M*, the TF-A exposes a SiP (Silicon Provider) service
for DDR frequency scaling. The imx8m-ddrc-devfreq driver calls the
SiP and then does clk_set_parent on the DDR muxes to synchronize
the clock tree.

Since 936c383673b9 ("clk: imx: fix composite peripheral flags"),
these TF-A managed muxes have SET_PARENT_GATE set, which results
in imx8m-ddrc-devfreq's clk_set_parent after SiP failing with -EBUSY:

echo 25000000 > userspace/set_freq
imx8m-ddrc-devfreq 3d400000.memory-controller: failed to set
dram_apb parent: -16

Fix this by adding a new i.MX composite flag for firmware managed
clocks, which clears SET_PARENT_GATE.

This is safe to do, because updating the Linux clock tree to reflect
reality will always be glitch-free.

Fixes: 936c383673b9 ("clk: imx: fix composite peripheral flags")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20210810151432.9228-1-a.fatoum@pengutronix.de
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>

clk: imx: clk-divider-gate: Switch to clk_divider.determine_rate

.determine_rate is meant to replace .round_rate in CCF in the future.
Switch over to .determine_rate now that clk_divider_ops has gained
support for that.

Cc: Guenter Roeck <linux@roeck-us.net>
Cc: Abel Vesa <abel.vesa@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20210702225145.2643303-3-martin.blumenstingl@googlemail.com
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>

clk: imx8mn: use correct mux type for clkout path

The mux in the clkout path needs the current selected parent to
be enabled for the switch to work. Use the correct mux type
to have the clk framework take care of this requirement.

Fixes: af4df655040 ("clk: imx8mn: add clkout1/2 support")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20210628211554.2510238-2-l.stach@pengutronix.de
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>

clk: imx8mm: use correct mux type for clkout path

The mux in the clkout path needs the current selected parent to
be enabled for the switch to work. Use the correct mux type
to have the clk framework take care of this requirement.

Fixes: c1ae5c6f789a ("clk: imx8mm: add clkout1/2 support")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20210628211554.2510238-1-l.stach@pengutronix.de
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>

clk: renesas: Make CLK_R9A06G032 invisible

When configuring a kernel including support for Renesas ARM/ARM64 Socs,
but excluding support for the RZ/N1D SoC, the user is always asked about
the RZ/N1D clock driver.  As this driver is already auto-selected when
building a kernel including support for the RZ/N1D SoC, there is no need
to make the CLK_R9A06G032 symbol visible, unless compile-testing.

Align the symbol description with the other symbols.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/4f3d30c730c30546f702715ffc648922a8156703.1628672649.git.geert+renesas@glider.be

clk: fractional-divider: Document the arithmetics used behind the code

It appears that some code lines raise the question why they are needed
and how they are participated in the calculus of the resulting values.

Document this in a form of the top comment in the module file.

Reported-by: Liu Ying <victor.liu@nxp.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20210812170025.67074-4-andriy.shevchenko@linux.intel.com
[sboyd@kernel.org: Remove "die" as it isn't relevant]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: fractional-divider: Introduce POWER_OF_TWO_PS flag

The newly introduced POWER_OF_TWO_PS flag, when set, makes the flow
to skip the assumption that the caller will use an additional 2^scale
prescaler to get the desired clock rate.

Reported-by: Liu Ying <victor.liu@nxp.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20210812170025.67074-3-andriy.shevchenko@linux.intel.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: fractional-divider: Hide clk_fractional_divider_ops from wide audience

The providers are all located in drivers/clk/ and hence no need
to export the clock operations to wider audience. Hide them by
moving to drivers/clk/clk-fractional-divider.h.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20210812170025.67074-2-andriy.shevchenko@linux.intel.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: fractional-divider: Export approximation algorithm to the CCF users

At least one user currently duplicates some functions that are provided
by fractional divider module. Let's export approximation algorithm and
replace the open-coded variant.

As a bonus the exported function will get better documentation in place.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20210812170025.67074-1-andriy.shevchenko@linux.intel.com
[sboyd@kernel.org: Add header guard because why not]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: tegra: Remove CLK_IS_CRITICAL flag from fuse clock

FUSE driver now takes care of keeping the clock enabled when necessary.
Remove the CLK_IS_CRITICAL flag from the clock.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

Merge branch 'for-5.15/soc' into for-5.15/clk

soc/tegra: fuse: Enable fuse clock on suspend for Tegra124

The FUSE clock should be enabled during suspend on Tegra124. Currently
clk driver enables it on all SoCs, but FUSE may require a higher core
voltage on Tegra30 while enabled. Move the quirk into the FUSE driver
and make it specific to Tegra124.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

soc/tegra: fuse: Add runtime PM support

The Tegra FUSE belongs to the core power domain and we're going to enable
GENPD support for the core domain. Now FUSE device must be resumed using
runtime PM API in order to initialize the FUSE power state. Add runtime PM
support to the FUSE driver.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

soc/tegra: fuse: Clear fuse->clk on driver probe failure

The fuse->clk must be cleared if FUSE driver fails to probe, otherwise
tegra_fuse_readl() will crash. It's unlikely to happen in practice,
nevertheless let's correct it for completeness.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

soc/tegra: pmc: Prevent racing with cpuilde driver

Both PMC and cpuidle drivers are probed at the same init level and
cpuidle depends on the PMC suspend mode. Add new default suspend mode
that indicates whether PMC driver has been probed and reset the mode in
a case of deferred probe of the PMC driver.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

soc/tegra: bpmp: Remove unused including <linux/version.h>

Remove including <linux/version.h> that don't need it.

V1->V2: Split the patch in two

Signed-off-by: Cai Huoqing <caihuoqing@baidu.com>
Acked-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

clk: qcom: a53-pll: Add MSM8939 a53pll support

MSM8939 has 3 a53pll clocks with different frequency table for Cluster0,
Cluster1 and CCI.  It adds function qcom_a53pll_get_freq_tbl() to create
pll_freq_tbl from OPP, so that those a53pll frequencies can be defined
in DT with operating-points-v2 bindings rather than being coded in the
driver.  In this case, one compatible rather than three would be needed
for these 3 a53pll clocks.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Link: https://lore.kernel.org/r/20210704024032.11559-5-shawn.guo@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

dt-bindings: clock: Update qcom,a53pll bindings for MSM8939 support

Update qcom,a53pll bindings for MSM8939 support:

 - Add optional operating-points-v2 property
 - Add MSM8939 specific compatible

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Link: https://lore.kernel.org/r/20210704024032.11559-4-shawn.guo@linaro.org
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: qcom: a53pll/mux: Use unique clock name

Different from MSM8916 which has only one a53pll/mux clock, MSM8939 gets
three for Cluster0 (little cores), Cluster1 (big cores) and CCI (Cache
Coherent Interconnect).  That said, a53pll/mux clock needs to be named
uniquely.  Append @unit-address of device node to the clock name, so
that a53pll/mux will be named like below on MSM8939.

  a53pll@b016000
  a53pll@b116000
  a53pll@b1d0000

  a53mux@b1d1000
  a53mux@b011000
  a53mux@b111000

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Link: https://lore.kernel.org/r/20210704024032.11559-3-shawn.guo@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: qcom: apcs-msm8916: Flag a53mux instead of a53pll as critical

The clock source for MSM8916 cpu cores is like below.

                        |\
         a53pll --------| \ a53mux     +------+
                        | |------------| cpus |
     gpll0_vote --------| /            +------+
                        |/

So a53mux rather than a53pll is actually the parent clock of cpu cores.
It makes more sense to flag a53mux as critical instead, so that when
either a53pll or gpll0_vote is used by cpu cores, the clock will be kept
enabled while the other can be disabled.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Link: https://lore.kernel.org/r/20210704024032.11559-2-shawn.guo@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: qcom: gpucc-sm8150: Add SC8180x support

The GPU clock controller found in SC8180x is a variant of the same block
found in SM8150, but with one additional clock frequency for the
gmu_clk_src clock.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210721225329.3035779-1-bjorn.andersson@linaro.org
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: qcom: smd-rpm: Add mdm9607 clocks

Add support for RPM-managed clocks on the MDM9607 platform.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210805222400.39027-2-konrad.dybcio@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

dt-bindings: clock: qcom: rpmcc: Document MDM9607 compatible

Add the dt-binding for the RPM Clock Controller on the MDM9607 SoC.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210805222400.39027-1-konrad.dybcio@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: qcom: rpmcc: Add support for MSM8953 RPM clocks.

Add definitions for RPM clocks used on MSM8953 platform.

Signed-off-by: Vladimir Lypak <junak.pub@gmail.com>
Signed-off-by: Adam Skladowski <a_skl39@protonmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Sireesh Kodali <sireeshkodali@protonmail.com>
Link: https://lore.kernel.org/r/QZ0fkozlubDdc7CvqjZPhAviFmjJ28ht7Y4PT3rYM@cp4-web-038.plabs.ch
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

dt-bindings: clock: qcom-rpmcc: Add compatible for MSM8953 SoC

Add compatible for MSM8953 SoC.

Signed-off-by: Vladimir Lypak <junak.pub@gmail.com>
Signed-off-by: Sireesh Kodali <sireeshkodali@protonmail.com>
Link: https://lore.kernel.org/r/c662hoLme5MIdelk5BVPsVgN77IqTLS0KwYwpauJiDs@cp3-web-047.plabs.ch
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: qcom: smd: Add support for SM6115 rpm clocks

Add rpm smd clocks, PMIC and bus clocks which are required on
SM4250/6115 for clients to vote on.

Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
Link: https://lore.kernel.org/r/20210731164827.2756798-2-iskren.chernev@gmail.com
[sboyd@kernel.org: Drop duplicate define, merge with sm6125 support]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: qcom: smd: Add support for SM6125 rpm clocks

Add rpm smd clocks, PMIC and bus clocks which are required on SM6125
for clients to vote on.

Signed-off-by: Martin Botka <martin.botka@somainline.org>
Link: https://lore.kernel.org/r/20210730215924.733350-2-martin.botka@somainline.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: stm32mp1: Switch to clk_divider.determine_rate

.determine_rate is meant to replace .round_rate in CCF in the future.
Switch over to .determine_rate now that clk_divider_ops has gained
support for that.

Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20210702225145.2643303-7-martin.blumenstingl@googlemail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: stm32h7: Switch to clk_divider.determine_rate

.determine_rate is meant to replace .round_rate in CCF in the future.
Switch over to .determine_rate now that clk_divider_ops has gained
support for that.

Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20210702225145.2643303-6-martin.blumenstingl@googlemail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: stm32f4: Switch to clk_divider.determine_rate

.determine_rate is meant to replace .round_rate in CCF in the future.
Switch over to .determine_rate now that clk_divider_ops has gained
support for that.

Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20210702225145.2643303-5-martin.blumenstingl@googlemail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: bcm2835: Switch to clk_divider.determine_rate

.determine_rate is meant to replace .round_rate in CCF in the future.
Switch over to .determine_rate now that clk_divider_ops has gained
support for that.

Cc: Marek Szyprowski <m.szyprowski@samsung.com>
Cc: Nicolas Saenz Julienne <nsaenz@kernel.org>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Ray Jui <rjui@broadcom.com>
Cc: Scott Branden <sbranden@broadcom.com>
Cc: bcm-kernel-feedback-list@broadcom.com
Cc: linux-rpi-kernel@lists.infradead.org
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20210702225145.2643303-4-martin.blumenstingl@googlemail.com
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: divider: Implement and wire up .determine_rate by default

.determine_rate is meant to replace .round_rate. The former comes with a
benefit which is especially relevant on 32-bit systems: since
.determine_rate uses an "unsigned long" (compared to a "signed long"
which is used by .round_rate) the maximum value on 32-bit systems
increases from 2^31 (or approx. 2.14GHz) to 2^32 (or approx. 4.29GHz).

Implement .determine_rate in addition to .round_rate so drivers that are
using clk_divider_{ro_,}ops can benefit from this by default. Keep the
.round_rate callback for now since some drivers rely on
clk_divider_ops.round_rate being implemented.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20210702225145.2643303-2-martin.blumenstingl@googlemail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: palmas: Add a missing SPDX license header

Add the missing SPDX license header to drivers/clk/clk-palmas.c.

Signed-off-by: Jason Wang <wangborong@cdjrlc.com>
Link: https://lore.kernel.org/r/20210731132226.424853-1-wangborong@cdjrlc.com
[sboyd@kernel.org: Also remove boilerplate from comment]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: Align provider-specific CLK_* bit definitions

The definition of CLK_MULTIPLIER_ROUND_CLOSEST is not aligned to the two
bit definitions next to it.  A deeper inspection reveals that the
alignment of CLK_MULTIPLIER_ROUND_CLOSEST does match the most common
alignment.

Align the bit definitions for the various provider types throughout the
file at 40 columns, to increase uniformity.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/5468cd9e50cda8fc59cb6baab9413c6c0de1a974.1626257689.git.geert+renesas@glider.be
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

Merge tag 'renesas-clk-for-v5.15-tag1' of git://git./linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Add display (DU and DSI) clocks on R-Car V3U
 - Add I2C, DMAC, USB, sound (SSIF-2), GPIO, CANFD, and ADC clocks and
  resets on RZ/G2L
 - Miscellaneous fixes and improvements

* tag 'renesas-clk-for-v5.15-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r9a07g044: Add entry for fixed clock P0_DIV2
  dt-bindings: clock: r9a07g044-cpg: Add entry for P0_DIV2 core clock
  clk: renesas: r9a07g044: Add clock and reset entries for ADC
  clk: renesas: r9a07g044: Add clock and reset entries for CANFD
  clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch]
  clk: renesas: r9a07g044: Add GPIO clock and reset entries
  clk: renesas: r9a07g044: Add SSIF-2 clock and reset entries
  clk: renesas: r9a07g044: Add USB clocks/resets
  clk: renesas: r9a07g044: Add DMAC clocks/resets
  clk: renesas: r9a07g044: Add I2C clocks/resets
  clk: renesas: r8a779a0: Add the DSI clocks
  clk: renesas: r8a779a0: Add the DU clock
  clk: renesas: rzg2: Rename i2c-dvfs to iic-pmic
  clk: renesas: rzg2l: Fix off-by-one check in rzg2l_cpg_clk_src_twocell_get()
  clk: renesas: rzg2l: Avoid mixing error pointers and NULL
  clk: renesas: rzg2l: Fix a double free on error
  clk: renesas: rzg2l: Fix return value and unused assignment
  clk: renesas: rzg2l: Remove unneeded semicolon

clk: rockchip: make rk3308 ddrphy4x clock critical

Currently, no driver support for DDR memory controller (DMC) is present,
as a result, no driver is explicitly consuming the ddrphy clock. This means
that VPLL1 (parent of ddr clock) will be shutdown if we enable
and then disable any child clock of VPLL1 (e.g. SCLK_I2S0_8CH_TX).
If VPLL1 is disabled, the whole system will freeze, because the DDR
controller will lose its clock. So, it's necessary to prevent VPLL1 from
shutting down, by marking the ddrphy4x CLK_IS_CRITICAL.

This bug was discovered when I was porting rockchip_i2s_tdm driver to
mainline kernel from Rockchip 4.4 kernel. I guess that other Rockchip
SoCs without DMC driver may need the same patch. If this applies to
other devices, please let us know.

Signed-off-by: Yunhao Tian <t123yh@outlook.com>
Link: https://lore.kernel.org/r/BYAPR20MB24886765F888A9705CBEB70789E39@BYAPR20MB2488.namprd20.prod.outlook.com
[adapted subject, changed to add the clock to the critical list]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

clk: rockchip: drop GRF dependency for rk3328/rk3036 pll types

The rk3036/rk3328 pll types were converted to checking the lock status
via the internal register in january 2020, so don't need the grf
reference since then.

But it was forgotten to remove grf check when deciding between the
pll rate ops (read-only vs. read-write), so a clock driver without
the needed grf reference might've been put into the read-only mode
just because the grf reference was missing.

This affected the rk356x that needs to reclock certain plls at boot.

Fix this by removing the check for the grf for selecting the utilized
operations.

Suggested-by: Heiko Stuebner <heiko@sntech.de>
Fixes: 7f6ffbb885d1 ("clk: rockchip: convert rk3036 pll type to use internal lock status")
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
[adjusted the commit message, adjusted the fixes tag]
Link: https://lore.kernel.org/r/20210728180034.717953-3-pgwipeout@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

dt-bindings: clk: qcom: smd-rpm: Document SM6125 compatible

Document the newly added compatible for sm6125 rpmcc.

Signed-off-by: Martin Botka <martin.botka@somainline.org>
Link: https://lore.kernel.org/r/20210629102624.194378-3-martin.botka@somainline.org
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

dt-bindings: clock: qcom: rpmcc: Document SM6115 compatible

Add the dt-binding for the RPM Clock Controller on the SM4250/6115 SoCs.

Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
Link: https://lore.kernel.org/r/20210627185927.695411-3-iskren.chernev@gmail.com
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: x86: Rename clk-lpt to more specific clk-lpss-atom

The LPT stands for Lynxpoint PCH. However the driver is used on a few
Intel Atom SoCs. Rename it to reflect this in a way how another clock
driver, i.e. clk-pmc-atom, is called.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20210722193450.35321-1-andriy.shevchenko@linux.intel.com
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: lmk04832: drop redundant fallthrough statements

When the body of a case statement is empty, it is well understood that
it is intentional and explicit fallthrough statements are not required.
Drop them.

Signed-off-by: Liam Beguin <liambeguin@gmail.com>
Link: https://lore.kernel.org/r/20210708211645.3621902-1-liambeguin@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: mediatek: make COMMON_CLK_MT8167* depend on COMMON_CLK_MT8167

I found that COMMON_CLK_MT8167* do not depend on COMMON_CLK_MT8167,
so it is possible to config:

CONFIG_COMMON_CLK_MT8167=n
CONFIG_COMMON_CLK_MT8167_*=y

Although it does not cause build breaks with such configuration,
I think it is clearer to make COMMON_CLK_MT8167* depend on
COMMON_CLK_MT8167.

Signed-off-by: Miles Chen <miles.chen@mediatek.com>
Link: https://lore.kernel.org/r/20210716051732.3422-1-miles.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: qcom: dispcc-sm8250: Add additional parent clocks for DP

The clock controller has two additional clock source pairs, in order to
support more than a single DisplayPort PHY. List these, so it's possible
to describe them all.

Also drop the unnecessary freq_tbl for the link clock sources, to allow
these parents to be used.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210721224610.3035258-1-bjorn.andersson@linaro.org
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: mediatek: Add MT8192 vencsys clock support

Add MT8192 vencsys clock provider

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Link: https://lore.kernel.org/r/20210726105719.15793-22-chun-jie.chen@mediatek.com
Reviewed-by: Ikjoon Jang <ikjn@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: mediatek: Add MT8192 vdecsys clock support

Add MT8192 vdecsys and vdecsys soc clock providers

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Link: https://lore.kernel.org/r/20210726105719.15793-21-chun-jie.chen@mediatek.com
Reviewed-by: Ikjoon Jang <ikjn@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: mediatek: Add MT8192 scp adsp clock support

Add MT8192 scp adsp clock provider

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Link: https://lore.kernel.org/r/20210726105719.15793-20-chun-jie.chen@mediatek.com
Reviewed-by: Ikjoon Jang <ikjn@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: mediatek: Add MT8192 msdc clock support

Add MT8192 msdc and msdc top clock providers

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Link: https://lore.kernel.org/r/20210726105719.15793-19-chun-jie.chen@mediatek.com
Reviewed-by: Ikjoon Jang <ikjn@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: mediatek: Add MT8192 mmsys clock support

Add MT8192 mmsys clock provider

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Link: https://lore.kernel.org/r/20210726105719.15793-18-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: mediatek: Add MT8192 mfgcfg clock support

Add MT8192 mfgcfg clock provider

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Link: https://lore.kernel.org/r/20210726105719.15793-17-chun-jie.chen@mediatek.com
Reviewed-by: Ikjoon Jang <ikjn@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: mediatek: Add MT8192 mdpsys clock support

Add MT8192 mdpsys clock provider

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Link: https://lore.kernel.org/r/20210726105719.15793-16-chun-jie.chen@mediatek.com
Reviewed-by: Ikjoon Jang <ikjn@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

clk: mediatek: Add MT8192 ipesys clock support

Add MT8192 ipesys clock provider

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Link: https://lore.kernel.org/r/20210726105719.15793-15-chun-jie.chen@mediatek.com
Reviewed-by: Ikjoon Jang <ikjn@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>