Icecream95 [Sun, 3 Jan 2021 02:16:55 +0000 (15:16 +1300)]
panfrost: Make the width argument to panfrost_new_texture 32 bits
This is needed to represent a width of exactly 65536, which is
required by ARB_texture_buffer_object.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8300>
Icecream95 [Mon, 4 Jan 2021 07:44:49 +0000 (20:44 +1300)]
st/mesa: Use samplers for buffer textures if requested
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8300>
Icecream95 [Thu, 7 Jan 2021 22:20:02 +0000 (11:20 +1300)]
docs: Mention PIPE_CAP_TEXTURE_BUFFER_SAMPLER
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8300>
Icecream95 [Mon, 4 Jan 2021 07:41:57 +0000 (20:41 +1300)]
gallium: Add new cap PIPE_CAP_TEXTURE_BUFFER_SAMPLER
This indicates whether a driver wants samplers for buffer textures as
well as normal textures.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8300>
Timur Kristóf [Wed, 2 Dec 2020 11:06:28 +0000 (12:06 +0100)]
aco: Wait for stores when NGG or legacy VS can finish early.
When there are no param exports in an NGG (or legacy VS) shader,
the NO_PC_EXPORT=1 is set, which means PS waves can launch before
the current stage finishes.
If the current stage has any stores, we need to make sure to wait for
those before we allow PS waves to start, so that PS can read what
these instructions stored.
Fossil DB results on Navi 10:
Totals from 45 (0.03% of 136420) affected shaders:
CodeSize: 87224 -> 87404 (+0.21%)
Instrs: 16750 -> 16795 (+0.27%)
Cycles: 69580 -> 69760 (+0.26%)
VMEM: 8022 -> 8167 (+1.81%)
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7868>
Timur Kristóf [Mon, 11 Jan 2021 17:36:20 +0000 (18:36 +0100)]
aco: Note if rasterization can start early.
When there are no param exports in an NGG (or legacy VS) shader,
the NO_PC_EXPORT=1 is set by RADV, which means PS waves can launch
before the current stage finishes.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7868>
Daniel Schürmann [Tue, 12 Jan 2021 11:45:46 +0000 (12:45 +0100)]
aco/ra: fix infinite recursion in get_reg_simple() with subdword registers
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes:
f8c7661ecaa782fdde105a4bf756023eb88ea780 ('aco: try to better align 8+ dword SGPR vectors')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8425>
Daniel Schürmann [Fri, 8 Jan 2021 22:03:21 +0000 (23:03 +0100)]
aco: simplify and fix operand/definition sizes
These are mainly needed for constant propagation
and subdword register allocation.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8425>
Daniel Schürmann [Thu, 27 Aug 2020 14:11:13 +0000 (15:11 +0100)]
radv: enable .lower_ineg
We already emit ineg as isub most of the time.
The results are a bit mixed, but shouldn't really make a difference.
A couple of additional copies are needed as isub writes scc.
Totals from 5975 (4.29% of 139391) affected shaders:
CodeSize:
31508648 ->
31509264 (+0.00%); split: -0.00%, +0.00%
Instrs: 6073379 -> 6073531 (+0.00%); split: -0.00%, +0.00%
Cycles:
47186280 ->
47187116 (+0.00%); split: -0.00%, +0.00%
VMEM: 2528515 -> 2529139 (+0.02%); split: +0.03%, -0.01%
SMEM: 596842 -> 596924 (+0.01%); split: +0.02%, -0.00%
SClause: 280596 -> 280594 (-0.00%)
Copies: 288554 -> 288669 (+0.04%); split: -0.00%, +0.04%
PreSGPRs: 240390 -> 240397 (+0.00%)
PreVGPRs: 349630 -> 349749 (+0.03%)
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8425>
Daniel Schürmann [Fri, 8 Jan 2021 21:05:26 +0000 (22:05 +0100)]
radv: don't lower_pack() after load-store-vectorization
Totals from 7 (0.01% of 139391) affected shaders:
CodeSize: 282900 -> 283324 (+0.15%); split: -0.01%, +0.16%
Instrs: 45287 -> 45338 (+0.11%); split: -0.01%, +0.12%
Cycles:
11496332 ->
11510396 (+0.12%); split: -0.00%, +0.12%
VMEM: 2355 -> 2335 (-0.85%)
Copies: 15506 -> 15561 (+0.35%)
A bit of noise in some parallel-rdp shaders.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8425>
Daniel Schürmann [Mon, 11 Jan 2021 13:34:26 +0000 (14:34 +0100)]
radv: call nir_opt_algebraic_late() after lowering idiv for small bitsizes
This is needed because lower_idiv() introduces ineg again
which we'll remove next.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8425>
Daniel Schürmann [Mon, 11 Jan 2021 18:05:52 +0000 (19:05 +0100)]
radv: optimize idiv_const for small bitsizes
No fossil-db changes.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8425>
Samuel Pitoiset [Tue, 5 Jan 2021 09:19:03 +0000 (10:19 +0100)]
radv: fix color resolves if the dest image has DCC
Using the graphics resolve path when DCC is enabled should only be
a hint to avoid DCC fixup.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3388
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8326>
Samuel Pitoiset [Tue, 5 Jan 2021 08:26:36 +0000 (09:26 +0100)]
radv: fixup DCC after color resolves using the compute path
If the dest image has DCC it should be re-initialized to the
uncompressed state.
Note that the driver always selects the graphics path if the dest
image has DCC, so this has no effect for now.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8326>
Samuel Pitoiset [Fri, 8 Jan 2021 10:56:00 +0000 (11:56 +0100)]
radv: decompress DCC for partial resolves using the compute path
Because DCC is re-initialized to the uncompressed state after the
resolve, so if the app does a partial resolve it should be
decompressed first.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8326>
Samuel Pitoiset [Fri, 8 Jan 2021 10:41:29 +0000 (11:41 +0100)]
radv: set depth to 1 for subpass resolves using the compute path
To match Vulkan convention.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8326>
Rhys Perry [Mon, 11 Jan 2021 17:11:05 +0000 (17:11 +0000)]
aco: improve nir_op_vec with constant operands
Could still be improved a little. For example, 8-bit pack without
constants could be:
(s_pack_ll(x, z) & 0x00ff00ff) | ((s_pack_ll(y, w) & 0x00ff00ff) << 8)
fossil-db (Sienna):
Totals from 136 (0.10% of 139391) affected shaders:
CodeSize: 279776 -> 278144 (-0.58%)
Instrs: 50742 -> 50470 (-0.54%)
Cycles: 211560 -> 210472 (-0.51%)
SMEM: 3607 -> 3557 (-1.39%)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8421>
Louis-Francis Ratté-Boulianne [Wed, 9 Dec 2020 03:57:39 +0000 (22:57 -0500)]
wgl: Don't crash in stw_make_current if current framebuffer is NULL
Fixes #3878
Signed-off-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7999>
Rhys Perry [Mon, 14 Dec 2020 22:00:23 +0000 (22:00 +0000)]
radv: set invariantgeom for Shadow of the Tomb Raider
Work around flickering foliage on GFX10.3
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4064
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8104>
Rhys Perry [Mon, 14 Dec 2020 21:54:28 +0000 (21:54 +0000)]
radv: add RADV_DEBUG=invariantgeom
This can be used to work around a common class of bugs appearing as
flickering.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8104>
Daniel Schürmann [Tue, 12 Jan 2021 12:01:34 +0000 (13:01 +0100)]
nir/divergence_analysis: mark load_push_constant as uniform
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8439>
Samuel Pitoiset [Tue, 12 Jan 2021 13:30:10 +0000 (14:30 +0100)]
radv: mark some sparse texture CTS as expected failures on GFX9
It's likely a RADV bug but marking them as expected failures
to avoid more breakage in the meantime.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8442>
Samuel Pitoiset [Mon, 11 Jan 2021 16:21:54 +0000 (17:21 +0100)]
ci: mark some sparse tests as expected failures on Pitcairn (GFX6)
Two CTS bugs reported.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8436>
Samuel Pitoiset [Tue, 12 Jan 2021 10:45:14 +0000 (11:45 +0100)]
aco: fix inserting expcnt for MIMG on GFX6
MIMG VDATA has moved to its own operand.
Fixes:
962c917cea9 ("aco: move MIMG VDATA to its own operand")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8435>
Tapani Pälli [Mon, 11 Jan 2021 11:01:53 +0000 (13:01 +0200)]
vbo/dlist: free prim_store->prims when vbo_save is destroyed
Fixes:
83149e1c2d8 ("vbo/dlist: refactor prim_store/vertex_store allocations")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4067
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8410>
Mike Blumenkrantz [Mon, 4 Jan 2021 21:05:11 +0000 (16:05 -0500)]
glcpp: disable 'windows' tests
these timeout a lot
Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8321>
Leo Liu [Sun, 10 Jan 2021 16:15:38 +0000 (11:15 -0500)]
frontends/omx: fix build warning
From code path, it's easy to see that the variable is only used
with condition, and the variable gets initialized with the same
condition before getting used, but we can initialize it when defined
to avoid the warning.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8404>
Ilia Mirkin [Sat, 9 Jan 2021 06:33:08 +0000 (01:33 -0500)]
nouveau: add drm-shim support
Seems to work reasonably well with shader-db's run.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8406>
Ilia Mirkin [Sat, 9 Jan 2021 18:13:42 +0000 (13:13 -0500)]
nouveau: change fence destruction logic on screen destroy
With the drm shim, we can't actually wait for the hardware to do
anything. But why wait for it at all? We just need to make sure to
execute all the work and clean up any resources. Add a helper to do
that.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8406>
Alyssa Rosenzweig [Mon, 11 Jan 2021 20:50:03 +0000 (15:50 -0500)]
panfrost: Advertise ES3.0 on Bifrost
Doing so fixes our remaining dEQP-GLES2 failures.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Maciej Matuszczyk <maccraft123mc@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8427>
Boris Brezillon [Tue, 24 Nov 2020 07:30:56 +0000 (08:30 +0100)]
panfrost: Test GLES3 on Bifrost
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Maciej Matuszczyk <maccraft123mc@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8427>
Alyssa Rosenzweig [Mon, 11 Jan 2021 21:00:41 +0000 (16:00 -0500)]
panfrost: Disable AFBC of 3D, 2D arrays
These are broken at least on v7 and likely elsewhere. Until this can be
investigated, let's disable it so we don't break dEQP-GLES3.
Example of a failing test without this patch:
dEQP-GLES3.functional.texture.filtering.2d_array.sizes.128x32x64_nearest
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Maciej Matuszczyk <maccraft123mc@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8427>
Boris Brezillon [Fri, 20 Nov 2020 15:58:53 +0000 (16:58 +0100)]
panfrost: Promote 8b to 16b for blend descriptors
There is no 8-bit register_format applicable. Some lowering is needed
at the compiler level to make it work.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Maciej Matuszczyk <maccraft123mc@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8427>
Boris Brezillon [Fri, 20 Nov 2020 15:57:46 +0000 (16:57 +0100)]
pan/bi: Lower 8bit fragment outputs to 16bit
Bifrost does not support passing fragment colors through 8 bit registers.
(Rewrote to use NIR helpers -Alyssa)
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Maciej Matuszczyk <maccraft123mc@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8427>
Alyssa Rosenzweig [Mon, 11 Jan 2021 18:50:43 +0000 (13:50 -0500)]
pan/bi: Assert immediate indices fit
This would have caught the assortment of bugs fixed in the previous two
commits, and should help lint going forward.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Maciej Matuszczyk <maccraft123mc@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8427>
Alyssa Rosenzweig [Mon, 11 Jan 2021 19:02:38 +0000 (14:02 -0500)]
pan/bi: Parametrize intrinsic immediate limits
Fixes issues on:
dEQP-GLES3.functional.transform_feedback.array_element.separate.points.lowp_mat2x3
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Maciej Matuszczyk <maccraft123mc@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8427>
Alyssa Rosenzweig [Mon, 11 Jan 2021 18:52:53 +0000 (13:52 -0500)]
pan/bi: Use TEXC for indices >= 8
Otherwise it can't fit, fixes
dEQP-GLES3.functional.texture.units.all_units.only_2d.*
dEQP-GLES3.functional.texture.units.all_units.only_cube.*
dEQP-GLES3.functional.texture.units.all_units.mixed.*
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Maciej Matuszczyk <maccraft123mc@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8427>
Alyssa Rosenzweig [Wed, 6 Jan 2021 00:22:25 +0000 (19:22 -0500)]
pan/bi: Implement scalar i2i8/u2u8
Doesn't work for vectors though that's the vectorization branch's
problem to deal with now. Suffices for fragment output.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Maciej Matuszczyk <maccraft123mc@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8427>
Alyssa Rosenzweig [Wed, 6 Jan 2021 00:21:26 +0000 (19:21 -0500)]
pan/bi: Allow passing thorugh 8-bit scalars
Needed for fragment output. Not nearly sufficient for actual 8-bit
types in e.g OpenCL.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Maciej Matuszczyk <maccraft123mc@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8427>
Alyssa Rosenzweig [Mon, 11 Jan 2021 17:57:50 +0000 (12:57 -0500)]
pan/bi: Don't suppress Inf/NaN
glmark2 was fixed upstream and we don't have Bifrost trace testing
anyway. Fixes isinf/isnan tests.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Maciej Matuszczyk <maccraft123mc@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8427>
Alyssa Rosenzweig [Wed, 6 Jan 2021 00:08:15 +0000 (19:08 -0500)]
pan/bi: Fix ATEST with pure integers
It doesn't matter what we pass due to a subtlety in the spec but the
assert is still wrong.
Fixes:
49f38aa9e79 ("pan/bi: Implement fragment_out by builder")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Maciej Matuszczyk <maccraft123mc@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8427>
Alyssa Rosenzweig [Wed, 6 Jan 2021 00:07:33 +0000 (19:07 -0500)]
pan/bi: Pull out bi_dontcare helper
Where we need a power efficient encoding but don't care about the value
read, corresponding to rNULL in canonical assembly.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Maciej Matuszczyk <maccraft123mc@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8427>
Jordan Justen [Wed, 9 Dec 2020 00:20:26 +0000 (16:20 -0800)]
intel/common: Build mi_builder_test for gen 12.5
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8424>
Gert Wollny [Sat, 9 Jan 2021 12:19:11 +0000 (13:19 +0100)]
r600: Support TGSI_OPCODE_I64NEG
This is needed for removing the use of TGSI source modifiers on integers
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8401>
Boris Brezillon [Fri, 8 Jan 2021 13:41:46 +0000 (14:41 +0100)]
pan/bi: Allow non-terminal BLEND operations
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8417>
Boris Brezillon [Fri, 8 Jan 2021 18:21:33 +0000 (19:21 +0100)]
pan/bi: Use the interference mechanism to describe blend shader reg use
Blend shader might clobber r0-r15, we must make sure the RA is aware
when compiling fragment shaders that have BLEND operations.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8417>
Boris Brezillon [Fri, 8 Jan 2021 18:18:36 +0000 (19:18 +0100)]
pan/bi: Restrict registers to r0-r15 when compiling blend shaders
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8417>
Boris Brezillon [Thu, 7 Jan 2021 12:14:21 +0000 (13:14 +0100)]
pan/bi: Port bi_collect_blend_ret_addr() to the new compiler infra
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8417>
Boris Brezillon [Fri, 8 Jan 2021 13:26:19 +0000 (14:26 +0100)]
pan/bi: Pass bundle pointers to bi_pack_tuple()
So we have updated regs and can use that to collect blend return
addresses.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8417>
Alyssa Rosenzweig [Thu, 7 Jan 2021 14:28:11 +0000 (09:28 -0500)]
pan/bi: Workaround BLEND precolour with explicit moves
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8417>
Boris Brezillon [Fri, 8 Jan 2021 18:14:03 +0000 (19:14 +0100)]
panfrost: Set the RT index when emitting a Bifrost blend descriptor
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8417>
Pavel Asyutchenko [Tue, 22 Dec 2020 21:05:54 +0000 (00:05 +0300)]
vulkan/overay: fix violation of VUID-VkDeviceCreateInfo-pNext-00373
We can't use VkDeviceCreateInfo::pEnabledFeatures when
VkPhysicalDeviceFeatures2 is present in pNext chain.
Fixes:
ea7a6fa98055ad ("vulkan/overlay: add pipeline statistic & timestamps support")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8208>
Ilia Mirkin [Fri, 8 Jan 2021 00:19:48 +0000 (19:19 -0500)]
nv50: use 2d blit when m2mf doesn't support the copy
Looks like m2mf bails if a line is >64k in width for tiled textures
(even if only a sub-section is copied as long as any part is beyond the
64k mark).
Fixes a number of GLES3 accuracy tests which made 8k-wide textures which
were read out as RGBA32_UINT, leading to problems.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8396>
Ilia Mirkin [Fri, 8 Jan 2021 06:37:35 +0000 (01:37 -0500)]
nv50,nvc0: serialize between before/after using a zeta surface as color
This happens during "3d" blit operations, where we must reinterpret it
as color in order to support stencil/depth masking. However the hardware
isn't necessarily amused by this, esp when multiple draws are queued up.
Throw in serialize calls in order to get it to flush out previous draws.
This was noticeable in the test
dEQP-GLES3.functional.fbo.invalidate.sub.unbind_blit_msaa_stencil,
although 3d blit operation had to be forced on nvc0 where it's much
rarer.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8396>
Ilia Mirkin [Fri, 8 Jan 2021 01:39:54 +0000 (20:39 -0500)]
nv50: fix instancing of client-side vertex buffers
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8396>
Ilia Mirkin [Wed, 6 Jan 2021 19:18:05 +0000 (14:18 -0500)]
nv50/ir: allow a mov to emit directly to a shader output
Under some very rare circumstances, the OP_EXPORT will refer to a def
provided by a mov. When we then try to make the defining op write to the
export directly, it blows up. Reuse the existing setDst helper which
handles this and more for the long encoding.
Fixes dEQP-GLES3.functional.shaders.precision.int.highp_mul_vertex
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8396>
Michel Zou [Mon, 11 Jan 2021 19:31:51 +0000 (20:31 +0100)]
drisw: fix unused variables warnings
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8337>
Michel Zou [Mon, 11 Jan 2021 19:31:32 +0000 (20:31 +0100)]
llvmpipe: fix unused variables warnings
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8337>
Daniel Schürmann [Fri, 4 Sep 2020 10:24:26 +0000 (11:24 +0100)]
nir: replace .lower_sub with .has_fsub and .has_isub
This allows a more fine-grained control about whether
a backend supports one of these instructions.
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6597>
Daniel Schürmann [Thu, 27 Aug 2020 13:35:04 +0000 (14:35 +0100)]
nir,vc4: Lower fneg to fmul(x, -1.0)
This patch also replaces lower_negate with lower_ineg / lower_fneg.
The fneg semantics have been clarified as of Version 1.5, Revision 1
of the SPIR-V specification, which means that the previous lowering
to fsub is not a viable solution anymore, and is replaced with
lowering to fmul(x, -1.0).
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6597>
Boris Brezillon [Mon, 23 Nov 2020 22:03:59 +0000 (23:03 +0100)]
pan/bi: Fix constant slot selection
The fau_index field contains the lower 4 bits of the 64bit constant,
which allows one to reuse the same clause constant slot from different
bundles if the upper 60 bits match. That doesn't work for constants
referenced from the same instruction or for constants referenced from
two instructions that are part of the same bundle though, since the
fau_index is shared in that case.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8418>
Boris Brezillon [Sun, 22 Nov 2020 17:53:22 +0000 (18:53 +0100)]
panfrost: Fix UBO count calculation on Bifrost
The Bifrost compiler relies on nir_lower_uniforms_to_ubo() to lower
uniforms to UBOs, and s->info.num_ubos is already incremented when a
UBO #0 is created.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8418>
Georg Lehmann [Thu, 31 Dec 2020 16:17:34 +0000 (17:17 +0100)]
vulkan/device-select: fix vkGetInstanceProcAddr self-resolving
vkGetInstanceProcAddr(instance, "vkGetInstanceProcAddr") should return our
vkGetInstanceProcAddr not the next in the chain.
CC: mesa-stable
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8286>
Samuel Pitoiset [Mon, 11 Jan 2021 15:00:47 +0000 (16:00 +0100)]
radv: mark VK_IMAGE_CREATE_SPARSE_RESIDENCY_BIT as unsupported on GFX6-7
This is only supported on GFX8+, this fixes a ton of CTS failures
on my Pitcairn (GFX6).
Fixes:
af7fb4df50f ("radv: Add sparse image queries.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8415>
Rhys Perry [Thu, 27 Aug 2020 11:11:46 +0000 (12:11 +0100)]
aco: remove can_reorder semantic in get_sync_info_with_hack
No fossil-db changes.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8416>
Rhys Perry [Tue, 25 Aug 2020 18:10:52 +0000 (19:10 +0100)]
aco: try to better align 8+ dword SGPR vectors
This doesn't have much of an effect, but it helps avoid a
pathological case for Assassin's Creed Valhalla and a RDR2 shader with a
future change.
fossil-db (Sienna):
Totals from 55074 (39.51% of 139391) affected shaders:
SGPRs: 3515076 -> 3567744 (+1.50%); split: -0.01%, +1.51%
CodeSize:
206942120 ->
206941868 (-0.00%); split: -0.00%, +0.00%
Instrs:
39625900 ->
39625837 (-0.00%); split: -0.00%, +0.00%
Cycles:
1640088780 ->
1640088828 (+0.00%); split: -0.00%, +0.00%
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4070
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8416>
Erik Faye-Lund [Fri, 8 Jan 2021 10:25:34 +0000 (11:25 +0100)]
mesa/st: fix regression for basic drivers
Drivers that doesn't support conditional rendering can't really require
respecting conditional rendering, so let's not ask for it to be
respected in the first place.
This fixes a problem where util_can_blit_via_copy_region started
unconditionally rejecting all blits that originate from
glBlitFramebuffer, even for drivers where this can't possibly be a
problem.
Fixes:
767f70dfe13 ("gallium/util: fix util_can_blit_via_copy_region for conditional rendering")
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8378>
Ilia Mirkin [Fri, 8 Jan 2021 18:37:45 +0000 (13:37 -0500)]
mesa/teximage: show internal format when printing verbose api log
This would have saved me some time to determine that the problem was
coming from lack of RGBA32F / 8x MSAA support on nv50.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8405>
Samuel Pitoiset [Thu, 7 Jan 2021 13:55:54 +0000 (14:55 +0100)]
radv: enable DCC for layered color images on GFX10+
There is still some CTS failures on GFX9.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8368>
Samuel Pitoiset [Thu, 7 Jan 2021 17:39:52 +0000 (18:39 +0100)]
radv: do not use predication when the range doesn't cover the whole image
The predication is based on the mip level, so if the image has layers
and DCC is enabled, it should only be used if the range of layers
covers the whole image.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8368>
Samuel Pitoiset [Thu, 7 Jan 2021 15:16:38 +0000 (16:16 +0100)]
radv: clean up radv_decompress_dcc_compute()
Remove one old comment because it supports decompressing layers.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8368>
Samuel Pitoiset [Thu, 7 Jan 2021 15:18:03 +0000 (16:18 +0100)]
radv: add support for fast-clearing DCC layers on GFX9+
Layers are contiguous in memory.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8368>
Samuel Pitoiset [Thu, 7 Jan 2021 15:18:31 +0000 (16:18 +0100)]
ac/surface: initialize dcc_slice_size on GFX9+
Will be used by RADV to implement DCC layers.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8368>
Michel Dänzer [Fri, 8 Jan 2021 17:45:33 +0000 (18:45 +0100)]
wsi/x11: Make sure wsi_x11_connection::is_xwayland is always initialized
We wouldn't initialize it if the X server didn't support the RANDR
extension (though that's unlikely these days).
Fixes:
b5268d532a01 "wsi/x11: Detect Xwayland"
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8393>
Michel Dänzer [Fri, 8 Jan 2021 17:54:09 +0000 (18:54 +0100)]
wsi/x11: Always free randr_reply in wsi_x11_connection_create
Fixes memory leak.
Fixes:
b5268d532a01 "wsi/x11: Detect Xwayland"
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8393>
Michel Dänzer [Fri, 8 Jan 2021 17:49:20 +0000 (18:49 +0100)]
wsi/x11: Use wsi_x11_get_connection in x11_present_to_x11_dri3
Instead of creating a new wsi_x11_connection every time.
Fixes memory leak and bad performance.
Fixes:
4292fb213928 "wsi/x11: Use PresentOptionAsync for MAILBOX present mode with Xwayland"
Reported-by: Chris Rankin <rankincj@yahoo.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8393>
Erico Nunes [Sun, 30 Aug 2020 13:07:23 +0000 (15:07 +0200)]
nir/lower_vec_to_movs: don't vectorize unsupports ops
If the instruction being coalesced would be vectorized but the target
doesn't support vectorizing that op, skip coalescing.
Reuse the callbacks from alu_to_scalar to describe which ops should not
be vectorized.
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6506>
Timur Kristóf [Wed, 25 Nov 2020 19:05:25 +0000 (20:05 +0100)]
aco: Spill more optimally before loops.
This further reduces the dead code emitted by the spiller.
Some minimal amount of dead IR is still emitted sometimes,
but that doesn't generate any compiled code at the end.
Totals from 1953 (1.40% of 139391) affected shaders:
VGPRs: 206980 -> 206588 (-0.19%)
SpillSGPRs: 24719 -> 16423 (-33.56%); split: -33.58%, +0.02%
CodeSize:
28448516 ->
28343836 (-0.37%); split: -0.38%, +0.01%
MaxWaves: 8960 -> 8992 (+0.36%)
Instrs: 5422049 -> 5408334 (-0.25%); split: -0.26%, +0.01%
Cycles:
511240864 ->
512460764 (+0.24%); split: -0.02%, +0.26%
VMEM: 346681 -> 346468 (-0.06%); split: +0.27%, -0.33%
SMEM: 124160 -> 122802 (-1.09%); split: +0.33%, -1.42%
VClause: 81102 -> 81163 (+0.08%); split: -0.01%, +0.09%
SClause: 174404 -> 174237 (-0.10%); split: -0.23%, +0.13%
Copies: 530216 -> 532961 (+0.52%); split: -0.90%, +1.42%
Branches: 189114 -> 189221 (+0.06%); split: -0.13%, +0.18%
PreSGPRs: 206017 -> 206526 (+0.25%); split: -0.08%, +0.33%
PreVGPRs: 183103 -> 182964 (-0.08%)
Co-authored-by: Daniel Schürmann <daniel@schuermann.dev>
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8026>
Timur Kristóf [Wed, 25 Nov 2020 18:57:05 +0000 (19:57 +0100)]
aco: Keep live-though variables and constants spilled.
This noticably reduces the amount of dead code emitted by our
spiller, when eg. previously a constant was spilled then
rematerialized before a loop, but then spilled again inside the loop.
Fossil DB changes on Navi 10:
Totals from 263 (0.19% of 139391) affected shaders:
VGPRs: 30044 -> 30028 (-0.05%)
SpillSGPRs: 8800 -> 4948 (-43.77%)
CodeSize: 4496040 -> 4335448 (-3.57%); split: -3.57%, +0.00%
Instrs: 843942 -> 819219 (-2.93%); split: -2.93%, +0.00%
Cycles:
76485744 ->
73549080 (-3.84%); split: -4.04%, +0.20%
VMEM: 38204 -> 38147 (-0.15%); split: +0.08%, -0.23%
SMEM: 17872 -> 17959 (+0.49%)
SClause: 24298 -> 24012 (-1.18%)
Copies: 98023 -> 82960 (-15.37%); split: -15.38%, +0.01%
Branches: 29074 -> 27632 (-4.96%)
PreVGPRs: 25291 -> 25241 (-0.20%)
Co-authored-by: Daniel Schürmann <daniel@schuermann.dev>
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8026>
Bas Nieuwenhuizen [Tue, 24 Nov 2020 22:02:54 +0000 (23:02 +0100)]
radv: Enable sparse buffer and image support.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7953>
Bas Nieuwenhuizen [Sun, 6 Dec 2020 20:42:35 +0000 (21:42 +0100)]
radv: Add sparse image queries.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7953>
Bas Nieuwenhuizen [Sun, 6 Dec 2020 18:17:03 +0000 (19:17 +0100)]
radv: Add image sparse memory update implementation.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7953>
Bas Nieuwenhuizen [Sat, 28 Nov 2020 01:56:20 +0000 (02:56 +0100)]
radv: Create sparse images.
Disable all metadata for now.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7953>
Bas Nieuwenhuizen [Fri, 8 Jan 2021 23:39:51 +0000 (00:39 +0100)]
radv/winsys: Fix offset in range merging.
If we change the virtual address we also have to change the offset in the buffer
to be mapped.
Fixes:
715df30a4e2 "radv/amdgpu: Add winsys implementation of virtual buffers."
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7953>
Bas Nieuwenhuizen [Sun, 6 Dec 2020 15:05:41 +0000 (16:05 +0100)]
radv/winsys: Fix inequality for sparse buffer remapping.
Found a case where we mapped a range too many.
Per the comment the constraint is:
/* [first, last] is exactly the range of ranges that either overlap the
* new parent, or are adjacent to it. This corresponds to the bind ranges
* that may change.
*/
So that means that after the ++last we the ranges[last] should still
be adjacent. So we need to test the post-increment value to see whether
it is adjacent.
Failure case:
ranges:
0: 0 - ffff
1: 10000 - 1ffff
2: 20000 - 2ffff
3: 30000 - 3ffff
new range: 10000 - 1ffff
wrong first, last: 0,3
However range 3 clearly isn't adjacent at all.
Fixes:
715df30a4e2 "radv/amdgpu: Add winsys implementation of virtual buffers."
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7953>
Bas Nieuwenhuizen [Wed, 23 Dec 2020 20:07:38 +0000 (21:07 +0100)]
ac/surf: Use correct tilemodes on GFX8 for PRT.
Otherwise addrlib will assign the non-PRT tiling indices anyway ...
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7953>
Bas Nieuwenhuizen [Sun, 6 Dec 2020 18:13:53 +0000 (19:13 +0100)]
ac/surf: Add sparse texture info to radeon_surf.
For GFX9 I didn't reuse the existing mipmap offset/pitch because
last time we did that there was a revert request from Marek.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7953>
Bas Nieuwenhuizen [Sat, 28 Nov 2020 01:51:05 +0000 (02:51 +0100)]
ac/surf: Implement PRT layout.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7953>
Bas Nieuwenhuizen [Sat, 28 Nov 2020 01:46:29 +0000 (02:46 +0100)]
ac/surf: Prepare for 64-bit flags.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7953>
Samuel Pitoiset [Fri, 8 Jan 2021 13:39:40 +0000 (14:39 +0100)]
radv: only re-initialize HTILE after ds compute resolves if compressed
If the current layout isn't compressed we don't have to re-initialize
the HTILE metadata.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8389>
Samuel Pitoiset [Fri, 8 Jan 2021 13:35:36 +0000 (14:35 +0100)]
radv: re-initialize HTILE properly after depth/stencil compute resolves
This was added to workaround some CTS failures which no longer happen.
Note that radv_clear_htile() will only clear the depth or stencil
bytes of the HTILE buffer based on the aspect.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8389>
Samuel Pitoiset [Thu, 7 Jan 2021 07:38:01 +0000 (08:38 +0100)]
radv: disable TC-compat HTILE in GENERAL for Detroit: Become Human
The game has invalid usage of render loops and enabling TC-compat
HTILE in GENERAL introduces rendering issues.
Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3063
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8359>
Samuel Pitoiset [Mon, 11 Jan 2021 08:20:48 +0000 (09:20 +0100)]
radv: fix crashes when fast-clearing in a secondary command buffer
iview can be NULL inside a secondary command buffer.
Fixes:
00064713a30 ("radv: determine at creation if an image view can be fast cleared")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8408>
Erik Faye-Lund [Sun, 10 Jan 2021 12:57:15 +0000 (13:57 +0100)]
zink: use hardware int64 when supported
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8403>
Erik Faye-Lund [Sun, 10 Jan 2021 12:58:26 +0000 (13:58 +0100)]
zink: add missing 64-bit integer ops
This seems to be all that's missing to support hardware int64 instead of
lowering it.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8403>
Erik Faye-Lund [Sun, 10 Jan 2021 12:52:41 +0000 (13:52 +0100)]
zink: add missing opcodes
This fixes a bunch of conversion-tests in the arb_gpu_shader_int64
piglit test-suite for me.
Fixes:
55e2d836f37 ("zink: enable 64bit pipe caps")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8403>
Pierre-Eric Pelloux-Prayer [Fri, 8 Jan 2021 12:17:42 +0000 (13:17 +0100)]
dri: enable glthread + radeonsi workaround for CS:GO
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4021
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8383>
Pierre-Eric Pelloux-Prayer [Fri, 8 Jan 2021 09:51:37 +0000 (10:51 +0100)]
ac/rgp: add missing include
The build would fail without this include if -std=gnu17 is used.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4057
Fixes:
ffdfe136e67 ("ac/sqtt: move rgp/sqtt def to ac")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8376>
Samuel Pitoiset [Fri, 8 Jan 2021 12:09:59 +0000 (13:09 +0100)]
ci: re-mark some depth/stencil resolve CTS as expected failures
They were removed during the last update but they still fail.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8385>
Samuel Pitoiset [Tue, 5 Jan 2021 13:28:53 +0000 (14:28 +0100)]
radv: do not predicate FMASK decompression when DCC+MSAA is used
Even if the FCE predicate is FALSE, we might still need to decompress
FMASK if compressed rendering was used. FMASK decompressions should
never been predicated.
This fixes a ton of CTS failures and a rendering issue with Control
when DCC+MSAA is force-enabled.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8331>