Thomas H.P. Andersen [Sat, 18 Dec 2021 00:46:43 +0000 (01:46 +0100)]
r600: remove a set but not used variable
grid_size was never used. Not even when introduced
in
6a829a1b724ca0d960decee217d260b4de8a5463
Fixes a warning on clang
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14252>
Thomas H.P. Andersen [Sat, 18 Dec 2021 00:23:37 +0000 (01:23 +0100)]
r300: remove a set but not used variable
The use of phase_refmask was removed 12 years ago
in
b7cf887ca74561469c144f1d12227e1bcf277e7e
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14252>
Thomas H.P. Andersen [Fri, 17 Dec 2021 16:11:51 +0000 (17:11 +0100)]
i915g: fix implicit-fallthrough warning
Fixes a warning on clang.
Uses FALLTHROUGH like the surrounding code.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14252>
Thomas H.P. Andersen [Fri, 17 Dec 2021 16:09:57 +0000 (17:09 +0100)]
lavapipe: fix implicit-fallthrough warning
Fixes a warning on clang
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14252>
Marcin Ślusarz [Tue, 21 Dec 2021 11:16:21 +0000 (12:16 +0100)]
intel/compiler: disable workaround not applicable to gfx >= 11
There's nothing in bspec that would suggest this is still needed.
It only affected gfx 9 and 10.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14280>
Guido Günther [Wed, 15 Dec 2021 14:14:36 +0000 (15:14 +0100)]
etnaviv: Use mesa_log*
Makes it consistent with the DRM bits
Signed-off-by: Guido Günther <guido.gunther@puri.sm>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10546>
Guido Günther [Wed, 15 Dec 2021 14:11:44 +0000 (15:11 +0100)]
entaviv/drm: Use same log format as gallium bits
We prefix with __func__:__LINE__ there.
Signed-off-by: Guido Günther <guido.gunther@puri.sm>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10546>
Guido Günther [Wed, 15 Dec 2021 13:43:05 +0000 (14:43 +0100)]
etnaviv/drm: Use mesa_log* for debugging
This makes sure errors, warnings and info messages don't get
compiled out in non debug builds.
Signed-off-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10546>
Guido Günther [Wed, 15 Dec 2021 13:34:53 +0000 (14:34 +0100)]
etnaviv/drm: Print gpu model at debug verbosity
Otherwise we print it at every application start.
Signed-off-by: Guido Günther <guido.gunther@puri.sm>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10546>
Guido Günther [Tue, 27 Apr 2021 09:43:11 +0000 (11:43 +0200)]
etnaviv/drm: Add some bo debug output
This makes it simpler to trace BO usage.
Signed-off-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10546>
Guido Günther [Tue, 27 Apr 2021 09:21:32 +0000 (11:21 +0200)]
etnaviv/drm: Use etna_mesa_debug for debugging messages
We use the variable from gallium but fall back to a weak symbol
in case there's usage out of galllium in the future.
Signed-off-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10546>
Tapani Pälli [Thu, 16 Dec 2021 17:01:34 +0000 (19:01 +0200)]
glsl: fix invariant qualifer usage and matching rule for GLSL 4.20
I noticed that GLSL version referenced here was wrong, version 4.20 is
first spec that does not allow invariant keyword for inputs.
v2: fix all comments (Timothy Arceri)
Fixes:
f9f462936ad ("glsl: Fix invariant matching in GLSL 4.30 and GLSL ES 1.00.")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14241>
Thomas H.P. Andersen [Mon, 20 Dec 2021 21:31:58 +0000 (22:31 +0100)]
ci: debian-clang: drop -Wno-error for self-assign
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14272>
Thomas H.P. Andersen [Mon, 20 Dec 2021 21:25:53 +0000 (22:25 +0100)]
gallivm: avoid a self-assign warning
Fixes a clang warning
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14272>
Vinson Lee [Mon, 20 Dec 2021 04:08:37 +0000 (20:08 -0800)]
panfrost: Avoid double unlock.
Fix defect reported by Coverity Scan.
Double unlock (LOCK)
double_unlock: pthread_mutex_unlock unlocks dev->indirect_draw_shaders.lock while it is unlocked.
Fixes:
2e6d94c198e ("panfrost: Add helpers to support indirect draws")
Suggested-by: Alyssa Rosenzweig <alyssa@collabora.com>
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14262>
Vinson Lee [Sun, 19 Dec 2021 23:41:51 +0000 (15:41 -0800)]
ir3: Make shift operand 64-bit.
Fix defect reported by Coverity Scan.
Unintentional integer overflow (OVERFLOW_BEFORE_WIDEN)
overflow_before_widen: Potentially overflowing expression 2 << W
with type int (32 bits, signed) is evaluated using 32-bit
arithmetic, and then used in a context that expects an expression
of type uint64_t (64 bits, unsigned).
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Acked-by: Rob Clark <robclark@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14258>
Timur Kristóf [Tue, 21 Dec 2021 14:24:21 +0000 (15:24 +0100)]
aco/optimizer_postRA: Fix applying VCC to branches.
Fixes:
a93092d0edc92eea8e8e96709ad9857f05c45cef
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14281>
Timur Kristóf [Tue, 21 Dec 2021 14:21:32 +0000 (15:21 +0100)]
aco/optimizer_postRA: Fix combining DPP into VALU.
Fixes:
4ac47ad1cd7976d7effbbfae37fa69e26a288ad2
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14281>
Thomas H.P. Andersen [Mon, 20 Dec 2021 19:09:15 +0000 (20:09 +0100)]
ci: clean up debian-clang no-error list
I see no warnings for these on a local build
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14269>
Caio Oliveira [Mon, 20 Dec 2021 23:19:35 +0000 (15:19 -0800)]
anv: Simplify assertions related to graphics stages
In all three cases, COMPUTE was on the table but with an invalid
value (zero). Drop it from the tables and the extra assertion, so if
a COMPUTE is passed it will just fail the ARRAY_SIZE assertion.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14274>
Daniel Schürmann [Tue, 21 Dec 2021 11:17:24 +0000 (12:17 +0100)]
aco/ra: fix get_reg_for_operand() in case of stride mismatches
We have to clear the register file from the previous operand
as otherwise, there might be no space left.
Totals from 5 (0.00% of 134572) affected shaders: (GFX10.3)
CodeSize: 21144 -> 21000 (-0.68%); split: -0.72%, +0.04%
Instrs: 3738 -> 3720 (-0.48%); split: -0.51%, +0.03%
Latency: 517229 -> 516319 (-0.18%); split: -0.18%, +0.00%
InvThroughput: 49068 -> 48902 (-0.34%); split: -0.38%, +0.04%
Copies: 501 -> 483 (-3.59%); split: -3.79%, +0.20%
Cc: mesa-stable
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14279>
Jesse Natalie [Mon, 20 Dec 2021 23:29:57 +0000 (15:29 -0800)]
d3d12: Fix NV12 resource importing
Fixes:
a6db8054 ("d3d12: Handle opening planar resources")
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14276>
Daniel Schürmann [Thu, 7 Oct 2021 18:21:24 +0000 (20:21 +0200)]
nir/opt_algebraic: lower fneg_hi/lo to fmul
This pattern, found in the FSR upscaling shader,
helps the vectorization efforts by keeping the
chain of vectorized instructions intact.
Radeon can optimize it to per-component fneg modifiers.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13688>
Daniel Schürmann [Mon, 13 Dec 2021 18:58:46 +0000 (19:58 +0100)]
aco/optimizer: propagate and fold inline constants on VOP3P instructions
This patch aims to propagate and fold constants on VOP3P instructions
by using omod selection and the fneg modifier.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13688>
Daniel Schürmann [Thu, 4 Nov 2021 17:40:44 +0000 (18:40 +0100)]
aco: change fneg for VOP3P to use fmul with +1.0
This will be useful to be able to also apply
fneg_lo and fneg_hi.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13688>
Daniel Schürmann [Thu, 4 Nov 2021 17:37:03 +0000 (18:37 +0100)]
aco/optimizer: fix fneg modifier propagation on VOP3P
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13688>
Caio Oliveira [Tue, 21 Dec 2021 08:40:53 +0000 (00:40 -0800)]
anv: Refactor dirty masking in cmd_buffer_flush_state
Instead of masking the dirty variable itself, use an appropriate mask
in the users of dirty. This will avoid extra tracking when dealing
with Task/Mesh later.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14275>
Caio Oliveira [Tue, 21 Dec 2021 08:36:10 +0000 (00:36 -0800)]
anv/blorp: Split blorp_exec into a render and compute
And set the relevant push_constants_dirty for each case.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14275>
Roman Stratiienko [Wed, 8 Dec 2021 10:15:38 +0000 (12:15 +0200)]
v3dv: add Android support
Acknowledgements to android-rpi team and lineage-rpi maintainer (KonstaT)
for creating/testing initial vulkan support. Their experience was used as
a baseline for this work.
Most of the code is a copy of turnip and anv.
Improved by cleaning dEQP failures:
- Improved gralloc support (use allocation time stride, size, modifier).
- Fixed some dEQP crashes due to memory allocation issues.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14016>
Emma Anholt [Mon, 20 Dec 2021 20:48:15 +0000 (12:48 -0800)]
r300/vs: Fix flow control processing just after an endloop.
We tried to step over the instruction we just generated, except we didn't
always just generate one. In the sequence_vertex tests, that meant we
skipped processing the next BGNLOOP and then underflowed our stack.
Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14271>
Emma Anholt [Mon, 20 Dec 2021 19:28:36 +0000 (11:28 -0800)]
r300/vs: Reuse rc_match_bgnloop().
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14271>
Emma Anholt [Mon, 20 Dec 2021 20:09:28 +0000 (12:09 -0800)]
r300/vs: Allocate temps we see a use as a source, too.
This is a quick hack for a bunch of the fail in #5766.
Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14271>
Emma Anholt [Mon, 20 Dec 2021 20:27:01 +0000 (12:27 -0800)]
ci/r300: Add another xfail on the main branch.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14271>
Francisco Jerez [Tue, 14 Dec 2021 21:40:49 +0000 (13:40 -0800)]
intel/fs: Add physical fall-through CFG edge for unconditional BREAK instruction.
This adds a missing CFG edge that represents a possible physical
control flow path the EU might take under some conditions which isn't
part of the logical CFG of the program. This possibility shouldn't
have led to problems on platforms prior to Gfx12, since the missing
control flow edge cannot possibly influence liveness intervals.
However on Gfx12+ it becomes the compiler's responsibility to resolve
data dependencies across instructions, and the missing physical
control flow paths may lead to a WaR data hazard currently not visible
to the software scoreboard pass, which could lead to data corruption.
Worse, the possibility for this path to be taken by the EU increases
on Gfx12+ due to a hardware bug affecting EU fusion -- However the
same physical path can be potentially taken on earlier platforms as
well, so this patch extends the CFG on all platforms for consistency,
even though the lack of this edge shouldn't lead to any functional
issues on platforms earlier than Gfx12. There are no shader-db
changes on earlier platforms, so there seems to be no disadvantage
from using the same CFG representation as on later platforms.
This issue has ben reported on TGL with the following conformance
test, thanks to Ian for bringing the FULSIM dependency check warning
to my attention:
dEQP-VK.graphicsfuzz.spv-stable-pillars-volatile-nontemporal-store
Fixes:
4d1959e69328cf ("intel/cfg: Represent divergent control flow paths caused by non-uniform loop execution.")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4940
Reported-by: Tapani Pälli <tapani.palli@intel.com>
Reported-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14248>
Emma Anholt [Fri, 17 Dec 2021 21:33:08 +0000 (13:33 -0800)]
glsl: Retire unused modes for lower_64bit_integer_instructions.
Unused since
424ac809bfac ("i965: Do int64 lowering in NIR")
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14249>
Emma Anholt [Fri, 17 Dec 2021 21:11:49 +0000 (13:11 -0800)]
glsl: Remove comment about non-existing DFREXP_TO_ARITH
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14249>
Emma Anholt [Fri, 17 Dec 2021 21:00:41 +0000 (13:00 -0800)]
glsl: Remove dead prototype for old do_discard_simplification().
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14249>
Emma Anholt [Fri, 17 Dec 2021 20:56:51 +0000 (12:56 -0800)]
glsl: Delete the optimize_redundant_jumps pass.
Nothing here that NIR doesn't do. No effect on shader-db of hsw or
softpipe.
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14249>
Emma Anholt [Fri, 17 Dec 2021 20:41:10 +0000 (12:41 -0800)]
glsl: Delete the vectorization opt pass.
Nothing uses it, and i965 was the last thing to. Even if I enable it for
softpipe or crocus, it quickly causes NIR validation failures in shader-db
from swizzles outside the bounds of vectors. Retire it in favor of
nir_opt_vectorize().
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14249>
Rob Clark [Sat, 4 Dec 2021 00:29:13 +0000 (16:29 -0800)]
freedreno/ir3: Dump const state with shader disasm
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14231>
Rob Clark [Fri, 3 Dec 2021 00:23:13 +0000 (16:23 -0800)]
freedreno/computerator: Mark shader bo for dumping
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14231>
Rob Clark [Fri, 3 Dec 2021 00:10:39 +0000 (16:10 -0800)]
freedreno/computerator: Fix @buf header
Order is important in the grammar, the more specific match needs to go
first.
Fixes:
ba1c989348d ("freedreno/computerator: pass iova of buffer to const register")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14231>
Rob Clark [Thu, 2 Dec 2021 01:06:20 +0000 (17:06 -0800)]
freedreno/ir3: Handle instr->address when cloning
Without this, a cloned instruction that takes full regs will trigger an
ir3_validate assert. This can happen, for ex, if an instruction that
writes p0.x and has a relative src gets cloned in ir3_sched.
Fixes an assert in Genshin Impact with a debug build.
Fixes:
9af795d9b98 ("ir3: Make ir3_instruction::address a normal register")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14231>
Alyssa Rosenzweig [Mon, 13 Dec 2021 20:26:13 +0000 (15:26 -0500)]
pan/bi: Specialize shaders for IDVS
We need to compile multiple variants and report them together in a
common shader info. To do so, we split off per-variant shader infos and
combine at the end.
glmark2 is very happy: https://people.collabora.com/~alyssa/idvs-g52.txt
Highlights include -bshading up 41% fps and -bbump:bump-render=high-poly
up 62% faster
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
Alyssa Rosenzweig [Mon, 13 Dec 2021 20:25:54 +0000 (15:25 -0500)]
pan/bi: Add helper to decide if IDVS should be used
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
Alyssa Rosenzweig [Fri, 10 Dec 2021 18:35:41 +0000 (13:35 -0500)]
pan/bi: Use position shader ST_CVT path
We need to use a preload instead of the LEA_ATTR. Not sure why.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
Alyssa Rosenzweig [Mon, 13 Dec 2021 17:59:43 +0000 (12:59 -0500)]
pan/bi: Split out varying store paths
This means we don't need to special case IDVS quite so hard.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
Alyssa Rosenzweig [Mon, 13 Dec 2021 20:24:15 +0000 (15:24 -0500)]
pan/bi: Remove the "wrong" stores in IDVS variants
Position shaders should only write gl_Position (and gl_PointSize on
Valhall), varying shaders should only write varyings.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
Alyssa Rosenzweig [Mon, 13 Dec 2021 20:23:37 +0000 (15:23 -0500)]
pan/bi: Add IDVS mode to bi_context
Various parts of the compiler switch behaviour based on IDVS variant.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
Alyssa Rosenzweig [Mon, 13 Dec 2021 20:22:30 +0000 (15:22 -0500)]
pan/bi: Allow UBO pushing to run multiple times
For IDVS.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
Alyssa Rosenzweig [Fri, 10 Dec 2021 16:23:38 +0000 (11:23 -0500)]
pan/bi: Extract bi_finalize_nir
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
Alyssa Rosenzweig [Mon, 13 Dec 2021 18:25:21 +0000 (13:25 -0500)]
panfrost: Add panfrost_compile_inputs->no_idvs option
panvk will want IDVS support eventually, but not right now. Allow the
driver to opt out of IDVS in the mean time.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
Alyssa Rosenzweig [Fri, 10 Dec 2021 19:31:25 +0000 (14:31 -0500)]
panfrost: Align instance size for IDVS
Hardware requirement. Failing to do this raises a DATA_INVALID_FAULT.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
Alyssa Rosenzweig [Fri, 10 Dec 2021 19:21:02 +0000 (14:21 -0500)]
panfrost: Skip rasterizer discard draws without side effects
Minor optimization, but more importantly fixes an interaction of IDVS
with rasterizer discard.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
Alyssa Rosenzweig [Fri, 10 Dec 2021 00:05:28 +0000 (19:05 -0500)]
panfrost: Extract panfrost_batch_skip_rasterization
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
Alyssa Rosenzweig [Thu, 9 Dec 2021 23:42:01 +0000 (18:42 -0500)]
panfrost: Emit IDVS jobs
When trying to draw with an IDVS capable shader.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
Alyssa Rosenzweig [Thu, 9 Dec 2021 23:41:27 +0000 (18:41 -0500)]
panfrost: Extract panfrost_draw_emit_vertex_section
To be shared with IDVS.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
Alyssa Rosenzweig [Thu, 9 Dec 2021 22:13:45 +0000 (17:13 -0500)]
panfrost: Set secondary_* fields for IDVS
Easy now that we've split everything out nicely.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
Alyssa Rosenzweig [Thu, 9 Dec 2021 22:10:55 +0000 (17:10 -0500)]
panfrost: Remove regalloc from v6.xml
These fields were not introduced until v7, fix that.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
Alyssa Rosenzweig [Thu, 9 Dec 2021 22:08:13 +0000 (17:08 -0500)]
panfrost: Split out regalloc/preload helpers
The logic gets duplicated if IDVS is in use.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
Alyssa Rosenzweig [Thu, 9 Dec 2021 21:26:25 +0000 (16:26 -0500)]
panfrost: Add IDVS fields to shader_info
This lets the compiler decide if IDVS should be used.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
Alyssa Rosenzweig [Sat, 23 Oct 2021 21:29:14 +0000 (17:29 -0400)]
panfrost: Treat IDVS jobs as tiler for scoreboarding
These need to be chained and need to provoke a fragment job when we're
done.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
Alyssa Rosenzweig [Sat, 23 Oct 2021 19:25:02 +0000 (15:25 -0400)]
panfrost: Fix Secondary Shader field
Off-by-one on the start.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reported-by: Icecream95 <ixn@disroot.org>
Fixes:
73e80994d50 ("panfrost: Add secondary shader XML fields")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
Alyssa Rosenzweig [Thu, 9 Dec 2021 21:54:43 +0000 (16:54 -0500)]
panfrost: Remove unused shader info bits
These were only used to infer preloading and can be deleted.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
Alyssa Rosenzweig [Thu, 9 Dec 2021 21:51:02 +0000 (16:51 -0500)]
panfrost: Set preload descriptor more accurately
Preload exactly what the shader needs, based on the compiler's mask of
uninitialized registers, rather than trying to sync pan_shader.h with
the behaviour of code gen. Would've saved me some debugging over the
years...
As a bonus this avoids preloading unnecessary registers, particularly in
compute shaders. In theory this should reduce power consumption.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
Alyssa Rosenzweig [Thu, 9 Dec 2021 21:50:21 +0000 (16:50 -0500)]
panfrost: Track preloaded registers
We already collect this information. We may as well make use of it.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
Alyssa Rosenzweig [Mon, 13 Dec 2021 17:45:50 +0000 (12:45 -0500)]
pan/indirect_draw: Support IDVS jobs
Handle as tiler jobs with an extra vertex DCD at the end.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
Alyssa Rosenzweig [Mon, 13 Dec 2021 17:15:55 +0000 (12:15 -0500)]
pan/indirect_draw: Split out update_dcd
This is common between vertex/tiler jobs and needs to be duplicated for
IDVS jobs.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
Alyssa Rosenzweig [Mon, 13 Dec 2021 20:18:56 +0000 (15:18 -0500)]
pan/indirect_draw: Don't upload garbage UBO
There should never be a CPU pointer in GPU memory, let's say that...
Fixes:
2e6d94c198e ("panfrost: Add helpers to support indirect draws")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14154>
Rafael Antognolli [Tue, 9 Oct 2018 21:14:15 +0000 (14:14 -0700)]
intel: Emit 3DSTATE_BINDING_TABLE_POOL_ALLOC for XeHP
On XeHP+, Binding Table Pointers are an offset relative to the Surface
State Base Address anymore. Instead, they are relative to the State
Binding Table Pool Address, which is set by the command above.
We emit that command (pointing to the same address as the Surface
State Base Addresss), and everything should stay working as before.
Reworks:
* Jordan: Add iris
* Jordan: Drop i965
* Ken: Set MOCS to avoid a major perf impact. (Found by Felix DeGrood.)
* Jordan: Shrink size from 2MiB to actual iris, anv usage
* Lionel: Add BINDING_TABLE_POOL_BLOCK_SIZE
Ref: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4995
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
[jordan.l.justen@intel.com: Add Iris, adjust sizes]
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13992>
Jordan Justen [Mon, 20 Dec 2021 06:22:26 +0000 (22:22 -0800)]
anv: Add BINDING_TABLE_POOL_BLOCK_SIZE
Suggested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13992>
Jordan Justen [Mon, 20 Dec 2021 05:31:08 +0000 (21:31 -0800)]
intel/genxml/12.5: Remove bt-pool enable from 3DSTATE_BINDING_TABLE_POOL_ALLOC
This was dropped in gfx12.5.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13992>
Alyssa Rosenzweig [Tue, 14 Dec 2021 19:27:47 +0000 (14:27 -0500)]
docs/macos: Update for recent Mesa changes
- Default c_std is now c11, no need to workaround
89b4f337d50 ("c_std=c11 in meson default_options")
- gallium-xlib has been renamed to xlib:
76791db0882 ("mesa/x11: Remove the swrast-classic-based fake libGL")
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14216>
Jason Ekstrand [Fri, 10 Dec 2021 16:34:20 +0000 (10:34 -0600)]
vulkan/runtime: Validate instance version on 1.0 implementations
This isn't something that ANV or RADV have cared about in a long time
but, as people bring up new Vulkan drivers, shipping Vulkan 1.0 is still
a thing that happens in Mesa. The common code should also implement the
1.0 rules.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14150>
Jesse Natalie [Sat, 11 Dec 2021 18:49:21 +0000 (10:49 -0800)]
microsoft/compiler: Load synthesized sysvals via lowered io
Reviewed-by: Enrico Galli <enrico.galli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14175>
Jesse Natalie [Sat, 11 Dec 2021 17:57:36 +0000 (09:57 -0800)]
microsoft/compiler: Delete non-sysval deref load/store code
Reviewed-by: Enrico Galli <enrico.galli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14175>
Jesse Natalie [Sat, 11 Dec 2021 18:16:21 +0000 (10:16 -0800)]
microsoft/compiler: Lower io
Reviewed-by: Enrico Galli <enrico.galli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14175>
Jesse Natalie [Sat, 11 Dec 2021 17:42:03 +0000 (09:42 -0800)]
microsoft/compiler: Support lowered io (nir_intrinsic_load_input/store_output)
Reviewed-by: Enrico Galli <enrico.galli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14175>
Simon Ser [Tue, 17 Aug 2021 16:43:45 +0000 (18:43 +0200)]
renderonly: write down usage rules
The renderonly helpers are extremely easy to mis-use. Write down
the expectations.
I've seen *many* mistakes in the past, including:
- Forgetting to create the scanout resource on import [1] [2], causing
bugs such as [3].
- Assuming the scanout resource always exists [4].
- Returning a GEM handle valid for the driver's internal DRM FD, but
invalid for the caller's DRM FD [5].
- Not implementing resource_get_param, breaking stride/offset/modifier
queries when no scanout resource is available [6] [7].
Signed-off-by: Simon Ser <contact@emersion.fr>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Daniel Stone <daniels@collabora.com>
[1]: https://gitlab.freedesktop.org/mesa/mesa/-/commit/
4aac98f8a68b4c6407a5f41a91bfd7763f0607d7
[2]: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12018
[3]: https://github.com/swaywm/wlroots/issues/2795
[4]: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12081
[5]: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12074
[6]: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12362
[7]: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12370
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12418>
Dave Airlie [Fri, 10 Dec 2021 01:06:29 +0000 (11:06 +1000)]
mesa/st: move st strings handling into mesa
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14257>
Dave Airlie [Thu, 9 Dec 2021 19:03:04 +0000 (05:03 +1000)]
mesa/st: migrate barrier code into mesa
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14257>
Dave Airlie [Thu, 9 Dec 2021 06:55:18 +0000 (16:55 +1000)]
mesa/st: move msaa functionality into multisample.c
This moves some state track code into main
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14257>
Dave Airlie [Thu, 9 Dec 2021 06:52:46 +0000 (16:52 +1000)]
mesa/st: move get sample position code to static in mesa
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14257>
Dave Airlie [Wed, 15 Dec 2021 01:46:36 +0000 (11:46 +1000)]
mesa/compute: refactor compute launch to look more like draw
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14256>
Dave Airlie [Wed, 15 Dec 2021 00:51:31 +0000 (10:51 +1000)]
mesa/st: migrate compute dispatch to mesa
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14256>
Dave Airlie [Thu, 9 Dec 2021 00:56:49 +0000 (10:56 +1000)]
mesa/st: refactor compute dispatch to fill grid info earlier.
This fills the grid info earlier and uses info in validation
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14256>
Kostiantyn Lazukin [Thu, 16 Dec 2021 11:23:49 +0000 (13:23 +0200)]
util/ra: Fix numeric overflow during bitset allocation
Reviewed-by: Emma Anholt <emma@anholt.net>
Signed-off-by: Kostiantyn Lazukin <kostiantyn.lazukin@globallogic.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5752
Fixes:
d4a4cd20d52 ("util/ra: use adjacency matrix for undirected graph")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14224>
Thomas H.P. Andersen [Thu, 16 Dec 2021 22:09:55 +0000 (23:09 +0100)]
meson: drop a temp formatting variable
This was only needed in meson < 0.50
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14240>
Thomas H.P. Andersen [Thu, 16 Dec 2021 22:06:37 +0000 (23:06 +0100)]
docs: update the required meson version
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14240>
Thomas H.P. Andersen [Thu, 16 Dec 2021 21:58:58 +0000 (22:58 +0100)]
meson: drop a comment relating to old meson version
This comment was related to an if/else on meson version that has
already been removed in
c1a290bdd57536d6afcff6a02f1512fba7328729
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14240>
Thomas H.P. Andersen [Thu, 16 Dec 2021 21:28:42 +0000 (22:28 +0100)]
meson: drop compatability with < 0.48
Before meson 0.48 the cpu_family() would return 'ppc64le' on little
endian power8. In newer versions it returns 'ppc64' and endianness
should be checked with endian()
We now require meson >= 0.53 so we can drop the compatability with
older versions.
The old behavior was added in
e430a034b9d2be626557931cd29808a3161889f1
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14240>
Jason Ekstrand [Wed, 10 Nov 2021 04:55:49 +0000 (22:55 -0600)]
intel/fs: Add a NONE scheduling mode
While our LIFO scheduling mode attempts to optimize for register
pressure, it's often hard for a scheduling algorithm to do better than
the instruction order provided by the shader author. Shader authors
often do perfectly reasonable things like using texture results
immediately after fetching them or constructing texture coordinates
immediately before the texture op. When we throw all the instruction
ordering information away, we loose any help the author may have given
us. By attempting NONE before we fall back to the worst case LIFO mode.
And, yes, I tried this with NONE both before and after LIFO and doing
NONE before LIFO is substantially better, according to shader-db.
total instructions in shared programs:
19673152 ->
19665202 (-0.04%)
instructions in affected programs: 33669 -> 25719 (-23.61%)
helped: 20
HURT: 0
helped stats (abs) min: 15 max: 4609 x̄: 397.50 x̃: 107
helped stats (rel) min: 2.33% max: 67.50% x̄: 14.60% x̃: 9.12%
95% mean confidence interval for instructions value: -867.61 72.61
95% mean confidence interval for instructions %-change: -21.74% -7.46%
Inconclusive result (value mean confidence interval includes 0).
total cycles in shared programs:
935562500 ->
935020920 (-0.06%)
cycles in affected programs:
18620349 ->
18078769 (-2.91%)
helped: 104
HURT: 48
helped stats (abs) min: 88 max: 60986 x̄: 8031.48 x̃: 3680
helped stats (rel) min: 0.61% max: 51.44% x̄: 14.95% x̃: 8.87%
HURT stats (abs) min: 10 max: 54724 x̄: 6118.62 x̃: 1530
HURT stats (rel) min: 0.13% max: 46.45% x̄: 10.28% x̃: 6.46%
95% mean confidence interval for cycles value: -5724.34 -1401.71
95% mean confidence interval for cycles %-change: -9.86% -4.10%
Cycles are helped.
total spills in shared programs: 12158 -> 10327 (-15.06%)
spills in affected programs: 1831 -> 0
helped: 20
HURT: 0
total fills in shared programs: 14749 -> 12635 (-14.33%)
fills in affected programs: 2114 -> 0
helped: 20
HURT: 0
LOST: 8
GAINED: 649
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13734>
Jason Ekstrand [Wed, 10 Nov 2021 01:03:19 +0000 (19:03 -0600)]
intel/fs: Reset instruction order before re-scheduling
The way the current scheduler loop is implemented, each scheduling pass
starts with what the previous pass had. This means that, if PRE screwed
everything up majorly, PRE_NON_LIFO would have to try to fix it. It
also meant that tiny changes to one pass would affect every later pass.
Instead, reset the order of the instructions before each scheduling
pass. This makes the passes entirely independent of each other.
Shader-db results on Ice Lake:
total instructions in shared programs:
19670486 ->
19670648 (<.01%)
instructions in affected programs: 25317 -> 25479 (0.64%)
helped: 2
HURT: 7
helped stats (abs) min: 4 max: 4 x̄: 4.00 x̃: 4
helped stats (rel) min: 0.07% max: 0.07% x̄: 0.07% x̃: 0.07%
HURT stats (abs) min: 8 max: 70 x̄: 24.29 x̃: 12
HURT stats (rel) min: 0.41% max: 4.95% x̄: 1.47% x̃: 0.87%
95% mean confidence interval for instructions value: -1.28 37.28
95% mean confidence interval for instructions %-change: -0.04% 2.30%
Inconclusive result (value mean confidence interval includes 0).
total cycles in shared programs:
935535948 ->
935490243 (<.01%)
cycles in affected programs:
421994824 ->
421949119 (-0.01%)
helped: 1269
HURT: 879
helped stats (abs) min: 1 max: 12008 x̄: 259.38 x̃: 52
helped stats (rel) min: <.01% max: 28.02% x̄: 1.12% x̃: 0.14%
HURT stats (abs) min: 1 max: 29931 x̄: 322.46 x̃: 20
HURT stats (rel) min: <.01% max: 32.17% x̄: 1.74% x̃: 0.22%
95% mean confidence interval for cycles value: -71.37 28.81
95% mean confidence interval for cycles %-change: -0.11% 0.21%
Inconclusive result (value mean confidence interval includes 0).
total spills in shared programs: 12403 -> 12430 (0.22%)
spills in affected programs: 1355 -> 1382 (1.99%)
helped: 2
HURT: 7
total fills in shared programs: 15128 -> 15182 (0.36%)
fills in affected programs: 3294 -> 3348 (1.64%)
helped: 2
HURT: 7
LOST: 21
GAINED: 28
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13734>
Jason Ekstrand [Wed, 10 Nov 2021 02:17:42 +0000 (20:17 -0600)]
Revert "intel/fs: Do cmod prop again after scheduling"
This reverts commit
ba2fa1ceaf4ccb905e1d841b45f88505449db44e. Doing
optimizations after scheduling but before RA means doing them in the
middle of the scheduling loop which introduces additional dependencies
between one scheduling iteration and the next. That won't work if we
want to make the scheduling modes independent, at least not unless we
have some way of fully cloning the IR.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13734>
Jason Ekstrand [Tue, 9 Nov 2021 22:09:23 +0000 (16:09 -0600)]
intel/eu: Don't double-loop as often in brw_set_uip_jip
brw_find_next_block_end() scans through the instructions to find the end
of the block. We were calling it for every instruction in the program
which is, if you have a single basic block, makes the whole mess a nice
clean O(n^2) when it really doesn't need to be. Instead, only call
brw_find_next_block_end() as-needed. This brings it back to O(n) like
it should have been.
This cuts the runtime of the following Vulkan CTS on my SKL box by 5%
from 1:51 to 1:45: dEQP-VK.ssbo.phys.layout.random.16bit.scalar.13
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13734>
Jason Ekstrand [Tue, 9 Nov 2021 20:38:48 +0000 (14:38 -0600)]
intel/fs: Use OPT() for split_virtual_grfs
Now that we're being conservative in the pass, it's easy to tell when it
makes progress and we can put it in the OPT() macro. This way, we get
nice INTEL_DEBUG=optimizer dumps for it. While we're here, fix the
header comment which is massively out-of-date.
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13734>
Jason Ekstrand [Tue, 9 Nov 2021 20:37:57 +0000 (14:37 -0600)]
intel/fs: Be more conservative in split_virtual_grfs
Instead of modifying every single instruction, keep track of which VGRFs
are actually split in a bit-set, and only modify the instructions that
actually touch split regs.
This cuts the runtime of the following Vulkan CTS on my SKL box by 45%
from 3:21 to 1:51: dEQP-VK.ssbo.phys.layout.random.16bit.scalar.13
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13734>
Caio Oliveira [Wed, 15 Sep 2021 20:20:53 +0000 (13:20 -0700)]
spirv: Use the incorporated names
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14209>
Caio Oliveira [Mon, 20 Sep 2021 18:10:10 +0000 (11:10 -0700)]
spirv: Identify non-temporal image operand added in SPIR-V 1.6
Map it to the existing ACCESS_STREAM_CACHE_POLICY access mode.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14209>
Caio Oliveira [Wed, 15 Sep 2021 22:38:23 +0000 (15:38 -0700)]
nir: Handle volatile semantics for loading HelperInvocation builtin
SPV_EXT_demote_to_helper_invocation added OpDemoteToHelperInvocation
operation to turn an invocation into a helper invocation, but the
value of HelperInvocation (a builtin from Input storage class)
couldn't be modified dynamically without breaking compatibility.
For the extension the operation OpIsHelperInvocation was added to get
the dynamic value.
For SPIR-V 1.6, the demote operation was promoted, but now to get the
dynamic value the shader must issue a load to HelperInvocation with
Volatile memory access semantics.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14209>