Jonas Devlieghere [Wed, 5 Feb 2020 23:30:11 +0000 (15:30 -0800)]
Partially revert "[LLDB] Add DynamicLoaderWasmDYLD plugin for WebAssembly debugging"
This temporarily and partially reverts
3ec28da6d643 because it's missing
a directory.
Jessica Paquette [Wed, 5 Feb 2020 21:54:00 +0000 (13:54 -0800)]
[AArch64][GlobalISel] Emit TBNZ with G_BRCOND where the condition is SLT
When we have a G_ICMP which checks SLT, and the comparison is against 0, we
can emit a TBNZ instead of a CBZ.
This lets us fold in things into the branch, which can provide some code size
savings.
This is similar to the case in `AArch64TargetLowering::LowerBR_CC`.
https://reviews.llvm.org/D74090
Med Ismail Bennani [Wed, 5 Feb 2020 23:15:37 +0000 (00:15 +0100)]
[lldb/API] Fix non null-terminated stop-reason in SBThread::GetStopDescription
When trying to get the stop reason description using the SB API, the
buffer fetched was not null-terminated causing failures on the sanitized bot.
This patch should address those failures.
Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
Jessica Paquette [Wed, 5 Feb 2020 19:32:50 +0000 (11:32 -0800)]
[AArch64][GlobalISel][NFC] Factor out TB(N)Z emission code into its own function
Factor it out into `emitTestBit` and add some asserts to the new function.
This will be useful for implementing TB(N)Z emission for SLT/SGT compares.
Differential Revision: https://reviews.llvm.org/D74080
Jessica Paquette [Wed, 5 Feb 2020 18:25:48 +0000 (10:25 -0800)]
[AArch64][GlobalISel] Fold G_LSHR into test bit calculation
Add support for walking through G_LSHR in `getTestBitReg`. Equivalent to the
code in `getTestBitOperand` in AArch64ISelLowering.
```
(tbz (lshr x, c), b) -> (tbz x, b+c) when b + c is < # bits in x
```
Differential Revision: https://reviews.llvm.org/D74077
Jonas Paulsson [Mon, 20 Jan 2020 20:56:09 +0000 (21:56 +0100)]
[PHIElimination] Compile time optimization for huge functions.
This is a compile-time optimization for PHIElimination (splitting of critical
edges), which was reported at https://bugs.llvm.org/show_bug.cgi?id=44249. As
discussed there, the way to remedy the slowdowns with huge functions is to
pre-compute the live-in registers for each MBB in an efficient way in
PHIElimination.cpp and then pass that information along to
LiveVariabless::addNewBlock().
In all the huge test programs where this slowdown has been noticable, it has
dissapeared entirely with this patch.
Review: Björn Pettersson, Quentin Colombet.
Differential Revision: https://reviews.llvm.org/D73152
Jonas Devlieghere [Wed, 5 Feb 2020 23:08:18 +0000 (15:08 -0800)]
[lldb/CMake] Remove non-existing wasm-DYLD subdir
Jonas Devlieghere [Wed, 5 Feb 2020 22:34:15 +0000 (14:34 -0800)]
[lldb/debugserver] Link against Security
Jonas Devlieghere [Wed, 5 Feb 2020 17:53:10 +0000 (09:53 -0800)]
[lldb/Reproducers] (De)serialize char* like const char*
The current implementation has a discrepancy between how char pointers
are serialized and deserialized. The latter treats it like a const char*
while the former serializes it as a pointer to a basic type.
Both are potentially wrong, as char pointers are mostly used in
combination with a size, and nothing guarantees that the string's length
(its first null byte to be more precise) is greater or equal to its
size. The real solution is to have a custom (de)serializer that uses
both pieces of infromation.
However, the implementation should be consistent between serialization
and deserialization and I believe treating char* as const char* is the
better alternative.
Paolo Severini [Wed, 5 Feb 2020 18:33:13 +0000 (10:33 -0800)]
[LLDB] Add DynamicLoaderWasmDYLD plugin for WebAssembly debugging
Add a dynamic loader plug-in class for WebAssembly modules.
Differential Revision: https://reviews.llvm.org/D72751
Matt Arsenault [Sat, 25 Jan 2020 19:17:16 +0000 (14:17 -0500)]
AMDGPU: Make LDS_DIRECT an artifical register
Matt Arsenault [Tue, 4 Feb 2020 03:49:00 +0000 (22:49 -0500)]
GlobalISel: Allow CSE of G_IMPLICIT_DEF
The legalizer produces a lot of these, and they make reading legalized
MIR annoying. For some reason, this does seem to sometimes introduce
copies of implicit def, which is dumb.
David Blaikie [Wed, 5 Feb 2020 22:27:29 +0000 (14:27 -0800)]
DebugInfo: Stabilize DW_OP_convert tests so they don't depend on register allocation, etc
Fangrui Song [Wed, 5 Feb 2020 21:50:33 +0000 (13:50 -0800)]
[ELF][ARM] Fix regression of BL->BLX substitution after D73542
D73542 made a typo (`rel.type == R_PLT_PC`; should be `rel.expr`) and introduced a regression:
BL->BLX substitution was disabled when the target symbol is preemptible
(expr is R_PLT_PC).
The two added bl instructions in arm-thumb-interwork-shared.s check that
we patch BL to BLX.
Fixes https://bugs.chromium.org/p/chromium/issues/detail?id=1047531
Jonas Paulsson [Tue, 4 Feb 2020 23:12:36 +0000 (00:12 +0100)]
[SystemZ] Improve handling of inline asm constraints.
The "{=v0}" constraint did not result in the expected error message in the
abscence of the vector facility, because 'v0' matches as a string into the
AnyRegBitRegClass in common code.
This patch adds checks for vector support in case of "{v" and soft-float in
case of "{f" to remedy this.
Review: Ulrich Weigand.
Juneyoung Lee [Wed, 5 Feb 2020 21:41:58 +0000 (06:41 +0900)]
[MemCpyOpt] Simplify find*Alignment
Craig Topper [Wed, 5 Feb 2020 20:15:01 +0000 (12:15 -0800)]
[X86] Improve the gather scheduler models for SkylakeClient and SkylakeServer
The load ports need a cycle for each potentially loaded element just like Haswell and Skylake. Unlike Haswell and Broadwell, the number of uops does not scale with the number of elements. Instead the load uops run for multiple cycles.
I've taken the latency number from the uops.info. The port binding for the non-load uops is taken from the original IACA data I have.
Differential Revision: https://reviews.llvm.org/D74000
Matt Arsenault [Tue, 21 Jan 2020 22:23:07 +0000 (17:23 -0500)]
AMDGPU/GlobalISel: Remove bitcast legality hack
Juneyoung Lee [Wed, 5 Feb 2020 21:20:36 +0000 (06:20 +0900)]
MemCpyOpt cannot use ABI alignment even if it was not given
Summary: This patch fixes https://bugs.llvm.org/show_bug.cgi?id=44388 which incorrectly assigns an ABI alignment to memset when there was no explicit alignment given.
Reviewers: gchatelet, lenary, nikic
Reviewed By: nikic
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D74083
Jacques Pienaar [Wed, 5 Feb 2020 16:31:49 +0000 (08:31 -0800)]
[mlir] Update generic op ebnf to include region
Summary: Optional regions are supported in the generic op print/parse form, update the docs to match.
Differential Revision: https://reviews.llvm.org/D74061
Hans Wennborg [Wed, 5 Feb 2020 10:03:49 +0000 (11:03 +0100)]
Make llvm::crc32() work also for input sizes larger than 32 bits.
The problem was noticed by the Chrome OS toolchain folks
(crbug.com/1048445) because llvm-objcopy --add-gnu-debuglink would
insert the wrong checksum when processing a binary larger than 4 GB.
That use case regressed in
1e1e3ba2526 when we started using
llvm::crc32() in more places.
Differential revision: https://reviews.llvm.org/D74039
Matt Arsenault [Sun, 2 Feb 2020 17:13:48 +0000 (12:13 -0500)]
AMDGPU/GlobalISel: Add mem operand to s.buffer.load intrinsic
Really the intrinsic definition is wrong, but work around this
here. The DAG lowering introduces an MMO. We have to introduce a new
operation to avoid the verifier complaining about the missing mayLoad.
Sanjay Patel [Wed, 5 Feb 2020 19:41:50 +0000 (14:41 -0500)]
[x86] use getSplatIndex() in lowerShuffleAsBroadcast()
The old code was doing an N^2 search for splat index.
Differential Revision: https://reviews.llvm.org/D74064
Sanjay Patel [Wed, 5 Feb 2020 19:18:13 +0000 (14:18 -0500)]
[Analysis] add query to get splat value from array of ints
I was debug stepping through an x86 shuffle lowering and
noticed we were doing an N^2 search for splat index. I
didn't find the equivalent functionality anywhere else in
LLVM, so here's a helper that takes an array of int and
returns a splatted index while ignoring undefs (any
negative value).
This might also be used inside existing
ShuffleVectorInst/ShuffleVectorSDNode functions and/or
help with D72467.
Differential Revision: https://reviews.llvm.org/D74064
Victor Huang [Wed, 5 Feb 2020 19:47:54 +0000 (13:47 -0600)]
[PowerPC][NFC] Clang-format on commit 4b414d
Adrian McCarthy [Wed, 22 Jan 2020 00:45:51 +0000 (16:45 -0800)]
[VFS] More consistent support for Windows
Removed some #ifdefs specific to Windows handling of VFS paths. This
eliminates most of the differences between the Windows and non-Windows
code paths.
Making this work required some changes to account for the fact that VFS
file paths can be Posix style or Windows style, so you cannot just assume
that they use the host's native path style. In one case, this means
implementing our own version of make_absolute, since the filesystem code
in Support doesn't have styles in the sense that the path code does.
Differential Review: https://reviews.llvm.org/D71092
Matt Arsenault [Fri, 24 Jan 2020 15:01:15 +0000 (10:01 -0500)]
AMDGPU/GlobalISel: Legalize f64 G_FFLOOR for SI
Use cmp ord instead of cmp_class compared to the DAG version for the
nan check, but mostly try to match the existsing pattern.
I think the sign doesn't matter for fract, so we could do a little
better with the source modifier matching.
I think this is also still broken as in D22898, but I'm leaving it
as-is for now while I don't have an SI system to test on.
Nate Voorhies [Tue, 4 Feb 2020 19:30:30 +0000 (11:30 -0800)]
[NFC][RISCV] Fixing typo in comment.
Reviewers: luismarques, lenary
Reviewed By: lenary
Subscribers: hiraditya, asb, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, lenary, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73984
Stephen Neuendorffer [Wed, 29 Jan 2020 19:20:19 +0000 (11:20 -0800)]
[MLIR] Break cyclic dependencies with MLIRAnalysis
Summary:
MLIRAnalysis depended on MLIRVectorOps
MLIRVectorOps depended on MLIRAnalysis for Loop information.
Both of these can be solved by factoring out libraries related to loop
analysis into their own library. The new MLIRLoopAnalysis might be
better off with the Loop Dialect in the future.
Reviewers: nicolasvasilache, rriddle!, mehdi_amini
Reviewed By: mehdi_amini
Subscribers: Joonsoo, vchuravy, merge_guards_bot, mgorny, mehdi_amini, rriddle, jpienaar, burmako, shauheen, antiagainst, arpith-jacob, mgester, lucyrfox, aartbik, liufengdb, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73655
Stephen Neuendorffer [Wed, 5 Feb 2020 17:23:17 +0000 (09:23 -0800)]
[MLIR] Rename MemRefBoundCheck.cpp -> TestMemRefBoundCheck.cpp
Summary:
This makes it consistent with other test passes.
Reviewers: rriddle
Reviewed By: rriddle
Subscribers: merge_guards_bot, mgorny, mehdi_amini, jpienaar, burmako, shauheen, antiagainst, nicolasvasilache, arpith-jacob, mgester, lucyrfox, aartbik, liufengdb, Joonsoo, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D74068
Stephen Neuendorffer [Tue, 4 Feb 2020 17:19:03 +0000 (09:19 -0800)]
[MLIR] Move test passes out of lib/Analysis
Summary:
This breaks a cyclic library dependency where MLIRPass used the verifier
in MLIRAnalysis, but MLIRAnalysis also contained passes used for testing.
The presence of the test passes here is archaeology, predating
test/lib/Transform.
Reviewers: rriddle
Reviewed By: rriddle
Subscribers: merge_guards_bot, mgorny, mehdi_amini, jpienaar, burmako, shauheen, antiagainst, nicolasvasilache, arpith-jacob, mgester, lucyrfox, liufengdb, Joonsoo, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D74067
LLVM GN Syncbot [Wed, 5 Feb 2020 19:16:15 +0000 (19:16 +0000)]
[gn build] Port
b12176d2aaf
Nico Weber [Wed, 5 Feb 2020 19:15:11 +0000 (14:15 -0500)]
Revert "[llvm-reduce] add ReduceAttribute delta pass"
This reverts commit
fc62b36a000681c01e993242b583c5ec4ab48a3c.
Breaks tests on mac: http://45.33.8.238/mac/7301/step_11.txt
shafik [Wed, 5 Feb 2020 18:39:35 +0000 (10:39 -0800)]
[DebugInfo] Fix debug-info generation for block invocations so that we set the LinkageName
Currently when generating debug-info for a BlockDecl we are setting the Name to the mangled name and not setting the LinkageName.
This means we see the mangled name for block invcations ends up in DW_AT_Name and not in DW_AT_linkage_name.
This patch fixes this case so that we also set the LinkageName as well.
Differential Revision: https://reviews.llvm.org/D73282
Jan Korous [Wed, 5 Feb 2020 19:03:38 +0000 (11:03 -0800)]
Revert "Activate extension loading test on Darwin now that the underlying fix has landed"
This reverts commit
058070893428a480b76a137f647ae6b9c89ac2d4.
Kostya Kortchinsky [Wed, 5 Feb 2020 17:58:52 +0000 (09:58 -0800)]
[scudo][standalone] Fix a race in the secondary release
Summary:
I tried to move the `madvise` calls outside of one of the secondary
mutexes, but this backfired. There is situation when a low release
interval is set combined with secondary pressure that leads to a race:
a thread can get a block from the cache, while another thread is
`madvise`'ing that block, resulting in a null header.
I changed the secondary race test so that this situation would be
triggered, and moved the release into the cache mutex scope.
Reviewers: cferris, pcc, eugenis, hctim, morehouse
Subscribers: jfb, #sanitizers, llvm-commits
Tags: #sanitizers, #llvm
Differential Revision: https://reviews.llvm.org/D74072
Shu-Chun Weng [Tue, 4 Feb 2020 23:52:57 +0000 (15:52 -0800)]
[GlobalISel][AArch64] Fix contract cross-bank copies with SIMD instructions
contractCrossBankCopyIntoStore() finds the instruction defines the
source register and uses its output to replace the register. There are,
however, instructions that have multiple outputs, e.g. G_UNMERGE_VALUES.
Current implementation hardcodes to operand 0 and has no way of knowing
which output should be used.
This change adds another function to directly return the register that
is the source of the register and use that for folding.
This fixes https://bugs.llvm.org/show_bug.cgi?id=44783
Differential Revision: https://reviews.llvm.org/D74005
David Green [Wed, 5 Feb 2020 11:38:44 +0000 (11:38 +0000)]
[ARM] Add extra use test for MVE VPT blocks. NFC
River Riddle [Wed, 5 Feb 2020 18:28:30 +0000 (10:28 -0800)]
[mlir][ODS] Add documentation for the declarative assembly format.
Summary: This details the structure of the format, it's requirements, and gives a few examples.
Differential Revision: https://reviews.llvm.org/D73983
Fangrui Song [Wed, 5 Feb 2020 18:24:51 +0000 (10:24 -0800)]
[test] yaml2obj -docnum => --docnum=
Matt Arsenault [Mon, 20 Jan 2020 03:16:44 +0000 (22:16 -0500)]
GlobalISel: Assume G_INTRINSIC* are convergent
This is safer in case anyone tries to run MI optimization passes on
pre-selected MIR. If there turns out to be a real reason to do this,
we might need to add separate convergent intrinsic opcodes.
LLVM GN Syncbot [Wed, 5 Feb 2020 18:06:25 +0000 (18:06 +0000)]
[gn build] Port
fc62b36a000
Nick Desaulniers [Sun, 2 Feb 2020 15:38:14 +0000 (07:38 -0800)]
[llvm-reduce] add ReduceAttribute delta pass
Summary:
The output from llvm-reduce still has significantly more attributes than
bugpoint does. Teach llvm-reduce to remove attributes.
Reviewers: diegotf, dblaikie, george.burgess.iv
Subscribers: mgorny, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73853
Jessica Paquette [Mon, 3 Feb 2020 23:11:14 +0000 (15:11 -0800)]
[AArch64][GlobalISel] Fold G_ASHR into TB(N)Z bit calculation
This implements walking over G_ASHR in the same way as `getTestBitOperand` in
AArch64ISelLowering.
```
(tbz (ashr x, c), b) -> (tbz x, b+c) or (tbz x, msb) if b+c is > # bits in x
```
Differential Revision: https://reviews.llvm.org/D73933
Christopher Tetreault [Mon, 3 Feb 2020 20:46:42 +0000 (12:46 -0800)]
Reapply: [SVE] Fix bug in simplification of scalable vector instructions
This reverts commit
a05441038a3a4a011b9421751367c5c797d57137, reapplying
commit
31574d38ac5fa4646cf01dd252a23e682402134f
Petr Hosek [Fri, 31 Jan 2020 22:56:26 +0000 (14:56 -0800)]
[CMake] Filter libc++abi and libunwind from runtimes build in MSVC
These don't build on MSVC at the moment, so filter these out altogether
from the list of runtimes and print a warning.
Differential Revision: https://reviews.llvm.org/D73812
Matt Arsenault [Sun, 26 Jan 2020 17:50:24 +0000 (12:50 -0500)]
AMDGPU/GlobalISel: Prefer merge/unmerge ops to legalize TFE
These have a better chance of combining with other operations and are
currently much better supported than G_EXTRACT.
Jessica Paquette [Tue, 4 Feb 2020 23:10:53 +0000 (15:10 -0800)]
[AArch64][GlobalISel] Fix one use check in getTestBitReg
(1) The check needs to be on the 0th operand of whatever we're folding
(2) Checks for validity should happen before we change the bit
Fixes a bug which caused MultiSource/Applications/JM/lencod to fail at -O3.
Differential Revision: https://reviews.llvm.org/D74002
Matt Arsenault [Fri, 17 Jan 2020 19:16:58 +0000 (14:16 -0500)]
AMDGPU/GlobalISel: Legalize TFE image result loads
Rewrite the result register pair into the expected sinigle register
format in the legalizer.
I'm also operating under the assumption that TFE doesn't apply to
stores or atomics, but don't know if this is true or not.
Jonathan Coe [Wed, 5 Feb 2020 17:31:09 +0000 (17:31 +0000)]
[clang-format] Do not merge short C# class definitions into one line
Summary: Skip access specifiers before record definitions when deciding whether
or not to wrap lines so that C# class definitions do not get wrapped into a
single line.
Reviewers: krasimir, MyDeveloperDay
Reviewed By: krasimir
Tags: #clang-format
Differential Revision: https://reviews.llvm.org/D74050
Hiroshi Yamauchi [Fri, 17 Jan 2020 18:02:50 +0000 (10:02 -0800)]
[PGO][PGSO] Tune flags for profile guided size optimization.
Summary:
Tune the profile threshold flag value for instrumentation PGO based on internal
benchmarks.
Also, add flags to allow profile guided size optimizations for non-cold code
to be enabled separately for instrumentation and sample PGSO.
Neither changes the default behavior (yet) as it's disabled for non-cold code.
Reviewers: davidxl
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72937
Michał Górny [Fri, 31 Jan 2020 08:35:34 +0000 (09:35 +0100)]
[lldb] [test] Pass LLVM_LIBS_DIR from CMake for linking liblldb
Pass the correct library directory from CMake to dotest.py when linking
liblldb, instead of trying to reconstruct the path from executable path.
This fixes link failures on platforms having non-null
LLVM_LIBDIR_SUFFIX.
Differential Revision: https://reviews.llvm.org/D73767
Matt Arsenault [Fri, 31 Jan 2020 22:23:59 +0000 (17:23 -0500)]
AMDGPU: Fix divergence analysis of control flow intrinsics
The mask results of these should be uniform. The trickier part is the
dummy booleans used as IR glue need to be treated as divergent. This
should make the divergence analysis results correct for the IR the DAG
is constructed from.
This should allow us to eliminate requiresUniformRegister, which has
an expensive, recursive scan over all users looking for control flow
intrinsics. This should avoid recent compile time regressions.
Jonathan Coe [Wed, 5 Feb 2020 16:51:31 +0000 (16:51 +0000)]
[clang-format] Do not treat C# attribute targets as labels
Summary: Merge '[', 'target' , ':' into a single token for C# attributes to
prevent the target from being seen as a label.
Reviewers: MyDeveloperDay, krasimir
Reviewed By: krasimir
Tags: #clang-format
Differential Revision: https://reviews.llvm.org/D74043
Jordan Rupprecht [Wed, 5 Feb 2020 17:22:41 +0000 (09:22 -0800)]
NFC: fix unused var warnings in no-assert builds
Kazu Hirata [Wed, 5 Feb 2020 16:24:01 +0000 (08:24 -0800)]
Resubmit^2: [JumpThreading] Thread jumps through two basic blocks
This reverts commit
41784bed01543315a1d03141e6ddc023fd914c0b.
Since the original revision
ead815924e6ebeaf02c31c37ebf7a560b5fdf67b,
this revision fixes three issues:
- This revision fixes the Windows build. My original patch improperly
copied EH pads on Windows. This patch disregards jump threading
opportunities having to do with EH pads.
- This revision fixes jump threading to a wrong destination.
Specifically, my original patch treated any Constant other than 0 as 1
while evaluating the branch condition. This bug led to treating
constant expressions like:
icmp ugt i8* null, inttoptr (i64 4 to i8*)
to "true". This patch fixes the bug by calling isOneValue.
- This revision fixes the cost calculation of two basic blocks being
threaded through. Note that getJumpThreadDuplicationCost returns
"(unsigned)~0" for those basic blocks that cannot be duplicated. If
we sum of two return values from getJumpThreadDuplicationCost, we
could have an unsigned overflow like:
(unsigned)~0 + 5 = 4
and mistakenly determine that it's safe and profitable to proceed
with the jump threading opportunity. The patch fixes the bug by
checking each return value before summing them up.
[JumpThreading] Thread jumps through two basic blocks
Summary:
This patch teaches JumpThreading.cpp to thread through two basic
blocks like:
bb3:
%var = phi i32* [ null, %bb1 ], [ @a, %bb2 ]
%tobool = icmp eq i32 %cond, 0
br i1 %tobool, label %bb4, label ...
bb4:
%cmp = icmp eq i32* %var, null
br i1 %cmp, label bb5, label bb6
by duplicating basic blocks like bb3 above. Once we duplicate bb3 as
bb3.dup and redirect edge bb2->bb3 to bb2->bb3.dup, we have:
bb3:
%var = phi i32* [ @a, %bb2 ]
%tobool = icmp eq i32 %cond, 0
br i1 %tobool, label %bb4, label ...
bb3.dup:
%var = phi i32* [ null, %bb1 ]
%tobool = icmp eq i32 %cond, 0
br i1 %tobool, label %bb4, label ...
bb4:
%cmp = icmp eq i32* %var, null
br i1 %cmp, label bb5, label bb6
Then the existing code in JumpThreading.cpp can thread edge
bb3.dup->bb4 through bb4 and eventually create bb3.dup->bb5.
Reviewers: wmi
Subscribers: hiraditya, jfb, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70247
Alina Sbirlea [Mon, 27 Jan 2020 21:33:34 +0000 (13:33 -0800)]
[IRCE] Make IRCE a Function pass.
Summary: Make InductiveRangeCheckElimination a FunctionPass.
Reviewers: reames, mkazantsev
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D73592
Stephan Herhut [Wed, 5 Feb 2020 17:06:36 +0000 (17:06 +0000)]
[MLIR][GPU] Fix build files for mlir-opt.
The recent refactoring of build files broke building with the MIR CUDA
integration enabled. This fixes it by adding some additional
dependencies to mlir-opt.
Differential Revision: https://reviews.llvm.org/D74041
LLVM GN Syncbot [Wed, 5 Feb 2020 17:03:12 +0000 (17:03 +0000)]
[gn build] Port
b198f16e1e1
Matt Arsenault [Thu, 30 Jan 2020 22:34:33 +0000 (17:34 -0500)]
AMDGPU/GlobalISel: Legalize llvm.amdgcn.s.buffer.load
The 96-bit results need to be widened.
I find the interaction between LegalizerHelper and MIRBuilder somewhat
awkward. The custom legalization is called by the LegalizerHelper, but
then does not have access to the helper. You have to construct a new
helper, which then does not own the MachineIRBuilder, but does modify
it. Maybe custom legalization should be passed the helper?
Teresa Johnson [Wed, 22 Jan 2020 22:06:23 +0000 (14:06 -0800)]
[WPD/LowerTypeTests] Delay lowering/removal of type tests until after ICP
Summary:
Currently type test assume sequences inserted for devirtualization are
removed during WPD. This patch delays their removal until later in the
optimization pipeline. This is an enabler for upcoming enhancements to
indirect call promotion, for example streamlined promotion guard
sequences that compare against vtable address instead of the target
function, when there are small number of possible vtables (either
determined via WPD or by in-progress type profiling). We need the type
tests to correlate the callsites with the address point offset needed in
the compare sequence, and optionally to associated type summary info
computed during WPD.
This depends on work in D71913 to enable invocation of LowerTypeTests to
drop type test assume sequences, which will now be invoked following ICP
in the ThinLTO post-LTO link pipelines, and also after the existing
export phase LowerTypeTests invocation in regular LTO (which is already
after ICP). We cannot simply move the existing import phase
LowerTypeTests pass later in the ThinLTO post link pipelines, as the
comment in PassBuilder.cpp notes (it must run early because when
performing CFI other passes may disturb the sequences it looks for).
This necessitated adding a new type test resolution "Unknown" that we
can use on the type test assume sequences previously removed by WPD,
that we now want LTT to ignore.
Depends on D71913.
Reviewers: pcc, evgeny777
Subscribers: mehdi_amini, Prazek, hiraditya, steven_wu, dexonsmith, arphaman, davidxl, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D73242
Adam Balogh [Wed, 20 Nov 2019 08:15:42 +0000 (09:15 +0100)]
[Analyzer] Model STL Algoirthms to improve the iterator checkers
STL Algorithms are usually implemented in a tricky for performance
reasons which is too complicated for the analyzer. Furthermore inlining
them is costly. Instead of inlining we should model their behavior
according to the specifications.
This patch is the first step towards STL Algorithm modeling. It models
all the `find()`-like functions in a simple way: the result is either
found or not. In the future it can be extended to only return success if
container modeling is also extended in a way the it keeps track of
trivial insertions and deletions.
Differential Revision: https://reviews.llvm.org/D70818
Matt Arsenault [Sun, 2 Feb 2020 01:21:44 +0000 (20:21 -0500)]
AMDGPU/GlobalISel: Fix processing new phi in waterfall loop
The adjusted iterator range included the last we just inserted, and
don't want to process. Figure out the new iterator range before
inserting phis. This was a harmless problem, but added an unnecessary
complication for a future patch.
Matt Arsenault [Thu, 30 Jan 2020 23:05:12 +0000 (18:05 -0500)]
GlobalISel: Make LegalizerHelper primitives public
I want to re-use widenScalarDst/moreElementsVectorDst directly.
Matt Arsenault [Sat, 4 Jan 2020 20:35:26 +0000 (15:35 -0500)]
AMDGPU/GlobalISel: Don't use legal v2s16 G_BUILD_VECTOR
If we have s_pack_* instructions, legalize this to
G_BUILD_VECTOR_TRUNC from s32 elements. This is closer to how how the
s_pack_* instructions really behave.
If we don't have s_pack_ instructions, expand this by creating a merge
to s32 and bitcasting. This expands to the expected bit operations. I
think this eventually should go in a new bitcast legalize action type
in LegalizerHelper.
We already directly emit the shift operations in RegBankSelect for the
vector case. This could possibly be cleaned up, but I also may want to
defer doing this expansion to selection anyway. I'll see about that
when I try to actually match VOP3P instructions.
This breaks the selection of the build_vector since tablegen doesn't
know how to match G_BUILD_VECTOR_TRUNC yet, so just xfail it for now.
Med Ismail Bennani [Tue, 4 Feb 2020 16:53:26 +0000 (17:53 +0100)]
[lldb/Target] Add Assert StackFrame Recognizer
When a thread stops, this checks depending on the platform if the top frame is
an abort stack frame. If so, it looks for an assert stack frame in the upper
frames and set it as the most relavant frame when found.
To do so, the StackFrameRecognizer class holds a "Most Relevant Frame" and a
"cooked" stop reason description. When the thread is about to stop, it checks
if the current frame is recognized, and if so, it fetches the recognized frame's
attributes and applies them.
rdar://
58528686
Differential Revision: https://reviews.llvm.org/D73303
Signed-off-by: Med Ismail Bennani <medismail.bennani@gmail.com>
Momchil Velikov [Wed, 5 Feb 2020 15:19:03 +0000 (15:19 +0000)]
[ARM][TargetParser] Improve handling of dependencies between target features
The patch at https://reviews.llvm.org/D64048 added "negative"
dependency handling in `ARM::appendArchExtFeatures`: feature "noX"
removes all features, which imply "X".
This patch adds the "positive" handling: feature "X" adds all the
feature strings implied by "X".
(This patch also comes from the suggestion here
https://reviews.llvm.org/D72633#inline-658582)
Differential Revision: https://reviews.llvm.org/D72762
Sven van Haastregt [Wed, 5 Feb 2020 16:05:20 +0000 (16:05 +0000)]
[OpenCL] Fix tblgen support for cl_khr_mipmap_image_writes
Apply the fix of
f780e15caf1 ("[OpenCL] Fix support for
cl_khr_mipmap_image_writes", 2020-01-27) also to the TableGen OpenCL
builtin function definitions.
Alex Richardson [Wed, 5 Feb 2020 15:36:43 +0000 (15:36 +0000)]
Re-enable a update_cc_test_checks.py tests
This test was not running because it still had a REQUIRES: python3 line.
As this is no longer necessary, remove the REQUIRES to run the test
again.
Simon Pilgrim [Wed, 5 Feb 2020 15:31:38 +0000 (15:31 +0000)]
[clang][driver] Fix null pointer dereference warning inside PrintActions1 (PR43462)
As detailed on PR43462, clang static analyzer is complaining about a null pointer dereference as we provide a 'host' toolchain fallback if the ToolChain pointer is null, but then use that pointer anyhow to report the triple.
Tests indicate the ToolChain pointer is always valid and the 'host' code path is redundant.
Differential Revision: https://reviews.llvm.org/D74046
Sjoerd Meijer [Wed, 5 Feb 2020 15:15:46 +0000 (15:15 +0000)]
[ARM][MVE] LowOverheadLoops: DCE on the iteration count setup expression
Once we have created a tail-predicated hardware-loop, and thus know the number
of elements that are processed, we want to clean-up the iteration count
expression of that loop. In D73682, we bailed the analysis on conditionally
executed instructions. This adds support for IT-blocks, so that we can handle
these cases again. The restriction is that we only support IT blocks containing
1 statement, but that seems to cover most cases and forms of the iteration
count expression.
Differential Revision: https://reviews.llvm.org/D73947
Alexey Bataev [Wed, 5 Feb 2020 15:02:39 +0000 (10:02 -0500)]
[OPNEMP50][DOCS]Mark array shaping expression as claimed, NFC.
Alexey Bataev [Tue, 21 Jan 2020 19:16:29 +0000 (14:16 -0500)]
[OPENMP][NVPTX]Add NVPTX specific definitions for new/delete operators.
Summary:
To use new/delete in NVPTX code we need to define them. Implementation
copied from CUDA wrappers.
Reviewers: hfinkel, jdoerfert
Subscribers: mgorny, guansong, kkwli0, caomhin, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D73128
Stephan Herhut [Mon, 3 Feb 2020 15:33:36 +0000 (16:33 +0100)]
[MLIR] Add mapping based on ValueRange to BlockAndValueMapper.
Summary:
It is often needed to map entire ranges rather than single values. To avoid
writing the same for loop every time, I have added an overload to the map
method.
Differential Revision: https://reviews.llvm.org/D73894
Artem Dergachev [Tue, 4 Feb 2020 19:48:19 +0000 (22:48 +0300)]
[analyzer] Fix a couple of bugs in HTML report generation.
It should now produce valid HTML again.
Differential Revision: https://reviews.llvm.org/D73993
Momchil Velikov [Wed, 5 Feb 2020 13:54:18 +0000 (13:54 +0000)]
[ARM] Correct syntax of the CLRM insn
The predicate should be adjacent to the opcode.
Differential Revision: https://reviews.llvm.org/D74040
Andrea Di Biagio [Wed, 5 Feb 2020 12:51:29 +0000 (12:51 +0000)]
[MCA] Remove verification check on MayLoad and MayStore. NFCI
Field NumMicroOpcodes is currently used by mca to model the number of uOPs
dispatched from the uOp-Queue to the out of order backend. From a 'dispatch'
point of view, an instruction with zero opcodes is still valid; it simply
doesn't consume any dispatch group slots.
However, mca doesn't expect an instruction with zero uOPs to consume pipeline
resources because it is seen as a contradiction. In practice, it only makes
sense if such an instruction is eliminated and never really executed. It may be
that mca is being too conservative here. However I believe that mca is right,
and we should probably check that inconsistency in CodeGenSchedule.cpp (when we
also verify scheduling classes in general).
This patch removes the check for MayLoad and MayStore in mca. That check is
probably too conservative: we are already checking if a zero-uops instruction
consumes any processor resources. Note also that instructions with unmodelled
side-effects also tend to set the MayLoad/MayStore flags even if - theoretically
speaking - they might not even consume any hw resources in practice.
In future we may want to implement different checks (possibly outside of mca)
and potentially revisit the logic in mca that verifies instructions.
For that reason I have raised PR44797.
Simon Pilgrim [Wed, 5 Feb 2020 12:32:25 +0000 (12:32 +0000)]
visitINSERT_VECTOR_ELT - pull out repeated dyn_cast. NFCI.
This always gets called at least once.
Sam Parker [Wed, 5 Feb 2020 13:20:50 +0000 (13:20 +0000)]
[ARM][LowOverheadLoops] Fix loop count chain
Checking that the use-def chain that performs the loop count
isSafeToRemove is not sufficient because it means that we can
remove register copies that we need to restore lr to its correct
value. This change now prevents the transform from kicking in for the
'remove-elem-moves' test which needs to addressed later on.
Differential Revision: https://reviews.llvm.org/D74037
Sam Parker [Wed, 5 Feb 2020 12:47:03 +0000 (12:47 +0000)]
[ARM][LowOverheadLoops] Ensure memory predication
While validating each MVE instruction, check that all instructions
that touch memory are somehow predicated upon the VCTP.
Differential Revision: https://reviews.llvm.org/D73616
Raphael Isemann [Wed, 5 Feb 2020 13:07:19 +0000 (14:07 +0100)]
[lldb] Revert some change in data-formatter-objc/main.m that broke TestDataFormatterObjCNSDate.py
Changing the date2 to an timezone independent value broke the test as the data formatters
uses the current time zone for the summary (so changing it to a time zone independent value
would again break the test in some time zones). We anyway just care about this for date2
which will be printed in a timezone-independent summary.
Haojian Wu [Wed, 5 Feb 2020 08:56:13 +0000 (09:56 +0100)]
[clangd] Add the missing elaborated types in FindTarget.
Reviewers: sammccall
Subscribers: ilya-biryukov, MaskRay, jkorous, arphaman, kadircet, usaxena95, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D74025
Raphael Isemann [Wed, 5 Feb 2020 12:28:42 +0000 (13:28 +0100)]
[lldb][NFC] Remove some unnecessary curly braces
Michał Górny [Sun, 12 Jan 2020 21:49:36 +0000 (22:49 +0100)]
[lldb] Introduce i386 support in NetBSD Process plugin
Introduce support for i386 platform that is shared with amd64
in the same plugin. The concept is partially based on the Linux
implementation.
The plugin tries to reuse as much code as possible. As a result, i386
register enums are mapped into amd64 values and those are used in actual
code. The code for accessing FPU and debug registers is shared,
although general-purpose register layouts do not match between the two
kernel APIs and need to be #ifdef-ed.
This layout will also make it possible to add support for debugging
32-bit programs on amd64 with minimal added code.
In order for this to work, I had to add missing data for debug registers
on i386.
Differential Revision: https://reviews.llvm.org/D73802
Raphael Isemann [Wed, 5 Feb 2020 12:23:49 +0000 (13:23 +0100)]
[lldb] Make TestDataFormatterObjCCF.py pass outside California
Summary:
This test creates its dates with `NSDate dateWithNaturalLanguageString` which is deprecated and uses the current time zone of the machine to
interpret the input string. This causes that the created NSDate has a different value depending on the locale of the machine
and we hardcoded the value for California's time zone (PST) but the data formatter gives out the GMT value as a string.
This just replaces the use with the timezone-independent dateWithTimeIntervalSince1970 (which we also use in the rest of the test)
to make this pass independently of the time zone of the machine running the test.
Reviewers: mib
Reviewed By: mib
Subscribers: lldb-commits, JDevlieghere
Tags: #lldb
Differential Revision: https://reviews.llvm.org/D74038
Alexey Sotkin [Mon, 27 Jan 2020 09:25:03 +0000 (12:25 +0300)]
[OpenCL] Fix support for cl_khr_mipmap_image_writes
Text of the extension is available here:
https://github.com/KhronosGroup/OpenCL-Docs/blob/master/ext/cl_khr_mipmap_image.asciidoc
Patch by Ilya Mashkov
Differential Revision: https://reviews.llvm.org/D71460
Simon Pilgrim [Wed, 5 Feb 2020 11:36:36 +0000 (11:36 +0000)]
[X86] Fix missing load latencies (PR36894)
We weren't account for load latencies in the SSE42/AES/CLMUL schedule classes
Simon Pilgrim [Wed, 5 Feb 2020 10:49:43 +0000 (10:49 +0000)]
Fix MSVC signed/unsigned warning. NFCI.
Ayke van Laethem [Mon, 3 Feb 2020 19:01:44 +0000 (20:01 +0100)]
[AVR] Add disassembly tests for supported instructions
The disassembler of the AVR backend is incomplete: most instructions do
not correctly disassemble yet.
This patch is the first in a series to add disassembly support to the
AVR backend. It starts with adding disassembler tests for instructions
that already disassemble correctly.
Differential Revision: https://reviews.llvm.org/D73911
Martin Storsjö [Wed, 5 Feb 2020 11:29:48 +0000 (13:29 +0200)]
Partially revert
c1c9819ef91aab51b5a23fb3027adac5a2f551cc
Revert the part of that change that broke the
test Passes/./PluginsTests/PluginsTests.LoadPlugin.
Martin Storsjö [Sat, 1 Feb 2020 20:46:27 +0000 (22:46 +0200)]
[CMake] Add missing component dependencies, to fix building for mingw with BUILD_SHARED_LIBS
Differential Revision: https://reviews.llvm.org/D73840
Haojian Wu [Wed, 5 Feb 2020 11:03:29 +0000 (12:03 +0100)]
[clangd] Pull out a isProtoFile function.
Reviewers: kadircet
Reviewed By: kadircet
Subscribers: merge_guards_bot, mgorny, ilya-biryukov, MaskRay, jkorous, arphaman, usaxena95, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D73780
Raphael Isemann [Wed, 5 Feb 2020 10:44:28 +0000 (11:44 +0100)]
[lldb] Ignore type sugar in TypeSystemClang::GetPointerType
Summary:
Currently having a typedef for ObjC types is breaking member access in LLDB:
```
typedef NSString Str;
NSString *s; s.length; // OK
Str *s; s.length; // Causes: member reference base type 'Str *' (aka 'NSString *') is not a structure or union
```
This works for NSString as there the type building from `NSString` -> `NSString *` will correctly
build a ObjCObjectPointerType (which is necessary to make member access with a dot possible),
but for the typedef the `Str` -> `Str *` conversion will produce an incorrect PointerType. The reason
for this is that our check in TypeSystemClang::GetPointerType is not desugaring the base type,
which causes that `Str` is not recognised as a type to a `ObjCInterface` as the check only sees the
typedef sugar that was put around it. This causes that we fall back to constructing a PointerType
instead which does not allow member access with the dot operator.
This patch just changes the check to look at the desugared type instead.
Fixes rdar://
17525603
Reviewers: shafik, mib
Reviewed By: mib
Subscribers: mib, JDevlieghere, lldb-commits
Tags: #lldb
Differential Revision: https://reviews.llvm.org/D73952
Sebastian Neubauer [Thu, 23 Jan 2020 13:58:38 +0000 (14:58 +0100)]
[AMDGPU] Fix lowering a16 image intrinsics
scalar_to_vector takes only one argument, not two.
The a16 tests now also check the packing of coordinates into registers
Differential Revision: https://reviews.llvm.org/D73482
Sebastian Neubauer [Wed, 29 Jan 2020 13:04:56 +0000 (14:04 +0100)]
[AMDGPU] Use v3f32 type in image instructions
This should lower the amount of used registers for gfx9.
I updated some of the changed tests with the update script because
changing them by hand is tedious.
Differential Revision: https://reviews.llvm.org/D73884
Georgii Rymar [Mon, 3 Feb 2020 14:10:36 +0000 (17:10 +0300)]
[yaml2obj][obj2yaml] - Simplify format of the SHT_LLVM_ADDRSIG section.
Previously the description allowed to describe symbols with use of
`Name` and `Index` keys. This patch removes them and now it is still
possible to use either names or symbol indexes, but the code is simpler
and the format is slightly different.
Such a change will be useful for another patches, e.g:
https://reviews.llvm.org/D73788#inline-671077
Differential revision: https://reviews.llvm.org/D73888
Kadir Cetinkaya [Wed, 5 Feb 2020 09:21:26 +0000 (10:21 +0100)]
[clangd] Use printf instead of `echo -e` to be compliant with dash
Djordje Todorovic [Wed, 5 Feb 2020 08:50:05 +0000 (09:50 +0100)]
[DebugInfo] Avoid the call site param for mem instrs with multiple defs
We currently only handle mem instructions with a single define.
Avoid the call site parameter debug info when we find the case with
multiple defs, rather than throwing an assert.
Differential Revision: https://reviews.llvm.org/D73954
Kadir Cetinkaya [Wed, 5 Feb 2020 08:55:56 +0000 (09:55 +0100)]
[clangd] Preserve -nostdinc and --sysroot when calling query driver
Solves this issue: https://github.com/clangd/clangd/issues/157
This is my first contribution to an llvm project, so I hope I'm doing it right!
Patch by @topisani (Tobias Pisani)!
Reviewers: kadircet, klimek
Differential Revision: https://reviews.llvm.org/D73811
Craig Topper [Tue, 4 Feb 2020 07:35:16 +0000 (23:35 -0800)]
[X86] Add a DAG combine for (i32 (sext (i8 (x86isd::setcc_carry)))) -> (i32 (x86isd::setcc_carry)) and remove isel patterns.
Same for any_extend though we don't have coverage for that.
The test changes are because isel didn't check one use of the
setcc_carry. So in isel we would end up with two different
sized setcc_carry instructions. And since it clobbers
the flags we would need to recreate the flags for the second
instruction.
This code handles additional uses by truncating the new wide
setcc_carry back to the original size for those uses.