Marek Olšák [Sat, 25 Feb 2023 22:52:24 +0000 (17:52 -0500)]
radeonsi: increase NGG workgroup size to 256 for VS/TES with streamout and GS
NGG streamout performance is limited by the workgroup size, so make it as
large as possible.
Since this uses si_get_max_workgroup_size() to set the NGG workgroup size,
the side effect is that all GS is also getting an increase to 256, which
is OK.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403>
Marek Olšák [Sat, 25 Feb 2023 22:41:39 +0000 (17:41 -0500)]
radeonsi: allow using 64K LDS for NGG to allow larger workgroups
This should help with NGG streamout performance, which is limited by
the workgroup size (it should be as large as possible).
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403>
Marek Olšák [Sat, 25 Feb 2023 22:32:01 +0000 (17:32 -0500)]
radeonsi: other cosmetic changes in si_state_shaders.cpp
VS_W32_EN has no effect on Gfx11, but we better not set it.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403>
Marek Olšák [Sat, 25 Feb 2023 22:31:31 +0000 (17:31 -0500)]
radeonsi: reorganize si_shader_ps
To make branching based on gfx_level nicer and the code in a logical order.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403>
Marek Olšák [Sat, 25 Feb 2023 22:30:08 +0000 (17:30 -0500)]
radeonsi: reorganize si_shader_ngg
To make branching based on gfx_level nicer and the code in a logical order.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403>
Marek Olšák [Sat, 25 Feb 2023 22:26:17 +0000 (17:26 -0500)]
radeonsi: reorganize si_shader_hs
To make branching based on gfx_level nicer and the code in a logical order.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403>
Marek Olšák [Sat, 25 Feb 2023 22:25:56 +0000 (17:25 -0500)]
radeonsi: reindent si_shader_ls, si_shader_es, si_shader_gs, si_shader_vs
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403>
Marek Olšák [Sat, 25 Feb 2023 22:19:06 +0000 (17:19 -0500)]
radeonsi: set pm4.atom.emit in si_get_shader_pm4_state
except gfx10_shader_ngg, which isn't as trivial
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403>
Marek Olšák [Thu, 23 Feb 2023 17:58:16 +0000 (12:58 -0500)]
radeonsi: lower nir_texop_sampler_descriptor_amd
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403>
Marek Olšák [Thu, 23 Feb 2023 18:01:45 +0000 (13:01 -0500)]
radeonsi: separate nir_texop_descriptor_amd lowering
This moves the code to a separate branch to make it less intertwined
with the rest to allow sampler descriptor lowering later.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403>
Marek Olšák [Wed, 22 Feb 2023 11:38:00 +0000 (06:38 -0500)]
radeonsi: merge si_emit_initial_compute_regs with si_init_cs_preamble_state
It's better to set all immutable registers in one place.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403>
Marek Olšák [Mon, 20 Feb 2023 06:07:58 +0000 (01:07 -0500)]
radeonsi: emulate VGT_ESGS_RING_ITEMSIZE in the shader on gfx9-11
The hardware uses the register to premultiply GS vertex indices
in input VGPRs.
This changes the behavior as follows:
- VGT_ESGS_RING_ITEMSIZE is always 1 on gfx9-11, set in the preamble.
- The value is passed to the shader via current_gs_state (vs_state_bits).
- The shader does the multiplication.
The reason is that VGT_ESGS_RING_ITEMSIZE will be removed in the future.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403>
Timur Kristóf [Thu, 2 Mar 2023 05:47:30 +0000 (00:47 -0500)]
ac/nir: clear nir_var_shader_out from TCS barriers
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403>
Timur Kristóf [Fri, 3 Mar 2023 19:52:52 +0000 (11:52 -0800)]
aco: Don't include headers from radv.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21696>
Timur Kristóf [Fri, 3 Mar 2023 19:47:02 +0000 (11:47 -0800)]
aco, radv: Don't use radv_shader_args in aco.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21696>
Timur Kristóf [Fri, 3 Mar 2023 19:35:19 +0000 (11:35 -0800)]
aco, radv: Move PS epilog and VS prolog args to their info structs.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21696>
Timur Kristóf [Fri, 3 Mar 2023 19:25:21 +0000 (11:25 -0800)]
aco, radv: Rename aco_*_key to aco_*_info.
The naming of aco_*_key didn't make sense because they
were never actually used as cache keys, only radv_*_key
are used as cache keys.
Rename the aco structs to aco_*_info instead.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21696>
Qiang Yu [Thu, 22 Sep 2022 07:21:07 +0000 (15:21 +0800)]
aco, radv: Move is_trap_handler_shader to aco info.
v2 by Timur Kristóf:
- Rebase this patch on latest main.
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21696>
Qiang Yu [Thu, 22 Sep 2022 13:47:49 +0000 (21:47 +0800)]
aco, radv: Add load_grid_size_from_user_sgpr to aco options.
v2 by Timur Kristóf:
- Rebase this patch.
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21696>
Timur Kristóf [Fri, 3 Mar 2023 01:30:49 +0000 (17:30 -0800)]
aco: Generalize vs_inputs to args_pending_vmem.
Handle arguments that need a waitcnt without relying on
RADV specific VS input information.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21696>
Timur Kristóf [Fri, 3 Mar 2023 01:29:53 +0000 (17:29 -0800)]
radv: Set pending_vmem on dynamic VS input args.
These are loaded from VMEM and need a waitcnt before use.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21696>
Timur Kristóf [Fri, 3 Mar 2023 01:29:26 +0000 (17:29 -0800)]
ac: Add pending_vmem field to args.
This is to indicate when an argument was loaded from VMEM
and needs a waitcnt before it can be used.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21696>
Rob Clark [Sun, 26 Feb 2023 19:58:21 +0000 (11:58 -0800)]
freedreno: Promote non-drawing batches to sysmem
Sometimes we can end up with a sequence where we need to flush a batch
with no clears and no draws (for ex, to get a fence). Promote these to
sysmem.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21747>
Mike Blumenkrantz [Mon, 27 Feb 2023 18:50:13 +0000 (13:50 -0500)]
zink: hook up buffer TRANSFER_DST barrier optimizing
this should massively optimize e.g., incremental index buffer overwrites
ref #8358
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21779>
Mike Blumenkrantz [Tue, 7 Mar 2023 20:15:44 +0000 (15:15 -0500)]
zink: add a driver workaround to disable copy box optimizations
turnip is nonconformant regarding cache access (see noted issue),
meaning that any attempt to omit barriers breaks things
qcom proprietary may also be affected
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21779>
Mike Blumenkrantz [Tue, 7 Mar 2023 18:40:20 +0000 (13:40 -0500)]
zink: add a mechanism to trigger copy box resets from batch state reset
the resource isn't available during batch state reset, so a new flag
is needed to force a reset the next time the copy boxes would be used
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21779>
Mike Blumenkrantz [Mon, 27 Feb 2023 18:48:48 +0000 (13:48 -0500)]
zink: add a mechanism for managing TRANSFER_DST buffer barriers
this enables successive or unrelated transfer writes to avoid triggering
barriers, and ensuing reads of those writes should trigger their own
barriers
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21779>
Mike Blumenkrantz [Mon, 27 Feb 2023 21:41:14 +0000 (16:41 -0500)]
zink: track the last write access for resources
this enables some optimization
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21779>
SureshGuttula [Mon, 27 Feb 2023 09:23:17 +0000 (14:53 +0530)]
radeonsi: Add support for DPB resize
This patch will add support for dpb resize when low to high resolution
change/ svc use-cases.
With DPB tier1 type,vp9 svc decoder use cases are failed. This
Change will fix this[VCN1/VCN2].
Signed-off-by: SureshGuttula <suresh.guttula@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21548>
Rose Hudson [Tue, 7 Mar 2023 20:15:07 +0000 (20:15 +0000)]
asahi: disable disk cache in debug runs
With debug flags enabled, shaders might get compiled differently and
running compilation might be desired e.g. for logging, so don't try to
cache them.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21776>
Rose Hudson [Sun, 5 Mar 2023 15:46:58 +0000 (15:46 +0000)]
agx: isolate compiler debug flags
The gallium disk cache is about to depend on these, and I don't want to
create a dependency on agx_opcodes.h.py for that. So, make a new header
for them that doesn't have build dependencies.
Rename them to agx_compiler_* too, to avoid collisions with the other
driver debug flags.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21776>
Väinö Mäkelä [Sun, 5 Mar 2023 14:55:37 +0000 (16:55 +0200)]
intel/ci: Remove skipped float_controls tests from hasvk xfails
These tests are skipped now because preserving denorms isn't supported.
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21719>
Väinö Mäkelä [Sun, 5 Mar 2023 14:52:38 +0000 (16:52 +0200)]
intel/ci: Remove hasvk xfails missing from the CTS
These broken tests no longer exist in the CTS and all dynamic rendering
tests pass now.
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21719>
Väinö Mäkelä [Sun, 5 Mar 2023 14:49:20 +0000 (16:49 +0200)]
intel/ci: Remove outdated hasvk copy_and_blit xfails
These were fixed by commit
e509afac.
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21719>
Patrick Lerda [Thu, 16 Feb 2023 00:43:20 +0000 (01:43 +0100)]
mesa/program: fix memory leak triggered by arb alias
The function _mesa_symbol_table_add_symbol() copies the string with strdup(),
the original string should be freed.
For instance, with "piglit/fp-fragment-position -auto -fbo":
Direct leak of 7 byte(s) in 1 object(s) allocated from:
#0 0xffff99c59050 in __interceptor_strdup (/usr/lib64/libasan.so.6+0x59050)
#1 0xffff8f53d24c in handle_ident ../src/mesa/program/program_lexer.l:129
#2 0xffff8f53d24c in _mesa_program_lexer_lex ../src/mesa/program/program_lexer.l:312
#3 0xffff8f529d10 in yylex ../src/mesa/program/program_parse.y:289
#4 0xffff8f529d10 in yyparse src/mesa/program/program_parse.tab.c:2140
#5 0xffff8f5341a4 in _mesa_parse_arb_program ../src/mesa/program/program_parse.y:2589
#6 0xffff8f51e96c in _mesa_parse_arb_fragment_program ../src/mesa/program/arbprogparse.c:82
#7 0xffff8f4d867c in set_program_string ../src/mesa/main/arbprogram.c:402
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21728>
Patrick Lerda [Tue, 28 Feb 2023 17:38:56 +0000 (18:38 +0100)]
mesa/program: fix memory leak triggered by multiple targets used on one texture image unit
For instance, with "piglit-2000/bin/asmparsertest ARBfp1.0 tests/asmparsertest/shaders/ARBfp1.0/shadow-02.txt":
Direct leak of 192 byte(s) in 2 object(s) allocated from:
#0 0x7f6e8378f987 in calloc (/usr/lib64/libasan.so.6+0xb1987)
#1 0x7f6e7769d620 in asm_instruction_copy_ctor ../src/mesa/program/program_parse.y:2146
#2 0x7f6e7769d620 in yyparse ../src/mesa/program/program_parse.y:439
#3 0x7f6e776a6725 in _mesa_parse_arb_program ../src/mesa/program/program_parse.y:2590
#4 0x7f6e77687f69 in _mesa_parse_arb_fragment_program ../src/mesa/program/arbprogparse.c:82
#5 0x7f6e77630765 in set_program_string ../src/mesa/main/arbprogram.c:402
#6 0x7f6e76ec3e8a in _mesa_unmarshal_ProgramStringARB src/mapi/glapi/gen/marshal_generated2.c:4152
#7 0x7f6e76a0e585 in glthread_unmarshal_batch ../src/mesa/main/glthread.c:122
#8 0x7f6e76a1031d in _mesa_glthread_finish ../src/mesa/main/glthread.c:383
#9 0x7f6e76a1031d in _mesa_glthread_finish ../src/mesa/main/glthread.c:348
#10 0x7f6e76e6a062 in _mesa_marshal_GetError src/mapi/glapi/gen/marshal_generated1.c:1809
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21728>
Patrick Lerda [Tue, 28 Feb 2023 16:49:14 +0000 (17:49 +0100)]
mesa/program: fix memory leak triggered by invalid extended swizzle selector
For instance, with "piglit/bin/asmparsertest ARBfp1.0 tests/asmparsertest/shaders/ARBfp1.0/swz-04.txt":
Direct leak of 18 byte(s) in 2 object(s) allocated from:
#0 0x7f97e99050 in __interceptor_strdup (/usr/lib64/libasan.so.6+0x59050)
#1 0x7f8d4160ac in handle_ident ../src/mesa/program/program_lexer.l:129
#2 0x7f8d4160ac in _mesa_program_lexer_lex ../src/mesa/program/program_lexer.l:312
#3 0x7f8d402b50 in yylex ../src/mesa/program/program_parse.y:289
#4 0x7f8d402b50 in yyparse src/mesa/program/program_parse.tab.c:2140
#5 0x7f8d40d01c in _mesa_parse_arb_program ../src/mesa/program/program_parse.y:2590
#6 0x7f8d3f77ac in _mesa_parse_arb_fragment_program ../src/mesa/program/arbprogparse.c:82
#7 0x7f8d3ad468 in set_program_string ../src/mesa/main/arbprogram.c:402
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21728>
Georg Lehmann [Fri, 3 Feb 2023 12:28:32 +0000 (13:28 +0100)]
aco/assembler/gfx11: simplify 16bit VOP12C promotion to VOP3
With the shared struct for modifies, this is can be a lot cleaner now.
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21761>
Marek Olšák [Sat, 25 Feb 2023 01:32:34 +0000 (20:32 -0500)]
radeonsi/gfx11: only allocate GDS OA for streamout, GDS memory is not needed
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21584>
Marek Olšák [Thu, 2 Jun 2022 19:43:07 +0000 (15:43 -0400)]
amd/llvm,radeonsi/gfx11: switch to using GDS_STRMOUT registers
This is required by register shadowing (required by the new PAIRS packets),
preemption, user queues, and we only have to wait for VS after streamout,
not PS. This is how gfx11 streamout should have been done.
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21584>
Marek Olšák [Tue, 28 Feb 2023 04:07:02 +0000 (23:07 -0500)]
amd: add nir_intrinsic_xfb_counter_sub_amd and fix overflowed streamout offsets
Fixes:
5ec79f989988ba - ac/nir/ngg: nogs support streamout
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21584>
Mark Janes [Sat, 21 Jan 2023 07:19:34 +0000 (23:19 -0800)]
intel/fs: use generated workaround helpers for Wa_14017989577
Wa_14017989577 is a clone of Wa_14015360517, which applies to several
platforms beyond INTEL_PLATFORM_DG2_G10.
Update references to Wa_14017989577, and use the generated workaround
helper to ensure application to the proper platforms.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21744>
Emma Anholt [Tue, 7 Mar 2023 17:23:48 +0000 (09:23 -0800)]
ci/etnaviv: Drop the dEQP-GLES2.functional.uniform_api.random.94 xfail.
This has been consistently passing. I think I just missed it in my
previous update.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21769>
Emma Anholt [Tue, 7 Mar 2023 17:20:25 +0000 (09:20 -0800)]
ci: Add some xfail updates from VKCTS 1.3.5.0 for the manual jobs.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21769>
Mike Blumenkrantz [Thu, 16 Feb 2023 17:42:51 +0000 (12:42 -0500)]
llvmpipe: fix LP_PERF=no_depth to ignore depth format
cc: mesa-stable
Reviewed-by: Brian Paul brianp@vmware.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21582>
Juan A. Suarez Romero [Mon, 20 Feb 2023 11:51:00 +0000 (12:51 +0100)]
v3d/v3dv: define performance counters in common
Both OpenGL and Vulkan drivers share the same performance counters.
Let's move them to a common place instead of duplicating.
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21420>
Antonio Gomes [Tue, 27 Dec 2022 06:13:34 +0000 (03:13 -0300)]
iris: Add support for 2d images created from buffers
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20378>
Antonio Gomes [Sat, 7 Jan 2023 02:54:24 +0000 (23:54 -0300)]
llvmpipe: Add new caps PIPE_CAP_LINEAR_IMAGE_(PITCH_ALIGNMENT|BASE_ADDRESS_ALIGNMENT)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20378>
Antonio Gomes [Sat, 7 Jan 2023 02:54:04 +0000 (23:54 -0300)]
rusticl: Implement spec for cl_khr_image2d_from_buffer
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20378>
Antonio Gomes [Sat, 7 Jan 2023 02:52:05 +0000 (23:52 -0300)]
gallium: Add new caps PIPE_CAP_LINEAR_IMAGE_(PITCH_ALIGNMENT|BASE_ADDRESS_ALIGNMENT)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20378>
Antonio Gomes [Mon, 12 Dec 2022 21:22:31 +0000 (18:22 -0300)]
lvmpipe/cs: Add support for 2d images created from buffers
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20378>
Antonio Gomes [Sun, 26 Feb 2023 19:29:45 +0000 (16:29 -0300)]
mesa/st, nine, nouveau: Fix uninitialized pipe_sampler_view structs
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20378>
Antonio Gomes [Mon, 12 Dec 2022 20:35:49 +0000 (17:35 -0300)]
gallium, rusticl: Add tex2d_from_buf in image_view and sampler_view
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20378>
Antonio Gomes [Wed, 7 Dec 2022 21:35:44 +0000 (18:35 -0300)]
rusticl: Enable mapImage for images created from buffers
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20378>
Antonio Gomes [Wed, 7 Dec 2022 16:04:00 +0000 (13:04 -0300)]
rusticl: Enable copy for images created from buffers
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20378>
Antonio Gomes [Tue, 6 Dec 2022 21:39:59 +0000 (18:39 -0300)]
rusticl: Enabling image fill for images created from buffers
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20378>
Antonio Gomes [Tue, 6 Dec 2022 03:54:12 +0000 (00:54 -0300)]
rusticl: Enabling reading/writing for images created from buffers
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20378>
Daniel Schürmann [Fri, 3 Mar 2023 18:49:43 +0000 (19:49 +0100)]
radv/rt: move radv_pipeline_key from rt_variables to traversal_data
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21764>
Daniel Schürmann [Tue, 7 Mar 2023 12:30:57 +0000 (13:30 +0100)]
radv: remove unused parameters from radv_compute_pipeline_compile()
Also make this function static.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21764>
Daniel Schürmann [Tue, 7 Mar 2023 11:40:08 +0000 (12:40 +0100)]
radv/rt: introduce and use radv_rt_pipeline_compile()
This is essentially a code-duplication of radv_compute_pipeline_compile()
but will later be more specialized for the needs of RT pipelines.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21764>
Daniel Schürmann [Tue, 7 Mar 2023 12:19:24 +0000 (13:19 +0100)]
radv: expose radv_pipeline_capture_shaders()
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21764>
Daniel Schürmann [Tue, 7 Mar 2023 12:17:12 +0000 (13:17 +0100)]
radv: expose radv_postprocess_nir()
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21764>
Samuel Pitoiset [Tue, 7 Mar 2023 12:21:55 +0000 (13:21 +0100)]
radv: fix defining RADV_USE_WSI_PLATFORM
RADV_USE_WSI_PLATFORM was unused in radv_CreateImage().
Fixes:
2a5d7f4926c ("radv: fix missing implementation of creating images from swapchains")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21763>
José Roberto de Souza [Mon, 24 Oct 2022 21:08:55 +0000 (14:08 -0700)]
iris: Move iris_bo_wait_gem() to i915/iris_bufmgr.c
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21494>
José Roberto de Souza [Mon, 24 Oct 2022 20:53:34 +0000 (13:53 -0700)]
iris: Move iris_bo_busy_gem() to i915/iris_bufmgr.c
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21494>
José Roberto de Souza [Mon, 6 Mar 2023 17:11:00 +0000 (09:11 -0800)]
iris: Move bo_set_caching to kmd backend
For the platforms that call it, it a function in the hot path so
moving it to kmd backend.
After this patch i915/iris_bufmgr.c is empty but not removing it
as next patch will add functions to it.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21494>
José Roberto de Souza [Mon, 6 Mar 2023 17:04:53 +0000 (09:04 -0800)]
iris: Move bo_madvise to kmd backend
bo_madvise() is on hot path, so moving it to kmd backend.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21494>
José Roberto de Souza [Thu, 9 Feb 2023 17:57:56 +0000 (09:57 -0800)]
intel/common: Implement the Xe functions for intel_gem
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21699>
José Roberto de Souza [Thu, 9 Feb 2023 17:45:56 +0000 (09:45 -0800)]
intel/common: Implement the Xe functions for intel_engine
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21699>
Samuel Pitoiset [Thu, 23 Feb 2023 08:50:17 +0000 (09:50 +0100)]
radv: fix border color swizzle for stencil-only format on GFX9+
Swizzle of 8-bit stencil format is defined as _x__ but the hw expects
BC_SWIZZLE_XYZW.
Fixes dEQP-VK.pipeline.monolithic.sampler.border_swizzle.*s8_uint*.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21482>
Tapani Pälli [Tue, 7 Mar 2023 11:39:28 +0000 (13:39 +0200)]
anv: fix sends_count_expectation assert on simd32
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21758>
Yogesh Mohan Marimuthu [Tue, 28 Feb 2023 14:48:17 +0000 (20:18 +0530)]
ac/surface: only adjust pitch if surf_pitch was modified
Modifying pitch for all LINEAR surface isn't correct;
the original change that modified surf_pitch was only
intended for YUV textures.
This fixes vkGetImageSubresourceLayout rowPitch return value
for VK_FORMAT_BC3_UNORM_BLOCK + VK_IMAGE_TILING_LINEAR.
Fixes:
fcc499d5 (ac/surface: adjust gfx9.pitch[*] based on surf->blk_w)
v2: add check for UYVY format (Pierre-Eric)
v3: move blk_w division to above if check (Pierre-Eric)
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21595>
David Heidelberg [Tue, 7 Mar 2023 12:15:26 +0000 (13:15 +0100)]
ci/lavapipe: fixes typo
Fixes:
5ee724e180bd ("ci/lavapipe: add recent occasional flake")
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21759>
Georg Lehmann [Tue, 14 Feb 2023 15:47:40 +0000 (16:47 +0100)]
aco: use bitfield array helpers for valu modifiers
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21023>
Georg Lehmann [Tue, 14 Feb 2023 15:39:20 +0000 (16:39 +0100)]
aco: add bitfield array helper classes
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21023>
Georg Lehmann [Tue, 21 Feb 2023 19:08:42 +0000 (20:08 +0100)]
aco: remove VOP[123C]P? structs
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21023>
Georg Lehmann [Tue, 31 Jan 2023 17:03:01 +0000 (18:03 +0100)]
aco/optimizer: simplify using VALU instruction
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21023>
Georg Lehmann [Wed, 11 Jan 2023 12:09:20 +0000 (13:09 +0100)]
aco/print_ir: simplify using VALU instruction
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21023>
Georg Lehmann [Tue, 31 Jan 2023 12:14:46 +0000 (13:14 +0100)]
aco: validate VALU modifiers
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21023>
Georg Lehmann [Tue, 31 Jan 2023 17:04:29 +0000 (18:04 +0100)]
aco/ra: set opsel_hi to zero when converting to VOP2
Otherwise the new modifier validation will fail.
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21023>
Georg Lehmann [Wed, 11 Jan 2023 11:12:33 +0000 (12:12 +0100)]
aco/ir: rework IR to have one common valu instruction struct
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21023>
Georg Lehmann [Fri, 3 Feb 2023 12:08:14 +0000 (13:08 +0100)]
aco: treat VINTERP_INREG as VALU
It's just v_fma with fixed DPP8 and builtin s_waitcnt_expcnt, so it can mostly
be handled as a pure VALU instruction.
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21023>
Samuel Pitoiset [Thu, 2 Mar 2023 09:24:37 +0000 (10:24 +0100)]
radv: fix incorrect stride for primitives generated query with GDS
When the query pool uses GDS (for NGG), the stride is 40.
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8412
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21650>
Lionel Landwerlin [Sun, 5 Mar 2023 21:12:36 +0000 (23:12 +0200)]
nir: fix nir_ishl_imm
Both GLSL & SPIRV have undefined values for shift > bitsize. But SM5
says :
"This instruction performs a component-wise shift of each 32-bit
value in src0 left by an unsigned integer bit count provided by
the LSB 5 bits (0-31 range) in src1, inserting 0."
Better to not hard code the wrong behavior in NIR.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
e227bb9fd5 ("nir/builder: add ishl_imm helper")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@colllabora.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21720>
Samuel Pitoiset [Fri, 13 Jan 2023 16:04:01 +0000 (17:04 +0100)]
radv: do not add descriptor BOs on update when the global BO list is used
It's unnecessary and already checked elsewhere like in
vkCmdBindDescriptorSets(). This improves performance of vkoverhead
test #76 (descriptor_1image) by +18%. It's the same performance as
PRO on my Threadripper 1950X now. This should also slightly improve
texel and buffer descriptors.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20699>
Karol Herbst [Wed, 1 Mar 2023 12:39:47 +0000 (13:39 +0100)]
gallivm: fix lp_vec_add_offset_ptr for 32 bit builds
The function assumed ptrs are always 64 bit sized.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8267
Fixes:
442d1fe5ad6 ("gallivm: use masked intrinsics for global and scratch access.")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21604>
Karol Herbst [Tue, 28 Feb 2023 18:50:05 +0000 (19:50 +0100)]
rusticl/kernel: Images arg sizes also have to match the host pointer size
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8267
Fixes:
b0d698c5328 ("rusticl: correctly check global argument size")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21604>
Alyssa Rosenzweig [Fri, 3 Mar 2023 21:18:52 +0000 (16:18 -0500)]
agx: Assert that memory index is 32-bit reg
Semantics will be wrong otherwise (reading garbage).
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21643>
Alyssa Rosenzweig [Fri, 3 Mar 2023 21:19:17 +0000 (16:19 -0500)]
agx/lower_address: Handle 16-bit offsets
These need to be upconverted for correctness.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21643>
Alyssa Rosenzweig [Fri, 3 Mar 2023 21:27:26 +0000 (16:27 -0500)]
agx/lower_address: Fix handling of 64-bit immediates
We can't add a 64-bit immediate with the hardware iadd, that won't work. What we
can do is add a 32-bit immediate, derived as the low 32-bits of a 64-bit
nir_ssa_def.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21643>
Alyssa Rosenzweig [Fri, 3 Mar 2023 20:25:42 +0000 (15:25 -0500)]
agx/lower_address: Handle 8-bit load/store
Should work ok with the implicit up-conversion that the backend does.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21643>
Alyssa Rosenzweig [Thu, 2 Mar 2023 06:06:39 +0000 (01:06 -0500)]
agx/lower_address: Handle large shifts
If we manage to fold in a left shift that's bigger than the hardware can do, we
should at least avoid generating a useless right shift to feed the hardware
rather bailing completely.
For motivation, this form of address arithmetic is encountered when indexing
into arrays with large power-of-two element sizes (array-of-structs).
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21643>
Alyssa Rosenzweig [Thu, 2 Mar 2023 05:54:32 +0000 (00:54 -0500)]
agx/lower_address: Optimize "shift + constant"
Optimize address arithmetic of the form
base + u2u64((index << shift) + const)
into hardware operands
base, index << (shift - format_shift) + const'
which (if format_shift = shift) can be simply
base, index + const'
rather than the current naive translation
base, ((index << shift) + const) >> format_shift
This saves at least one pointless shift. We can't do this optimization with
nir_opt_algebraic, because explicitly optimizing "(a << #b) >> #b" to "a" isn't
sound due to overflow. But there's no overflow issue here, which is what this
whole pass is designed around.
For motivation, this address arithmetic implements "dynamically indexing into an
array inside of a C structure", where the const is the offset of the array
relative to the structure.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21643>
Alyssa Rosenzweig [Tue, 7 Mar 2023 02:15:25 +0000 (21:15 -0500)]
agx/lower_address: Break on match
Once we've matched a summand, commit to it. This avoids needlessly checking the
second source if the first matched, and removes some indentation/funny control
flow.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21643>
Sergi Blanch Torne [Thu, 16 Feb 2023 09:47:07 +0000 (10:47 +0100)]
Revert "ci: disable Collabora's LAVA lab for maintance"
This reverts commit https://gitlab.freedesktop.org/mesa/mesa/-/commit/
6be7469df1e12bd57c697ff7e34bbda8286d67a2
Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21356>
Mike Blumenkrantz [Fri, 3 Mar 2023 15:43:04 +0000 (10:43 -0500)]
zink: always set batch usage for descriptors after barrier
this otherwise breaks unordered promotion calc
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21739>
Mike Blumenkrantz [Thu, 2 Mar 2023 15:01:44 +0000 (10:01 -0500)]
zink: set dynamic pcp for unordered cmdbuf
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21739>
Mike Blumenkrantz [Thu, 2 Mar 2023 14:56:11 +0000 (09:56 -0500)]
zink: bind descriptor buffers to unordered cmdbuf
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21739>
Mike Blumenkrantz [Tue, 28 Feb 2023 20:41:07 +0000 (15:41 -0500)]
zink: always set color writes on the unordered cmdbuf
this state has to be set, so ensure it is
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21739>
Mike Blumenkrantz [Wed, 1 Mar 2023 22:13:34 +0000 (17:13 -0500)]
zink: explicitly flush src clears when u_blittering
this otherwise relies on set_framebuffer_state flushing them,
which may or may not be accurate/desired
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21739>